Integrated
Circuit
Systems, Inc.
ICS950810
0472F—01/12/04
Block Diagram
Recommended Application:
CK-408 clock for BANIAS processor/ ODEM and
MONTARA-G chipsets.
Output Features:
• 3 0.7V Differential CPU Clock Pairs
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
• Supports spread spectrum modulation,
down spread 0 to -0.5%. (CPU, 3V66, PCI)
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
•CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
Frequency Generator with 200MHz Differential CPU Clocks
Functionality
* These inputs have 150K internal pull-up resistor to VDD.
2SF1SF0SF UPC
)zHM(
)0:5(66V3
)zHM(
F_ICP
ICP
)zHM(
X00 66.66166.6633.33
X0 1 00.00166.6633.33
X10 00.00266.6633.33
X11 33.33166.6633.33
diM00 e
tatsirTetatsirTetatsirT
diM01 2/KLCT4/KLCT8/KLCT
diM10 devreseRdevreseRdevreseR
diM11 devreseRdevreseRdevreseR
PLL2
PLL1
Spread
Spectrum
3V66_5
3V66_3
3V66_(4,2)
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
3V66
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
S DATA
SCLK
FS (2:0)
I REF
Control
Logic
Config.
Reg.
REF
3V66_0
CPU
DIVDER
3
3CPUCLKT (2:0)
CPUCLKC (2:0)
Stop
3V66_1/VCH_CLK
PCICLK (6:0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
VDDREF 156
REF
X1 255
FS1
X2 354
FS0
GND 453
CPU_STOP#*
PCICLK_F0 552
CPUCLKT0
PCICLK_F1 651
CPUCLKC0
PCICLK_F2 750
VDDCPU
VDDPCI 849
CPUCLKT1
GND 948
CPUCLKC1
PCICLK0 10 47 GND
PCICLK1 11 46 VDDCPU
PCICLK2 12 45 CPUCLKT2
PCICLK3 13 44 CPUCLKC2
VDDPCI 14 43 MULTSEL0*
GND 15 42 IREF
PCICLK4 16 41 GND
PCICLK5 17 40 FS2
PCICLK6 18 39 48MHz_USB
VDD3V66 19 38 48MHz_DOT
GND 20 37 VDD48
3V66_2 21 36 GND
3V66_3 22 35 3V66_1/VCH_CLK
3V66_4 23 34 PCI_STOP#*
3V66_5 24 33 3V66_0
*PD# 25 32 VDD3V66
VDDA 26 31 GND
GND 27 30 SCLK
Vtt_PWRGD# 28 29 SDATA
ICS950810
2
ICS950810
0472F—01/12/04
NIP
REBMUN EMANNIPEPYTNOITPIRCSED
1FERDDVRWPV3.3lanimon,ylppusrewopLATX,feR
21XNI.zHM813.41yllanimon,tupnilatsyrC
32XTUO.zHM813.41yllanimon,tuptuo
latsyrC
4
DNGRWP.stuptuoV3rofnipdnuorG
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61F_KLCICPTUO.#POTS_ICPybdetceffatonkcolcICPgninnure
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ewoP
9DNGRWP.stuptuoV3rofnipdnuorG
010KLCICPTUO.stuptuokcolcICP
111KLCICPTUO.stuptuokcolcICP
212KLCICP
TUO.stuptuokcolcICP
313KLCICP
TUO.stuptuokcolcICP
41ICPDDV
RWP
V3.3lanimon,KLCICPdnaF_KLCICProfylppusrewoP
51DNGRWP.stuptuoV3rofnipdnuorG
614KLCICPTUO.stuptuokcolcICP
715KLCI
CPTUO.stuptuokcolcICP
816KLCICPTUO.stuptuokcolcICP
9166V3DDVRWP.skcolc66V3ehtrofniprewoP
02DNGRWP.stuptuoV3rofnipdn
uorG
122_66V3TUO.V3.3tastuptuozHM66
223_66V3TUO.V3.3tastuptuozHM66
324_66V3TUO.V3.3tastuptuozHM66
425_66V3TUO.V3.3tat
uptuo/tupnizHM66
52#DPNI
wolaotniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
eralatsyrcehtdnaOCV
ehtdnadelbasideraskcolclanretniehT.etatsrewop
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62ADDVRWP.erocLLPehtrofrewopV3.3
72DNGRWP.stuptuoV3rofnipdnuorG
Pin Configuration
3
ICS950810
0472F—01/12/04
Pin Configuration (Continued)
NIP
REBMUN EMANNIPEPYTNOITPIRCSED
82#DGRWP_ttVNI
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.delpmasebotydaereradnadilaverastupni0LESITLUMdna]0:2[SF
)wolevitca(
92ATADSO/ItnarelotV5yrtiucricC2IrofnipataD
03KLCSNItnarelotV5yrtiucric
C2IfonipkcolC
13DNGRWP.stuptuoV3rofnipdnuorG
2366V3DDVRWP.skcolc66V3ehtrofniprewoP
330_66V3TUO.V3.3tastuptuozHM66
43#POTS_ICPNInehw,level0cigoltaskcolcF_KLCICPehtsedisebsKLCICPllaspotS
woltupni
53KLC_HCV/1_66V3TUOtuptuokco
lcCSSzHM66roCSS-nonzHM84elbatceleS
63DNGRWP.stuptuoV3rofnipdnuorG
7384DDVRWP.erocLLPdexifdnasreffubtuptuozHM8
4rofrewoP
83TOD_zHM84TUOkcolctuptuozHM84
93BSU_zHM84TUOkcolctuptuozHM84
042SFNI.niptcelesycneuqerF
14DNGRWP.stuptuoV3
rofnipdnuorG
24FERITUO
nipsihT.sriapKLCUPCehtroftnerrucecnereferehtsehsilbatsefnipsihT
ehthsilbatseotredro
nidnuorgotdeitrotsisernoisicerpdexifaseriuqer
.tnerrucetairporppa
340LESTLUMNI stuptuoUPCrofreilpitlumtner
rucehtnoitcelesroftupniLTTVLV3.3
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elpmoC"
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64UPCDDVRWPlanimonV3.
3,skcolcUPCrofylppuS
74DNGRWP.stuptuoV3rofnipdnuorG
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551SFNI.niptcelesycneuqerF
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4
ICS950810
0472F—01/12/04
Host Swing Select Functions
0LESITLUM tegraTdraoB
ZmreT/ecarT
,RecnerefeR
=ferI
V
DD
)rR*3(/
tuptuO
tnerruC Z@hoV
0- - --
1smho05 ,%1574=rR
Am23.2=ferI FERI*6=hoI05@V7.0
Truth Table
Maximum Allowed Current
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ICP
)zHM(
0FER
)zHM(
TOD/BSU
)zHM(
X00 66.66166.6633.33813.4100.84
X0 1 00.00166.6633.3381
3.4100.84
X10 00.00266.6633.33813.4100.84
X11 33.33166.6633.33813.4100.84
diM00 etatsirTetatsirTetatsirTetatsirTetatsirT
diM01 2/KLCT4/
KLCT8/KLCTKLCT2/KLCT
diM10 devreseRdevreseRdevreseRdevreseRdevreseR
diM11 devreseRdevreseRdevreseRdevreseRdevreseR
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
(Digital)
VDDPCI
VDD3V66
VDDCPU
NOTE: MULTSEL0 = 0 not supported in ICS950810. Refer to ICS950805 for Buffered Mode support.
5
ICS950810
0472F—01/12/04
Power Management
PD# CPU_STOP# PCI_STOP# VCO CPU CPU# PCICLK 3v66 48MHz REF
0 X X STOP Iref*2 FLOAT LOW LOW LOW LOW
1 1 1 RUN RUN RUN RUN RUN RUN RUN
1 0 1 RUN Iref*2 FLOAT RUN RUN RUN RUN
1 1 0 RUN RUN RUN LOW RUN RUN RUN
1 1 1 RUN RUN RUN RUN RUN RUN RUN
Note: PCI_F is not affected by PCI_STOP# and CPU_STOP#
State Byte0 bit6
PD#
Byte1bit6
C
p
u_sto
p
#
Pin
PD#
Pin
C
p
u_Sto
p
#
Stoppable
CPU out
p
uts
Free-Running
CPU out
p
uts
0 0 0 1 1 Runnin
g
Runnin
g
1 0 0 1 0 Irefx6 Runnin
g
2 0 0 0 1 Irefx2 Irefx2
3 0 0 0 0 Irefx2 Irefx2
4 0 1 1 1 Runnin
g
Runnin
g
5 0 1 1 0 Hi-Z Runnin
g
60 1 0 1 Hi-Z Irefx2
70 1 0 0 Hi-Z Irefx2
8 1 0 1 1 Runnin
g
Runnin
g
9 1 0 1 0 Irefx6 Runnin
g
10 1 0 0 1 Hi-Z Hi-Z
11 1 0 0 0 Hi-Z Hi-Z
12 1 1 1 1 Runnin
g
Runnin
g
13 1 1 1 0 Hi-Z Runnin
g
14 1 1 0 1 Hi-Z Hi-Z
15 1 1 0 0 Hi-Z Hi-Z
Tri-State Control of CPU Outputs
6
ICS950810
0472F—01/12/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2VDD +0.3 V
Input Low Voltage VIL VSS -0.3 0.8 V
Input High Current IIH VIN = VDD -5 5
IIL1
VIN = 0 V; Inputs with no pull-up
resistors -5
IIL2
VIN = 0 V; Inputs with pull-up
resistors -200
IDD3.3OP CL = Full load; Select @ 100 MHz 229 230 360 mA
IDD3.3OP CL =Full load; Select @ 133 MHz 220 233 360 mA
Powerdown Current IDD3.3PD IREF=2.32 mA 22 25 mA
Input Frequency FiVDD = 3.3 V 14.318 MHz
Pin Inductance Lpin 7nH
CIN Logic Inputs 5 pF
COUT Output pin capacitance 6 pF
CINX X1 & X2 pins 27 30 45 pF
Clk Stabilization1,2 TSTAB
From PowerUp or deassertion of
PowerDown to 1st clock. 11.8 ms
tPZH,tPZL Output enable delay (all outputs) 1 10 ns
tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
2See timin
g
dia
g
rams for buffered and un-buffered timin
g
re
q
uirements.
Delay1
Input Capacitance1
Input Low Current µA
Operating Supply Current
7
ICS950810
0472F—01/12/04
Electrical Characteristics - CPU (0.7V Select)
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Current Source Output
Impedance Zo1 VO = Vx3000 Ω
Voltage High VHigh 660 810 850
Voltage Low VLow -150 20 150
Max Voltage Vovs 850 1150
Min Voltage Vuds -450 -15
Crossing Voltage (abs) Vcross(abs) 250 380 550 mV
Crossing Voltage (var) d-Vcross Variation of crossing over all
edges 22 140 mV
Rise Time trVOL = 0.175V, VOH = 0.525V 175 290 700 ps
Fall Time tfVOH = 0.525V VOL = 0.175V 175 310 700 ps
Rise Time Variation d-tr10 125 ps
Fall Time Variation d-tf10 125 ps
Duty Cycle dt3
Measurement from differential
wavefrom 45 51 55 %
Skew tsk3 V
T
= 50% 16 100 ps
Jitter, Cycle to cycle tjcyc-cyc1VT = 50% 48 150 ps
1Guaranteed by design, not 100% tested in production.
2 IOW
T
can be varied and is selectable thru the MULTSEL pin.
Statistical measurement on
single ended signal using mV
Measurement on single ended
signal using absolute value. mV
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP11VO = VDD*(0.5) 12 33 55 W
Output High Voltage VOH1IOH = -1 mA 2.4 3.28 V
Output Low Voltage VOL1IOL = 1 mA 0.08 0.55 V
V OH@MIN = 1.0 V -33 -110
V OH@MAX = 3.135 V -20 -33 mA
VOL @MIN = 1.95 V 30 110
VOL @MAX = 0.4 V 37 38 mA
Rise Time tr11VOL = 0.4 V, VOH = 2.4 V 0.5 1.28 2 ns
Fall Time tf11VOH = 2.4 V, VOL = 0.4 V 0.5 1.37 2 ns
Duty Cycle dt11VT = 1.5 V 45 51.1 55 %
Skew tsk11VT = 1.5 V 127 500 ps
Jitter,cycle to cyc tjcyc-cyc1VT = 1.5 V 164 250 ps
1Guaranteed by design, not 100% tested in production.
Output High Current IOH1
Output Low Current IOL1
8
ICS950810
0472F—01/12/04
Electrical Characteristics - 3V66 Mode: 3V66 [5:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP1
1VO = VDD*(0.5) 12 33 55 Ω
Output High Voltage VOH
1IOH = -1 mA 2.4 3.28 V
Output Low Voltage VOL
1IOL = 1 mA 0.08 0.55 V
V OH@MIN = 1.0 V -33 -110
V OH@MAX = 3.135 V -20 -33 mA
VOL @MIN = 1.95 V 30 110
VOL @MAX = 0.4 V 37 38 mA
Rise Time tr1
1VOL = 0.4 V, VOH = 2.4 V 0.5 1.15 2 ns
Fall Time tf1
1VOH = 2.4 V, VOL = 0.4 V 0.5 1.53 2 ns
Duty Cycle dt1
1VT = 1.5 V 45 51.3 55 %
Skew tsk1
1VT = 1.5 V 67 250 ps
Jitter t
c
c-c
c
1VT = 1.5 V 3V66 175 250 ps
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Output High Current IOH
1
IOL
1
Output Low Current
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP1
1VO = VDD*(0.5) 20 48 60 Ω
Output High Voltage VOH
1IOH = -1 mA 2.4 3.27 V
Output Low Voltage VOL
1IOL = 1 mA 0.08 0.4 V
V OH@MIN = 1.0 V -29 -61
V OH@MAX = 3.135 V -12 -23 mA
VOL @MIN = 1.95 V 29
VOL @MAX = 0.4 V 27 mA
48DOT Rise Time tr1
1VOL = 0.4 V, VOH = 2.4 V 0.5 0.69 1 ns
48DOT Fall Time tf1
1VOH = 2.4 V, VOL = 0.4 V 0.5 0.81 1 ns
VCH 48 USB Rise Time tr1
1VOL = 0.4 V, VOH = 2.4 V 11.372 ns
VCH 48 USB Fall Time tf1
1VOH = 2.4 V, VOL = 0.4 V 11.472 ns
48 DOT Duty Cycle dt1
1VT = 1.5 V 45 51.2 55 %
VCH 48 USB Duty Cycle dt1
1VT = 1.5 V 45 53.5 55 %
48 DOT Jitter t
c
c-c
c
1VT = 1.5 V 111 350 ps
48 USB Jitter t
c
c-c
c
1VT = 1.5 V 99 350 ps
USB to DOT Skew tsk1
1VT = 1.5 V (0 OR 180 degrees) 1ns
VCH Jitter t
c
c-c
c
1VT = 1.5 V 147 350 ps
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Output High Current IOH
1
Output Low Current IOL
1
9
ICS950810
0472F—01/12/04
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP1
1VO = VDD*(0.5) 20 48 60 Ω
Output High Voltage VOH
1IOH = -1 mA 2.4 3.28 V
Output Low Voltage VOL
1IOL = 1 mA 0.08 0.4 V
V OH@MIN = 1.0 V -33 -110
V OH@MAX = 3.135 V -20 -33 mA
VOL @MIN = 1.95 V 30 110
VOL @MAX = 0.4 V 37 38 mA
Rise Time tr1
1VOL = 0.4 V, VOH = 2.4 V 11.692 ns
Fall Time tf1
1VOH = 2.4 V, VOL = 0.4 V 11.562 ns
Duty Cycle dt1
1VT = 1.5 V 45 53 55 %
Jitter t
c
c-c
c
1VT = 1.5 V 152 1000 ps
1Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
Output High Current IOH
1
Output Low Current IOL
1
10
ICS950810
0472F—01/12/04
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2(H)
A
CK
Du mmy Command Code
A
CK
Dummy Byte Count ACK
By te 0
A
CK
By te 1
A
CK
By te 2 ACK
By te 3
A
CK
By te 4
A
CK
By te 5 ACK
By te 6 ACK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3(H)
A
CK
Byte Count
ACK Byte 0
ACK Byte 1
ACK Byte 2
ACK Byte 3
ACK Byte 4
ACK Byte 5
ACK Byte 6
ACK
Stop Bit
How to Read:
11
ICS950810
0472F—01/12/04
I2C Tables
Pin # Name 0 1 PWD
Bit 7 - Spread Enabled Spread Spectrum Control RW OFF ON 0
Bit 6 - CPU_T(2:0)
Power down mode output
level
0= CPU driven in power
down
1= undriven
RW HIGH LOW 0
Bit 5 35 3V66_1/VCH_CLK VCH/66.66 Select RW 66.66 48.00 0
Bit 4 53 CPU_STOP#* Reflects value of pin R Stop Active X
Bit 3 34 PCI_STOP#* Reflects value of pin at
power up. Also can be set. R/RW Stop Active 1
Bit 2 40 FS2 Frequency Selection RW - - X
Bit 1 55 FS1 Frequency Selection RW - - X
Bit 0 54 FS0 Frequency Selection RW - - X
Control Function
Affected Pin
BYTE
0T
y
pe
Bit Control
Pin # Name 0 1 PWD
Bit 7 43 MULTSEL0* Reflects value of pin R - - x
Bit 6 - CPU_T(2:0)
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
RW HIGH LOW 0
Bit 5 45, 44 CPUCLKT2
CPUCLKC2
Allow control of output with
assertion of CPU_STOP#. RW Not
Freerun Freerun 0
Bit 4 49, 48 CPUCLKT1
CPUCLKC1
Allow control of output with
assertion of CPU_STOP#. RW Not
Freerun Freerun 0
Bit 3 52, 51 CPUCLKT0
CPUCLKC0
Allow control of output with
assertion of CPU_STOP#. RW Not
Freerun Freerun 0
Bit 2 45, 44 CPUCLKT2
CPUCLKC2 Output control RW Disable Enable 1
Bit 1 49, 48 CPUCLKT1
CPUCLKC1 Output control RW Disable Enable 1
Bit 0 52, 51 CPUCLKT2
CPUCLKC2 Output control RW Disable Enable 1
BYTE
1Control Function
Affected Pin Type Bit Control
12
ICS950810
0472F—01/12/04
Pin # Name 0 1 PWD
Bit 7 - - (Reserved) - - - 0
Bit 6 18 PCICLK6 Output control RW Disable Enable 1
Bit 5 17 PCICLK5 Output control RW Disable Enable 1
Bit 4 16 PCICLK4 Output control RW Disable Enable 1
Bit 3 13 PCICLK3 Output control RW Disable Enable 1
Bit 2 12 PCICLK2 Output control RW Disable Enable 1
Bit 1 11 PCICLK1 Output control RW Disable Enable 1
Bit 0 10 PCICLK0 Output control RW Disable Enable 1
BYTE
2Control Function
Affected Pin Type Bit Control
Pin # Name 0 1 PWD
Bit 7 38 48MHz_DOT Output control RW Disable Enable 1
Bit 6 39 48MHz_USB Output control RW Disable Enable 1
Bit 5 7 PCICLK_F2 Allow control of output with
assertion of PCI_STOP#. RW Freerun Not
Freerun 0
Bit 4 6 PCICLK_F1 Allow control of output with
assertion of PCI_STOP#. RW Freerun Not
Freerun 0
Bit 3 5 PCICLK_F0 Allow control of output with
assertion of PCI_STOP#. RW Freerun Not
Freerun 0
Bit 2 7 PCICLK_F2 Output control RW Disable Enable 1
Bit 1 6 PCICLK_F1 Output control RW Disable Enable 1
Bit 0 5 PCICLK_F0 Output control RW Disable Enable 1
Control Function
BYTE
3
Affected Pin Bit Control
Type
Pin # Name 0 1 PWD
Bit 7 - - (Reserved) RW Disable Enable 0
Bit 6 - - (Reserved) RW Disable Enable 0
Bit 5 33 3V66_0 Output control RW Disable Enable 1
Bit 4 35 3V66_1/VCH_CLK Output control RW Disable Enable 1
Bit 3 24 3V66_5 Output control RW Disable Enable 1
Bit 2 23 3V66_4 Output control RW Disable Enable 1
Bit 1 22 3V66_3 Output control RW Disable Enable 1
Bit 0 21 3V66_2 Output control RW Disable Enable 1
Type Bit Control
Control Function
Affected PinBYTE
4
13
ICS950810
0472F—01/12/04
Pin # Name 0 1 PWD
Bit 7 X - (Reserved) - - - 0
Bit 6 X - (Reserved) - - - 0
Bit 5 X - (Reserved) - - - 0
Bit 4 X - (Reserved) - - - 0
Bit 3 X - (Reserved) - - - 0
Bit 2 X - (Reserved) - - - 0
Bit 1 X - (Reserved) - - - 0
Bit 0 X - (Reserved) - - - 0
Affected Pin Type Bit ControlBYTE
5Control Function
Pin # Name 0 1 PWD
Bit 7 X Revision ID Bit 3 (Reserved) R - - 1
Bit 6 X Revision ID Bit 2 (Reserved) R - - 1
Bit 5 X Revision ID Bit 1 (Reserved) R - - 1
Bit 4 X Revision ID Bit 0 (Reserved) R - - 1
Bit 3 X Vendor ID Bit 3 (Reserved) R - - 1
Bit 2 X Vendor ID Bit 2 (Reserved) R - - 1
Bit 1 X Vendor ID Bit 1 (Reserved) R - - 1
Bit 0 X Vendor ID Bit 0 (Reserved) R - - 1
Affected Pin Type Bit ControlBYTE
6Control Function
14
ICS950810
0472F—01/12/04
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there
is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the
standard skew described below as Tpci.
3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0) Tpci
Skews at Common Transition Edges
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
PCI PCI ts
k
1VT = 1.5 V 127 500 ps
3V66 3V66 ts
k
1VT = 1.5 V 67 250 ps
3V66 to PCI S3V66-PCI 3V66 (5:0) leads 33MHz PCI 1.5 3.5 ns
1Guarenteed b
y
desi
g
n, not 100% tested in
p
roduction.
15
ICS950810
0472F—01/12/04
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#POTS_UPCTUPCCUPC
1lamroNlamroN
0tluM*feritaolF
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive
current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU
and CPU# outputs will not be driven.
CPU_STOP#
CPUT
CPUC
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
De-assertion of CPU_STOP# Waveforms
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the
de-assertion to active outputs is to be defined to be tetween 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit
6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion.
16
ICS950810
0472F—01/12/04
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both
CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and
description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than
one clock cycle to complete.
PD# - Assertion (transition from logic "1" to logic "0")
Power Down Assertion of Waveforms
0ns
PD #
CPUT 100MHz
CPUC 100MHz
3V66MHz
PCI 33MHz
USB 48MHz
REF 14.318MHz
25ns 50ns
Power Down De-Assertion Mode
The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping
of the power supply until the time that stable clocks are output from the clock chip. If the I2C Bit 6 of Byte 0 is programmed
to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration.
17
ICS950810
0472F—01/12/04
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch
low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next
rising edge.
18
ICS950810
0472F—01/12/04
300 mil SSOP Package
INDEX
AREA
INDEX
AREA
1 2
N
D
h x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α0° 8° 0° 8°
MIN MAX MIN MAX
56 18.31 18.55 .720 .730
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Ordering Information
ICS950810yFLF-T
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y F LF- T
19
ICS950810
0472F—01/12/04
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil) (20 mil)
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
V
ARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
SYMBOL In Millimeters In Inches
COMMON DIM EN SIONS COMMON DIMENSIONS
SEE VARIATION S SEE VARIATIONS
8.10 BASIC 0.319 BASI C
0.50 BASIC 0.020 BASI C
SEE VARIATION S SEE VARIATIONS
ND mm . D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
Ordering Information
ICS950810yGLF-T
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y G LF- T