RT8279
1
DS8279-01 December 2011 www.richtek.com
Ordering Information
Pin Configurations
(TOP VIEW)
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Applications
zDistributive Power Systems
zBattery Charger
zDSL Modems
zPre-regulator for Linear Regulators
SOP-8 (Exposed Pad)
5A, 36V, 500kHz Step-Down Converter
General Description
The RT8279 is a step-down regulator with an internal power
MOSFET. It achieves 5A of continuous output current over
a wide input supply range with excellent load and line
regulation. Current mode operation provides fast transient
response and eases loop stabilization.
For protection, the RT8279 provides cycle-by-cycle current
limiting and thermal shutdown protection. An adjustable
soft-start reduces the stress on the input source at
startup. In shutdown mode, the regulator draws only 25μA
of supply current.
The RT8279 requires a minimum number of readily
available external components, providing a compact
solution. The RT8279 is available in the SOP-8 (Exposed
Pad) package.
SW
BOOT
NC
FB
NC
EN
VIN
GND
2
3
45
8
7
6
GND
9
Features
zz
zz
z5A Output Current
zz
zz
zInternal Soft-Start
zz
zz
z110mΩΩ
ΩΩ
Ω Internal Power MOSFET Switch
zz
zz
zInternal Compensation Minimizes External Parts
Count
zz
zz
zHigh Efficiency up to 90%
zz
zz
z25μμ
μμ
μA Shutdown Mode
zz
zz
zFixed 500kHz Frequency
zz
zz
zThermal Shutdown
zz
zz
zCycle-by-Cycle Over Current Protection
zz
zz
zWide 5.5V to 36V Operating Input Range
zz
zz
zAdjustable Output Voltage from 1.222V to 26V
zz
zz
zAvailable In an SOP8 (Exposed Pad) Package
zz
zz
zRoHS Compliant and Halogen Free
RT8279
GSPYMDNN
Marking Information
RT8279GSP : Product Number
YMDNN : Date Code
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
RT8279
Lead Plating System
G : Green (Halogen Free and Pb Free)
RT8279
2
DS8279-01 December 2011www.richtek.com
Functional Pin Description
Pin No. Pin Name Pin Function
1 BOOT
High Side Gate Drive Boost Input. BOOT supplies the drive for the high side
N-MOSFET switch. Connect a 10nF or greater capacitor from SW to BOOT to
power the high side switch.
2, 3 NC No Internal Connection.
4 FB Feedback Input. The feedback threshold is 1.222V.
5 EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN
higher than 1.4V to turn on the regulator, lower than 0.4V to turn it off. For
automatic startup, leave EN unconnected.
6,
9 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
7 VIN
Power Input. A suitable large capacitor should be bypassed from VIN to GND to
eliminate noise on the input to the IC.
8 SW
Power Switching Output. Note that a capacitor is required from SW to BOOT to
power the high side switch.
Typical Application Circuit
Table 1. Recommended Component Selection
VOUT (V) R1 (kΩ) R2 (kΩ) CFF (pF) L (μH) COUT (μF)
2.5 100 100 82 6.8 22 x 2
3.3 100 58.6 82 10 22 x 2
5 100 31.6 82 15 22 x 2
8 100 18 82 22 22 x 2
VIN
EN
GND
BOOT
FB
SW
5
4
7
8
1
L1
10nF
22µF x 2
R1
R2
VOUT
4.7µF/
50V x 2
Chip Enable
VIN
5.5V to 36V RT8279
D1
B550A
6, 9 (Exposed Pad)
CBOOT
COUT
CIN
Open = Automatic
Startup CFF
RT8279
3
DS8279-01 December 2011 www.richtek.com
Function Block Diagram
S
Q
R
Driver
Bootstrap
Control
-
+
Current Sense
Amplifier
PWM
Comparator
Oscillator
500kHz
Ramp
Generator
Regulator
Reference +
-
12k
Error
Amplifier
30pF
400k
13pF
SW
BOOT
FB
EN
VIN
GND
+
-
RT8279
4
DS8279-01 December 2011www.richtek.com
Absolute Maximum Ratings (Note 1)
zSupply Voltage, VIN ------------------------------------------------------------------------------------------ −0.3V to 40V
zSwitching Voltage, SW ------------------------------------------------------------------------------------- −0.3V to VIN + 0.3V
zBOOT Voltage ------------------------------------------------------------------------------------------------- (VSW − 0.3V) to (VSW + 6V)
zThe Other Pins ------------------------------------------------------------------------------------------------ −0.3V to 6V
zPower Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------- 1.333W
zPackage Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA --------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC -------------------------------------------------------------------------------- 15°C/W
zJunction Temperature ---------------------------------------------------------------------------------------- 150°C
zLead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
zStorage Temperature Range ------------------------------------------------------------------------------- −65°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) --------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
zSupply Voltage, VIN ------------------------------------------------------------------------------------------ 5.5V to 36V
zJunction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
zAmbient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
Reference Voltage VREF 5.5V ≤ VIN ≤ 36V 1.202 1.222 1.239 V
High Side Switch-On Resistance RDS(ON)1 -- 110 160 mΩ
Low Side Switch-On Resistance RDS(ON)2 -- 10 15 Ω
High Side Switch Leakage VEN = 0V, VSW = 0V -- -- 10 μA
Current Limit ILIM Duty = 90%, VBOOT−SW = 4.8V 6 7.5 9 A
Oscillator Frequency fOSC 425 500 575 kHz
Short Circuit Frequency VFB = 0V -- 150 -- kHz
Maximum Duty Cycle DMAX V
FB = 0.8V 85 90 95 %
Minimum On-Time tON -- 100 150 ns
Under Voltage Lockout Threshold
Rising 3.8 4.2 4.5 V
Under Voltage Lockout Threshold
Hysteresis -- 315 -- mV
Logic-High VIH EN_hys = 350mV 1.4 -- --
EN Threshold
Voltage Logic-Low VIL -- -- 0.4
V
Enable Pull Up Current -- 1 -- μA
Shutdown Current ISHDN V
EN = 0V -- 25 45 μA
Quiescent Current IQ V
EN = 2V, VFB = 1.5V -- 0.6 1 mA
Soft-Start Period CSS = 0.1μF 3 5 8.2 ms
Thermal Shutdown TSD -- 150 -- °C
(VIN = 12V, TA = 25°C unless otherwise specified)
RT8279
5
DS8279-01 December 2011 www.richtek.com
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
RT8279
6
DS8279-01 December 2011www.richtek.com
Typical Operating Characteristics
Frequency vs. Tem perature
440
450
460
470
480
490
500
510
520
530
540
-50 -25 0 25 50 75 100 125
Temperature (°C)
Frequency (kHz
)
VOUT = 5V
VIN = 12V
VIN = 24V
VIN = 36V
Frequency vs. Input Voltage
440
450
460
470
480
490
500
510
520
530
540
4 8 12 16 20 24 28 32 36
Input Voltage (V)
Frequency (kHz
)
VOUT = 5V, IOUT = 0A
Reference Voltage vs. Temperature
1.210
1.212
1.214
1.216
1.218
1.220
1.222
1.224
1.226
1.228
1.230
-50 -25 0 25 50 75 100 125
Temperature (°C)
Reference Voltage (V)
IOUT = 0A
VIN = 12V
VIN = 24V
VIN = 36V
Output Voltage vs. Output Current
4.960
4.964
4.968
4.972
4.976
4.980
4.984
4.988
4.992
4.996
5.000
5.004
5.008
012345
Output Current (A)
Output Voltage (V)
VOUT = 5V
VIN = 36V
VIN = 24V
VIN = 12V
Reference Voltage vs. Input Voltage
1.210
1.214
1.218
1.222
1.226
1.230
4 8 12 16 20 24 28 32 36
Input Voltage (V)
Reference Voltage (V)
VOUT = 5V, IOUT = 0A
Efficiency vs. Output Current
0
10
20
30
40
50
60
70
80
90
100
012345
Output Current (A)
Efficiency (%)
VOUT = 5V
VIN = 12V
VIN = 32V
VIN = 36V
RT8279
7
DS8279-01 December 2011 www.richtek.com
Current Limit vs . Te m pe rature
5
6
7
8
9
10
11
12
-50 -25 0 25 50 75 100 125
Temperature (°C)
Current Limit (A)
VIN = 12V
Shutdown Current vs. Input Voltage
0
10
20
30
40
50
60
4 8 12 16 20 24 28 32 36
Input Voltage (V)
Shutdown Current (μA
)
VEN = 0V
Quiescent Current vs. Temperature
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-50 -25 0 25 50 75 100 125
Temperature (°C)
Quiescent Current (mA)
VIN = 36V
VIN = 24V
VIN = 12V
Load Transient Response
Time (100μs/Div)
VOUT
(200mV/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 5V, IOUT = 0.2A to 5A
Load Transient Response
Time (100μs/Div)
VOUT
(200mV/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 5V, IOUT = 2.5A to 5A
Switching
Time (1μs/Div)
VOUT
(10mV/Div)
IL
(5A/Div)
VIN = 12V, VOUT = 5V, IOUT = 5A
VSW
(10V/Div)
RT8279
8
DS8279-01 December 2011www.richtek.com
Power Off from EN
Time (2.5ms/Div)
VEN
(5V/Div)
IL
(5A/Div)
VIN = 12V, VOUT = 5V, IOUT = 5A
VOUT
(5V/Div)
Power On from EN
Time (2.5ms/Div)
VEN
(5V/Div)
IL
(5A/Div)
VIN = 12V, VOUT = 5V, IOUT = 5A
VOUT
(5V/Div)
RT8279
9
DS8279-01 December 2011 www.richtek.com
Application Information
The RT8279 is an asynchronous high voltage buck
converter that can support the input voltage range from
5.5V to 32V and the output current can be up to 5A.
Output Voltage Setting
The resistive divider allows the FB pin to sense the output
voltage as shown in Figure 1.
Figure 1. Output Voltage Setting
The output voltage is set by an external resistive divider
according to the following equation :
OUT REF R1
V = V 1
R2
⎛⎞
+
⎜⎟
⎝⎠
Where VREF is the reference voltage (1.222V typ.).
Where R1 = 100kΩ.
External Bootstrap Diode
Connect a 10nF low ESR ceramic capacitor between the
BOOT pin and SW pin. This capacitor provides the gate
driver voltage for the high side MOSFET.
It is recommended to add an external bootstrap diode
between an external 5V and BOOT pin for efficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65% .The bootstrap diode can be a
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the
RT8279.
Figure 2. External Bootstrap Diode
Soft-Start
The RT8279 contains an internal soft-start clamp that
gradually raises the output voltage. The typical soft-start
time is 5ms.
Chip Enable Operation
The EN pin is the chip enable input. Pull the EN pin low
(<0.4V) will shutdown the device. During shutdown mode,
the RT8279 quiescent current drops to lower than 25μA.
Drive the EN pin to high (>1.4V, <5.5V) will turn on the
device again. If the EN pin is open, it will be pulled to high
by internal circuit. For external timing control (e.g.RC),the
EN pin can also be externally pulled to High by adding a
100kΩ or greater resistor from the VIN pin (see Figure 3).
Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
OUT OUT
LIN
VV
I = 1
fL V
⎡⎤⎡ ⎤
Δ×−
⎢⎥⎢ ⎥
×
⎣⎦⎣ ⎦
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
highest efficiency operation. However, it requires a large
inductor to achieve this goal.
For the ripple current selection, the value of ΔIL = 0.2(IMAX)
will be a reasonable starting point. The largest ripple
current occurs at the highest VIN. To guarantee that the
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
OUT OUT
L(MAX) IN(MAX)
VV
L = 1
fI V
⎡⎤⎡ ⎤
×−
⎢⎥⎢ ⎥
×Δ
⎣⎦⎣ ⎦
The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
see Table 2 for the inductor selection reference.
RT8279
GND
FB
R1
R2
VOUT
SW
BOOT
5V
RT8279 10nF
RT8279
10
DS8279-01 December 2011www.richtek.com
Checking Tra n sient Re spon se
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR) also begins to charge or discharge
COUT generating a feedback error signal for the regulator
to return VOUT to its steady-state value. During this
OUT IN
RMS OUT(MAX) IN OUT
VV
I = I 1
VV
−
OUT L OUT
1
VIESR
8fC
⎡⎤
Δ≤Δ +
⎢⎥
⎣⎦
The output ripple will be highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Dry tantalum,
special polymer, aluminum electrolytic and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors offer very low ESR value.
However, it provides lower capacitance density than other
types. Although Tantalum capacitors have the highest
capacitance density, it is important to only use types that
pass the surge test for use in switching power supplies.
Aluminum electrolytic capacitors have significantly higher
ESR. However, it can be used in cost-sensitive applications
for ripple current rating and long term reliability
considerations. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant
ringing.
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
Diode Selection
When the power switch turns off, the path for the current
is through the diode connected between the switch output
and ground. This forward biased diode must have a
minimum voltage drop and recovery times. Schottky diode
is recommended and it should be able to handle those
current. The reverse voltage rating of the diode should be
greater than the maximum input voltage, and current rating
should be greater than the maximum load current. For
more detail please refer to Table 4.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
Table 2. Suggested Inductors for Typical
Application Circuit
Component
Supplier Series Dimensions
(mm)
TAIYO
YUDEN NR10050 10 x 9.8 x 5
TDK SLF12565 12.5 x 12.5 x 6.5
The output ripple, ΔVOUT , is determined by :
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the input capacitor, two 4.7μF low ESR ceramic
capacitors are recommended. For the recommended
capacitor, please refer to table 3 for more detail.
The selection of COUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response as described in a later section.
RT8279
11
DS8279-01 December 2011 www.richtek.com
Figure 3. Reference Circuit with Snubber and Enable Timing Control
recovery time, VOUT can be monitored for overshoot or
ringing that would indicate a stability problem.
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on SW pin when
high side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One is to place an R-C
snubber between SW and GND and make them as close
as possible to the SW pin (see Figure 3). Another method
is to add a resistor in series with the bootstrap
capacitor, CBOOT. But this method will decrease the driving
capability to the high side MOSFET. It is strongly
recommended to reserve the R-C snubber during PCB
layout for EMI improvement. Moreover, reducing the SW
trace area and keeping the main power in a small loop will
be helpful on EMI performance. For detailed PCB layout
guide, please refer to the section of Layout Consideration.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature. The maximum power
dissipation depends on the thermal resistance of IC
package, PCB layout, the rate of surroundings airflow and
temperature difference between junction to ambient. The
maximum power dissipation can be calculated by following
formula :
PD(MAX) = (TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8279, the maximum junction temperature is 125°C. The
junction to ambient thermal resistance θJA is layout
dependent. For PSOP-8 package, the thermal resistance
θJA is 75°C/W on the standard JEDEC 51-7 four-layers
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W (70mm2
copper area PCB layout)
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θJA can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
As shown in Figure 4, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 4a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 4.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 4.e)
reduces the θJA to 49°C/W.
VIN
EN
GND
BOOT
FB
SW
5
4
7
8
1
L
10µH
10nF
R1
10k
R2
3.16k
VOUT
5V/5A
4.7µF x 2
VIN
5.5V to 32V RT8279
D
B550C
6, 9 (Exposed Pad)
CBOOT
COUT
CIN
RBOOT*
RS*
CS*
REN*
CEN*
* : Optional
47µFx2
(POSCAP)
RT8279
12
DS8279-01 December 2011www.richtek.com
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT8279.
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` SW node is with high frequency voltage swing and should
be kept at small area. Keep analog components away
from the SW node to prevent stray capacitive noise pick-
up.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT8279.
` Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
` An example of PCB layout guide is shown in Figure 6 for
reference.
(a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W
(b) Copper Area = 10mm2, θJA = 64°C/W
(c) Copper Area = 30mm2 , θJA = 54°C/W
(d) Copper Area = 50mm2 , θJA = 51°C/W
(e) Copper Area = 70mm2 , θJA = 49°C/W
Figure 4. Thermal Resistance vs. Copper Area Layout
Design
Figure 5. Derating Curves for RT8279 Package
The maximum power dissipation depends on operating
ambient temperature for fixed TJ (MAX) and thermal
resistance θJA. For the RT8279, the Figure 5 of derating
curves allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation
allowed.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
0 25 50 75 100 125
Ambient Temperature (°C)
Power Dissipation (W)
Copper Area
70mm2
50mm2
30mm2
10mm2
Min.Layout
Four Layer PCB
RT8279
13
DS8279-01 December 2011 www.richtek.com
Figure 6. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT
Componen t S upplier Series VRRM (V) IOUT (A) Package
DIODES B550C 50 5 SMC
PANJIT SK55 50 5 SMC
Table 4. Suggested Diode
Location Component Supplier Part No. Capacitance (μF) Case Size
CIN MURATA GRM32ER71H475K 4.7 1206
CIN TAIYO YUDEN UMK325BJ475MM-T 4.7 1206
COUT MURATA GRM31CR60J476M 47 1206
COUT TDK C3225X5R0J476M 47 1210
COUT MURATA GRM32ER71C226M 22 1210
COUT TDK C3225X5R1C22M 22 1210
BOOT
NC
NC
FB
SW
VIN
EN
GND
GND
2
3
45
6
7
8
9CIN
VOUT
GND
VOUT R1
R2
SW
CBOOT
D1
The feedback components
should be connected as close
to the device as possible.
SW should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.
L1
COUT
CIN
COUT
Input capacitor should be
placed as close to the IC
as possible.
RT8279
14
DS8279-01 December 2011www.richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Outline Dimension
A
B
J
F
H
M
C
D
I
Y
X
EXPOSED THERMAL PAD
(Bottom of Package)
8-Lead SOP (Exposed Pad) Plastic Package
Dimensions In Millimeters Dimensions In Inches
Symbol Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1 Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2 Y 3.000 3.500 0.118 0.138
