August 2009 Rev 6 1/87
1
M58BW16F
M58BW32F
16 or 32 Mbit (x 32, boot block, burst)
3.3 V supply Flash memories
Features
Supply voltage
–V
DD = 2.7 V to 3.6 V (45 ns) or
VDD = 2.5 V to 3.3 V (55 ns)
–V
DDQ = VDDQIN = 2.4 V to 3.6 V for I/O
buffers
High performance
– Access times: 45 and 55 ns
– Synchronous burst reads
– 75 MHz effective zero wait-state burst read
– Asynchronous page reads
M58BW32F memory organization:
– Eight 64 Kbit small parameter blocks
– Four 128 Kbit large parameter blocks
– Sixty-two 512 Kbit main blocks
M58BW16F memory organization:
– Eight 64 Kbit parameter blocks
– Thirty-one 512 Kbit main blocks
Hardware block protection
–WP
pin to protect any block combination
from Program and Erase operations
– PEN signal for Program/Erase Enable
Irreversible modify protection (OTP like) on
128 Kbits:
– Block 1 (bottom device) or block 72 (top
device) in the M58BW32F
– Blocks 2 and 3 (bottom device) or blocks
36 and 35 (top device) in the M58BW16F
Security
– 64-bit unique device identifier (UID)
Fast programming
– Write to buffer and program capability
Optimized for FDI drivers
– Common Flash interface (CFI)
– Fast Program/Erase Suspend feature in
each block
Low power consumption
– 100 μA typical Standby current
Electronic signature
– Manufacturer code: 0020h
– Top device codes:
M58BW32FT: 8838h
M58BW16FT: 883Ah
– Bottom device codes:
M58BW32FB: 8837h
M58BW16FB: 8839h
Automotive device grade 3:
– Temperature: –40 to 125 °C
– Automotive grade certified
LBGA
LBGA80 (ZA)
10 x 8 ball array
PQFP80 (T)
www.numonyx.com
Contents M58 BW16F , M58BW32F
2/87
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Data inputs/outputs (DQ0-DQ31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Output Disable (GD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7 Reset/Power-down (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.8 Program/Erase Enable (PEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.10 Burst Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.11 Burst Address Advance (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.12 Valid Data Ready (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.13 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.14 Supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.15 Output supply voltage (VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.16 Input supply voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.17 Ground (VSS and VSSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.18 Don’t use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.19 Not connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Asynchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.1 Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1.2 Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . 24
3.1.3 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.4 Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.5 Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . 25
3.1.6 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M58BW16F, M58BW32F Contents
3/87
3.1.7 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.8 Reset/Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 Synchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.1 Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.2 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.1 Read Select bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.2 Standby Disable bit (M14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.3 X-Latency bits (M13-M11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.4 Y-Latency bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.5 Valid Data Ready bit (M8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.6 Wrap Burst bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.7 Burst Length bit (M2-M0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.7 Erase All Main Blocks command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.8 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.9 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.12 Set Burst Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . 38
4.13 Set Block Protection Configuration Register command . . . . . . . . . . . . . . 38
4.14 Clear Block Protection Configuration Register command . . . . . . . . . . . . 38
5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1 Program/Erase Controller Status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 Erase Suspend Status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3 Erase Status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4 Program/Write to Buffer and Program Status (bit 4) . . . . . . . . . . . . . . . . . 42
Contents M58 BW16F , M58BW32F
4/87
5.5 PEN Status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.6 Program Suspend Status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.7 Block Protection Status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.8 Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 Ma ximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Appendix A Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Ap pe n d ix B Co mm o n F la s h inte r f ace (CFI ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8
Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
M58BW16F, M58BW32F List of tables
5/87
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. M58BW32F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. M58BW32F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. M58BW16F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. M58BW16F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Asynchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Synchronous Burst Read Bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Burst Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. Program, Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15. Data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 16. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 17. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 18. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 19. Asynchronous Bus Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 20. Asynchronous Page Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 21. Asynchronous Write and Latch controlled Write AC characteristics. . . . . . . . . . . . . . . . . . 54
Table 22. Synchronous Burst Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 23. Power supply AC and DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 24. Reset, Power-down and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 25. LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 26. PQFP80 - 80 lead plastic quad flat pack, package mechanical data . . . . . . . . . . . . . . . . . 66
Table 27. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 28. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 29. CFI - Query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 30. CFI - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 31. M58BW16F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 32. M58BW16F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 33. M58BW32F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 34. M58BW32F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 35. Protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 36. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
List o f figures M58 BW16F , M58BW32F
6/87
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. LBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. PQFP connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Example burst configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5. AC measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 6. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Asynchronous Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 8. Asynchronous Latch Controlled Bus Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9. Asynchronous Chip Enable Controlled Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . 49
Figure 10. Asynchronous Address Controlled Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . 49
Figure 11. Asynchronous Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 12. Asynchronous Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 13. Asynchronous Latch controlled Write AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from ’n’ clock rising edge). 55
Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from ’n’ clock rising edge) . 56
Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid
from ’n’ clock rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 17. Synchronous Burst Read (data valid from ’n’ clock rising edge). . . . . . . . . . . . . . . . . . . . . 58
Figure 18. Synchronous Burst Read - valid data ready output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 19. Synchronous Burst Read - Burst Address Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 20. Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 21. Power supply slope specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 22. Reset, Power-down and Power-up AC waveforms - Control pins Low. . . . . . . . . . . . . . . . 62
Figure 23. Reset, Power-down and Power-up AC waveforms - Control pins toggling. . . . . . . . . . . . . 62
Figure 24. LBGA80 10 × 12 mm - 8 × 10 ball array, 1 mm pitch, bottom view package outline . . . . . 64
Figure 25. PQFP80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 26. Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 27. Program Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 28. Block Erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 29. Erase Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 30. Power-up sequence followed by Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 31. Command interface and Program/Erase controller flowchart (a) . . . . . . . . . . . . . . . . . . . . 73
Figure 32. Command interface and Program/Erase controller flowchart (b) . . . . . . . . . . . . . . . . . . . . 74
Figure 33. Command interface and Program/Erase controller flowchart (c) . . . . . . . . . . . . . . . . . . . . 75
Figure 34. Command interface and Program/Erase controller flowchart (d) . . . . . . . . . . . . . . . . . . . . 76
Figure 35. Command interface and Program/Erase controller flowchart (e) . . . . . . . . . . . . . . . . . . . . 77
M58BW16F, M58BW32F Description
7/87
1 Description
The M58BW16F and M58BW32F are 16 and 32 Mbit non-volatile Flash memories,
respectively. They can be erased electrically at block level and programmed in-system on a
double-word basis using a 2.7 V to 3.6 V or 2.5 V to 3.3 V VDD supply for the circuit and a
2.4 V to 3.6 V VDDQ supply voltage for the input and output buffers.
In the rest of the document the M58BW16F and M58BW32F will be referred to as
M58BWxxF unless otherwise specified.
The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous
Bus operations. The Synchronous Burst Read interface allows a high data transfer rate
controlled by the Burst Clock signal, K. It is capable of bursting fixed or unlimited lengths of
data. The burst type, latency and length are configurable and can be easily adapted to a
large variety of system clock frequencies and microprocessors. All write operations are
asynchronous. On power-up the memory defaults to Read mode with an Asynchronous
Bus.
The device features an asymmetrical block architecture:
The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large
parameter blocks of 128 Kbits each and 8 small parameter blocks of 64 Kbits each.
The large and small parameter blocks are located either at the top (M58BW32FT) or at
the bottom (M58BW32FB) of the address space. The first large parameter block is
referred to as boot block and can be used either to store a boot code or parameters.
The memory array organization is detailed in Table 2: M58BW32F top boot block
addresses and Table 3: M58BW32F bottom boot block addresses.
The M58BW16F has an array of 8 parameter blocks of 64 Kbits each and 31 main
blocks of 512 Kbits each. In the M58BW16FT the parameter blocks are located at the
top of the address space whereas in the M58BW16FB, they are located at the bottom.
The memory array organization is detailed in Table 4: M58BW16F top boot block
addresses and Table 5: M58BW16F bottom boot block addresses.
Program and Erase commands are written to the command interface of the memory. An on-
chip Program/Erase controller simplifies the process of programming or erasing the memory
by taking care of all of the special operations that are required to update the memory
contents. The end of a Program or Erase operation can be detected and any error
conditions identified in the Status Register. The command set required to control the
memory is consistent with JEDEC standards.
Erase can be suspended in order to perform either Read or Program in any other block, and
then resumed. Program can be suspended to Read data in any other block, and then
resumed. Each block can be programmed and erased over 100,000 cycles.
Description M58 BW16F , M58BW32F
8/87
All blocks are protected during power-up. The M58BWxxF features five different levels of
hardware and software block protection to avoid unwanted Program/Erase operations:
Write/Protect Enable input, WP
, hardware protects a combination of blocks from
Program and Erase operations. The blocks to be protected are configured individually
by issuing a Set Block Protection Configuration Register or a Clear Block Protection
Configuration Register command.
All Program or Erase operations are blocked when Reset, RP, is held Low.
A Program/Erase Enable input, PEN, is used to protect all blocks, preventing Program
and Erase operations from affecting their data.
A permanent user-enabled protection against Modify operations is available:
– on one specific 128-Kbit parameter block in the M58BW32F – block 1 for bottom
devices or block 72 for top devices
– on two specific 64-Kbit parameter blocks in the M58BW16F – blocks 2 and 3 for
bottom devices or blocks 36 and 35 for top devices.
A Reset/Power-down mode is entered when the RP input is Low. In this mode the power
consumption is reduced to the standby level, the device is write protected and both the
Status and Burst Configuration Registers are cleared. A recovery time is required when the
RP input goes High.
A manufacturer code and a device code are available. They can be read from the memory
allowing programming equipment or applications to automatically match their interface to
the characteristics of the memory.
Finally, the M58BWxxF features a 64-bit unique device identifier (UID) which is programmed
by Numonyx on the production line. It is unique for each die and can be used to implement
cryptographic algorithms to improve security. Information is available in the CFI area (see
Table 32: M58BW16F extended query information).
The memory is offered in PQFP80 (14 x 20 mm) and LBGA80 (1.0 mm pitch) packages and
it is supplied with all the bits erased (set to ’1’).
M58BW16F, M58BW32F Description
9/87
Figure 1. Logi c diagra m
AI13224b
A0-Amax(1)
L
DQ0-DQ31
VDD
E
VSS
RP
G
GD
VDDQ
W
WP
R
K
B
VSSQ
VDDQIN
M58BW16F
M58BW32F
PEN
Description M58 BW16F , M58BW32F
10/87
Table 1. Signal names
Signal name Function Direction
A0-Amax(1) Address inputs Inputs
DQ0-DQ7 Data input/output, command input I/O
DQ8-DQ15 Data input/output, Burst Configuration Register I/O
DQ16-DQ31 Data input/output I/O
BBurst Address Advance input Input
EChip Enable input Input
GOutput Enable input Input
K Burst Clock input Input
LLatch Enable input Input
R Valid Data Ready output Output
RP Reset/Power-down input Input
WWrite Enable input Input
GD Output Disable input Input
WP Write Protect input Input
VDD Supply voltage
VDDQ Power supply for output buffers
VDDQIN Power supply for input buffers only
PEN Program/Erase Enable Input
VSS Ground
VSSQ Input/output ground
NC Not connected internally
DU Don’t use as internally connected
1. Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F.
M58BW16F, M58BW32F Description
11/87
Figure 2. LBG A connections (top view through packa ge)
1. Ball D3 is NC in the M58BW16F and A19 in the M58BW32F.
AI12854b
B
DQ24DQ7VSSQ
F
VDDQ
DQ26DQ4VDDQ
E
DQ29
VSS
DQ0DQ3D
A0
NCA7A11A18A17C
A1
A4A5A8
RP
E
A13A16B
A2
A3A6
VDD
PENVDD
A14A
87654321
DQ20DQ18DQ19DQ17DQ11DQ12DQ13
VDDQ
DQ23DQ8VDDQ
H
G
NC
GDW
VDDQIN
DQ16RGLDQ14DQ15
K
J
A15 VSS
A12 A9
A10 NC
A19/
NC(1) NC DQ31 DQ30
DQ2 DQ28
DQ6 DQ25 VSSQ
DQ10 DQ9 DQ21
WP
K
NC
DQ1 DQ27
DQ5 NC
DQ22
Description M58 BW16F , M58BW32F
12/87
Figure 3. PQFP conne ction s (top view through package)
AI13225b
12
1
73
M58BW16F
M58BW32F 53
VDDQ
DQ24
DQ25
DQ18
DQ17
DQ16
DQ19
DQ20
DQ21
DQ22
DQ23
VDDQ
DQ29
DQ26
DQ30
DU
DQ31
DQ28
DQ27
A2
A5
A3
A4
A0
A1
A11
VSS
A12
A13
A14
A10
GD
WP
W
DU
G
VSS
E
K
L
NC
B
RP
VDDQ
DQ7
DQ6
DQ13
DQ14
DQ15
DQ12
DQ11
DQ10
DQ9
VSSQ
DQ8
DQ2
DQ5
DQ0
A19/NC(1
)
A18
A16
A17
DQ3
DQ4
VSSQ
VSSQ
A8
A6
A7
PEN
VDD
A9
A15
DQ1
VDDQ
VSSQ
R
VDD
NC
VDDQIN
24
25
32
40
41
64
65
80
M58BW16F, M58BW32F Description
13/87
1.1 Block protection
The M58BWxxF features four different levels of block protection.
Write Pr otect pin, WP, - When WP is Low, VIL, the protection status that has been
configured in the Block Protection Configuration Register is activated. The Block
Protection Configuration Register is volatile. Any combination of blocks is possible. Any
attempt to program or erase a protected block will return an error in the Status Register
(see Table 13: Status Register bits).
Reset/P ower-down pin, RP, - If the device is held in reset mode (RP at VIL), no
Program or Erase operation can be performed on any block.
Program/ E rase Enable , PEN , - The Program/Erase Enable input, PEN, protects all
blocks by preventing Program and Erase operations from modifying the data.
Prior to issuing a Program or Erase command, the Program/Erase Enable must be set
to High (VIH). If it is Low (VIL), the Program or Erase operation is not accepted and an
error is generated in the Status Register.
Permanent protection against modify operations - specific OTP-like blocks can be
permanently protected against modify operations (Program/Erase):
– in the M58BW32F, a unique 128-Kbit parameter block – block 1 (01000h-01FFFh)
for bottom devices or block 72 (FE000h-FEFFFh) for top devices
– in the M58BW16F, two 64-Kbit parameter blocks – blocks 2 and 3 (01000h-
01FFFh) for bottom devices or blocks 36 and 35 (7E000h-7EFFFh) for top devices
This protection is user-enabled. Details of how this protection is activated are provided
in a dedicated application note.
After a device reset the first two kinds of block protection (WP, RP) can be combined to give
a flexible block protection. All blocks are protected at power-up.
Description M58 BW16F , M58BW32F
14/87
Table 2. M58BW 32F top boot block addre ss es
# Size (Kbit) Address range(1)
73 128 FF000h-FFFFFh
72 128 FE000h-FEFFFh(2)
71 128 FD000h-FDFFFh
70 128 FC000h-FCFFFh
69 64 FB800h-FBFFFh
68 64 FB000h-FB7FFh
67 64 FA800h-FAFFFh
66 64 FA000h-FA7FFh
65 64 F9800h-F9FFFh
64 64 F9000h-F97FFh
63 64 F8800h-F8FFFh
62 64 F8000h-F87FFh
61 512 F4000h-F7FFFh
60 512 F0000h-F3FFFh
59 512 EC000h-EFFFFh
58 512 E8000h-EBFFFh
57 512 E4000h-E7FFFh
56 512 E0000h-E3FFFh
55 512 DC000h-DFFFFh
54 512 D8000h-DBFFFh
53 512 D4000h-D7FFFh
52 512 D0000h-D3FFFh
51 512 CC000h-CFFFFh
50 512 C8000h-CBFFFh
49 512 C4000h-C7FFFh
48 512 C0000h-C3FFFh
47 512 BC000h-BFFFFh
46 512 B8000h-BBFFFh
45 512 B4000h-B7FFFh
44 512 B0000h-B3FFFh
43 512 AC000h-AFFFFh
42 512 A8000h-ABFFFh
41 512 A4000h-A7FFFh
40 512 A0000h-A3FFFh
39 512 9C000h-9FFFFh
38 512 98000h-9BFFFh
37 512 94000h-97FFFh
36 512 90000h-93FFFh
M58BW16F, M58BW32F Description
15/87
35 512 8C000h-8FFFFh
34 512 88000h-8BFFFh
33 512 84000h-87FFFh
32 512 80000h-83FFFh
31 512 7C000h-7FFFFh
30 512 78000h-7BFFFh
29 512 74000h-77FFFh
28 512 70000h-73FFFh
27 512 6C000h-6FFFFh
26 512 68000h-6BFFFh
25 512 64000h-67FFFh
24 512 60000h-63FFFh
23 512 5C000h-5FFFFh
22 512 58000h-5BFFFh
21 512 54000h-57FFFh
20 512 50000h-53FFFh
19 512 4C000h-4FFFFh
18 512 48000h-4BFFFh
17 512 44000h-47FFFh
16 512 40000h-43FFFh
15 512 3C000h-3FFFFh
14 512 38000h-3BFFFh
13 512 34000h-37FFFh
12 512 30000h-33FFFh
11 512 2C000h-2FFFFh
10 512 28000h-2BFFFh
9 512 24000h-27FFFh
8 512 20000h-23FFFh
7 512 1C000h-1FFFFh
6 512 18000h-1BFFFh
5 512 14000h-17FFFh
4 512 10000h-13FFFh
3 512 0C000h-0FFFFh
2 512 08000h-0BFFFh
1 512 04000h-07FFFh
0 512 00000h-03FFFh
1. Addresses are indicated in 32-bit addressing.
2. OTP block.
Table 2. M58BW 32F top boot block addre ss es (cont inued)
# Size (Kbit) Address range(1)
Description M58 BW16F , M58BW32F
16/87
Table 3. M58BW32F bottom boot block addresses
# Size (Kbit) Address range(1)
73 512 FC000h-FFFFFh
72 512 F8000h-FBFFFh
71 512 F4000h-F7FFFh
70 512 F0000h-F3FFFh
69 512 EC000h-EFFFFh
68 512 E8000h-EBFFFh
67 512 E4000h-E7FFFh
66 512 E0000h-E3FFFh
65 512 DC000h-DFFFFh
64 512 D8000h-DBFFFh
63 512 D4000h-D7FFFh
62 512 D0000h-D3FFFh
61 512 CC000h-CFFFFh
60 512 C8000h-CBFFFh
59 512 C4000h-C7FFFh
58 512 C0000h-C3FFFh
57 512 BC000h-BFFFFh
56 512 B8000h-BBFFFh
55 512 B4000h-B7FFFh
54 512 B0000h-B3FFFh
53 512 AC000h-AFFFFh
52 512 A8000h-ABFFFh
51 512 A4000h-A7FFFh
50 512 A0000h-A3FFFh
49 512 9C000h-9FFFFh
48 512 98000h-9BFFFh
47 512 94000h-97FFFh
46 512 90000h-93FFFh
45 512 8C000h-8FFFFh
44 512 88000h-8BFFFh
43 512 84000h-87FFFh
42 512 80000h-83FFFh
41 512 7C000h-7FFFFh
40 512 78000h-7BFFFh
39 512 74000h-77FFFh
38 512 70000h-73FFFh
37 512 6C000h-6FFFFh
36 512 68000h-6BFFFh
M58BW16F, M58BW32F Description
17/87
35 512 64000h-67FFFh
34 512 60000h-63FFFh
33 512 5C000h-5FFFFh
32 512 58000h-5BFFFh
31 512 54000h-57FFFh
30 512 50000h-53FFFh
29 512 4C000h-4FFFFh
28 512 48000h-4BFFFh
27 512 44000h-47FFFh
26 512 40000h-43FFFh
25 512 3C000h-3FFFFh
24 512 38000h-3BFFFh
23 512 34000h-37FFFh
22 512 30000h-33FFFh
21 512 2C000h-2FFFFh
20 512 28000h-2BFFFh
19 512 24000h-27FFFh
18 512 20000h-23FFFh
17 512 1C000h-1FFFFh
16 512 18000h-1BFFFh
15 512 14000h-17FFFh
14 512 10000h-13FFFh
13 512 0C000h-0FFFFh
12 512 08000h-0BFFFh
11 64 07800h-07FFFh
10 64 07000h-077FFh
9 64 06800h-06FFFh
8 64 06000h-067FFh
7 64 05800h-05FFFh
6 64 05000h-057FFh
5 64 04800h-04FFFh
4 64 04000h-047FFh
3 128 03000h-03FFFh
2 128 02000h-02FFFh
1 128 01000h-01FFFh(2)
0 128 00000h-00FFFh
1. Addresses are indicated in 32-bit word addressing.
2. OTP block.
Table 3. M58BW32F bottom boot block addresses (continued)
# Size (Kbit) Address range(1)
Description M58 BW16F , M58BW32F
18/87
Table 4. M58BW16F top boot block addre sses
# Size (Kbit ) Address range
38 64 7F800h-7FFFFh
37 64 7F000h-7F7FFh
36(1)
1. OTP block.
64 7E800h-7EFFFh
35(1) 64 7E000h-7E7FFh
34 64 7D800h-7DFFFh
33 64 7D000h-7D7FFh
32 64 7C800h-7CFFFh
31 64 7C000h-7C7FFh
30 512 78000h-7BFFFh
29 512 74000h-77FFFh
28 512 70000h-73FFFh
27 512 6C000h-6FFFFh
26 512 68000h-6BFFFh
25 512 64000h-67FFFh
24 512 60000h-63FFFh
23 512 5C000h-5FFFFh
22 512 58000h-5BFFFh
21 512 54000h-57FFFh
20 512 50000h-53FFFh
19 512 4C000h-4FFFFh
18 512 48000h-4BFFFh
17 512 44000h-47FFFh
16 512 40000h-43FFFh
15 512 3C000h-3FFFFh
14 512 38000h-3BFFFh
13 512 34000h-37FFFh
12 512 30000h-33FFFh
11 512 2C000h-2FFFFh
10 512 28000h-2BFFFh
9 512 24000h-27FFFh
8 512 20000h-23FFFh
7 512 1C000h-1FFFFh
6 512 18000h-1BFFFh
5 512 14000h-17FFFh
4 512 10000h-13FFFh
3 512 0C000h-0FFFFh
2 512 08000h-0BFFFh
1 512 04000h-07FFFh
0 512 00000h-03FFFh
M58BW16F, M58BW32F Description
19/87
Table 5. M58BW16F bottom boot block addresses
# Size (Kbit) Address range
38 512 7C000h-7FFFFh
37 512 78000h-7BFFFh
36 512 74000h-77FFFh
35 512 70000h-73FFFh
34 512 6C000h-6FFFFh
33 512 68000h-6BFFFh
32 512 64000h-67FFFh
31 512 60000h-63FFFh
30 512 5C000h-5FFFFh
29 512 58000h-5BFFFh
28 512 54000h-57FFFh
27 512 50000h-53FFFh
26 512 4C000h-4FFFFh
25 512 48000h-4BFFFh
24 512 44000h-47FFFh
23 512 40000h-43FFFh
22 512 3C000h-3FFFFh
21 512 38000h-3BFFFh
20 512 34000h-37FFFh
19 512 30000h-33FFFh
18 512 2C000h-2FFFFh
17 512 28000h-2BFFFh
16 512 24000h-27FFFh
15 512 20000h-23FFFh
14 512 1C000h-1FFFFh
13 512 18000h-1BFFFh
12 512 14000h-17FFFh
11 512 10000h-13FFFh
10 512 0C000h-0FFFFh
9 512 08000h-0BFFFh
8 512 04000h-07FFFh
7 64 03800h-03FFFh
6 64 03000h-037FFh
5 64 02800h-02FFFh
4 64 02000h-027FFh
3(1)
1. OTP block.
64 01800h-01FFFh
2(1) 64 01000h-017FFh
1 64 00800h-00FFFh
0 64 00000h-007FFh
Signal descriptions M58BW16F, M58BW32F
20/87
2 Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1 Address inputs (A0-Amax)
Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F.
The Address inputs are used to select the cells to access in the memory array during Bus
operations. During Bus Write operations they control the commands sent to the command
interface of the Program/Erase controller. Chip Enable must be Low when selecting the
addresses.
The Address inputs are latched on the rising edge of Latch Enable L or Burst Clock K,
whichever occurs first, in a Read operation. The Address inputs are latched on the rising
edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write
operation. The address latch is transparent when Latch Enable is Low, VIL. The address is
internally latched in an Erase or Program operation.
2.2 Dat a inputs/outputs (DQ0-DQ31)
The Data inputs/outputs output the data stored at the selected address during a Bus Read
operation, or are used to input the data during a program operation. During Bus Write
operations they represent the commands sent to the command interface of the
Program/Erase controller. When used to input data or Write commands they are latched on
the rising edge of Write Enable or Chip Enable, whichever occurs first.
When Chip Enable and Output Enable are both Low, VIL, and Output Disable is at VIH, the
data bus outputs data from the memory array, the Electronic Signature, the Block Protection
Configuration Register, the CFI information or the contents of Burst Configuration Register
or Status Register. The data bus is high impedance when the device is deselected with Chip
Enable at VIH, Output Enable at VIH, Output Disable at VIL or Reset/Power-down at VIL. The
Status Register content is output on DQ0-DQ7 and DQ8-DQ31 are at VIL.
2.3 Chip Enable (E)
The Chip Enable, E, input activates the memory control logic, input buffers, decoders and
sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power
consumption to the standby level.
2.4 Output Enable (G)
The Output Enable, G, gates the outputs through the data output buffers during a Read
operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs
are high impedance independently of Output Disable.
M58BW16F, M58BW32F Signal descriptions
21/87
2.5 Output Disable (GD)
The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is
at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the
outputs are high impedance independently of Output Enable. The Output Disable pin must
be connected to an external pull-up resistor as there is no internal pull-up resistor to drive
the pin.
2.6 Write Enable (W)
The Write Enable, W, input controls writing to the command interface, input address and
data latches. Both addresses and data can be latched on the rising edge of Write Enable
(also see Latch Enable, L).
2.7 Reset/Power-down (RP)
The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware
reset is achieved by holding Reset/Power-down Low, VIL, for at least tPLPH. Writing is
inhibited to protect data, the command interface and the Program/Erase controller are reset.
The Status Register information is cleared and power consumption is reduced to the
standby level (IDD1). The device acts as deselected, that is the data outputs are high
impedance.
After Reset/Power-down goes High, VIH, the memory will be ready for Bus Read operations
after a delay of tPHEL or Bus Write operations after tPHWL.
If Reset/Power-down goes Low, VIL, during a Block Erase or a Program operation, the
internal state machine handles the operation as a Program/Erase Suspend, so the
maximum time defined inTable 12: Program, Erase times and endurance cycles must be
applied.
During power-up power should be applied simultaneously to VDD and VDDQIN with RP held
at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E,
and Write Enable, W, should be held at VIH during power-up.
In an application, it is recommended to associate the Reset/Power-down pin, RP, with the
reset signal of the microprocessor. Otherwise, if a Reset operation occurs while the memory
is performing an Erase or program operation, the memory may output the Status Register
information instead of being initialized to the default Asynchronous Random Read mode.
See Table 24 and Figure 22: Reset, Power-down and Power-up AC waveforms - Control
pins Low, for more details.
2.8 Program/Erase Enable (PEN)
The Program/Erase Enable input, PEN, protects all blocks by preventing Program and
Erase operations from modifying the data.
Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to
High (VIH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is
generated in the Status Register.
Signal descriptions M58BW16F, M58BW32F
22/87
2.9 Latch Enable (L)
The Bus Interface can be configured to latch the Address inputs on the rising edge of Latch
Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst
Read operations. In Synchronous Burst Read operations the address is latched on the
active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may
change without affecting the address used by the memory. When Latch Enable is Low, VIL,
the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read
and Write operations.
2.10 Burst Clock ( K)
The Burst Clock, K, is used to synchronize the memory with the external bus during
Synchronous Burst Read operations. Bus signals are latched on the active edge of the
Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge
when Latch Enable is Low, VIL, or on the rising edge of Latch Enable, whichever occurs first.
During Asynchronous Bus Operations the Clock is not used.
2.11 Bu rst Ad dr ess Advan ce (B)
The Burst Address Advance, B, controls the advancing of the address by the internal
address counter during Synchronous Burst Read operations.
Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the
X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address
counter advances. If Burst Address Advance is High, VIH, the internal address counter does
not change; the same data remains on the Data inputs/outputs and Burst Address Advance
is not sampled until the Y-latency expires.
The Burst Address Advance, B, may be tied to VIL.
2.12 Va lid Data Rea dy (R)
The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to
identify if the memory is ready to output data or not. The Valid Data Ready output can be
configured to be active on the clock edge of the invalid data read cycle or one cycle before.
Valid Data Ready, at VIH, indicates that new data is or will be available. When Valid Data
Ready is Low, VIL, the previous data outputs remain active.
2.13 Write Protect (WP)
The Write Protect, WP, provides protection against Program or Erase operations. When
Write Protect, WP, is at VIL, the protection status that has been configured in the Block
Protection Configuration Register is activated. Program and Erase operations to protected
blocks are disabled. When Write Protect WP is at VIH all the blocks can be programmed or
erased, if no other protection is used.
M58BW16F, M58BW32F Signal descriptions
23/87
2.14 Supply voltage (VDD)
The supply voltage, VDD, is the core power supply. All internal circuits draw their current
from the VDD pin, including the Program/Erase controller.
2.15 Output supply voltage (VDDQ)
The output supply voltage, VDDQ, is the output buffer power supply for all operations (Read,
Program and Erase) used for DQ0-DQ31 when used as outputs.
2.16 Input supply voltage (VDDQIN)
The input supply voltage, VDDQIN, is the power supply for all input signal. Input signals are: K,
B, L, W, GD, G, E, A0-Amax and DQ0-DQ31, when used as inputs.
2.17 Ground (VSS and VSSQ)
The ground VSS is the reference for the internal supply voltage VDD. The ground VSSQ is the
reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS
and VSSQ together.
Note: A 0.1 μF capacitor should be connected between the supply voltages, VDD, VDDQ and
VDDQIN and the grounds, VSS and VSSQ to decouple the current surges from the power
supply. The PCB track widths must be sufficient to carry the currents required during all
operations of the parts, see Table 18: DC characteristics, for maximum current supply
requirements.
2.18 Don’t use (DU)
This pin should not be used as it is internally connected. Its voltage level can be between
VSS and VDDQ or leave it unconnected.
2.19 Not connected (NC)
This pin is not physically connected to the device.
Bus operations M58BW16F, M58BW32F
24/87
3 Bus operations
Each bus operations that controls the memory is described in this section, see tables 6 and
7 Bus operations, for a summary. The bus operation is selected through the Burst
Configuration Register; the bits in this register are described at the end of this section.
On power-up or after a hardware reset the memory defaults to Asynchronous Bus Read and
Asynchronous Bus Write. No synchronous operation can be performed until the Burst
Control Register has been configured.
The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read
in asynchronous mode regardless of the Burst Control Register settings.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
3.1 Asynchronous Bus operations
For asynchronous bus operations refer to Table 6 together with the following text. The read
access will start at whichever of the three following events occurs last: valid address
transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL.
3.1.1 Asynchronous Bus Read
Asynchronous Bus Read operations read from the memory cells, or specific registers
(Electronic Signature, Block Protection Configuration Register, Status Register, CFI and
Burst Configuration Register) in the command interface. A valid bus operation involves
setting the desired address on the Address inputs, applying a Low signal, VIL, to Chip
Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The
Data inputs/outputs will output the value, see Figure 7: Asynchronous Bus Read AC
waveforms, and Table 19: Asynchronous Bus Read AC characteristics, for details of when
the output becomes valid.
Asynchronous Read is the default read mode which the device enters on power-up or on
return from Reset/Power-down.
3.1.2 Asynchronous Latch Controlled Bus Read
Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific
registers in the command interface. The address is latched in the memory before the value
is output on the data bus, allowing the address to change during the cycle without affecting
the address that the memory uses.
A valid bus operation involves setting the desired address on the Address inputs, setting
Chip Enable and Latch Enable Low, VIL and keeping Write Enable High, VIH; the address is
latched on the rising edge of Latch Enable. Once latched, the Address inputs can change.
Set Output Enable Low, VIL, to read the data on the Data inputs/outputs; see Figure 8:
Asynchronous Latch Controlled Bus Read AC waveforms and Table 19: Asynchronous Bus
Read AC characteristics, for details on when the output becomes valid.
Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus
Read operations can be performed when the memory is configured for Asynchronous Latch
Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation.
M58BW16F, M58BW32F Bus operations
25/87
3.1.3 Asynchronous Page Read
Asynchronous Page Read operations are used to read from several addresses within the
same memory page. Each memory page is 4 double-words and is addressed by the
address inputs A0 and A1.
Data is read internally and stored in the page buffer. Valid bus operations are the same as
Asynchronous Bus Read operations but with different timings. The first read operation within
the page has identical timings, subsequent reads within the same page have much shorter
access times. If the page changes then the normal, longer timings apply again. Page Read
does not support Latched Controlled Read.
See Figure 11: Asynchronous Page Read AC waveforms, and Table 20: Asynchronous
Page Read AC characteristics, for details on when the outputs become valid.
3.1.4 Asynchronous Bus Write
Asynchronous Bus Write operations write to the command interface in order to send
commands to the memory or to latch addresses and input data to program. Bus Write
operations are asynchronous, the clock, K, is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins by setting the desired address on the
Address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, VIL, and
Output Enable High, VIH, or Output Disable Low, VIL. The Address inputs are latched by the
command interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write
Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable
Low, during the whole Asynchronous Bus Write operation.
See Figure 12: Asynchronous Write AC waveforms, and Table 21: Asynchronous Write and
Latch controlled Write AC characteristics, for details of the timing requirements.
3.1.5 Asynchronous Latch Controlled Bus Write
Asynchronous Latch Controlled Bus Write operations write to the command interface in
order to send commands to the memory or to latch addresses and input data to program.
Bus Write operations are asynchronous, the clock, K, is Don’t care during Bus Write
operations.
A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired
address on the Address inputs and pulsing Latch Enable Low, VIL. The Address inputs are
latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip
Enable, whichever occurs first. Commands and input data are latched on the rising edge of
Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole Asynchronous Bus Write operation.
See Figure 13: Asynchronous Latch controlled Write AC waveforms, and Table 21:
Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing
requirements.
3.1.6 Output Disable
The data outputs are high impedance when the Output Enable, G, is at VIH or Output
Disable, GD, is at VIL.
Bus operations M58BW16F, M58BW32F
26/87
3.1.7 Standby
When Chip Enable is High, VIH, and the Program/Erase controller is idle, the memory enters
Standby mode, the power consumption is reduced to the standby level (IDD1) and the Data
inputs/outputs pins are placed in the high impedance state regardless of Output Enable,
Write Enable or Output Disable inputs.
The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst
Configuration Register to ‘1’ (see Table 18: DC characteristics).
3.1.8 Reset/Power-down
The memory is in Reset/Power-down mode when Reset/Power-down, RP, is at VIL. The
power consumption is reduced to the standby level (IDD1) and the outputs are high
impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or
Write Enable, W, inputs. In this mode the device is write protected and both the Status and
the Burst Configuration Registers are cleared. A recovery time is required when the RP
input goes High.
Table 6 . Asynchronous Bus operations(1)
Bus op eration Step E GGD WRP LA0-Amax DQ0-DQ31
Asynchronous Bus Read(2) VIL VIL VIH VIH VIH VIL Address Data output
Asynchronous Latch
Controlled Bus Read
Address Latch VIL VIH VIH VIL VIH VIL Address High Z
Read VIL VIL VIH VIH VIH VIH X Data output
Asynchronous Page Read VIL VIL VIH VIH VIH X Address Data output
Asynchronous Bus Write VIL VIH XV
IL VIH VIL Address Data input
Asynchronous Latch
Controlled Bus Write
Address Latch VIL VIH XV
IH VIH VIL Address High Z
Write VIL VIH XV
IL VIH VIH X Data input
Output Enable, G VIL VIH VIH VIH VIH X X High Z
Output Disable, GD VIL VIL VIL VIH VIH X X High Z
Standby VIH XXXV
IH X X High Z
Reset/Power-down X X X X VIL X X High Z
1. X = Don’t care.
2. Data, Manufacturer code, Device code, Burst Configuration Register, Standby Status and Block Protection Configuration
Register are read using the Asynchronous Bus Read command.
M58BW16F, M58BW32F Bus operations
27/87
3.2 Synchronous Bus operations
For Synchronous Bus Operations refer to Table 7 together with the following text. The read
access will start at whichever of the three following events occurs last: valid address
transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL.
3.2.1 Synchronous Burst Read
Synchronous Burst Read operations are used to read from the memory at specific times
synchronized to an external reference clock. The valid edge of the Clock signal is the rising
edge. Once the Flash memory is configured in Burst mode, it is mandatory to have an active
clock signal since the switching of the output buffer databus is synchronized to the rising
edge of the clock. In the absence of clock, no data is output.
The burst type, length and latency can be configured. The different configurations for
Synchronous Burst Read operations are described in the Burst Configuration Register
section. Refer to Figure 4 for examples of Synchronous Burst operations.
A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip
Enable and Latch Enable are Low, VIL. The burst start address is latched and loaded into
the internal Burst Address counter on the valid Burst Clock K edge or on the rising edge of
Latch Enable, whichever occurs first.
After an initial memory latency time, the memory outputs data each clock cycle. The Burst
Address Advance B input controls the memory burst output. The second burst output is on
the next clock valid edge after the Burst Address Advance B has been pulled Low.
Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst
Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low
on the rising clock edge, no new data is available and the memory does not increment the
internal address counter at the active clock edge even if Burst Address Advance, B, is Low.
Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid
immediately at the rising clock edge.
Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH.
If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid.
If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address
Advance, B, is at VIL the internal Burst Address counter is incremented at each Burst Clock
K rising edge.
The Synchronous Burst Read timing diagrams and AC characteristics are described in the
AC and DC parameters section. See Figures 14, 17, 18 and 19, and Table 22.
Bus operations M58BW16F, M58BW32F
28/87
3.2.2 Synchronous Burst Read Suspend
During a Synchronous Burst Read operation it is possible to suspend the operation, freeing
the data bus for other higher priority devices.
A valid Synchronous Burst Read operation is suspended when both Output Enable and
Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops
the Burst counter and the Output Enable going High, VIH, inhibits the data outputs. The
Synchronous Burst Read operation can be resumed by setting Output Enable Low.
3.3 Burst Configuration Register
The Burst Configuration Register is used to configure the type of bus access that the
memory will perform.
The Burst Configuration Register is set through the command interface and will retain its
information until it is re-configured, the device is reset, or the device goes into Reset/Power-
down mode. The Burst Configuration Register bits are described in Ta bl e 8 . They specify
the selection of the Burst length, Burst type, Burst X and Y latencies and the Read
operation. Refer to Figure 4 for examples of Synchronous Burst configurations.
3.3.1 Read Select bit (M15)
The Read Select bit, M15, is used to switch between Asynchronous and Synchronous Bus
Read operations. When the Read Select bit is set to ’1’, Bus Read operations are
asynchronous; when the Read Select bit is set to ’0’, Bus Read operations are synchronous.
On reset or power-up the Read Select bit is set to’1’ for asynchronous accesses.
3.3.2 St andby Disable bit (M14)
The Standby Disable bit, M14, is used to disable the Standby mode. When the Standby bit is
‘1’, the device will not enter Standby mode when Chip Enable goes High, VIH.
Table 7. Synchronous Burs t Read Bus oper ations (1)
1. X = Don't care, VIL or VIH.
Bus operation St ep E GGD RP KLBA0-Amax
DQ0-DQ31
Synchronous
Burst Read(2)
2. M15 = 0, Bit M15 is in the Burst Configuration Register.
Address Latch VIL VIH XV
IH R(3)
3. R = Rising edge.
VIL X Address input
Read VIL VIL VIH VIH R(3) VIH VIL Data output
Read Suspend VIL VIH XV
IH XV
IH VIH High Z
Read Resume VIL VIL VIH VIH R(3) VIH VIL Data output
Burst Address
Advance VIL VIH XV
IH R(3) VIH VIL High Z
Read Abort, E VIH XXV
IH XXX High Z
Read Abort, RP XXXV
IL XXX High Z
M58BW16F, M58BW32F Bus operations
29/87
3.3.3 X- La tency bits (M13-M11)
The X-Latency bits are used during Synchronous Bus Read operations to set the number of
clock edges between the address being latched and the edge where the first data become
available. For correct operation the X-Latency bits can only assume the values in Table 8:
Burst Configuration Register.
3.3.4 Y-Latency bit (M9)
The Y-Latency bit is used during Synchronous Bus Read operations to set the number of
clock cycles between consecutive reads. The Y-Latency value depends on both the X-
Latency value and the setting in M9.
When the Y-Latency is 1 the data changes each clock cycle.
3.3.5 Valid Data Ready bit (M8)
The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When
the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the rising
clock edge when invalid data is output on the bus.
3.3.6 Wrap Burst bit (M3)
Burst Read can be confined inside the 4 double-word boundary (wrap) or overcome the
boundary (no wrap). When the wrap burst bit is set to '1' the burst read does not wrap. The
wrap mode is not available (M3 is always ‘1’).
3.3.7 Burst Length bit (M2-M0)
The Burst Length bits set the maximum number of double-words that can be output during a
Synchronous Burst Read operation. Burst lengths of 4 or 8 are available.
Table 8: Burst Configuration Register gives the valid combinations of the Burst Length bits
that the memory accepts.
If a Burst Read operation (no wrap) has been initiated the device will output data
synchronously. Depending on the starting address, the device activates the Valid Data
Ready output to indicate that a delay is necessary before the data is output. If the starting
address is aligned to a 4 double word boundary, the 8-double-word burst mode will run
without activating the Valid Data Ready output. If the starting address is not aligned to a 4
double word boundary, Valid Data Ready is activated to indicate that the device needs an
internal delay to read the successive words in the array.
M10, M7 to M4 are reserved for future use.
Bus operations M58BW16F, M58BW32F
30/87
Table 8. Burst Configuration Re gi ster
Bit Description Value Description
M15 Read Select 0 Synchronous Burst Read
1 Asynchronous Read (default at power-on)
M14 Standby Disable 0 Standby mode enabled (default at power-up)
1 Standby mode disabled
M13-M11 X-Latency(1)
000 Reserved (default value)
001 3, 3-1-1-1, 3-2-2-2
010 4, 4-1-1-1, 4-2-2-2
011 5, 5-1-1-1, 5-2-2-2
100 6, 6-1-1-1, 6-2-2-2
101 7, 7-1-1-1, 7-2-2-2
110 8, 8-1-1-1, 8-2-2-2
111 Reserved
M10 0 Reserved (default value)
1 Reserved
M9 Y-Latency(2) 0 One Burst Clock cycle (default value)
1 Two Burst Clock cycle
M8 Valid Data Ready
0R valid Low during valid Burst Clock edge (default
value)
1R valid Low 1 data cycle before valid Burst Clock
edge
M7 0 Reserved (default value)
1 Reserved
M6(3) 0 Falling Burst Clock edge (default value)
1 Rising Burst Clock edge
M5-M4
00 Reserved (default value)
01 Reserved
10 Reserved
11 Reserved
M3 Wrapping 0 Wrap (default value)
1No Wrap
M58BW16F, M58BW32F Bus operations
31/87
M2-M0 Burst Length
000 Reserved (default value)
001 4 double-words
010 8 double-words
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Continuous
1. X latencies can be calculated as: (tAVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. X is an integer
number from 4 to 8, tK is the clock period and tSYSTEM MARGIN is the time margin required for the
calculation.
2. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK.
3. The M6 bit is Don’t care in the M58BW32F and the device has the Rising Burst Clock edge set. To
maintain the compatibility this could be modified and read.
Table 8. Burst Configuration Regi st er (continue d)
Bit Description Value Description
Bus operations M58BW16F, M58BW32F
32/87
Figure 4. Example burst conf igu ration X-1-1 -1
Table 9 . Burst type definition
Start address × 4 se que ntial × 8 sequential
0 0-1-2-3 0-1-2-3-4-5-6-7
1 1-2-3-4 1-2-3-4-5-6-7-8
2 2-3-4-5 2-3-4-5-6-7-8-9
3 3-4-5-6 3-4-5-6-7-8-9-10
4 4-5-6-7 4-5-6-7-8-9-10-11
5 5-6-7-8 5-6-7-8-9-10-11-12
6 6-7-8-9 6-7-8-9-10-11-12-13
7 7-8-9-10 7-8-9-10-11-12-13-14
8 8-9-10-11 8-9-10-11-12-13-14-15
AI03841b
K
DQ
L
ADD VALID
DQ
DQ
DQ
DQ
4-1-1-1
5-1-1-1
6-1-1-1
7-1-1-1
8-1-1-1
0123456789
VALIDVALIDVALIDVALID
VALIDVALIDVALIDVALIDVALIDVALID
VALIDVALIDVALID
VALID
VALIDVALID
VALID
VALIDVALID
VALID
DQ
3-1-1-1
VALIDVALIDVALIDVALID
VALID
VALIDVALID
M58BW16F, M58BW32F Command interface
33/87
4 Command interface
All Bus Write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential Bus Write operations. The commands are
summarized in Table 10: Commands. Refer to Table 10 in conjunction with the text
descriptions below.
4.1 Read Memory A rray command
The Read Memory Array command returns the memory to Read mode. One Bus Write cycle
is required to issue the Read Memory Array command and return the memory to Read
mode. Subsequent Read operations will output the addressed memory array data. Once the
command is issued the memory remains in Read mode until another command is issued.
From Read mode Bus Read commands will access the memory array.
4.2 Read El ectronic Signature command
The Read Electronic Signature command is used to read the Manufacturer code, the Device
code, the Block Protection Configuration Register and the Burst Configuration Register. One
Bus Write cycle is required to issue the Read Electronic Signature command. Once the
command is issued, subsequent Bus Read operations, depending on the address specified,
read the Manufacturer code, the Device code, the Block Protection Configuration or the
Burst Configuration Register until another command is issued; see Table 11: Read
electronic signature.
4.3 Read Query command
The Read Query command is used to read data from the common Flash interface (CFI)
memory area. One Bus Write cycle is required to issue the Read Query command. Once the
command is issued subsequent Bus Read operations, depending on the address specified,
read from the common Flash interface memory area.
Command interface M58BW16F, M58BW32F
34/87
4.4 Read S tatus Register command
The Read Status Register command is used to read the Status Register. One Bus Write
cycle is required to issue the Read Status Register command. Once the command is issued
subsequent Bus Read operations read the Status Register until another command is issued.
The Status Register information is present on the output data bus (DQ0-DQ7) when Chip
Enable E and Output Enable G are at VIL and Output Disable is at VIH.
An interactive update of the Status Register bits is possible by toggling Output Enable or
Output Disable. It is also possible during a Program or Erase operation, by de-activating the
device with Chip Enable at VIH and then reactivating it with Chip Enable and Output Enable
at VIL and Output Disable at VIH.
The content of the Status Register may also be read at the completion of a Program, Erase
or Suspend operation. During a Block Erase or Program command, DQ7 indicates the
Program/Erase controller status. It is valid until the operation is completed or suspended.
See the section on the Status Register and Table 1 3 for details on the definitions of the
Status Register bits.
4.5 Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status
Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once
the command is issued the memory returns to its previous mode, subsequent Bus Read
operations continue to output the same data.
The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new
Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs
then it is essential to clear any error bits in the Status Register by issuing the Clear Status
Register command before attempting a new Program, Erase or Resume command.
4.6 Block Erase command
The Block Erase command can be used to erase a block. It sets all of the bits in the block to
‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will
abort, the data in the block will not be changed and the Status Register will output the error.
Two Bus Write operations are required to issue the command; the first write cycle sets up
the Block Erase command, the second write cycle confirms the Block Erase command and
latches the block address in the Program/Erase controller and starts the Program/Erase
controller. The sequence is aborted if the Confirm command is not given and the device will
output the Status Register Data with bits 4 and 5 set to '1'.
Once the command is issued subsequent Bus Read operations read the Status Register.
See the section on the Status Register for details on the definitions of the Status Register
bits. During the Erase operation the memory will only accept the Read Status Register
command and the Program/Erase Suspend command. All other commands will be ignored.
If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation
aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re-
issued.
Typical Erase times are given in Table 12. See Appendix A, Figure 28: Block Erase
flowchart and pseudocode, for a suggested flowchart on using the Block Erase command.
M58BW16F, M58BW32F Command interface
35/87
4.7 Erase All Main Blocks command
The Erase All Main Blocks command is used to erase all 63 main blocks, without affecting
the parameter blocks.
Issuing the Erase All Main Blocks command sets every bit in each main block to '1'. All data
previously stored in the main blocks are lost.
Two Bus Write cycles are required to issue the Erase All Main Blocks command. The first
cycle sets up the command, the second cycle confirms the command and starts the
Program/Erase controller. If the Confirm command is not given the sequence is aborted,
and Status Register bits 4 and 5 are set to '1'.
If the address given in the second cycle is located in a protected block, the Erase All Main
Blocks operation aborts. The data remains unchanged in all blocks and the Status Register
outputs the error.
Once the Erase All Main Blocks command has been issued, subsequent Bus Read
operations output the Status Register. See the Status Register section for details.
During an Erase All Main Blocks operation, only the Read Status Register command is
accepted by the memory; any other command are ignored. Erase All Main Blocks, once
started, cannot be suspended.
If PEN is at VIH, the operation will be performed. If PEN is lower than VIH the operation
aborts and the Status Register PEN bit (bit 3) is set to '1'.
4.8 Program command
The Program command is used to program the memory array. Two Bus Write operations
are required to issue the command; the first write cycle sets up the Program command, the
second write cycle latches the address and data to be programmed and starts the
Program/Erase controller. A program operation can be aborted by writing FFFFFFFFh to
any address after the program set-up command has been given.
The Program command is also used to program the OTP block. Refer to Table 10:
Commands, for details of the address.
Once the command is issued subsequent Bus Read operations read the Status Register.
See the section on the Status Register for details on the definitions of the Status Register
bits. During the Program operation the memory will only accept the Read Status Register
command and the Program/Erase Suspend command. All other commands will be ignored.
If Reset/Power-down, RP
, falls to VIL during programming the operation will be aborted.
If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation
aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re-
issued.
See Appendix A, Figure 26: Program flowchart and pseudocode, for a suggested flowchart
on using the Program command.
Command interface M58BW16F, M58BW32F
36/87
4.9 Write to Buffer and Program command
The Write to Buffer and Program command makes use of the device’s double word (32 bit)
Write Buffer to speed up programming.
Up to eight double words can be loaded into the Write Buffer and programmed into the
memory.
Four successive steps are required to issue the command.
1. One Bus Write operation is required to set up the Write to Buffer and Program
command. Any Bus Read operations will start to output the Status Register after the 1st
cycle.
2. Use one Bus Write operation to write the selected memory block address (any address
in the block where the values will be programmed can be used) along with the value N
on the Data inputs/outputs, where N+1 is the number of words to be programmed. The
maximum value of N+1 is 8 words.
3. Use N+1 Bus Write operations to load the address and data for each word into the write
buffer. The address must be between Start address and Start address plus N, where
Start address is the first word address.
4. Finally, use one Bus Write operation to issue the final cycle to confirm the command
and start the Program operation.
If any address is outside the block boundaries or if the correct sequence is not followed,
Status Register bits 4 and 5 are set to ‘1’ and the operation will abort without affecting the
data in the memory array. A protected block must be unprotected using the Blocks
Unprotect command.
During a Write to Buffer and Program operation the memory will only accept the Read
Status Register and the Program/Erase Suspend commands. All other commands are
ignored. If PEN is at VIH, the operation will be performed. If PEN is lower than VIH the
operation aborts and the Status Register PEN bit (bit 3) is set to '1'.
The Status Register should be cleared before re-issuing the command.
M58BW16F, M58BW32F Command interface
37/87
4.10 Program/Erase Su spend command
The Program/Erase Suspend command is used to pause a Program or Erase operation. The
command will only be accepted during a Program or Erase operation. It can be issued at
any time during a Program or Erase operation. The command is ignored if the device is
already in suspend mode.
One Bus Write cycle is required to issue the Program/Erase Suspend command and pause
the Program/Erase controller. Once the command is issued it is necessary to poll the
Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase controller
has paused; no other commands will be accepted until the Program/Erase controller has
paused. After the Program/Erase controller has paused, the memory will continue to output
the Status Register until another command is issued.
During the polling period between issuing the Program/Erase Suspend command and the
Program/Erase Controller pausing it is possible for the operation to complete. Once the
Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase controller is no
longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6)
can be used to determine if the operation has completed or is suspended. For timing on the
delay between issuing the Program/Erase Suspend command and the Program/Erase
controller pausing see Table 12.
During Program/Erase Suspend the Read Memory Array, Read Status Register, Read
Electronic Signature, Read Query and Program/Erase Resume commands will be accepted
by the command interface. Additionally, if the suspended operation was Erase then the
Program, the Write to Buffer and Program, the Set/Clear Block Protection Configuration
Register and the Program Suspend commands will also be accepted. When a program
operation is completed inside a Block Erase Suspend the Read Memory Array command
must be issued to reset the device in Read mode, then the Erase Resume command can be
issued to complete the whole sequence. Only the blocks not being erased may be read or
programmed correctly.
Erase operations can be suspended in a systematic and periodical way, however, in order to
ensure the effectiveness of erase operations and avoid infinite erase times, it is imperative
to wait a minimum time between successive Erase Resume and Erase Suspend
commands. This time, called the minimum effective erase time, is given in Table 12 on
page 40.
See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and
Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts
on using the Program/Erase Suspend command.
4.11 Progr am/Erase Re sume command
The Program/Erase Resume command can be used to restart the Program/Erase controller
after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to
issue the Program/Erase Resume command.
See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and
Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts
on using the Program/Erase Suspend command.
Command interface M58BW16F, M58BW32F
38/87
4.12 Set Burst Configuration Register command
The Set Burst Configuration Register command is used to write a new value to the Burst
Configuration Register which defines the burst length, type, X and Y latencies,
Synchronous/Asynchronous Read mode.
Two Bus Write cycles are required to issue the Set Burst Configuration Register command.
The first cycle writes the setup command. The second cycle writes the address where the
new Burst Configuration Register content is to be written, and confirms the command. If the
command is not confirmed, the sequence is aborted and the device outputs the Status
Register with bits 4 and 5 set to ‘1’. Once the command is issued the memory returns to
Read mode as if a Read Memory Array command had been issued.
The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0,
M1 on A1, etc.; the other address bits are ignored.
4.13 Set Block Protection Configuration Regist er command
The Set Block Protection Configuration Register command is used to configure the Block
Protection Configuration Register to ‘protected’, for a specific block. Protected blocks are
fully protected from program or erase when WP pin is Low, VIL. The status of a protected
block can be changed to ‘unprotected’ by using the Clear Block Protection Configuration
Register command. At power-up, all block are configured as ‘protected’.
Two bus operations are required to issue a Set Block Protection Configuration Register
command:
The first cycle writes the setup command
The second write cycle specifies the address of the block to protect and confirms the
command. If the command is not confirmed, the sequence is aborted and the device
outputs the Status Register with bits 4 and 5 set to ‘1’.
To protect multiple blocks, the Set Block Protection Configuration Register command must
be repeated for each block.
Any attempt to re-protect a block already protected does not change its status.
4.14 Clear Block Protection Conf iguration Register command
The Clear Block Protection Configuration Register command is used to configure the Block
Protection Configuration Register to ‘unprotected’, for a specific block thus allowing
program/erase operations to this block, regardless of the WP pin status.
Two bus operations are required to issue a Clear Block Protection Configuration Register
command:
The first cycle writes the setup command
The second write cycle specifies the address of the block to unprotect and confirms the
command. If the command is not confirmed, the sequence is aborted and the device
outputs the Status Register with bits 4 and 5 set to ‘1’.
To unprotect multiple blocks, the Clear Block Protection Configuration Register command
must be repeated for each block.
Any attempt to unprotect a block already unprotected does not affect its status.
M58BW16F, M58BW32F Command interface
39/87
Table 10. Commands (1)
Command
Cycles
Bus operations
1st cycle 2nd cycle 3rd cycle 4th cy cle
Op. Addr. Data Op. Addr. Data Op. Addr. Data Op. Addr. Data
Read Memory Array ≥ 2 Write X FFh Read RA RD
Read Electronic Signature(2) ≥ 2 Write X 90h Read IDA IDD
Read Status Register 1 Write X 70h
Read Query ≥ 2 Write X 98h Read RA RD
Clear Status Register 1 Write X 50h
Block Erase 2 Write 55h 20h Write BA D0h
Erase All Main Blocks 2 Write 55h 80h Write AAh D0h
Program any block 2 Write AAh 40h
10h Write PA PD
OTP block 2 Write AAh 40h Write PA PD
Write to Buffer and Program N+4 Write AAh E8h Write BA N Write PA PD Write X D0h
Program/Erase Suspend 1 Write X B0h
Program/Erase Resume 1 Write X D0h
Set Burst Configuration
Register Š3 Write X 60h Write BCRh 03h Read RA RD
Set Block Protection
Configuration Register 2Write X 60hWrite BA 01h
Clear Block Protection
Configuration Register 2 Write X 60h Write BA D0h
1. X Don’t care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status
Register Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block,
BCR Burst Configuration Register value, N+1 number of Words to program, BA Block address.
2. The Manufacturer code, the Device code, the Burst Configuration Register, and the Block Protection Configuration Register
of each block are read using the Read Electronic Signature command.
Command interface M58BW16F, M58BW32F
40/87
Tabl e 11. Re ad elec tronic signature
Code Device Amax-A0 DQ31-DQ0
Manufacturer All 00000h 00000020h
Device
M58BW16FT 00001h 0000883Ah
M58BW16FB 00001h 00008839h
M58BW32FT 00001h 00008838h
M58BW32FB 00001h 00008837h
Burst Configuration
Register 00005h BCR(1)
1. BCR = Burst Configuration Register.
Block Protection
Configuration Register All SBA+02h(2)
2. SBA is the start address of each block.
00000000h (Unprotected)
00000001h (Protected)
Table 12. Program, Erase tim es and endurance cyc les (1)
1. TA = –40 to 125 °C, VDD = 2.7 V to 3.6 V, VDDQ = 2.6 V to VDD.
Parameters M58BW16F M58BW32F Unit
Min Typ Max Min Typ Max
Full Chip Program 15 20 15 20 s
Double Word Program 15 35 15 35 μs
512 Kbit Block Erase 1 2 1 2 s
128 Kbit Block Erase 0.8 1.6 0.8 1.6 s
64 Kbit Block Erase 0.6 1.2 0.6 1.2 s
Erase all main blocks 45 60 30 50 s
Program Suspend Latency time 10 10 μs
Erase Suspend Latency time 30 30 μs
Minimum effective erase time(2)
2. The minimum effective erase time is defined as the minimum time required between the last Erase
Resume command and the next Erase Suspend command for the internal Flash memory Program/Erase
controller to be able to execute its algorithm.
40 40 μs
Program/Erase cycles (per block) 100,000 100,000 cycles
M58BW16F, M58BW32F Status Register
41/87
5 Status Register
The Status Register provides information on the current or previous Program, Erase or
Block Protect operation. The various bits in the Status Register convey information and
errors on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Register command can be issued. The Status
Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume
commands. The Status Register can be read from any address.
The contents of the Status Register can be updated during an erase or program operation
by toggling the Output Enable or Output Disable pins or by de-activating (Chip Enable, VIH)
and then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, VIH.) the
device.
The Status Register bits are summarized in Table 13: Status Register bits. Refer to Table 13
in conjunction with the following text descriptions.
5.1 Program/Erase Controller Status (bit 7)
The Program/Erase Controller Status bit indicates whether the Program/Erase controller is
active or inactive. When the Program/Erase Controller Status bit is set to ‘0’, the
Program/Erase controller is active; when bit 7 is set to ‘1’, the Program/Erase controller is
inactive.
The Program/Erase Controller Status is set to ‘0’ immediately after a Program/Erase
Suspend command is issued until the Program/Erase Controller pauses. After the
Program/Erase Controller pauses the bit is set to ‘1’.
During Program and Erase operations the Program/Erase Controller Status bit can be polled
to find the end of the operation. The other bits in the Status Register should not be tested
until the Program/Erase controller completes the operation and the bit is set to ‘1’.
After the Program/Erase controller completes its operation the Erase Status (bit 5), Program
Status (bit 4) bits should be tested for errors.
5.2 Erase Suspend Status (bit 6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended and is
waiting to be resumed. The Erase Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is set to ‘1’ (Program/Erase controller inactive); after a
Program/Erase Suspend command is issued the memory may still complete the operation
rather than entering the Suspend mode.
When the Erase Suspend Status bit is set to ‘0’, the Program/Erase controller is active or
has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command
has been issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
to ‘0’.
Stat u s Register M58 BW16F, M58BW32F
42/87
5.3 Erase Status (bit 5)
The Erase Status bit can be used to identify if the memory has failed to verify that the block
has erased correctly. The Erase Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase controller inactive).
When the Erase Status bit is set to ‘0’, the memory has successfully verified that the block
has erased correctly. When the Erase Status bit is set to ‘1’, the Program/Erase controller
has applied the maximum number of pulses to the block and still failed to verify that the
block has erased correctly.
Once set to ‘1’, the Erase Status bit can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
5.4 Program/Write to Buffer and Program Status (bit 4)
The Program/Write to Buffer and Program Status bit is used to identify a Program failure or
a Write to Buffer and Program failure. Bit 4 should be read once the Program/Erase
Controller Status bit is High (Program/Erase controller inactive).
When bit 4 is set to ‘0’ the memory has successfully verified that the device has
programmed correctly. When bit 4 is set to ‘1’ the device has failed to verify that the data has
been programmed correctly.
Once set to ‘1’, the Program Status bit can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase
command is issued, otherwise the new command will appear to fail.
5.5 PEN Status (bit 3)
The PEN Status bit can be used to identify if a Program or Erase operation has been
attempted when PEN is Low, VIL.
When bit 3 is set to ‘0’ no Program or Erase operations have been attempted with PEN Low,
VIL, since the last Clear Status Register command, or hardware reset.
When bit 3 is set to ‘1’ a Program or Erase operation has been attempted with PEN Low,
VIL.
Once set to ‘1’, bit 3 can only be reset by a Clear Status Register command or a hardware
reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued,
otherwise the new command will appear to fail.
M58BW16F, M58BW32F Status Register
43/87
5.6 Program Sus pend Status (bit 2)
The Program Suspend Status bit indicates that a Program operation has been suspended
and is waiting to be resumed. The Program Suspend Status should only be considered valid
when the Program/Erase Controller Status bit is set to ‘1’ (Program/Erase Controller
inactive); after a Program/Erase Suspend command is issued the memory may still
complete the operation rather than entering the Suspend mode.
When the Program Suspend Status bit is set to ‘0’, the Program/Erase controller is active or
has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command
has been issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued the Program Suspend Status bit
returns to ‘0’.
5.7 Block Protection Status (bit 1)
The Block Protection Status bit can be used to identify if a Program or Erase operation has
tried to modify the contents of a protected block.
When the Block Protection Status bit is set to ‘0’, no Program or Erase operations have
been attempted to protected blocks since the last Clear Status Register command or
hardware reset; when the Block Protection Status bit is set to ‘1’, a Program or Erase
operation has been attempted on a protected block.
Once set to ‘1’, the Block Protection Status bit can only be reset Low by a Clear Status
Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program
or Erase command is issued, otherwise the new command will appear to fail.
5.8 Bit 0
Reserved bit (set to ‘1’).
Stat u s Register M58 BW16F, M58BW32F
44/87
Tabl e 13. Stat u s Register b its
Bit Name Logic level Defini ti on
7 Program/Erase Controller Status ’1’ Ready
’0’ Busy
6 Erase Suspend Status ’1’ Suspended
’0’ In progress or completed
5 Erase Status ’1’ Erase error
’0’ Erase success
4 Program Status, ’1’ Program error
’0’ Program success
3 PEN Status bit ‘0’ No program or erase attempted
‘1’ Program or erase attempted
2 Program Suspend Status ’1’ Suspended
’0’ In progress or completed
1Erase/Program in a protected
block
’1’ Program/erase on protected block,
abort
’0’ No operations to protected blocks
0 Reserved ’1’ Reserved
M58BW16F, M58BW32F Maximum rating
45/87
6 Maximum rating
Stressing the device above the ratings listed in Table 14: Absolute maximum ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 14. Absolute maximu m ratings
Symbol Parameter Value Unit
Min Max
TBIAS Temperature under bias –40 125 °C
TSTG Storage temperature –55 155 °C
VIO Input or output voltage –0.6 VDDQ +0.6
VDDQIN +0.6 V
VDD, VDDQ, VDDQIN Supply voltage –0.6 4.2 V
Tabl e 15. Data retent ion
Powe r sup p ly
VDD Unit External temperature Unit
25 °C 125 °C
0 V 20 7 Years
2.5 V – 25 Years
2.7 V – 15 Years
DC and AC parameters M58BW16F, M58BW32F
46/87
7 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 16: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Figure 5. AC meas urement input/output waveform
1. VDD = VDDQ.
Fig u re 6. AC measur em ent lo ad circuit
Table 16. Operating and AC measu rement conditions
Parameter
M58BW16F, M58BW32F
Units45 ns 55 ns
Min Max Min Max
Supply voltage (VDD) 2.7 3.6 2.5 3.3 V
Input/output supply voltage (VDDQ) 2.4 3.6 2.4 3.6 V
Ambient temperature (TA) Grade 3 –40 125 –40 125 °C
Load capacitance (CL)3030pF
Clock rise and fall times 3 3 ns
Input rise and fall times 3 3 ns
Input pulses voltages 0 to VDDQ 0 to VDDQ V
Input and output timing ref. voltages VDDQ/2 VDDQ/2 V
AI04153
VDDQ
VDDQIN
0 V
VDDQ/2
VDDQIN/2
AI04154b
OUT
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
M58BW16F, M58BW32F DC and AC parameters
47/87
Table 17. Device capacitance(1)(2)
1. TA = 25 °C, f = 1 MHz.
2. Sampled only, not 100% tested.
Symbol Pa r ameter Test condition Typ Max Unit
CIN Input capacitance VIN =0V 6 8 pF
COUT Output capacitance VOUT =0V 8 12 pF
Tabl e 18. DC characteristi cs
Symbol Parameter Test condition Min Typ Max Unit
ILI Input Leakage current 0 V≤VIN ≤VDDQIN ±1 μA
ILO Output Leakage current 0 V ≤VOUT ≤VDDQ ±5 μA
IDD Supply current (Random
Read)
E = VIL, G = VIH,
fadd = 6 MHz 25 mA
IDDP-UP(1)
1. IDDP-UP is the current needed from the device until RP goes to its logic high level when the power supply is
stable (tVDHPH). See Figure 22and Figure 23.
Supply current (power-up) 20 mA
IDDB Supply current (Burst
Read)
E = VIL, G = VIH,
fclock = 75 MHz 50 mA
IDD1(2)
2. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration
Register to ‘1’.
Supply current (Standby) E=RP =
VDD ±0.2V 150 μA
IDD2 Supply current (Program
or Erase)
Program, Erase in
progress 30 mA
IDD3
Supply current
(Erase/Program Suspend) E = VIH 150 μA
IDD4 Supply current (Standby
Disable) 510mA
VIL Input Low voltage –0.5 0.2VDDQIN V
VIH Input High voltage (for DQ
lines) 0.8VDDQIN VDDQ +0.3 V
VIH Input High voltage (for
input only lines) 0.8VDDQIN 3.6 V
VOL Output Low voltage IOL =100μA0.1V
VOH Output High voltage
CMOS IOH = –100 μAV
DDQ –0.1 V
VLKO VDD supply voltage (Erase
and Program lockout) 2.2 V
DC and AC parameters M58BW16F, M58BW32F
48/87
Figure 7. A synchronous Bus Read AC wav eforms
Figure 8. Asynchronous Latc h Controlled Bus Read AC waveform s
AI08921b
E
G
L
A0-A19
DQ0-DQ31
VALID
tAXQX
tELQX
tELQV
tAVQV
tGLQX
tGLQV tEHQX
tEHQZ
tGHQX
tGHQZ
See also Page Read
OUTPUT
tEHLX
tAVAV
GD
AI08922b
L
E
G
A0-A19
DQ0-DQ31
VALID
tEHLXtLHLL
tLHAX
tLLLH
tEHQX
tEHQZ
tGHQX
GHQZ
tLLQV
tLLQX
tGLQX
tGLQV
See also Page Read
OUTPUT
M58BW16F, M58BW32F DC and AC parameters
49/87
Figure 9. As ynchronous Chip Enable Controlled Bus Read AC wave form s
Figure 10. Async hronous Address Controlled Bus Read AC waveforms
AI13434
L
E
G
A0-A19
DQ0-DQ31
VALID
tEHLX
tLHAX
tEHQX
tEHQZ
tGHQX
GHQZ
tELQX
tELQV
tGLQX
tGLQV
See also Page Read
OUTPUT
AI13435
L
E
G
A0-A19
DQ0-DQ31
VALID
tEHLX
tLHAX
tEHQX
tEHQZ
tGHQX
GHQZ
tAVQV
tGLQX
tGLQV
See also Page Read
OUTPUT
DC and AC parameters M58BW16F, M58BW32F
50/87
Table 19. Asynchronous Bus Read AC charact erist ics
Symbol Parameter Test condition M58BWxxF Unit
45 55
tAVAV Address Valid to Address Valid E =V
IL, G = VIL Min 45 55 ns
tAVQV Address Valid to Output Valid E =V
IL, G = VIL Max 45 55 ns
tAXQX Address Transition to Output Transition L =V
IL, G =V
IL Min00ns
tEHLX Chip Enable High to Latch Enable
Transition Min00ns
tEHQX Chip Enable High to Output Transition G =V
IL Min00ns
tEHQZ Chip Enable High to Output Hi-Z G =V
IL Max 20 20 ns
tELQV(1)
1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without
increasing tELQV.
Chip Enable Low to Output Valid G =V
IL Max 45 55 ns
tGHQX Output Enable High to Output Transition E =V
IL Min00ns
tGHQZ Output Enable High to Output Hi-Z E =V
IL Max 15 15 ns
tGLQV Output Enable Low to Output Valid E =V
IL Max 15 15 ns
tGLQX Output Enable Low to Output Transition E =V
IL Min00ns
tLHAX Latch Enable High to Address
Transition E=V
IL Min55ns
tLHLL Latch Enable High to Latch Enable Low Min 10 10 ns
tLLLH Latch Enable Low to Latch Enable High E =V
IL Min 10 10 ns
tLLQV
Latch Enable Low to Output Valid
Chip Enable Low to Output Valid E=V
IL, G =V
IL Max 45 55 ns
tLLQX Latch Enable Low to Output Transition E =V
IL, G =V
IL Min00ns
tELQX Chip Enable Low to Output Transition L =V
IL, G =V
IL Min00ns
M58BW16F, M58BW32F DC and AC parameters
51/87
Figure 11. Asynchronous P age Read AC waveforms
AI03646
A0-A1
DQ0-DQ31
A0 and/or A1
tAVQV1
OUTPUT
tAXQX
OUTPUT + 1
Table 20. Asynchronous Page Read AC char acteristi cs(1)
Symbol Parameter Test condition M58BWxxF Unit
45 55
tAVQV1 Address Valid to Output Valid E = VIL, G = VIL Max 25 25 ns
tAXQX Address Transition to Output Transition E = VIL, G = VIL Min 0 0 ns
1. For other timings see Table 19: Asynchronous Bus Read AC characteristics.
DC and AC parameters M58BW16F, M58BW32F
52/87
Figure 12. Async hronous Write AC wav eform s
AI13223b
DQ0-DQ31
W
RP
A0-A19
E = L
G
INPUT
VALID VALID
tWHEH
VALID
tAVWH
tWLWH
tELWL
INPUT VALID SR
PEN
tWHAX
tWHWL
tWHDX
tDVWH
tWHGL
tWHQV
tVPHWH tQVVPL
tQVPL
tPHWH
RP = V
DD
RP = V
HH
Read Status RegisterWrite CycleWrite Cycle
tAVLL
tAVAV
M58BW16F, M58BW32F DC and AC parameters
53/87
Figure 13. Async hronous Latch cont rol led Write AC waveforms
AI13222b
DQ0-DQ31
W
RP
A0-A19
L
G
INPUT
VALID VALID VALID
tAVLH
INPUT VALID SR
PEN
tLHAX
Read Status RegisterWrite CycleWrite Cycle
E
tLLLH
tLLWH
tWHAX
tELWL
tWLWH
tWHEH
tWHWL tWHGL
tWHQV
tDVWH
tWHDX tVPHWH tQVVPL
tQVPL
RP = VHH RP = VDD
tAVWH
tELLL
tAVLL
tAVAV
DC and AC parameters M58BW16F, M58BW32F
54/87
Table 21. Asynchronous Write and Latch controlled Write AC characteristics
Symbol Parameter Test condition M58BWxxF Unit
45 55
tAVAV Address Valid to Address Valid Min 45 55 ns
tAVLH Address Valid to Latch Enable High Min 8 8 ns
tAVLL Address Valid to Latch Enable Low Min 0 0 ns
tAVWH Address Valid to Write Enable High E = VIL Min2530ns
tDVWH Data Input Valid to Write Enable High E = VIL Min2530ns
tELLL Chip Enable Low to Latch Enable Low Min 0 0 ns
tELWL Chip Enable Low to Write Enable Low Min 0 0 ns
tLHAX Latch Enable High to Address Transition Min 5 5 ns
tLLLH Latch Enable Low to Latch Enable High Min 10 10 ns
tLLWH latch Enable Low to Write Enable High E = VIL Min2530ns
tQVVPL Output Valid to PEN Low Min 0 0 ns
tVPHWH PEN High to Write Enable High Min 0 0 ns
tWHAX Write Enable High to Address Transition E = VIL Min 0 0 ns
tWHDX Write Enable High to Input Transition E = VIL Min 0 0 ns
tWHEH Write Enable High to Chip Enable High Min 0 0 ns
tWHGL Write Enable High to Output Enable Low Min 150 150 ns
tWHQV Write Enable High to Output Valid Min 165 165 ns
tWHWL Write Enable High to Write Enable Low Min 20 20 ns
tWLWH Write Enable Low to Write Enable High E = VIL Min2530ns
tQVPL Output Valid to Reset/Power-down Low Min 0 0 ns
M58BW16F, M58BW32F DC and AC parameters
55/87
Figure 14. Sync hronous Burst Read, Latch Enable c ontrolled (data va lid from ’n’
clock rising edge)
AI08925c
DQ0-DQ31
A0-A19
L
E
G
K
VALID
tKHAX
n+2
n+1n
1
0
tKHLL
tLLKH
tELLL
tAVLL
tKHLH
tEHQX
tEHQZ
tGHQX
tGHQZ
tGLQV
Setup
OUTPUT
tKHQV
Note: n depends on Burst X-Latency.
DC and AC parameters M58BW16F, M58BW32F
56/87
Figure 15. Sync hronous Burst Read, Chip Enable c ontrolled (data valid from ’n’
clock rising edge)
AI13284
DQ0-DQ31
A0-A19
L
E
G
K
VALID
tKHAX
n+2
n+1n
1
0
tKHEL
tELKH tKHLH
tEHQX
tEHQZ
tGHQX
tGHQZ
tGLQV
Setup
OUTPUT
tKHQV
Note: n depends on Burst X-Latency.
B
tBLKH
M58BW16F, M58BW32F DC and AC parameters
57/87
Figure 16. Sync hronous Burst Read, Valid Address transi tion cont rol led (data valid
from ’n’ clock rising edge)
AI13285
DQ0-DQ31
A0-A19
L
E
G
K
VALID
tKHAX
n+2
n+1n
1
0
tAVKH
tKHLH
tEHQX
tEHQZ
tGHQX
tGHQZ
tGLQV
Setup
OUTPUT
tKHQV
Note: n depends on Burst X-Latency.
B
tBLKH
DC and AC parameters M58BW16F, M58BW32F
58/87
Figure 17. Synchron ous Bu rst Read (data valid from ’n’ clock rising edge)
1. For set up signals and timings see Synchronous Burst Read.
Figure 18. Synchron ous Bu rst Read - valid data ready output
1. Valid Data Ready = Valid Low during valid clock edge.
2. V= Valid output.
3. The internal timing of R follows DQ.
AI04408c
K
n+5
n+4
n+3
n+2
n+1
n
DQ0-DQ31
tKHQX
Q0 Q1 Q2 Q3 Q4 Q5
SETUP Burst Read
Q0 to Q3
tKHQV
Note: n depends on Burst X-Latency
AI03649b
K
Output (1) VVVV
tRLKH
R
V
(2)
M58BW16F, M58BW32F DC and AC parameters
59/87
Figure 19. Synchronous Burst Read - Burst Address Adv anc e
Figure 20. Clock input AC wave form
AI03650
K
Q0 Q1
L
Q2
VALID
G
tGLQV
tBLKH tBHKH
B
DQ0-DQ31
A0-A19
tKHKL
tKLKH
K
ai1328
6
DC and AC parameters M58BW16F, M58BW32F
60/87
Tabl e 22. Synch ronous Burst Read AC ch a r acteristics(1)(2)
Symbol Parameter Test condition M58BWxxF Unit
45 55
f Clock frequency
X-Latency = 3 Max 40 33 MHz
X-Latency = 4 Max 56 40 MHz
X-Latency = 5 or 6 Max 75 56 MHz
tAVKH Address Valid to Valid Clock Edge
E=V
IL, L=V
IL
X-Latency = 3 Min 12 13 ns
E=V
IL, L=V
IL
X-Latency = 4, 5 or 6 Min 6 7 ns
tKHKL Clock High time Min 6 6 ns
tKLKH Clock Low time Min 6 6 ns
tBHKH Burst Address Advance High to Valid
Clock Edge E=V
IL, G =V
IL, L =V
IH Min 8 8 ns
tBLKH Burst Address Advance Low to Valid
Clock Edge E=V
IL, G =V
IL, L =V
IH Min 8 8 ns
tELKH Chip Enable Low to Valid Clock Edge
L=V
IL
X-Latency = 3 Min 12 13 ns
L=V
IL
X-Latency = 4, 5 or 6 Min 6 7 ns
tGLQV Output Enable Low to Output Valid E =V
IL, L =V
IH Max 15 15 ns
tKHAX Valid Clock Edge to Address
Transition E=V
IL Min 5 5 ns
tKHEL Valid Clock Edge to Chip Enable Low L =V
IL Min 0 0 ns
tKHLL Valid Clock Edge to Latch Enable
Low E=V
IL Min 0 0 ns
tKHLH Valid Clock Edge to Latch Enable
High E=V
IL Min 0 0 ns
tKHQX Valid Clock Edge to Output Transition E =V
IL, G =V
IL, L =V
IH Min 2 2 ns
tLLKH Latch Enable Low to Valid Clock
Edge
E=V
IL
X-Latency = 3 Min 12 13 ns
E=V
IL
X-Latency = 4, 5 or 6
M58BW16F Min 6 5 ns
M58BW32F Min 6 7 ns
tRLKH Valid Data Ready Low to Valid Clock
Edge E=V
IL, G =V
IL, L =V
IH Min 6 6 ns
tKHQV Valid Clock Edge to Output Valid E =V
IL, G =V
IL, L =V
IH Max 8 8 ns
1. Data output should be read on the valid clock edge.
2. For other timings see Table 19: Asynchronous Bus Read AC characteristics.
M58BW16F, M58BW32F DC and AC parameters
61/87
Figure 21. Power supply slope specificat ion
1. Please refer to the application note AN2601.
Table 23. Power supply AC and DC charac te ri stics
Symbol Description Min Max Unit
VDH Minimum value of power supply (VDD)(1)
1. This threshold is 90% of the minimum value allowed to VDD.
0.9VDD V
VDHH Maximum value of power supply (VDD)3.6V
tVDH Time required from power supply to reach the VDH value 300 50000 μs
AI1423
0b
VDH
VDHH
Voltage
Time
tVDH
DC and AC parameters M58BW16F, M58BW32F
62/87
Figure 22. Reset, Powe r-down and Power-up AC waveform s - Control pins Low
Figure 23. Reset, Powe r-down and Power-up AC waveform s - Control pins toggling
AI14239
W,
RP
tPHWL
tPHEL
tPHGL
tPHLL
E, G, L
VDD, VDDQ
tVDHPH tPLPH
Power-up Reset
RHi-Z
tPHRH tPLRZ
Hi-Z
tPHRH
AI14240
W,
RP
tPHWL
tPHEL
tPHGL
tPHLL
E, G, L
VDD, VDDQ
tVDHPH tPLPH
Power-up Reset
RHi-Z
tPHRH
tPLRZ Hi-Z
tPHRH
tWLRH
tGLRH
tELRH
tLLRH
M58BW16F, M58BW32F DC and AC parameters
63/87
Table 24. R eset, Power-down and Po we r-up A C cha rac te ri stics
Symbol Parameter Min Max Unit
tPHEL Reset/Power-down High to Chip Enable Low 50 ns
tPHLL Reset/Power-down High to Latch Enable Low 50 ns
tPHQV(1) Reset/Power-down High to Output Valid 95 ns
tPHWL Reset/Power-down High to Write Enable Low 50 ns
tPHGL Reset/Power-down High to Output Enable Low 50 ns
tPLPH Reset/Power-down Low to Reset/Power-down High 100 ns
tPHRH(1) Reset/Power-down High to Valid Data Ready High 95 ns
tVDHPH Supply voltages High to Reset/Power-down High 50 μs
tPLRZ Reset/Power-down Low to Data Ready High Impedance 80 ns
tWLRH Write Enable Low to Data Ready High Impedance 80 ns
tGLRH Output Enable Low to Data Ready High Impedance 80 ns
tELRH Chip Enable Low to Data Ready High Impedance 80 ns
tLLRH Latch Enable Low to Data Ready High Impedance 80 ns
1. This time is tPHEL + tAVQV or tPHEL + tELQV.
Package mechanical M58BW16F, M58BW32F
64/87
8 Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second-level interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
Figure 24. LBGA8 0 10 × 12 mm - 8 × 10 ball array, 1 mm pitch, bottom view package
outline
1. Drawing is not to scale.
E1E
D1
D
eb
A2
A1
A
JE_ME
ddd
FD
FE SD
SE
e
BALL "A1"
M58BW16F, M58BW32F Package mechanical
65/87
Tabl e 25. LBG A80 10 × 12 mm - 8 × 10 ac ti ve ball array, 1 mm pitch, pack ag e
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.60 0.063
A1 0.40 0.016
A2 1.05 0.041
b 0.60 0.024
D 10.00 – – 0.394 – –
D1 7.00 – – 0.276 – –
ddd 0.15 0.006
E 12.00 – – 0.472 – –
E1 9.00 – – 0.354 – –
e 1.00 – – 0.039 – –
FD 1.50 – – 0.059 – –
FE 1.50 – – 0.059 – –
SD 0.50 0.020
SE 0.50 0.020
Package mechanical M58BW16F, M58BW32F
66/87
Figure 25. PQFP80 - 80 lead plastic quad flat pac k, package outline
1. Drawing is not to scale.
Tabl e 26. PQFP80 - 80 lead p la stic qua d fl at pack, package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 3.40 0.134
A1 0.25 0.010
A2 2.80 2.55 3.05 0.110 0.100 0.120
b 0.30 0.45 0.012 0.018
CP 0.10 0.004
c 0.13 0.23 0.005 0.009
D 23.20 22.95 23.45 0.913 0.903 0.923
D1 20.00 19.90 20.10 0.787 0.783 0.791
D218.40– –0.724– –
e 0.80 – – 0.031 – –
E 17.20 16.95 17.45 0.677 0.667 0.687
E1 14.00 13.90 14.10 0.551 0.547 0.555
E212.00– –0.472– –
L 0.80 0.65 0.95 0.031 0.026 0.037
L1 1.60 – – 0.063 – –
α0° 7° 0° 7°
N80 80
Nd 24 24
Ne 16 16
QFP-B
D1
CP
b
e
A2
A
N
LA1 α
E1
E2
1
D
c
E
D2
L1
Nd
Ne
M58BW16F, M58BW32F Ordering information
67/87
9 Ordering information
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (speed, package, etc) or for further information on any aspect
of this device, please contact the Numonyx Sales Office nearest to you.
Table 27. Ordering informat io n scheme
Example: M58BW32F T 4 T 3 T
Device type
M58
Architecture
B = Burst mode
O per a t in g vo l tag e
W = [2.7 V to 3.6 V] VDD range for 45 ns speed class
[2.5 V to 3.3 V] VDD range for 55 ns speed class
[2.4 V to VDD] VDDQ range for 45 ns and 55 ns speed classes
Device function
32F = 32 Mbit (x 32), boot block, burst, 0.11 μm technology
16F = 16 Mbit (x 32), boot block, burst, 0.11 μm technology
Array matrix
T = Top boot
B = Bottom boot
Speed
4 = 45 ns
5 = 55 ns
Package
T = PQFP80
ZA = LBGA80, 1.0 mm pitch
Device grade
3 = Automotive grade certified(1), –40 to 125 °C
1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening
according to AEC Q001 & Q002 or equivalent.
Option
Blank = Standard packing
T = Tape & reel packing
F = ECOPACK® package, tape & reel 24 mm packing
Flowcharts M58BW16F, M58BW32F
68/87
Appendix A Flowcharts
Figure 26. Program flowc hart and ps eudoc ode
1. If an error is found, the Status Register must be cleared before further P/E operations.
Write 40h
AI03850e
Start
Write Address
& Data
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
NO
b4 = 0
PEN Invalid
Error (1)
Program
Error (1)
Program command:
– write 40h, Address AAh
– write Address & Data
(memory enters read status
state after the Program command)
do:
– read status register
(E or G must be toggled)
while b7 = 1
If b3 = 1, PEN invalid error:
– error handler
If b4 = 1, Program error:
– error handler
YES
End
NO
b1 = 0 Program to Protect
Block Error If b1 = 1, Program to Protected Block Error:
– error handler
YES
M58BW16F, M58BW32F Flowcharts
69/87
Figure 27. Program Suspen d & Resume f lowcha rt and pseudocode
Write 70h
AI00612b
Read Status
Register
YES
NO
b7 = 1
YES
NO
b2 = 1
Program Continues
Write FFh
Program/Erase Suspend command:
– write B0h
– write 70h
do:
– read status register
while b7 = 1
If b2 = 0, Program completed
Read Memory Array command:
– write FFh
– one or more data reads
from other blocks
Write D0h Program Erase Resume command:
– write D0h
to resume programming
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
Read data from
another block
Start
Write B0h
Program Complete
Write FFh
Read Data
Flowcharts M58BW16F, M58BW32F
70/87
Figure 28. Block Erase flowchart and pseudocode
1. If an error is found, the Status Register must be cleared before further Program/Erase operations.
Write 20h
AI08623d
Start
Write Block Address
& D0h
Read Status
Register
YES
NO
b7 = 1
YES
NO
b3 = 0
YES
b4 and b5
= 1
PEN Invalid
Error (1)
Command
Sequence Error
Erase command:
– write 20h, Address 55h
– write Block Address
(A11-A19) & D0h
(memory enters read status
state after the Erase command)
do:
– read status register
(E or G must be toggled)
if Erase command given execute
suspend erase loop
while b7 = 1
If b3 = 1, PEN invalid error:
– error handler
If b4, b5 = 1, Command Sequence error:
– error handler
NO
NO
b5 = 0 Erase
Error (1)
YES
NO
Suspend
Suspend
Loop
If b5 = 1, Erase error:
– error handler
YES
End
YES
NO
b1 = 0 Erase to Protected
Block Error If b1 = 1, Erase to Protected Block Error:
– error handler
M58BW16F, M58BW32F Flowcharts
71/87
Figure 29. Erase Suspend & Resum e flowc hart and pseudocode
Write 70h
AI00615c
Read Status
Register
YES
NO
b7 = 1
YES
NO
b6 = 1
Erase Continues
Write FFh
Program/Erase Suspend command
Do:
– Read status register while b7 = 1
(b7 = Program/Erase status bit)
If b6 = 0, Erase is completed
(b6 = Erase Suspend status bit)
Read Memory Array command:
– Write FFh
– One or more data reads
from other blocks
Write D0h
Read data from
another block
or Program
Erase cycle in progress
Write B0h
Erase Complete
Write FFh
Read Data
Program/Erase Resume command:
– Write D0h to resume the Erase
operation
The device returns to Read mode as normal
(as if the Program/Erase Suspend was not issued).
Flowcharts M58BW16F, M58BW32F
72/87
Figure 30. Power-up sequ ence follo wed by Synchron ous B urst Read
AI03834
Power-up
or Reset
Asynchronous Read
Write 60h command
Write 03h with A15-A0
BCR inputs
Synchronous Read
BCR bit 15 = '1'
Set Burst Configuration Register command:
– write 60h
– write 03h
and BCR on A15-A0
BCR bit 15 = '0'
BCR bit 14-bit 0 = '1'
M58BW16F, M58BW32F Flowcharts
73/87
Figure 31. Command interface and Prog ram/Erase cont rolle r flowc hart (a)
AI03835
READ ELEC.
SIGNATURE
YES
NO
90h
READ
STATUS
YES
70h NO
ERASE
SET-UP
YES
20h NO
PROGRAM
SET-UP
YES
40h NO
CLEAR
STATUS
YES
50h NO
WAIT FOR
COMMAND
WRITE
READ
STATUS
READ
ARRAY
YES
D
B
C
READ CFI
YES
98h NO
NO D0h
A
ERASE
COMMAND
ERROR E
D
Flowcharts M58BW16F, M58BW32F
74/87
Figure 32. Command interface and Prog ram/Erase cont rolle r flowc hart (b)
AI03836
TP
PROGRAM
SET_UP
YES
NO
48h
SET BCR
SET_UP
YES
60h NO
D
TP
UNLOCK
SET_UP
YES
78h NO
FFh
03h
NO
YES
NO
E
F
G
YES
M58BW16F, M58BW32F Flowcharts
75/87
Figu r e 33. Command interface an d Program/Eras e cont ro l ler flowchart (c)
READ
STATUS
70h
B
ERASE
READY
NO
A
B0h NO READ
STATUS
YES READY
NO
ERASE
SUSPEND
YES
READ
ARRAY
YES
ERASE
SUSPENDED
READ
STATUS YES
NO
40h
NO
D0h
NO
PROGRAM
SET_UP
AI03837
YES
YES
NO YES READ
STATUS
C
Flowcharts M58BW16F, M58BW32F
76/87
Figu r e 34. Command interface an d Program/Eras e cont ro l ler flowchart (d )
READ
STATUS
70h
B
PROGRAM
READY
NO
C
B0h NO READ
STATUS
YES READY
NO
PROGRAM
SUSPEND
READ
ARRAY
YES
PROGRAM
SUSPENDED
READ
STATUS YES
NO
NO
D0h
AI03838
YES
NO YES READ
STATUS
YES
M58BW16F, M58BW32F Flowcharts
77/87
Figu r e 35. Command interface an d Program/Eras e cont ro l ler flowchart (e)
B
TP
PROGRAM
READY
F
NO READ
STATUS
AI03839
YES
B
TP
UNLOCK
READY
G
NO READ
STATUS
YES
Common Fl ash interface (CFI) M58 BW16F , M58BW32F
78/87
Appendix B Common Flash interface (CFI)
The common Flash interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query command (RCFI) is issued the device enters CFI Query mode and the
data structure is read from the memory. Tab le 2 8, Table 29, Tab le 30, Tab le 33 and Ta bl e 3 2
show the addresses used to retrieve the data.
Table 28. Query structu re overview
Offset Sub-section name Description
00h 0020h Manufacturer code Numonyx
01h
883A
8839
8838
8837
Device code
M58BW16FT (top)
M58BW16FB (bottom)
M58BW32FT (top)
M58BW32FB (bottom)
10h CFI query identification string Command set ID and algorithm data offset
1Bh System interface information Device timing and voltage information
27h Device geometry definition Flash memory layout
P(h)(1)
1. Offset 15h defines P which points to the primary algorithm extended query address table.
Primary algorithm-specific extended query
table
Additional information specific to the
primary algorithm (optional)
A(h)(2)
2. Offset 19h defines A which points to the alternate algorithm extended query address table.
Alternate algorithm-specific extended query
table
Additional information specific to the
alternate algorithm (optional)
M5 8BW16F, M5 8BW32F Common Fla sh int erface (CF I )
79/87
Table 29. CFI - Query address and data output(1)(2)
1. The x 8 or byte address and the x 16 or word address mode are not available.
2. Query data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'.
Address A0-Amax Data Instruction
10h 51h "Q" 51h; "Q"
Query ASCII string 52h; "R"
59h; "Y"
11h 52h "R"
12h 59h "Y"
13h 03h Primary vendor:
Command set and control interface ID code
14h 00h
15h 35h (M58BW16F)
39h (M58BW32F) Primary algorithm extended query address table:
P(h)
16h 00h
17h 00h Alternate vendor:
Command set and control interface ID code
18h 00h
19h 00h Alternate algorithm extended query address table
1Ah 00h
Tabl e 30. CFI - device voltage and timin g sp ecifi cation
Address
A0-Amax Data Description Value
1Bh 27h(1)
1. Bits are coded in binary code decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
VDD min 2.7 V
1Ch 36h(1) VDD max 3.6 V
1Dh xxxx xxxxh Reserved
1Eh xxxx xxxxh Reserved
1Fh 04h 2n μs typical for word, double word program 16 μs
20h xxxx xxxxh Reserved
21h 0Ah 2n ms, typical time-out for Erase Block 1 s
22h xxxx xxxxh Reserved
23h xxxx xxxxh Reserved
24h xxxx xxxxh Reserved
25h xxxx xxxxh Reserved
26h xxxx xxxxh Reserved
Common Fl ash interface (CFI) M58 BW16F , M58BW32F
80/87
Table 31. M58BW16F device geometry definition
Address A0-Amax Data Description Value
27h 15h 2n number of bytes memory size 2 Mbytes
28h 03h Device interface sync./async. x 32
29h 00h Organization sync./async. Async.
2Ah 00h Maximum number of byte in multi-byte program = 2n32 bytes
2Bh 00h
2Ch 02h Bit7-0 = number of Erase Block regions in device 2
2Dh 1Eh Number (n-1) of Erase Blocks of identical size; n=31 31 blocks
2Eh 00h
2Fh 00h Erase Block region information x 256 bytes per Erase
Block (64 Kbytes) 512 Kbits
30h 01h
31h 07h Number (n-1) of Erase Blocks of identical size; n=8 8 blocks
32h 00h
33h 20h Erase Block region information x 256 bytes per Erase
Block (8 Kbytes) 64 Kbits
34h 00h
M5 8BW16F, M5 8BW32F Common Fla sh int erface (CF I )
81/87
Table 32. M58BW16F extended query information
Addre ss offset Address
Amax-A0 Data (hex) Description
(P)h 35h 50 P
Query ASCII string - extended table(P+1)h 36h 52 R
(P+2)h 37h 49 Y
(P+3)h 38h 31h Major revision number
(P+4)h 39h 31h Minor revision number
(P+5)h 3Ah 86h
Optional feature: (1=yes, 0=no)
bit0, Chip Erase supported (0= no)
bit1, Suspend Erase supported (1=yes)
bit2, Suspend Program supported (1=yes)
bit3, Lock/Unlock supported (0=no)
bit4, Queue Erase supported (0=no)
bit5, Instant individual block locking (0=no)
bit6, Protection bits supported (0=no)
bit7, Page Read supported (1=yes)
bit8, Synchronous Read supported (1=yes)
Bit9, Reserved
(P+6)h 3Bh 01h
Synchronous Read supported(P+7)h 3Ch 00h
(P+8)h 3Dh 00h
(P+9)h 3Eh 01h
Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
(P+A)h-(P+D)h 3Fh-42h Reserved
(P+13)h-(P+40)h 48h-7Fh Reserved
(P+41)h 80h xxxx xxxxh Unique device ID - 1 (16 bits)
(P+42)h 81h xxxx xxxxh Unique device ID - 2 (16 bits)
(P+43)h 82h xxxx xxxxh Unique device ID - 3 (16 bits)
(P+44)h 83h xxxx xxxxh Unique device ID - 4 (16 bits)
Common Fl ash interface (CFI) M58 BW16F , M58BW32F
82/87
Table 33. M58BW32F device geometry definition
Address A0-Amax Data Description Value
27h 15h 2n number of bytes memory size 4 Mbytes
28h 03h Device interface sync./async. x 32
29h 00h Organization sync./async. Async.
2Ah 00h Maximum number of byte in multi-byte program = 2n32 bytes
2Bh 00h
2Ch 02h Bit7-0 = number of Erase Block regions in device 3
2Dh 1Eh Number (n-1) of Erase Block regions of identical size;
n = 31 62 blocks
2Eh 00h
2Fh 00h Erase Block region information x 256 bytes per Erase
Block (64 Kbytes) 512 Kbits
30h 01h
31h 07h Number (n-1) of Erase blocks of identical size; n = 8 8 blocks
32h 00h
33h 20h Erase Block region information x 256 bytes per Erase
Block (8 Kbytes) 64 Kbits
34h 00h
35h 03h Number (n-1) of Erase Block of identical size; n = 8 8 blocks
36h 00h
37h 40h Erase Block region information x 256 bytes per Erase
block (16 Kbytes) 128 Kbits
38h 00h
M5 8BW16F, M5 8BW32F Common Fla sh int erface (CF I )
83/87
Tabl e 34. M58BW32F extend ed query in formati o n
Address offset Address
Amax-A0 Data (hex) Descripti on
(P)h 39h 50 P
Query ASCII string - extended table(P+1)h 3Ah 52 R
(P+2)h 3Bh 49 Y
(P+3)h 3Ch 31h Major revision number
(P+4)h 3Dh 31h Minor revision number
(P+5)h 3Eh 86h
Optional feature: (1=yes, 0=no)
bit0, Chip Erase supported (0= no)
bit1, Suspend Erase supported (1=yes)
bit2, Suspend Program supported (1=yes)
bit3, Lock/Unlock supported (0=no)
bit4, Queue Erase supported (0=no)
bit5, Instant individual block locking (0=no)
bit6, Protection bits supported (0=no)
bit7, Page Read supported (1=yes)
bit8, Synchronous Read supported (1=yes)
Bit 9, Reserved
(P+6)h 3Fh 01h
Synchronous Read supported(P+7)h 40h 00h
(P+8)h 41h 00h
(P+9)h 42h 01h
Function allowed after Suspend:
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
(P+A)h-(P+D)h 43h-46h Reserved
(P+13)h-(P+40)h 4Ch-7Fh Reserved
(P+41)h 80h xxxx xxxxh Unique device ID - 1 (16 bits)
(P+42)h 81h xxxx xxxxh Unique device ID - 2 (16 bits)
(P+43)h 82h xxxx xxxxh Unique device ID - 3 (16 bits)
(P+44)h 83h xxxx xxxxh Unique device ID - 4 (16 bits)
Common Fl ash interface (CFI) M58 BW16F , M58BW32F
84/87
Table 35. Prote ction reg i ster informatio n
Address
A0-Amax
Data
Instruction
Value
M58BW16FT
M58BW16FB
M58BW32FT
M58BW32FB
M58BW16FT
M58BW16FB
M58BW32FT
M58BW32FB
(P+E)h 0x02
0x02
0x01
0x01
Number of Protection
register field in JEDEC
ID space, Block region
information X256 bytes
2x64Kb
2x64Kb
1x128Kb
1x128Kb
(P+F)h 0x01
0xFE
0x01
0xFE
Protection field: this field
describes user-available
OTP Protection Register
bytes.
Bits 7-0=physical low
address
Bits 15-8=physical high
address
Bits 23-16=’n’,
2n=Factory pre-
programmed bytes
Bits 31-24=’n’, 2n=user
programmable bytes
--
(P+10)h 0x01
0xFE
0x01
0xFE --
(P+11)h 0x0
0x0
0x0
0x0 --
x256 0x12
0x12
0x12
0x12
2x64Kb
2x64Kb
1x128Kb
1x128Kb
M58BW16F, M58BW32F Block protection
85/87
Appendix C Block protection
OTP protection
The OTP protection is an user-enabled feature that permanently protects specific blocks, so
called “OTP blocks”, against modify operations (program/erase). It is available:
on one specific 128-kbit parameter block in the M58BW32F- block 1 (01000h-01FFFh)
for bottom devices or block 72 (FE000h-FEFFFh) for top devices
on two specific 64-kbit parameter blocks in the M58BW16F- block 2 and 3 (01000h-
01FFFh) for bottom devices or block 36 and 35 (7E000h-7EFFFh) for top devices.
The default state is unprotected. However, once the protection has been enabled, it is
impossible to disable it and the OTP blocks will remain “modify protected” for ever.
Obviously, this information is stored in internal non volatile registers.
Activation seque nce
If the user wants to make the OTP protection effective on a part, he has to issue the Lock
OTP protection command.
The Lock OTP protection requires 2 write cycles:
write (ADD=000AAh, DATA=49h) - Lock OTP Protection command 1
write (ADD=00003h, DATA=0000 0000h) - Lock OTP Protection command 2
This sequence of commands has to be given with the Tuning Protection unlocked (if this
protection is enabled on the part) and with Write Protect Enable WP_N=’1’. The user can
check its execution polling on the SR in the same way as a normal Program Word
command.
The program duration lasts about 35 μs like for a standard Program Word command. It is
also possible to detect the end of the operation by polling the Status Register.
Any Erase attempt returns A3h in the Status Register while any Program attempt returns
93h.
Once the first write cycle of the Lock OTP protection command is issued, a wrong address
on second write cycle will cause the activation sequence to fail. The Status Register allows
detecting this event and its value is then B1h (invalid sequence).
As a consequence, the protection is not active and the sequence must be restarted.
The Lock OTP Protection command cannot be suspended.
Revisio n h istory M58 BW16F , M58BW32F
86/87
10 Revision history
Table 36. Document revision history
Date Revision Changes
09-Jun-2006 1Initial release.
23-Nov-2006 2
VPEN signal renamed as PEN and Program/Erase Enable (PEN)
modified.
Continuous burst and wrap options are not available, X-Latencies
7 and 8 removed (see Table 8: Burst Configuration Register and
Table 9: Burst type definition). Notes removed below Table 8.
tWHQV timing modified in Table 21: Asynchronous Write and Latch
controlled Write AC characteristics.
IDD max modified and IDD4 added to Table 18: DC characteristics.
tAXQX modified in Table 20: Asynchronous Page Read AC
characteristics.
Read access specified in Asynchronous Bus Read and
Synchronous Burst Read.
tAVKH and tALKH added and tKHQV for 55 ns modified in Table 22:
Synchronous Burst Read AC characteristics. Figure 9, Figure 10,
Figure 18 and Figure 19 added. Double Word Program max
modified and Minimum effective erase time added to Table 12:
Program, Erase times and endurance cycles.
All Asynchronous Bus Read AC characteristics brought together in
Table 19: Asynchronous Bus Read AC characteristics. tLLEL
removed from Table 19 and Figure 7. Appendix B: Common Flash
interface (CFI) modified.
01-Oct-2007 3
Table 8: Burst Configuration Register, Table 30: CFI - device
voltage and timing specification and Table 33: M58BW32F device
geometry definition updated.
Minimum values for tKHKL, tKLKH and tLLKH modified in Table 22:
Synchronous Burst Read AC characteristics.
tPHLL, tPHRH, tVDHPH, tWLRH, tGLRH, tELRH, and tLLRH added in
Table 24: Reset, Power-down and Power-up AC characteristics.
tPLRH removed from Table 24.
Modified Figure 22: Reset, Power-down and Power-up AC
waveforms - Control pins Low and Section 3.3.3: X-Latency bits
(M13-M11).
Appendix C: Block protection, Figure 23: Reset, Power-down and
Power-up AC waveforms - Control pins toggling and Table 35:
Protection register information added.
15-Jan-2008 4
Updated mechanical data of the LBGA package and Table 8: Burst
Configuration Register, Table 12: Program, Erase times and
endurance cycles, Table 18: DC characteristics, Table 21:
Asynchronous Write and Latch controlled Write AC characteristics,
Table 22: Synchronous Burst Read AC characteristics, and
Section 2.7: Reset/Power-down (RP).
Added Figure 21: Power supply slope specification and Tab l e 23:
Power supply AC and DC characteristics.
Minor text changes.
M58BW16F, M58BW32F Revision history
87/87
19-Mar-2008 5 Applied Numonyx branding.
3-August-2009 6 Minor text updates.
Table 36. Document revision history
Date Revision Changes
M58BW16F, M58BW32F
88/87
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