M58BW16F M58BW32F 16 or 32 Mbit (x 32, boot block, burst) 3.3 V supply Flash memories Features Supply voltage - VDD = 2.7 V to 3.6 V (45 ns) or VDD = 2.5 V to 3.3 V (55 ns) - VDDQ = VDDQIN = 2.4 V to 3.6 V for I/O buffers High performance - Access times: 45 and 55 ns - Synchronous burst reads - 75 MHz effective zero wait-state burst read - Asynchronous page reads PQFP80 (T) LBGA M58BW32F memory organization: - Eight 64 Kbit small parameter blocks - Four 128 Kbit large parameter blocks - Sixty-two 512 Kbit main blocks LBGA80 (ZA) 10 x 8 ball array M58BW16F memory organization: - Eight 64 Kbit parameter blocks - Thirty-one 512 Kbit main blocks Hardware block protection - WP pin to protect any block combination from Program and Erase operations - PEN signal for Program/Erase Enable Irreversible modify protection (OTP like) on 128 Kbits: - Block 1 (bottom device) or block 72 (top device) in the M58BW32F - Blocks 2 and 3 (bottom device) or blocks 36 and 35 (top device) in the M58BW16F Security - 64-bit unique device identifier (UID) Fast programming - Write to buffer and program capability - 100 A typical Standby current Electronic signature - Manufacturer code: 0020h - Top device codes: M58BW32FT: 8838h M58BW16FT: 883Ah - Bottom device codes: M58BW32FB: 8837h M58BW16FB: 8839h Automotive device grade 3: - Temperature: -40 to 125 C - Automotive grade certified Optimized for FDI drivers - Common Flash interface (CFI) - Fast Program/Erase Suspend feature in each block Low power consumption August 2009 Rev 6 1/87 www.numonyx.com 1 Contents M58BW16F, M58BW32F Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 2 3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 Data inputs/outputs (DQ0-DQ31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5 Output Disable (GD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.7 Reset/Power-down (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.8 Program/Erase Enable (PEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.9 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.10 Burst Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.11 Burst Address Advance (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.12 Valid Data Ready (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.13 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.14 Supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.15 Output supply voltage (VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.16 Input supply voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.17 Ground (VSS and VSSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.18 Don't use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.19 Not connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 2/87 Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Asynchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.2 Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . 24 3.1.3 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.4 Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.5 Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . 25 3.1.6 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M58BW16F, M58BW32F Contents 3.1.7 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.8 Reset/Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 3.3 4 5 Synchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.2 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 Read Select bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.2 Standby Disable bit (M14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.3 X-Latency bits (M13-M11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.4 Y-Latency bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.5 Valid Data Ready bit (M8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6 Wrap Burst bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.7 Burst Length bit (M2-M0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.7 Erase All Main Blocks command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.8 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.9 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.12 Set Burst Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . 38 4.13 Set Block Protection Configuration Register command . . . . . . . . . . . . . . 38 4.14 Clear Block Protection Configuration Register command . . . . . . . . . . . . 38 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 Program/Erase Controller Status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 Erase Suspend Status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 Erase Status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4 Program/Write to Buffer and Program Status (bit 4) . . . . . . . . . . . . . . . . . 42 3/87 Contents M58BW16F, M58BW32F 5.5 PEN Status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6 Program Suspend Status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.7 Block Protection Status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.8 Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Appendix A Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10 4/87 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 M58BW16F, M58BW32F List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M58BW32F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 M58BW32F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M58BW16F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 M58BW16F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Asynchronous Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Synchronous Burst Read Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Burst Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Program, Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Asynchronous Bus Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Asynchronous Page Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Asynchronous Write and Latch controlled Write AC characteristics . . . . . . . . . . . . . . . . . . 54 Synchronous Burst Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power supply AC and DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset, Power-down and Power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 LBGA80 10 x 12 mm - 8 x 10 active ball array, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PQFP80 - 80 lead plastic quad flat pack, package mechanical data . . . . . . . . . . . . . . . . . 66 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CFI - Query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 CFI - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 M58BW16F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M58BW16F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 M58BW32F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 M58BW32F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5/87 List of figures M58BW16F, M58BW32F List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. 6/87 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 LBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PQFP connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Example burst configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Asynchronous Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Asynchronous Latch Controlled Bus Read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 48 Asynchronous Chip Enable Controlled Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . 49 Asynchronous Address Controlled Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . 49 Asynchronous Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Asynchronous Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Asynchronous Latch controlled Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Synchronous Burst Read, Latch Enable controlled (data valid from 'n' clock rising edge) . 55 Synchronous Burst Read, Chip Enable controlled (data valid from 'n' clock rising edge) . 56 Synchronous Burst Read, Valid Address transition controlled (data valid from 'n' clock rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Synchronous Burst Read (data valid from 'n' clock rising edge). . . . . . . . . . . . . . . . . . . . . 58 Synchronous Burst Read - valid data ready output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Synchronous Burst Read - Burst Address Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Power supply slope specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Reset, Power-down and Power-up AC waveforms - Control pins Low. . . . . . . . . . . . . . . . 62 Reset, Power-down and Power-up AC waveforms - Control pins toggling. . . . . . . . . . . . . 62 LBGA80 10 x 12 mm - 8 x 10 ball array, 1 mm pitch, bottom view package outline . . . . . 64 PQFP80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 66 Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Program Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 69 Block Erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Erase Suspend & Resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power-up sequence followed by Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . 72 Command interface and Program/Erase controller flowchart (a) . . . . . . . . . . . . . . . . . . . . 73 Command interface and Program/Erase controller flowchart (b) . . . . . . . . . . . . . . . . . . . . 74 Command interface and Program/Erase controller flowchart (c) . . . . . . . . . . . . . . . . . . . . 75 Command interface and Program/Erase controller flowchart (d) . . . . . . . . . . . . . . . . . . . . 76 Command interface and Program/Erase controller flowchart (e) . . . . . . . . . . . . . . . . . . . . 77 M58BW16F, M58BW32F 1 Description Description The M58BW16F and M58BW32F are 16 and 32 Mbit non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a double-word basis using a 2.7 V to 3.6 V or 2.5 V to 3.3 V VDD supply for the circuit and a 2.4 V to 3.6 V VDDQ supply voltage for the input and output buffers. In the rest of the document the M58BW16F and M58BW32F will be referred to as M58BWxxF unless otherwise specified. The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read interface allows a high data transfer rate controlled by the Burst Clock signal, K. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. All write operations are asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus. The device features an asymmetrical block architecture: The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large parameter blocks of 128 Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small parameter blocks are located either at the top (M58BW32FT) or at the bottom (M58BW32FB) of the address space. The first large parameter block is referred to as boot block and can be used either to store a boot code or parameters. The memory array organization is detailed in Table 2: M58BW32F top boot block addresses and Table 3: M58BW32F bottom boot block addresses. The M58BW16F has an array of 8 parameter blocks of 64 Kbits each and 31 main blocks of 512 Kbits each. In the M58BW16FT the parameter blocks are located at the top of the address space whereas in the M58BW16FB, they are located at the bottom. The memory array organization is detailed in Table 4: M58BW16F top boot block addresses and Table 5: M58BW16F bottom boot block addresses. Program and Erase commands are written to the command interface of the memory. An onchip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. Erase can be suspended in order to perform either Read or Program in any other block, and then resumed. Program can be suspended to Read data in any other block, and then resumed. Each block can be programmed and erased over 100,000 cycles. 7/87 Description M58BW16F, M58BW32F All blocks are protected during power-up. The M58BWxxF features five different levels of hardware and software block protection to avoid unwanted Program/Erase operations: Write/Protect Enable input, WP, hardware protects a combination of blocks from Program and Erase operations. The blocks to be protected are configured individually by issuing a Set Block Protection Configuration Register or a Clear Block Protection Configuration Register command. All Program or Erase operations are blocked when Reset, RP, is held Low. A Program/Erase Enable input, PEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data. A permanent user-enabled protection against Modify operations is available: - on one specific 128-Kbit parameter block in the M58BW32F - block 1 for bottom devices or block 72 for top devices - on two specific 64-Kbit parameter blocks in the M58BW16F - blocks 2 and 3 for bottom devices or blocks 36 and 35 for top devices. A Reset/Power-down mode is entered when the RP input is Low. In this mode the power consumption is reduced to the standby level, the device is write protected and both the Status and Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. A manufacturer code and a device code are available. They can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. Finally, the M58BWxxF features a 64-bit unique device identifier (UID) which is programmed by Numonyx on the production line. It is unique for each die and can be used to implement cryptographic algorithms to improve security. Information is available in the CFI area (see Table 32: M58BW16F extended query information). The memory is offered in PQFP80 (14 x 20 mm) and LBGA80 (1.0 mm pitch) packages and it is supplied with all the bits erased (set to '1'). 8/87 M58BW16F, M58BW32F Figure 1. Description Logic diagram VDDQ VDDQIN VDD DQ0-DQ31 A0-Amax(1) E K PEN L RP M58BW16F M58BW32F R G GD W WP B VSS VSSQ AI13224b 9/87 Description Table 1. M58BW16F, M58BW32F Signal names Signal name Function Direction A0-Amax(1) Address inputs Inputs DQ0-DQ7 Data input/output, command input I/O DQ8-DQ15 Data input/output, Burst Configuration Register I/O DQ16-DQ31 Data input/output I/O B Burst Address Advance input Input E Chip Enable input Input G Output Enable input Input K Burst Clock input Input L Latch Enable input Input R Valid Data Ready output Output RP Reset/Power-down input Input W Write Enable input Input GD Output Disable input Input WP Write Protect input Input VDD Supply voltage VDDQ Power supply for output buffers VDDQIN Power supply for input buffers only PEN Program/Erase Enable VSS Ground VSSQ Input/output ground NC Not connected internally DU Don't use as internally connected 1. Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. 10/87 Input M58BW16F, M58BW32F Figure 2. Description LBGA connections (top view through package) 1 2 3 4 5 6 7 8 A A15 A14 VDD PEN VSS A6 A3 A2 B A16 A13 A12 A9 A8 A5 A4 A1 C A17 A18 A11 A10 NC A7 NC A0 D DQ3 DQ0 A19/ NC(1) NC NC DQ31 DQ30 DQ29 E VDDQ DQ4 DQ2 DQ1 DQ27 DQ28 DQ26 VDDQ F VSSQ DQ7 DQ6 DQ5 NC DQ25 DQ24 VSSQ G VDDQ DQ8 DQ10 DQ9 DQ22 DQ21 DQ23 VDDQ H DQ13 DQ12 DQ11 WP DQ17 DQ19 DQ18 DQ20 J DQ15 DQ14 L B E G R DQ16 K VDDQIN RP K VSS VDD W GD NC AI12854b 1. Ball D3 is NC in the M58BW16F and A19 in the M58BW32F. 11/87 Description M58BW16F, M58BW32F PQFP connections (top view through package) 1 53 40 41 DQ15 DQ14 DQ13 DQ12 VSSQ VDDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 A19/NC(1) A18 A17 A16 VSS PEN VDD A9 A10 A11 A12 A13 A14 A15 25 32 M58BW16F M58BW32F 12 24 65 64 A3 A4 A5 A6 A7 A8 DQ16 DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 DU A0 A1 A2 73 80 DU R GD WP W G E VDD B VSS L NC NC K RP VDDQIN Figure 3. AI13225b 12/87 M58BW16F, M58BW32F 1.1 Description Block protection The M58BWxxF features four different levels of block protection. Write Protect pin, WP, - When WP is Low, VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. The Block Protection Configuration Register is volatile. Any combination of blocks is possible. Any attempt to program or erase a protected block will return an error in the Status Register (see Table 13: Status Register bits). Reset/Power-down pin, RP, - If the device is held in reset mode (RP at VIL), no Program or Erase operation can be performed on any block. Program/Erase Enable, PEN, - The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase operations from modifying the data. Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to High (VIH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is generated in the Status Register. Permanent protection against modify operations - specific OTP-like blocks can be permanently protected against modify operations (Program/Erase): - - in the M58BW32F, a unique 128-Kbit parameter block - block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices in the M58BW16F, two 64-Kbit parameter blocks - blocks 2 and 3 (01000h01FFFh) for bottom devices or blocks 36 and 35 (7E000h-7EFFFh) for top devices This protection is user-enabled. Details of how this protection is activated are provided in a dedicated application note. After a device reset the first two kinds of block protection (WP, RP) can be combined to give a flexible block protection. All blocks are protected at power-up. 13/87 Description M58BW16F, M58BW32F Table 2. 14/87 M58BW32F top boot block addresses # Size (Kbit) Address range(1) 73 128 FF000h-FFFFFh 72 128 FE000h-FEFFFh(2) 71 128 FD000h-FDFFFh 70 128 FC000h-FCFFFh 69 64 FB800h-FBFFFh 68 64 FB000h-FB7FFh 67 64 FA800h-FAFFFh 66 64 FA000h-FA7FFh 65 64 F9800h-F9FFFh 64 64 F9000h-F97FFh 63 64 F8800h-F8FFFh 62 64 F8000h-F87FFh 61 512 F4000h-F7FFFh 60 512 F0000h-F3FFFh 59 512 EC000h-EFFFFh 58 512 E8000h-EBFFFh 57 512 E4000h-E7FFFh 56 512 E0000h-E3FFFh 55 512 DC000h-DFFFFh 54 512 D8000h-DBFFFh 53 512 D4000h-D7FFFh 52 512 D0000h-D3FFFh 51 512 CC000h-CFFFFh 50 512 C8000h-CBFFFh 49 512 C4000h-C7FFFh 48 512 C0000h-C3FFFh 47 512 BC000h-BFFFFh 46 512 B8000h-BBFFFh 45 512 B4000h-B7FFFh 44 512 B0000h-B3FFFh 43 512 AC000h-AFFFFh 42 512 A8000h-ABFFFh 41 512 A4000h-A7FFFh 40 512 A0000h-A3FFFh 39 512 9C000h-9FFFFh 38 512 98000h-9BFFFh 37 512 94000h-97FFFh 36 512 90000h-93FFFh M58BW16F, M58BW32F Table 2. Description M58BW32F top boot block addresses (continued) Size (Kbit) Address range(1) 35 512 8C000h-8FFFFh 34 512 88000h-8BFFFh 33 512 84000h-87FFFh 32 512 80000h-83FFFh 31 512 7C000h-7FFFFh 30 512 78000h-7BFFFh 29 512 74000h-77FFFh 28 512 70000h-73FFFh 27 512 6C000h-6FFFFh 26 512 68000h-6BFFFh 25 512 64000h-67FFFh 24 512 60000h-63FFFh 23 512 5C000h-5FFFFh 22 512 58000h-5BFFFh 21 512 54000h-57FFFh 20 512 50000h-53FFFh 19 512 4C000h-4FFFFh 18 512 48000h-4BFFFh 17 512 44000h-47FFFh 16 512 40000h-43FFFh 15 512 3C000h-3FFFFh 14 512 38000h-3BFFFh 13 512 34000h-37FFFh 12 512 30000h-33FFFh 11 512 2C000h-2FFFFh 10 512 28000h-2BFFFh 9 512 24000h-27FFFh 8 512 20000h-23FFFh 7 512 1C000h-1FFFFh 6 512 18000h-1BFFFh 5 512 14000h-17FFFh 4 512 10000h-13FFFh 3 512 0C000h-0FFFFh 2 512 08000h-0BFFFh 1 512 04000h-07FFFh 0 512 00000h-03FFFh # 1. Addresses are indicated in 32-bit addressing. 2. OTP block. 15/87 Description M58BW16F, M58BW32F Table 3. 16/87 M58BW32F bottom boot block addresses # Size (Kbit) Address range(1) 73 512 FC000h-FFFFFh 72 512 F8000h-FBFFFh 71 512 F4000h-F7FFFh 70 512 F0000h-F3FFFh 69 512 EC000h-EFFFFh 68 512 E8000h-EBFFFh 67 512 E4000h-E7FFFh 66 512 E0000h-E3FFFh 65 512 DC000h-DFFFFh 64 512 D8000h-DBFFFh 63 512 D4000h-D7FFFh 62 512 D0000h-D3FFFh 61 512 CC000h-CFFFFh 60 512 C8000h-CBFFFh 59 512 C4000h-C7FFFh 58 512 C0000h-C3FFFh 57 512 BC000h-BFFFFh 56 512 B8000h-BBFFFh 55 512 B4000h-B7FFFh 54 512 B0000h-B3FFFh 53 512 AC000h-AFFFFh 52 512 A8000h-ABFFFh 51 512 A4000h-A7FFFh 50 512 A0000h-A3FFFh 49 512 9C000h-9FFFFh 48 512 98000h-9BFFFh 47 512 94000h-97FFFh 46 512 90000h-93FFFh 45 512 8C000h-8FFFFh 44 512 88000h-8BFFFh 43 512 84000h-87FFFh 42 512 80000h-83FFFh 41 512 7C000h-7FFFFh 40 512 78000h-7BFFFh 39 512 74000h-77FFFh 38 512 70000h-73FFFh 37 512 6C000h-6FFFFh 36 512 68000h-6BFFFh M58BW16F, M58BW32F Table 3. Description M58BW32F bottom boot block addresses (continued) # Size (Kbit) Address range(1) 35 512 64000h-67FFFh 34 512 60000h-63FFFh 33 512 5C000h-5FFFFh 32 512 58000h-5BFFFh 31 512 54000h-57FFFh 30 512 50000h-53FFFh 29 512 4C000h-4FFFFh 28 512 48000h-4BFFFh 27 512 44000h-47FFFh 26 512 40000h-43FFFh 25 512 3C000h-3FFFFh 24 512 38000h-3BFFFh 23 512 34000h-37FFFh 22 512 30000h-33FFFh 21 512 2C000h-2FFFFh 20 512 28000h-2BFFFh 19 512 24000h-27FFFh 18 512 20000h-23FFFh 17 512 1C000h-1FFFFh 16 512 18000h-1BFFFh 15 512 14000h-17FFFh 14 512 10000h-13FFFh 13 512 0C000h-0FFFFh 12 512 08000h-0BFFFh 11 64 07800h-07FFFh 10 64 07000h-077FFh 9 64 06800h-06FFFh 8 64 06000h-067FFh 7 64 05800h-05FFFh 6 64 05000h-057FFh 5 64 04800h-04FFFh 4 64 04000h-047FFh 3 128 03000h-03FFFh 2 128 02000h-02FFFh 1 128 01000h-01FFFh(2) 0 128 00000h-00FFFh 1. Addresses are indicated in 32-bit word addressing. 2. OTP block. 17/87 Description M58BW16F, M58BW32F Table 4. # Size (Kbit) Address range 38 64 7F800h-7FFFFh 37 64 7F000h-7F7FFh (1) 64 7E800h-7EFFFh (1) 64 7E000h-7E7FFh 34 64 7D800h-7DFFFh 33 64 7D000h-7D7FFh 32 64 7C800h-7CFFFh 31 64 7C000h-7C7FFh 30 512 78000h-7BFFFh 29 512 74000h-77FFFh 28 512 70000h-73FFFh 27 512 6C000h-6FFFFh 26 512 68000h-6BFFFh 25 512 64000h-67FFFh 24 512 60000h-63FFFh 23 512 5C000h-5FFFFh 22 512 58000h-5BFFFh 21 512 54000h-57FFFh 20 512 50000h-53FFFh 19 512 4C000h-4FFFFh 18 512 48000h-4BFFFh 17 512 44000h-47FFFh 36 35 16 512 40000h-43FFFh 15 512 3C000h-3FFFFh 14 512 38000h-3BFFFh 13 512 34000h-37FFFh 12 512 30000h-33FFFh 11 512 2C000h-2FFFFh 10 512 28000h-2BFFFh 9 512 24000h-27FFFh 8 512 20000h-23FFFh 7 512 1C000h-1FFFFh 6 512 18000h-1BFFFh 5 512 14000h-17FFFh 4 512 10000h-13FFFh 3 512 0C000h-0FFFFh 2 512 08000h-0BFFFh 1 512 04000h-07FFFh 0 512 00000h-03FFFh 1. OTP block. 18/87 M58BW16F top boot block addresses M58BW16F, M58BW32F Table 5. # Description M58BW16F bottom boot block addresses Size (Kbit) Address range 38 512 7C000h-7FFFFh 37 512 78000h-7BFFFh 36 512 74000h-77FFFh 35 512 70000h-73FFFh 34 512 6C000h-6FFFFh 33 512 68000h-6BFFFh 32 512 64000h-67FFFh 31 512 60000h-63FFFh 30 512 5C000h-5FFFFh 29 512 58000h-5BFFFh 28 512 54000h-57FFFh 27 512 50000h-53FFFh 26 512 4C000h-4FFFFh 25 512 48000h-4BFFFh 24 512 44000h-47FFFh 23 512 40000h-43FFFh 22 512 3C000h-3FFFFh 21 512 38000h-3BFFFh 20 512 34000h-37FFFh 19 512 30000h-33FFFh 18 512 2C000h-2FFFFh 17 512 28000h-2BFFFh 16 512 24000h-27FFFh 15 512 20000h-23FFFh 14 512 1C000h-1FFFFh 13 512 18000h-1BFFFh 12 512 14000h-17FFFh 11 512 10000h-13FFFh 10 512 0C000h-0FFFFh 9 512 08000h-0BFFFh 8 512 04000h-07FFFh 7 64 03800h-03FFFh 6 64 03000h-037FFh 5 64 02800h-02FFFh 4 64 02000h-027FFh (1) 64 01800h-01FFFh (1) 64 01000h-017FFh 1 64 00800h-00FFFh 0 64 00000h-007FFh 3 2 1. OTP block. 19/87 Signal descriptions 2 M58BW16F, M58BW32F Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-Amax) Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F. The Address inputs are used to select the cells to access in the memory array during Bus operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. Chip Enable must be Low when selecting the addresses. The Address inputs are latched on the rising edge of Latch Enable L or Burst Clock K, whichever occurs first, in a Read operation. The Address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is Low, VIL. The address is internally latched in an Erase or Program operation. 2.2 Data inputs/outputs (DQ0-DQ31) The Data inputs/outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the command interface of the Program/Erase controller. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both Low, VIL, and Output Disable is at VIH, the data bus outputs data from the memory array, the Electronic Signature, the Block Protection Configuration Register, the CFI information or the contents of Burst Configuration Register or Status Register. The data bus is high impedance when the device is deselected with Chip Enable at VIH, Output Enable at VIH, Output Disable at VIL or Reset/Power-down at VIL. The Status Register content is output on DQ0-DQ7 and DQ8-DQ31 are at VIL. 2.3 Chip Enable (E) The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the standby level. 2.4 Output Enable (G) The Output Enable, G, gates the outputs through the data output buffers during a Read operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs are high impedance independently of Output Disable. 20/87 M58BW16F, M58BW32F 2.5 Signal descriptions Output Disable (GD) The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the outputs are high impedance independently of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. 2.6 Write Enable (W) The Write Enable, W, input controls writing to the command interface, input address and data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L). 2.7 Reset/Power-down (RP) The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-down Low, VIL, for at least tPLPH. Writing is inhibited to protect data, the command interface and the Program/Erase controller are reset. The Status Register information is cleared and power consumption is reduced to the standby level (IDD1). The device acts as deselected, that is the data outputs are high impedance. After Reset/Power-down goes High, VIH, the memory will be ready for Bus Read operations after a delay of tPHEL or Bus Write operations after tPHWL. If Reset/Power-down goes Low, VIL, during a Block Erase or a Program operation, the internal state machine handles the operation as a Program/Erase Suspend, so the maximum time defined inTable 12: Program, Erase times and endurance cycles must be applied. During power-up power should be applied simultaneously to VDD and VDDQIN with RP held at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up. In an application, it is recommended to associate the Reset/Power-down pin, RP, with the reset signal of the microprocessor. Otherwise, if a Reset operation occurs while the memory is performing an Erase or program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read mode. See Table 24 and Figure 22: Reset, Power-down and Power-up AC waveforms - Control pins Low, for more details. 2.8 Program/Erase Enable (PEN) The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase operations from modifying the data. Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to High (VIH). If it is Low (VIL), the Program or Erase operation is not accepted and an error is generated in the Status Register. 21/87 Signal descriptions 2.9 M58BW16F, M58BW32F Latch Enable (L) The Bus Interface can be configured to latch the Address inputs on the rising edge of Latch Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst Read operations. In Synchronous Burst Read operations the address is latched on the active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read and Write operations. 2.10 Burst Clock (K) The Burst Clock, K, is used to synchronize the memory with the external bus during Synchronous Burst Read operations. Bus signals are latched on the active edge of the Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge when Latch Enable is Low, VIL, or on the rising edge of Latch Enable, whichever occurs first. During Asynchronous Bus Operations the Clock is not used. 2.11 Burst Address Advance (B) The Burst Address Advance, B, controls the advancing of the address by the internal address counter during Synchronous Burst Read operations. Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the Data inputs/outputs and Burst Address Advance is not sampled until the Y-latency expires. The Burst Address Advance, B, may be tied to VIL. 2.12 Valid Data Ready (R) The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready, at VIH, indicates that new data is or will be available. When Valid Data Ready is Low, VIL, the previous data outputs remain active. 2.13 Write Protect (WP) The Write Protect, WP, provides protection against Program or Erase operations. When Write Protect, WP, is at VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. Program and Erase operations to protected blocks are disabled. When Write Protect WP is at VIH all the blocks can be programmed or erased, if no other protection is used. 22/87 M58BW16F, M58BW32F 2.14 Signal descriptions Supply voltage (VDD) The supply voltage, VDD, is the core power supply. All internal circuits draw their current from the VDD pin, including the Program/Erase controller. 2.15 Output supply voltage (VDDQ) The output supply voltage, VDDQ, is the output buffer power supply for all operations (Read, Program and Erase) used for DQ0-DQ31 when used as outputs. 2.16 Input supply voltage (VDDQIN) The input supply voltage, VDDQIN, is the power supply for all input signal. Input signals are: K, B, L, W, GD, G, E, A0-Amax and DQ0-DQ31, when used as inputs. 2.17 Ground (VSS and VSSQ) The ground VSS is the reference for the internal supply voltage VDD. The ground VSSQ is the reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS and VSSQ together. Note: A 0.1 F capacitor should be connected between the supply voltages, VDD, VDDQ and VDDQIN and the grounds, VSS and VSSQ to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 18: DC characteristics, for maximum current supply requirements. 2.18 Don't use (DU) This pin should not be used as it is internally connected. Its voltage level can be between VSS and VDDQ or leave it unconnected. 2.19 Not connected (NC) This pin is not physically connected to the device. 23/87 Bus operations 3 M58BW16F, M58BW32F Bus operations Each bus operations that controls the memory is described in this section, see tables 6 and 7 Bus operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section. On power-up or after a hardware reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write. No synchronous operation can be performed until the Burst Control Register has been configured. The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read in asynchronous mode regardless of the Burst Control Register settings. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Asynchronous Bus operations For asynchronous bus operations refer to Table 6 together with the following text. The read access will start at whichever of the three following events occurs last: valid address transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL. 3.1.1 Asynchronous Bus Read Asynchronous Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Block Protection Configuration Register, Status Register, CFI and Burst Configuration Register) in the command interface. A valid bus operation involves setting the desired address on the Address inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The Data inputs/outputs will output the value, see Figure 7: Asynchronous Bus Read AC waveforms, and Table 19: Asynchronous Bus Read AC characteristics, for details of when the output becomes valid. Asynchronous Read is the default read mode which the device enters on power-up or on return from Reset/Power-down. 3.1.2 Asynchronous Latch Controlled Bus Read Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the command interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address inputs, setting Chip Enable and Latch Enable Low, VIL and keeping Write Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the Address inputs can change. Set Output Enable Low, VIL, to read the data on the Data inputs/outputs; see Figure 8: Asynchronous Latch Controlled Bus Read AC waveforms and Table 19: Asynchronous Bus Read AC characteristics, for details on when the output becomes valid. Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read operations can be performed when the memory is configured for Asynchronous Latch Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation. 24/87 M58BW16F, M58BW32F 3.1.3 Bus operations Asynchronous Page Read Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 4 double-words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the page buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. Page Read does not support Latched Controlled Read. See Figure 11: Asynchronous Page Read AC waveforms, and Table 20: Asynchronous Page Read AC characteristics, for details on when the outputs become valid. 3.1.4 Asynchronous Bus Write Asynchronous Bus Write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Bus Write operation begins by setting the desired address on the Address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, VIL, and Output Enable High, VIH, or Output Disable Low, VIL. The Address inputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 12: Asynchronous Write AC waveforms, and Table 21: Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing requirements. 3.1.5 Asynchronous Latch Controlled Bus Write Asynchronous Latch Controlled Bus Write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is Don't care during Bus Write operations. A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired address on the Address inputs and pulsing Latch Enable Low, VIL. The Address inputs are latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 13: Asynchronous Latch controlled Write AC waveforms, and Table 21: Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing requirements. 3.1.6 Output Disable The data outputs are high impedance when the Output Enable, G, is at VIH or Output Disable, GD, is at VIL. 25/87 Bus operations 3.1.7 M58BW16F, M58BW32F Standby When Chip Enable is High, VIH, and the Program/Erase controller is idle, the memory enters Standby mode, the power consumption is reduced to the standby level (IDD1) and the Data inputs/outputs pins are placed in the high impedance state regardless of Output Enable, Write Enable or Output Disable inputs. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to `1' (see Table 18: DC characteristics). 3.1.8 Reset/Power-down The memory is in Reset/Power-down mode when Reset/Power-down, RP, is at VIL. The power consumption is reduced to the standby level (IDD1) and the outputs are high impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable, W, inputs. In this mode the device is write protected and both the Status and the Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. Table 6. Asynchronous Bus operations(1) Bus operation Step E G GD W RP L A0-Amax DQ0-DQ31 VIL VIL VIH VIH VIH VIL Address Data output Address Latch VIL VIH VIH VIL VIH VIL Address High Z Read VIL VIL VIH VIH VIH VIH X Data output Asynchronous Page Read VIL VIL VIH VIH VIH X Address Data output Asynchronous Bus Write VIL VIH X VIL VIH VIL Address Data input Address Latch VIL VIH X VIH VIH VIL Address High Z Write VIL VIH X VIL VIH VIH X Data input Output Enable, G VIL VIH VIH VIH VIH X X High Z Output Disable, GD VIL VIL VIL VIH VIH X X High Z Standby VIH X X X VIH X X High Z X X X X VIL X X High Z Asynchronous Bus Read(2) Asynchronous Latch Controlled Bus Read Asynchronous Latch Controlled Bus Write Reset/Power-down 1. X = Don't care. 2. Data, Manufacturer code, Device code, Burst Configuration Register, Standby Status and Block Protection Configuration Register are read using the Asynchronous Bus Read command. 26/87 M58BW16F, M58BW32F 3.2 Bus operations Synchronous Bus operations For Synchronous Bus Operations refer to Table 7 together with the following text. The read access will start at whichever of the three following events occurs last: valid address transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL. 3.2.1 Synchronous Burst Read Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock. The valid edge of the Clock signal is the rising edge. Once the Flash memory is configured in Burst mode, it is mandatory to have an active clock signal since the switching of the output buffer databus is synchronized to the rising edge of the clock. In the absence of clock, no data is output. The burst type, length and latency can be configured. The different configurations for Synchronous Burst Read operations are described in the Burst Configuration Register section. Refer to Figure 4 for examples of Synchronous Burst operations. A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip Enable and Latch Enable are Low, VIL. The burst start address is latched and loaded into the internal Burst Address counter on the valid Burst Clock K edge or on the rising edge of Latch Enable, whichever occurs first. After an initial memory latency time, the memory outputs data each clock cycle. The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance, B, is Low. Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid immediately at the rising clock edge. Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH. If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid. If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address Advance, B, is at VIL the internal Burst Address counter is incremented at each Burst Clock K rising edge. The Synchronous Burst Read timing diagrams and AC characteristics are described in the AC and DC parameters section. See Figures 14, 17, 18 and 19, and Table 22. 27/87 Bus operations 3.2.2 M58BW16F, M58BW32F Synchronous Burst Read Suspend During a Synchronous Burst Read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the Burst counter and the Output Enable going High, VIH, inhibits the data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable Low. Table 7. Synchronous Burst Read Bus operations(1) Bus operation Synchronous Burst Read(2) Step E G GD RP K A0-Amax L B (3) VIL X Address input DQ0-DQ31 Address Latch VIL VIH X VIH R Read VIL VIL VIH VIH R(3) VIH VIL Data output Read Suspend VIL VIH X VIH X VIH VIH High Z VIH VIL Data output Read Resume VIL VIL VIH VIH R(3) Burst Address Advance VIL VIH X VIH R(3) VIH VIL High Z Read Abort, E VIH X X VIH X X X High Z X X X VIL X X X High Z Read Abort, RP 1. X = Don't care, VIL or VIH . 2. M15 = 0, Bit M15 is in the Burst Configuration Register. 3. R = Rising edge. 3.3 Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Powerdown mode. The Burst Configuration Register bits are described in Table 8. They specify the selection of the Burst length, Burst type, Burst X and Y latencies and the Read operation. Refer to Figure 4 for examples of Synchronous Burst configurations. 3.3.1 Read Select bit (M15) The Read Select bit, M15, is used to switch between Asynchronous and Synchronous Bus Read operations. When the Read Select bit is set to '1', Bus Read operations are asynchronous; when the Read Select bit is set to '0', Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to'1' for asynchronous accesses. 3.3.2 Standby Disable bit (M14) The Standby Disable bit, M14, is used to disable the Standby mode. When the Standby bit is `1', the device will not enter Standby mode when Chip Enable goes High, VIH. 28/87 M58BW16F, M58BW32F 3.3.3 Bus operations X-Latency bits (M13-M11) The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock edges between the address being latched and the edge where the first data become available. For correct operation the X-Latency bits can only assume the values in Table 8: Burst Configuration Register. 3.3.4 Y-Latency bit (M9) The Y-Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the XLatency value and the setting in M9. When the Y-Latency is 1 the data changes each clock cycle. 3.3.5 Valid Data Ready bit (M8) The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is '0' the Valid Data Ready output pin is driven Low for the rising clock edge when invalid data is output on the bus. 3.3.6 Wrap Burst bit (M3) Burst Read can be confined inside the 4 double-word boundary (wrap) or overcome the boundary (no wrap). When the wrap burst bit is set to '1' the burst read does not wrap. The wrap mode is not available (M3 is always `1'). 3.3.7 Burst Length bit (M2-M0) The Burst Length bits set the maximum number of double-words that can be output during a Synchronous Burst Read operation. Burst lengths of 4 or 8 are available. Table 8: Burst Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts. If a Burst Read operation (no wrap) has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 double word boundary, the 8-double-word burst mode will run without activating the Valid Data Ready output. If the starting address is not aligned to a 4 double word boundary, Valid Data Ready is activated to indicate that the device needs an internal delay to read the successive words in the array. M10, M7 to M4 are reserved for future use. 29/87 Bus operations M58BW16F, M58BW32F Table 8. Bit Burst Configuration Register Description M15 Read Select M14 Standby Disable M13-M11 X-Latency(1) M10 M9 M8 Y-Latency(2) M6(3) M5-M4 30/87 Wrapping Description 0 Synchronous Burst Read 1 Asynchronous Read (default at power-on) 0 Standby mode enabled (default at power-up) 1 Standby mode disabled 000 Reserved (default value) 001 3, 3-1-1-1, 3-2-2-2 010 4, 4-1-1-1, 4-2-2-2 011 5, 5-1-1-1, 5-2-2-2 100 6, 6-1-1-1, 6-2-2-2 101 7, 7-1-1-1, 7-2-2-2 110 8, 8-1-1-1, 8-2-2-2 111 Reserved 0 Reserved (default value) 1 Reserved 0 One Burst Clock cycle (default value) 1 Two Burst Clock cycle 0 R valid Low during valid Burst Clock edge (default value) 1 R valid Low 1 data cycle before valid Burst Clock edge 0 Reserved (default value) 1 Reserved 0 Falling Burst Clock edge (default value) 1 Rising Burst Clock edge 00 Reserved (default value) 01 Reserved 10 Reserved 11 Reserved 0 Wrap (default value) 1 No Wrap Valid Data Ready M7 M3 Value M58BW16F, M58BW32F Table 8. Bit M2-M0 Bus operations Burst Configuration Register (continued) Description Burst Length Value Description 000 Reserved (default value) 001 4 double-words 010 8 double-words 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Continuous 1. X latencies can be calculated as: (tAVQV - tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. X is an integer number from 4 to 8, tK is the clock period and tSYSTEM MARGIN is the time margin required for the calculation. 2. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK. 3. The M6 bit is Don't care in the M58BW32F and the device has the Rising Burst Clock edge set. To maintain the compatibility this could be modified and read. 31/87 Bus operations Table 9. M58BW16F, M58BW32F Burst type definition Start address x 4 sequential x 8 sequential 0 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-4 1-2-3-4-5-6-7-8 2 2-3-4-5 2-3-4-5-6-7-8-9 3 3-4-5-6 3-4-5-6-7-8-9-10 4 4-5-6-7 4-5-6-7-8-9-10-11 5 5-6-7-8 5-6-7-8-9-10-11-12 6 6-7-8-9 6-7-8-9-10-11-12-13 7 7-8-9-10 7-8-9-10-11-12-13-14 8 8-9-10-11 8-9-10-11-12-13-14-15 Figure 4. Example burst configuration X-1-1-1 0 1 2 3 4 5 6 7 8 9 K ADD VALID L DQ 3-1-1-1 DQ 4-1-1-1 DQ DQ DQ DQ 5-1-1-1 6-1-1-1 7-1-1-1 8-1-1-1 VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID AI03841b 32/87 M58BW16F, M58BW32F 4 Command interface Command interface All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. The commands are summarized in Table 10: Commands. Refer to Table 10 in conjunction with the text descriptions below. 4.1 Read Memory Array command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent Read operations will output the addressed memory array data. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read commands will access the memory array. 4.2 Read Electronic Signature command The Read Electronic Signature command is used to read the Manufacturer code, the Device code, the Block Protection Configuration Register and the Burst Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued, subsequent Bus Read operations, depending on the address specified, read the Manufacturer code, the Device code, the Block Protection Configuration or the Burst Configuration Register until another command is issued; see Table 11: Read electronic signature. 4.3 Read Query command The Read Query command is used to read data from the common Flash interface (CFI) memory area. One Bus Write cycle is required to issue the Read Query command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read from the common Flash interface memory area. 33/87 Command interface 4.4 M58BW16F, M58BW32F Read Status Register command The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. The Status Register information is present on the output data bus (DQ0-DQ7) when Chip Enable E and Output Enable G are at VIL and Output Disable is at VIH. An interactive update of the Status Register bits is possible by toggling Output Enable or Output Disable. It is also possible during a Program or Erase operation, by de-activating the device with Chip Enable at VIH and then reactivating it with Chip Enable and Output Enable at VIL and Output Disable at VIH. The content of the Status Register may also be read at the completion of a Program, Erase or Suspend operation. During a Block Erase or Program command, DQ7 indicates the Program/Erase controller status. It is valid until the operation is completed or suspended. See the section on the Status Register and Table 13 for details on the definitions of the Status Register bits. 4.5 Clear Status Register command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to `0' when a new Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. 4.6 Block Erase command The Block Erase command can be used to erase a block. It sets all of the bits in the block to `1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the first write cycle sets up the Block Erase command, the second write cycle confirms the Block Erase command and latches the block address in the Program/Erase controller and starts the Program/Erase controller. The sequence is aborted if the Confirm command is not given and the device will output the Status Register Data with bits 4 and 5 set to '1'. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation aborts, the PEN Status bit in the Status Register is set to `1' and the command must be reissued. Typical Erase times are given in Table 12. See Appendix A, Figure 28: Block Erase flowchart and pseudocode, for a suggested flowchart on using the Block Erase command. 34/87 M58BW16F, M58BW32F 4.7 Command interface Erase All Main Blocks command The Erase All Main Blocks command is used to erase all 63 main blocks, without affecting the parameter blocks. Issuing the Erase All Main Blocks command sets every bit in each main block to '1'. All data previously stored in the main blocks are lost. Two Bus Write cycles are required to issue the Erase All Main Blocks command. The first cycle sets up the command, the second cycle confirms the command and starts the Program/Erase controller. If the Confirm command is not given the sequence is aborted, and Status Register bits 4 and 5 are set to '1'. If the address given in the second cycle is located in a protected block, the Erase All Main Blocks operation aborts. The data remains unchanged in all blocks and the Status Register outputs the error. Once the Erase All Main Blocks command has been issued, subsequent Bus Read operations output the Status Register. See the Status Register section for details. During an Erase All Main Blocks operation, only the Read Status Register command is accepted by the memory; any other command are ignored. Erase All Main Blocks, once started, cannot be suspended. If PEN is at VIH, the operation will be performed. If PEN is lower than VIH the operation aborts and the Status Register PEN bit (bit 3) is set to '1'. 4.8 Program command The Program command is used to program the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed and starts the Program/Erase controller. A program operation can be aborted by writing FFFFFFFFh to any address after the program set-up command has been given. The Program command is also used to program the OTP block. Refer to Table 10: Commands, for details of the address. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If Reset/Power-down, RP, falls to VIL during programming the operation will be aborted. If PEN is at VIH, the operation can be performed. If PEN goes below VIH, the operation aborts, the PEN Status bit in the Status Register is set to `1' and the command must be reissued. See Appendix A, Figure 26: Program flowchart and pseudocode, for a suggested flowchart on using the Program command. 35/87 Command interface 4.9 M58BW16F, M58BW32F Write to Buffer and Program command The Write to Buffer and Program command makes use of the device's double word (32 bit) Write Buffer to speed up programming. Up to eight double words can be loaded into the Write Buffer and programmed into the memory. Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program command. Any Bus Read operations will start to output the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the selected memory block address (any address in the block where the values will be programmed can be used) along with the value N on the Data inputs/outputs, where N+1 is the number of words to be programmed. The maximum value of N+1 is 8 words. 3. Use N+1 Bus Write operations to load the address and data for each word into the write buffer. The address must be between Start address and Start address plus N, where Start address is the first word address. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. If any address is outside the block boundaries or if the correct sequence is not followed, Status Register bits 4 and 5 are set to `1' and the operation will abort without affecting the data in the memory array. A protected block must be unprotected using the Blocks Unprotect command. During a Write to Buffer and Program operation the memory will only accept the Read Status Register and the Program/Erase Suspend commands. All other commands are ignored. If PEN is at VIH, the operation will be performed. If PEN is lower than VIH the operation aborts and the Status Register PEN bit (bit 3) is set to '1'. The Status Register should be cleared before re-issuing the command. 36/87 M58BW16F, M58BW32F 4.10 Command interface Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Erase operation. The command will only be accepted during a Program or Erase operation. It can be issued at any time during a Program or Erase operation. The command is ignored if the device is already in suspend mode. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase controller has paused; no other commands will be accepted until the Program/Erase controller has paused. After the Program/Erase controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase controller pausing see Table 12. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the command interface. Additionally, if the suspended operation was Erase then the Program, the Write to Buffer and Program, the Set/Clear Block Protection Configuration Register and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. Erase operations can be suspended in a systematic and periodical way, however, in order to ensure the effectiveness of erase operations and avoid infinite erase times, it is imperative to wait a minimum time between successive Erase Resume and Erase Suspend commands. This time, called the minimum effective erase time, is given in Table 12 on page 40. See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts on using the Program/Erase Suspend command. 4.11 Program/Erase Resume command The Program/Erase Resume command can be used to restart the Program/Erase controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. See Appendix A, Figure 27: Program Suspend & Resume flowchart and pseudocode, and Figure 29: Erase Suspend & Resume flowchart and pseudocode, for suggested flowcharts on using the Program/Erase Suspend command. 37/87 Command interface 4.12 M58BW16F, M58BW32F Set Burst Configuration Register command The Set Burst Configuration Register command is used to write a new value to the Burst Configuration Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous Read mode. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. The first cycle writes the setup command. The second cycle writes the address where the new Burst Configuration Register content is to be written, and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0, M1 on A1, etc.; the other address bits are ignored. 4.13 Set Block Protection Configuration Register command The Set Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to `protected', for a specific block. Protected blocks are fully protected from program or erase when WP pin is Low, VIL. The status of a protected block can be changed to `unprotected' by using the Clear Block Protection Configuration Register command. At power-up, all block are configured as `protected'. Two bus operations are required to issue a Set Block Protection Configuration Register command: The first cycle writes the setup command The second write cycle specifies the address of the block to protect and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. To protect multiple blocks, the Set Block Protection Configuration Register command must be repeated for each block. Any attempt to re-protect a block already protected does not change its status. 4.14 Clear Block Protection Configuration Register command The Clear Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to `unprotected', for a specific block thus allowing program/erase operations to this block, regardless of the WP pin status. Two bus operations are required to issue a Clear Block Protection Configuration Register command: The first cycle writes the setup command The second write cycle specifies the address of the block to unprotect and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. To unprotect multiple blocks, the Clear Block Protection Configuration Register command must be repeated for each block. Any attempt to unprotect a block already unprotected does not affect its status. 38/87 M58BW16F, M58BW32F Command interface Commands(1) Table 10. Command Cycles Bus operations 1st cycle Op. Addr. Data Read Memory Array Read Electronic Signature (2) Read Status Register Read Query 2nd cycle Op. 3rd cycle Addr. Data 2 Write X FFh Read RA RD 2 Write X 90h Read IDA IDD Write X 70h 2 Write X 98h Read RA RD X 50h 1 Clear Status Register 1 Write Block Erase 2 Write 55h 20h Write BA D0h Erase All Main Blocks 2 Write 55h 80h Write AAh D0h any block 2 Write AAh 40h 10h Write PA PD OTP block 2 Write AAh 40h Write PA PD Write to Buffer and Program N+4 Write AAh E8h Write BA N Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h S3 Write X 60h Write BCRh 03h Program Set Burst Configuration Register Set Block Protection Configuration Register 2 Write X 60h Write BA 01h Clear Block Protection Configuration Register 2 Write X 60h Write BA D0h 4th cycle Op. Addr. Data Op. Addr. Data Write PA PD Read RA RD Write X D0h 1. X Don't care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register value, N+1 number of Words to program, BA Block address. 2. The Manufacturer code, the Device code, the Burst Configuration Register, and the Block Protection Configuration Register of each block are read using the Read Electronic Signature command. 39/87 Command interface M58BW16F, M58BW32F Table 11. Read electronic signature Code Device Amax-A0 DQ31-DQ0 Manufacturer All 00000h 00000020h M58BW16FT 00001h 0000883Ah M58BW16FB 00001h 00008839h M58BW32FT 00001h 00008838h M58BW32FB 00001h 00008837h 00005h BCR(1) Device Burst Configuration Register Block Protection Configuration Register 00000000h (Unprotected) SBA+02h(2) All 00000001h (Protected) 1. BCR = Burst Configuration Register. 2. SBA is the start address of each block. Table 12. Program, Erase times and endurance cycles(1) M58BW16F M58BW32F Parameters Unit Min Typ Max Full Chip Program 15 Double Word Program Min Typ Max 20 15 20 s 15 35 15 35 s 512 Kbit Block Erase 1 2 1 2 s 128 Kbit Block Erase 0.8 1.6 0.8 1.6 s 64 Kbit Block Erase 0.6 1.2 0.6 1.2 s Erase all main blocks 45 60 30 50 s Program Suspend Latency time 10 10 s Erase Suspend Latency time 30 30 s 40 40 s 100,000 100,000 cycles Minimum effective erase time(2) Program/Erase cycles (per block) 1. TA = -40 to 125 C, VDD = 2.7 V to 3.6 V, VDDQ = 2.6 V to VDD . 2. The minimum effective erase time is defined as the minimum time required between the last Erase Resume command and the next Erase Suspend command for the internal Flash memory Program/Erase controller to be able to execute its algorithm. 40/87 M58BW16F, M58BW32F 5 Status Register Status Register The Status Register provides information on the current or previous Program, Erase or Block Protect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume commands. The Status Register can be read from any address. The contents of the Status Register can be updated during an erase or program operation by toggling the Output Enable or Output Disable pins or by de-activating (Chip Enable, VIH) and then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, VIH.) the device. The Status Register bits are summarized in Table 13: Status Register bits. Refer to Table 13 in conjunction with the following text descriptions. 5.1 Program/Erase Controller Status (bit 7) The Program/Erase Controller Status bit indicates whether the Program/Erase controller is active or inactive. When the Program/Erase Controller Status bit is set to `0', the Program/Erase controller is active; when bit 7 is set to `1', the Program/Erase controller is inactive. The Program/Erase Controller Status is set to `0' immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is set to `1'. During Program and Erase operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase controller completes the operation and the bit is set to `1'. After the Program/Erase controller completes its operation the Erase Status (bit 5), Program Status (bit 4) bits should be tested for errors. 5.2 Erase Suspend Status (bit 6) The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is set to `0', the Program/Erase controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to `0'. 41/87 Status Register 5.3 M58BW16F, M58BW32F Erase Status (bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). When the Erase Status bit is set to `0', the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to `1', the Program/Erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. Once set to `1', the Erase Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 5.4 Program/Write to Buffer and Program Status (bit 4) The Program/Write to Buffer and Program Status bit is used to identify a Program failure or a Write to Buffer and Program failure. Bit 4 should be read once the Program/Erase Controller Status bit is High (Program/Erase controller inactive). When bit 4 is set to `0' the memory has successfully verified that the device has programmed correctly. When bit 4 is set to `1' the device has failed to verify that the data has been programmed correctly. Once set to `1', the Program Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 5.5 PEN Status (bit 3) The PEN Status bit can be used to identify if a Program or Erase operation has been attempted when PEN is Low, VIL. When bit 3 is set to `0' no Program or Erase operations have been attempted with PEN Low, VIL, since the last Clear Status Register command, or hardware reset. When bit 3 is set to `1' a Program or Erase operation has been attempted with PEN Low, VIL. Once set to `1', bit 3 can only be reset by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 42/87 M58BW16F, M58BW32F 5.6 Status Register Program Suspend Status (bit 2) The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is set to `0', the Program/Erase controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to `0'. 5.7 Block Protection Status (bit 1) The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is set to `0', no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is set to `1', a Program or Erase operation has been attempted on a protected block. Once set to `1', the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 5.8 Bit 0 Reserved bit (set to `1'). 43/87 Status Register M58BW16F, M58BW32F Table 13. Status Register bits Bit Logic level Definition '1' Ready '0' Busy '1' Suspended '0' In progress or completed '1' Erase error '0' Erase success '1' Program error '0' Program success `0' No program or erase attempted `1' Program or erase attempted '1' Suspended '0' In progress or completed Erase/Program in a protected block '1' Program/erase on protected block, abort '0' No operations to protected blocks Reserved '1' Reserved 7 Program/Erase Controller Status 6 Erase Suspend Status 5 Erase Status 4 Program Status, 3 PEN Status bit 2 Program Suspend Status 1 0 44/87 Name M58BW16F, M58BW32F 6 Maximum rating Maximum rating Stressing the device above the ratings listed in Table 14: Absolute maximum ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 14. Absolute maximum ratings Value Symbol Parameter Unit Min Max TBIAS Temperature under bias -40 125 C TSTG Storage temperature -55 155 C Input or output voltage -0.6 VDDQ + 0.6 VDDQIN + 0.6 V -0.6 4.2 V VIO VDD, V DDQ, VDDQIN Supply voltage Table 15. Data retention External temperature Power supply VDD Unit 0 Unit 25 C 125 C V 20 7 Years 2.5 V - 25 Years 2.7 V - 15 Years 45/87 DC and AC parameters 7 M58BW16F, M58BW32F DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 16: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 16. Operating and AC measurement conditions M58BW16F, M58BW32F Parameter 45 ns 55 ns Min Max Min Max Supply voltage (VDD ) 2.7 3.6 2.5 3.3 V Input/output supply voltage (VDDQ) 2.4 3.6 2.4 3.6 V -40 125 -40 125 C Ambient temperature (TA) Grade 3 Load capacitance (CL) 30 30 pF Clock rise and fall times 3 3 ns Input rise and fall times 3 3 ns Input pulses voltages Input and output timing ref. voltages Figure 5. 0 to VDDQ 0 to VDDQ V VDDQ/2 VDDQ/2 V AC measurement input/output waveform VDDQ VDDQIN VDDQ/2 VDDQIN/2 0V AI04153 1. VDD = VDDQ. Figure 6. AC measurement load circuit DEVICE UNDER TEST OUT CL CL includes JIG capacitance 46/87 Units AI04154b M58BW16F, M58BW32F Table 17. DC and AC parameters Device capacitance(1)(2) Symbol CIN COUT Parameter Input capacitance Output capacitance Test condition Typ Max Unit VIN = 0 V 6 8 pF VOUT = 0 V 8 12 pF 1. TA = 25 C, f = 1 MHz. 2. Sampled only, not 100% tested. Table 18. DC characteristics Symbol Parameter Test condition Min Typ Max Unit ILI Input Leakage current 0 V VIN VDDQIN 1 A ILO Output Leakage current 0 V VOUT VDDQ 5 A IDD Supply current (Random Read) E = VIL, G = VIH, fadd = 6 MHz 25 mA 20 mA E = VIL, G = VIH, fclock = 75 MHz 50 mA IDDP-UP(1) Supply current (power-up) IDDB Supply current (Burst Read) IDD1(2) Supply current (Standby) E = RP = VDD 0.2 V 150 A IDD2 Supply current (Program or Erase) Program, Erase in progress 30 mA IDD3 Supply current (Erase/Program Suspend) E = VIH 150 A IDD4 Supply current (Standby Disable) 10 mA VIL Input Low voltage -0.5 0.2VDDQIN V VIH Input High voltage (for DQ lines) 0.8VDDQIN VDDQ + 0.3 V VIH Input High voltage (for input only lines) 0.8VDDQIN 3.6 V VOL Output Low voltage IOL = 100 A 0.1 V VOH Output High voltage CMOS IOH = -100 A VLKO VDD supply voltage (Erase and Program lockout) 5 VDDQ -0.1 V 2.2 V 1. IDDP-UP is the current needed from the device until RP goes to its logic high level when the power supply is stable (tVDHPH). See Figure 22and Figure 23. 2. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to `1'. 47/87 DC and AC parameters Figure 7. M58BW16F, M58BW32F Asynchronous Bus Read AC waveforms tAVAV A0-A19 VALID tEHLX tAVQV L tELQX tELQV tAXQX E tGLQX tGLQV tEHQX tEHQZ G GD tGHQX tGHQZ DQ0-DQ31 OUTPUT See also Page Read AI08921b Figure 8. Asynchronous Latch Controlled Bus Read AC waveforms A0-A19 VALID tLHAX L tLHLL tLLLH tEHLX E tGLQX tGLQV tEHQX tEHQZ G tLLQV tLLQX DQ0-DQ31 tGHQX GHQZ OUTPUT See also Page Read AI08922b 48/87 M58BW16F, M58BW32F Figure 9. A0-A19 DC and AC parameters Asynchronous Chip Enable Controlled Bus Read AC waveforms VALID tLHAX L tEHLX E tGLQX tGLQV tEHQX tEHQZ G tELQX tELQV DQ0-DQ31 tGHQX GHQZ OUTPUT See also Page Read AI13434 Figure 10. Asynchronous Address Controlled Bus Read AC waveforms A0-A19 VALID tLHAX L tEHLX E tGLQX tGLQV tEHQX tEHQZ G tGHQX GHQZ tAVQV DQ0-DQ31 OUTPUT See also Page Read AI13435 49/87 DC and AC parameters Table 19. M58BW16F, M58BW32F Asynchronous Bus Read AC characteristics M58BWxxF Symbol Parameter Test condition Unit 45 55 tAVAV Address Valid to Address Valid E = VIL, G = VIL Min 45 55 ns tAVQV Address Valid to Output Valid E = VIL, G = VIL Max 45 55 ns tAXQX Address Transition to Output Transition L = VIL, G = VIL Min 0 0 ns tEHLX Chip Enable High to Latch Enable Transition Min 0 0 ns tEHQX Chip Enable High to Output Transition G = VIL Min 0 0 ns tEHQZ Chip Enable High to Output Hi-Z G = VIL Max 20 20 ns tELQV(1) Chip Enable Low to Output Valid G = VIL Max 45 55 ns tGHQX Output Enable High to Output Transition E = VIL Min 0 0 ns tGHQZ Output Enable High to Output Hi-Z E = VIL Max 15 15 ns tGLQV Output Enable Low to Output Valid E = VIL Max 15 15 ns tGLQX Output Enable Low to Output Transition E = VIL Min 0 0 ns tLHAX Latch Enable High to Address Transition E = VIL Min 5 5 ns tLHLL Latch Enable High to Latch Enable Low Min 10 10 ns tLLLH Latch Enable Low to Latch Enable High E = VIL Min 10 10 ns tLLQV Latch Enable Low to Output Valid Chip Enable Low to Output Valid E = VIL, G = VIL Max 45 55 ns tLLQX Latch Enable Low to Output Transition E = VIL, G = VIL Min 0 0 ns tELQX Chip Enable Low to Output Transition L = VIL, G = VIL Min 0 0 ns 1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without increasing tELQV. 50/87 M58BW16F, M58BW32F Figure 11. DC and AC parameters Asynchronous Page Read AC waveforms A0-A1 A0 and/or A1 tAVQV1 tAXQX OUTPUT + 1 OUTPUT DQ0-DQ31 AI03646 Table 20. Asynchronous Page Read AC characteristics(1) M58BWxxF Symbol Parameter Test condition Unit 45 55 tAVQV1 Address Valid to Output Valid E = VIL, G = VIL Max 25 25 ns tAXQX Address Transition to Output Transition E = VIL, G = VIL Min 0 0 ns 1. For other timings see Table 19: Asynchronous Bus Read AC characteristics. 51/87 52/87 RP PEN DQ0-DQ31 W G E=L A0-A19 tAVLL tWHEH INPUT tDVWH tWHDX tWHWL tWHAX tWLWH Write Cycle tELWL tAVWH tAVAV VALID INPUT RP = VHH Write Cycle tPHWH tVPHWH VALID tWHQV tWHGL VALID Read Status Register RP = VDD tQVPL tQVVPL VALID SR AI13223b DC and AC parameters M58BW16F, M58BW32F Figure 12. Asynchronous Write AC waveforms RP PEN DQ0-DQ31 W G E L A0-A19 tAVLL tLLLH tWHDX Write Cycle tWLWH tELWL tAVWH tLHAX INPUT tLLWH tELLL tAVLH tAVAV VALID tDVWH tVPHWH tWHWL tWHEH tWHAX VALID Write Cycle RP = VHH INPUT tWHQV tWHGL VALID Read Status Register AI13222b RP = VDD tQVPL tQVVPL VALID SR M58BW16F, M58BW32F DC and AC parameters Figure 13. Asynchronous Latch controlled Write AC waveforms 53/87 DC and AC parameters Table 21. M58BW16F, M58BW32F Asynchronous Write and Latch controlled Write AC characteristics M58BWxxF Symbol Parameter Test condition Unit 45 55 tAVAV Address Valid to Address Valid Min 45 55 ns tAVLH Address Valid to Latch Enable High Min 8 8 ns tAVLL Address Valid to Latch Enable Low Min 0 0 ns tAVWH Address Valid to Write Enable High E = V IL Min 25 30 ns tDVWH Data Input Valid to Write Enable High E = V IL Min 25 30 ns tELLL Chip Enable Low to Latch Enable Low Min 0 0 ns tELWL Chip Enable Low to Write Enable Low Min 0 0 ns tLHAX Latch Enable High to Address Transition Min 5 5 ns tLLLH Latch Enable Low to Latch Enable High Min 10 10 ns tLLWH latch Enable Low to Write Enable High Min 25 30 ns tQVVPL Output Valid to PEN Low Min 0 0 ns tVPHWH PEN High to Write Enable High Min 0 0 ns tWHAX Write Enable High to Address Transition E = V IL Min 0 0 ns tWHDX Write Enable High to Input Transition E = V IL Min 0 0 ns tWHEH Write Enable High to Chip Enable High Min 0 0 ns tWHGL Write Enable High to Output Enable Low Min 150 150 ns tWHQV Write Enable High to Output Valid Min 165 165 ns tWHWL Write Enable High to Write Enable Low Min 20 20 ns tWLWH Write Enable Low to Write Enable High Min 25 30 ns tQVPL Output Valid to Reset/Power-down Low Min 0 0 ns 54/87 E = V IL E = V IL DQ0-DQ31 G E L A0-A19 K VALID tELLL tAVLL 1 Note: n depends on Burst X-Latency. tLLKH tKHLL 0 tKHLH tKHAX Setup tKHQV tGLQV n OUTPUT n+1 n+2 AI08925c tGHQX tGHQZ tEHQX tEHQZ M58BW16F, M58BW32F DC and AC parameters Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from 'n' clock rising edge) 55/87 56/87 DQ0-DQ31 G E L A0-A19 B K VALID 1 Note: n depends on Burst X-Latency. tELKH tKHEL 0 tKHLH tKHAX Setup tKHQV tGLQV n+1 OUTPUT tBLKH n n+2 AI13284 tGHQX tGHQZ tEHQX tEHQZ DC and AC parameters M58BW16F, M58BW32F Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from 'n' clock rising edge) M58BW16F, M58BW32F DC and AC parameters AI13285 tKHQV tKHLH Note: n depends on Burst X-Latency. DQ0-DQ31 G E L A0-A19 B K tAVKH 0 1 VALID Setup tKHAX tGLQV n tBLKH OUTPUT n+1 n+2 tEHQX tEHQZ tGHQX tGHQZ Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid from 'n' clock rising edge) 57/87 DC and AC parameters M58BW16F, M58BW32F Figure 17. Synchronous Burst Read (data valid from 'n' clock rising edge) n n+1 n+2 n+4 n+3 n+5 K tKHQV Q0 DQ0-DQ31 Q1 Q2 Q3 Q4 Q5 tKHQX SETUP Burst Read Q0 to Q3 Note: n depends on Burst X-Latency AI04408c 1. For set up signals and timings see Synchronous Burst Read. Figure 18. Synchronous Burst Read - valid data ready output K Output (1) V V V V V tRLKH R (2) AI03649b 1. Valid Data Ready = Valid Low during valid clock edge. 2. V= Valid output. 3. The internal timing of R follows DQ. 58/87 M58BW16F, M58BW32F DC and AC parameters Figure 19. Synchronous Burst Read - Burst Address Advance K A0-A19 VALID L DQ0-DQ31 Q0 Q1 Q2 tGLQV G tBLKH tBHKH B AI03650 Figure 20. Clock input AC waveform tKHKL K tKLKH ai13286 59/87 DC and AC parameters Table 22. M58BW16F, M58BW32F Synchronous Burst Read AC characteristics(1)(2) M58BWxxF Symbol f tAVKH Parameter Clock frequency Address Valid to Valid Clock Edge Test condition Unit 45 55 X-Latency = 3 Max 40 33 MHz X-Latency = 4 Max 56 40 MHz X-Latency = 5 or 6 Max 75 56 MHz E = VIL, L = VIL X-Latency = 3 Min 12 13 ns E = VIL, L = VIL X-Latency = 4, 5 or 6 Min 6 7 ns tKHKL Clock High time Min 6 6 ns tKLKH Clock Low time Min 6 6 ns tBHKH Burst Address Advance High to Valid Clock Edge E = VIL, G = VIL, L = VIH Min 8 8 ns tBLKH Burst Address Advance Low to Valid Clock Edge E = VIL, G = VIL, L = VIH Min 8 8 ns L = VIL X-Latency = 3 Min 12 13 ns L = VIL X-Latency = 4, 5 or 6 Min 6 7 ns E = VIL, L = VIH Max 15 15 ns tELKH Chip Enable Low to Valid Clock Edge tGLQV Output Enable Low to Output Valid tKHAX Valid Clock Edge to Address Transition E = VIL Min 5 5 ns tKHEL Valid Clock Edge to Chip Enable Low L = VIL Min 0 0 ns tKHLL Valid Clock Edge to Latch Enable Low E = VIL Min 0 0 ns tKHLH Valid Clock Edge to Latch Enable High E = VIL Min 0 0 ns tKHQX Valid Clock Edge to Output Transition E = VIL, G = VIL, L = VIH Min 2 2 ns E = VIL X-Latency = 3 Min 12 13 ns M58BW16F Min 6 5 ns M58BW32F Min 6 7 ns tLLKH Latch Enable Low to Valid Clock Edge E = VIL X-Latency = 4, 5 or 6 tRLKH Valid Data Ready Low to Valid Clock Edge E = VIL, G = VIL, L = VIH Min 6 6 ns tKHQV Valid Clock Edge to Output Valid E = VIL, G = VIL, L = VIH Max 8 8 ns 1. Data output should be read on the valid clock edge. 2. For other timings see Table 19: Asynchronous Bus Read AC characteristics. 60/87 M58BW16F, M58BW32F DC and AC parameters Figure 21. Power supply slope specification Voltage VDHH VDH Time tVDH AI14230b 1. Please refer to the application note AN2601. Table 23. Symbol Power supply AC and DC characteristics Description VDH Minimum value of power supply (VDD)(1) VDHH Maximum value of power supply (VDD) tVDH Time required from power supply to reach the VDH value Min Max 0.9V DD 300 Unit V 3.6 V 50000 s 1. This threshold is 90% of the minimum value allowed to VDD. 61/87 DC and AC parameters M58BW16F, M58BW32F Figure 22. Reset, Power-down and Power-up AC waveforms - Control pins Low tPHWL tPHEL tPHGL tPHLL W, E, G, L Hi-Z Hi-Z R tPLRZ tPHRH tPHRH RP tVDHPH tPLPH VDD, VDDQ Power-up Reset AI14239 Figure 23. Reset, Power-down and Power-up AC waveforms - Control pins toggling tPHWL tPHEL tPHGL tPHLL W, E, G, L tWLRH tGLRH tELRH tLLRH tPLRZ Hi-Z Hi-Z R tPHRH tPHRH RP tVDHPH tPLPH VDD, VDDQ Power-up Reset AI14240 62/87 M58BW16F, M58BW32F Table 24. DC and AC parameters Reset, Power-down and Power-up AC characteristics Symbol Parameter Min Max Unit tPHEL Reset/Power-down High to Chip Enable Low 50 ns tPHLL Reset/Power-down High to Latch Enable Low 50 ns tPHQV(1) Reset/Power-down High to Output Valid 95 ns tPHWL Reset/Power-down High to Write Enable Low 50 ns tPHGL Reset/Power-down High to Output Enable Low 50 ns tPLPH Reset/Power-down Low to Reset/Power-down High 100 ns tPHRH(1) Reset/Power-down High to Valid Data Ready High tVDHPH Supply voltages High to Reset/Power-down High 95 50 ns s tPLRZ Reset/Power-down Low to Data Ready High Impedance 80 ns tWLRH Write Enable Low to Data Ready High Impedance 80 ns tGLRH Output Enable Low to Data Ready High Impedance 80 ns tELRH Chip Enable Low to Data Ready High Impedance 80 ns tLLRH Latch Enable Low to Data Ready High Impedance 80 ns 1. This time is tPHEL + tAVQV or tPHEL + tELQV. 63/87 Package mechanical 8 M58BW16F, M58BW32F Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 24. LBGA80 10 x 12 mm - 8 x 10 ball array, 1 mm pitch, bottom view package outline D D1 FD FE SD SE E E1 BALL "A1" ddd e e b A A2 A1 JE_ME 1. Drawing is not to scale. 64/87 M58BW16F, M58BW32F Table 25. Package mechanical LBGA80 10 x 12 mm - 8 x 10 active ball array, 1 mm pitch, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.60 A1 0.063 0.40 A2 Max 0.016 1.05 0.041 b 0.60 0.024 D 10.00 - - 0.394 - - D1 7.00 - - 0.276 - - ddd 0.15 0.006 E 12.00 - - 0.472 - - E1 9.00 - - 0.354 - - e 1.00 - - 0.039 - - FD 1.50 - - 0.059 - - FE 1.50 - - 0.059 - - SD 0.50 0.020 SE 0.50 0.020 65/87 Package mechanical M58BW16F, M58BW32F Figure 25. PQFP80 - 80 lead plastic quad flat pack, package outline Ne A2 N 1 e D2 D1 D Nd b E2 A E1 CP L1 E c A1 QFP-B L 1. Drawing is not to scale. Table 26. PQFP80 - 80 lead plastic quad flat pack, package mechanical data millimeters inches Symbol Typ Min A Min 2.80 0.010 2.55 3.05 0.30 0.45 CP 0.110 0.100 0.120 0.012 0.018 0.10 c Max 0.134 0.25 b 66/87 Typ 3.40 A1 A2 Max 0.13 0.23 0.004 0.005 0.009 D 23.20 22.95 23.45 0.913 0.903 0.923 D1 20.00 19.90 20.10 0.787 0.783 0.791 D2 18.40 - - 0.724 - - e 0.80 - - 0.031 - - E 17.20 16.95 17.45 0.677 0.667 0.687 E1 14.00 13.90 14.10 0.551 0.547 0.555 E2 12.00 - - 0.472 - - L 0.80 0.65 0.95 0.031 0.026 0.037 L1 1.60 - - 0.063 - - 0 7 0 7 N 80 80 Nd 24 24 Ne 16 16 M58BW16F, M58BW32F 9 Ordering information Ordering information Table 27. Ordering information scheme Example: M58BW32F T 4 T 3 T Device type M58 Architecture B = Burst mode Operating voltage W = [2.7 V to 3.6 V] VDD range for 45 ns speed class [2.5 V to 3.3 V] VDD range for 55 ns speed class [2.4 V to VDD ] VDDQ range for 45 ns and 55 ns speed classes Device function 32F = 32 Mbit (x 32), boot block, burst, 0.11 m technology 16F = 16 Mbit (x 32), boot block, burst, 0.11 m technology Array matrix T = Top boot B = Bottom boot Speed 4 = 45 ns 5 = 55 ns Package T = PQFP80 ZA = LBGA80, 1.0 mm pitch Device grade 3 = Automotive grade certified(1), -40 to 125 C Option Blank = Standard packing T = Tape & reel packing F = ECOPACK(R) package, tape & reel 24 mm packing 1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (speed, package, etc) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 67/87 Flowcharts M58BW16F, M58BW32F Appendix A Flowcharts Figure 26. Program flowchart and pseudocode Start Program command: - write 40h, Address AAh - write Address & Data (memory enters read status state after the Program command) Write 40h Write Address & Data do: - read status register (E or G must be toggled) Read Status Register b7 = 1 NO while b7 = 1 YES b3 = 0 NO PEN Invalid Error (1) NO Program Error (1) NO Program to Protect Block Error If b3 = 1, PEN invalid error: - error handler YES b4 = 0 If b4 = 1, Program error: - error handler YES b1 = 0 If b1 = 1, Program to Protected Block Error: - error handler YES End AI03850e 1. If an error is found, the Status Register must be cleared before further P/E operations. 68/87 M58BW16F, M58BW32F Flowcharts Figure 27. Program Suspend & Resume flowchart and pseudocode Start Write B0h Program/Erase Suspend command: - write B0h - write 70h Write 70h do: - read status register Read Status Register b7 = 1 NO while b7 = 1 YES b2 = 1 NO Program Complete If b2 = 0, Program completed YES Read Memory Array command: - write FFh - one or more data reads from other blocks Write FFh Read data from another block Write D0h Write FFh Program Continues Read Data Program Erase Resume command: - write D0h to resume programming - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued). AI00612b 69/87 Flowcharts M58BW16F, M58BW32F Figure 28. Block Erase flowchart and pseudocode Start Erase command: - write 20h, Address 55h - write Block Address (A11-A19) & D0h (memory enters read status state after the Erase command) Write 20h Write Block Address & D0h NO Read Status Register Suspend b7 = 1 YES NO Suspend Loop do: - read status register (E or G must be toggled) if Erase command given execute suspend erase loop while b7 = 1 YES b3 = 0 NO PEN Invalid Error (1) YES Command Sequence Error NO Erase Error (1) NO Erase to Protected Block Error If b3 = 1, PEN invalid error: - error handler YES b4 and b5 =1 If b4, b5 = 1, Command Sequence error: - error handler NO b5 = 0 If b5 = 1, Erase error: - error handler YES b1 = 0 If b1 = 1, Erase to Protected Block Error: - error handler YES End AI08623d 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 70/87 M58BW16F, M58BW32F Flowcharts Figure 29. Erase Suspend & Resume flowchart and pseudocode Erase cycle in progress Write B0h Program/Erase Suspend command Write 70h Read Status Register Do: - Read status register while b7 = 1 (b7 = Program/Erase status bit) b7 = 1 NO YES b6 = 1 NO Erase Complete If b6 = 0, Erase is completed (b6 = Erase Suspend status bit) The device returns to Read mode as normal (as if the Program/Erase Suspend was not issued). YES Write FFh Write FFh Read data from another block or Program Write D0h Read Memory Array command: - Write FFh - One or more data reads from other blocks Read Data Program/Erase Resume command: - Write D0h to resume the Erase operation Erase Continues AI00615c 71/87 Flowcharts M58BW16F, M58BW32F Figure 30. Power-up sequence followed by Synchronous Burst Read Power-up or Reset Asynchronous Read Write 60h command BCR bit 15 = '1' Set Burst Configuration Register command: - write 60h - write 03h and BCR on A15-A0 Write 03h with A15-A0 BCR inputs Synchronous Read BCR bit 15 = '0' BCR bit 14-bit 0 = '1' AI03834 72/87 M58BW16F, M58BW32F Flowcharts Figure 31. Command interface and Program/Erase controller flowchart (a) WAIT FOR COMMAND WRITE 90h READ ARRAY NO YES READ ELEC. SIGNATURE 98h NO D YES READ CFI 70h NO YES READ STATUS 20h NO YES ERASE SET-UP 40h NO YES ERASE COMMAND ERROR NO D0h PROGRAM SET-UP 50h YES A YES C NO E CLEAR STATUS D READ STATUS B AI03835 73/87 Flowcharts M58BW16F, M58BW32F Figure 32. Command interface and Program/Erase controller flowchart (b) E 48h NO YES TP PROGRAM SET_UP 78h NO YES F TP UNLOCK SET_UP 60h NO YES FFh G SET BCR SET_UP 03h NO YES NO YES D AI03836 74/87 M58BW16F, M58BW32F Flowcharts Figure 33. Command interface and Program/Erase controller flowchart (c) A B ERASE YES READY NO NO B0h READ STATUS YES ERASE SUSPEND YES READY NO NO ERASE SUSPENDED READ STATUS YES READ STATUS YES 70h NO 40h YES PROGRAM SET_UP NO READ ARRAY NO D0h C YES READ STATUS AI03837 75/87 Flowcharts M58BW16F, M58BW32F Figure 34. Command interface and Program/Erase controller flowchart (d) C B PROGRAM YES READY NO B0h NO READ STATUS YES PROGRAM SUSPEND YES READY NO NO PROGRAM SUSPENDED READ STATUS YES READ STATUS YES 70h NO READ ARRAY NO D0h YES READ STATUS AI03838 76/87 M58BW16F, M58BW32F Flowcharts Figure 35. Command interface and Program/Erase controller flowchart (e) F B TP PROGRAM YES READY NO READ STATUS NO READ STATUS G B TP UNLOCK YES READY AI03839 77/87 Common Flash interface (CFI) Appendix B M58BW16F, M58BW32F Common Flash interface (CFI) The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Table 28, Table 29, Table 30, Table 33 and Table 32 show the addresses used to retrieve the data. Table 28. Query structure overview Offset Sub-section name Description 00h 0020h Manufacturer code Numonyx 01h 883A 8839 8838 8837 Device code 10h CFI query identification string Command set ID and algorithm data offset 1Bh System interface information Device timing and voltage information 27h Device geometry definition Flash memory layout P(h)(1) Primary algorithm-specific extended query table Additional information specific to the primary algorithm (optional) A(h)(2) Alternate algorithm-specific extended query table Additional information specific to the alternate algorithm (optional) M58BW16FT (top) M58BW16FB (bottom) M58BW32FT (top) M58BW32FB (bottom) 1. Offset 15h defines P which points to the primary algorithm extended query address table. 2. Offset 19h defines A which points to the alternate algorithm extended query address table. 78/87 M58BW16F, M58BW32F Common Flash interface (CFI) CFI - Query address and data output(1)(2) Table 29. Address A0-Amax Data Instruction 10h 51h "Q" 11h 52h "R" 12h 59h "Y" 51h; "Q" Query ASCII string 52h; "R" 59h; "Y" 13h 03h 14h 00h 15h 35h (M58BW16F) 39h (M58BW32F) 16h 00h 17h 00h 18h 00h 19h 00h 1Ah 00h Primary vendor: Command set and control interface ID code Primary algorithm extended query address table: P(h) Alternate vendor: Command set and control interface ID code Alternate algorithm extended query address table 1. The x 8 or byte address and the x 16 or word address mode are not available. 2. Query data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'. Table 30. CFI - device voltage and timing specification Address A0-Amax Data 1Bh 27h (1) 1Ch (1) 36h Description Value VDD min 2.7 V VDD max 3.6 V 1Dh xxxx xxxxh Reserved 1Eh xxxx xxxxh Reserved 1Fh 04h 20h xxxx xxxxh 21h 0Ah 22h xxxx xxxxh Reserved 23h xxxx xxxxh Reserved 24h xxxx xxxxh Reserved 25h xxxx xxxxh Reserved 26h xxxx xxxxh Reserved 2n s typical for word, double word program 16 s Reserved 2n ms, typical time-out for Erase Block 1s 1. Bits are coded in binary code decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV. 79/87 Common Flash interface (CFI) Table 31. 80/87 M58BW16F, M58BW32F M58BW16F device geometry definition Address A0-Amax Data Description Value 27h 15h 2n number of bytes memory size 2 Mbytes 28h 03h Device interface sync./async. x 32 29h 00h Organization sync./async. Async. 2Ah 00h 2Bh 00h Maximum number of byte in multi-byte program = 2n 32 bytes 2Ch 02h Bit7-0 = number of Erase Block regions in device 2 2Dh 1Eh 2Eh 00h Number (n-1) of Erase Blocks of identical size; n=31 31 blocks 2Fh 00h 30h 01h 31h 07h 32h 00h 33h 20h 34h 00h Erase Block region information x 256 bytes per Erase 512 Kbits Block (64 Kbytes) Number (n-1) of Erase Blocks of identical size; n=8 8 blocks Erase Block region information x 256 bytes per Erase 64 Kbits Block (8 Kbytes) M58BW16F, M58BW32F Table 32. Common Flash interface (CFI) M58BW16F extended query information Address offset Address Amax-A0 (P)h 35h 50 P (P+1)h 36h 52 R (P+2)h 37h 49 Y (P+3)h 38h 31h Major revision number (P+4)h 39h 31h Minor revision number Optional feature: (1=yes, 0=no) bit0, Chip Erase supported (0= no) bit1, Suspend Erase supported (1=yes) bit2, Suspend Program supported (1=yes) bit3, Lock/Unlock supported (0=no) bit4, Queue Erase supported (0=no) bit5, Instant individual block locking (0=no) bit6, Protection bits supported (0=no) bit7, Page Read supported (1=yes) bit8, Synchronous Read supported (1=yes) Bit9, Reserved Data (hex) Description Query ASCII string - extended table (P+5)h 3Ah 86h (P+6)h 3Bh 01h (P+7)h 3Ch 00h (P+8)h 3Dh 00h (P+9)h 3Eh 01h (P+A)h-(P+D)h 3Fh-42h Reserved (P+13)h-(P+40)h 48h-7Fh Reserved (P+41)h 80h xxxx xxxxh Unique device ID - 1 (16 bits) (P+42)h 81h xxxx xxxxh Unique device ID - 2 (16 bits) (P+43)h 82h xxxx xxxxh Unique device ID - 3 (16 bits) (P+44)h 83h xxxx xxxxh Unique device ID - 4 (16 bits) Synchronous Read supported Function allowed after Suspend: Program allowed after Erase Suspend (1=yes) Bit 7-1 reserved for future use 81/87 Common Flash interface (CFI) Table 33. 82/87 M58BW16F, M58BW32F M58BW32F device geometry definition Address A0-Amax Data Description Value 27h 15h 2n number of bytes memory size 4 Mbytes 28h 03h Device interface sync./async. x 32 29h 00h Organization sync./async. Async. 2Ah 00h 2Bh 00h Maximum number of byte in multi-byte program = 2n 32 bytes 2Ch 02h Bit7-0 = number of Erase Block regions in device 3 2Dh 1Eh 2Eh 00h Number (n-1) of Erase Block regions of identical size; 62 blocks n = 31 2Fh 00h 30h 01h 31h 07h 32h 00h 33h 20h 34h 00h 35h 03h 36h 00h 37h 40h 38h 00h Erase Block region information x 256 bytes per Erase 512 Kbits Block (64 Kbytes) Number (n-1) of Erase blocks of identical size; n = 8 8 blocks Erase Block region information x 256 bytes per Erase 64 Kbits Block (8 Kbytes) Number (n-1) of Erase Block of identical size; n = 8 8 blocks Erase Block region information x 256 bytes per Erase 128 Kbits block (16 Kbytes) M58BW16F, M58BW32F Table 34. Common Flash interface (CFI) M58BW32F extended query information Address offset Address Amax-A0 (P)h 39h 50 P (P+1)h 3Ah 52 R (P+2)h 3Bh 49 Y (P+3)h 3Ch 31h Major revision number (P+4)h 3Dh 31h Minor revision number Optional feature: (1=yes, 0=no) bit0, Chip Erase supported (0= no) bit1, Suspend Erase supported (1=yes) bit2, Suspend Program supported (1=yes) bit3, Lock/Unlock supported (0=no) bit4, Queue Erase supported (0=no) bit5, Instant individual block locking (0=no) bit6, Protection bits supported (0=no) bit7, Page Read supported (1=yes) bit8, Synchronous Read supported (1=yes) Bit 9, Reserved Data (hex) Description Query ASCII string - extended table (P+5)h 3Eh 86h (P+6)h 3Fh 01h (P+7)h 40h 00h (P+8)h 41h 00h (P+9)h 42h 01h (P+A)h-(P+D)h 43h-46h Reserved (P+13)h-(P+40)h 4Ch-7Fh Reserved (P+41)h 80h xxxx xxxxh Unique device ID - 1 (16 bits) (P+42)h 81h xxxx xxxxh Unique device ID - 2 (16 bits) (P+43)h 82h xxxx xxxxh Unique device ID - 3 (16 bits) (P+44)h 83h xxxx xxxxh Unique device ID - 4 (16 bits) Synchronous Read supported Function allowed after Suspend: Program allowed after Erase Suspend (1=yes) Bit 7-1 reserved for future use 83/87 Common Flash interface (CFI) Table 35. M58BW16F, M58BW32F Protection register information Data Address A0-Amax M58BW16FT M58BW32FT M58BW16FB M58BW32FB 84/87 (P+E)h 0x02 0x02 0x01 0x01 (P+F)h 0x01 0xFE 0x01 0xFE (P+10)h 0x01 0xFE 0x01 0xFE (P+11)h 0x0 0x0 0x0 0x0 x256 0x12 0x12 0x12 0x12 Value Instruction Number of Protection register field in JEDEC ID space, Block region information X256 bytes Protection field: this field describes user-available OTP Protection Register bytes. Bits 7-0=physical low address Bits 15-8=physical high address Bits 23-16='n', 2n=Factory preprogrammed bytes Bits 31-24='n', 2n=user programmable bytes M58BW16FT M58BW16FB M58BW32FT M58BW32FB 2 x 64 Kb 2 x 64 Kb 1 x 128 Kb 1 x 128 Kb - - - - - - 2 x 64 Kb 2 x 64 Kb 1 x 128 Kb 1 x 128 Kb M58BW16F, M58BW32F Appendix C Block protection Block protection OTP protection The OTP protection is an user-enabled feature that permanently protects specific blocks, so called "OTP blocks", against modify operations (program/erase). It is available: on one specific 128-kbit parameter block in the M58BW32F- block 1 (01000h-01FFFh) for bottom devices or block 72 (FE000h-FEFFFh) for top devices on two specific 64-kbit parameter blocks in the M58BW16F- block 2 and 3 (01000h01FFFh) for bottom devices or block 36 and 35 (7E000h-7EFFFh) for top devices. The default state is unprotected. However, once the protection has been enabled, it is impossible to disable it and the OTP blocks will remain "modify protected" for ever. Obviously, this information is stored in internal non volatile registers. Activation sequence If the user wants to make the OTP protection effective on a part, he has to issue the Lock OTP protection command. The Lock OTP protection requires 2 write cycles: write (ADD=000AAh, DATA=49h) - Lock OTP Protection command 1 write (ADD=00003h, DATA=0000 0000h) - Lock OTP Protection command 2 This sequence of commands has to be given with the Tuning Protection unlocked (if this protection is enabled on the part) and with Write Protect Enable WP_N='1'. The user can check its execution polling on the SR in the same way as a normal Program Word command. The program duration lasts about 35 s like for a standard Program Word command. It is also possible to detect the end of the operation by polling the Status Register. Any Erase attempt returns A3h in the Status Register while any Program attempt returns 93h. Once the first write cycle of the Lock OTP protection command is issued, a wrong address on second write cycle will cause the activation sequence to fail. The Status Register allows detecting this event and its value is then B1h (invalid sequence). As a consequence, the protection is not active and the sequence must be restarted. The Lock OTP Protection command cannot be suspended. 85/87 Revision history 10 M58BW16F, M58BW32F Revision history Table 36. Document revision history Date Revision 09-Jun-2006 1 Initial release. 2 VPEN signal renamed as PEN and Program/Erase Enable (PEN) modified. Continuous burst and wrap options are not available, X-Latencies 7 and 8 removed (see Table 8: Burst Configuration Register and Table 9: Burst type definition). Notes removed below Table 8. tWHQV timing modified in Table 21: Asynchronous Write and Latch controlled Write AC characteristics. IDD max modified and IDD4 added to Table 18: DC characteristics. tAXQX modified in Table 20: Asynchronous Page Read AC characteristics. Read access specified in Asynchronous Bus Read and Synchronous Burst Read. tAVKH and tALKH added and tKHQV for 55 ns modified in Table 22: Synchronous Burst Read AC characteristics. Figure 9, Figure 10, Figure 18 and Figure 19 added. Double Word Program max modified and Minimum effective erase time added to Table 12: Program, Erase times and endurance cycles. All Asynchronous Bus Read AC characteristics brought together in Table 19: Asynchronous Bus Read AC characteristics. tLLEL removed from Table 19 and Figure 7. Appendix B: Common Flash interface (CFI) modified. 3 Table 8: Burst Configuration Register, Table 30: CFI - device voltage and timing specification and Table 33: M58BW32F device geometry definition updated. Minimum values for tKHKL, tKLKH and tLLKH modified in Table 22: Synchronous Burst Read AC characteristics. tPHLL, tPHRH , tVDHPH, tWLRH, tGLRH, tELRH , and tLLRH added in Table 24: Reset, Power-down and Power-up AC characteristics. tPLRH removed from Table 24. Modified Figure 22: Reset, Power-down and Power-up AC waveforms - Control pins Low and Section 3.3.3: X-Latency bits (M13-M11). Appendix C: Block protection, Figure 23: Reset, Power-down and Power-up AC waveforms - Control pins toggling and Table 35: Protection register information added. 4 Updated mechanical data of the LBGA package and Table 8: Burst Configuration Register, Table 12: Program, Erase times and endurance cycles, Table 18: DC characteristics, Table 21: Asynchronous Write and Latch controlled Write AC characteristics, Table 22: Synchronous Burst Read AC characteristics, and Section 2.7: Reset/Power-down (RP). Added Figure 21: Power supply slope specification and Table 23: Power supply AC and DC characteristics. Minor text changes. 23-Nov-2006 01-Oct-2007 15-Jan-2008 86/87 Changes M58BW16F, M58BW32F Table 36. Revision history Document revision history Date Revision Changes 19-Mar-2008 5 Applied Numonyx branding. 3-August-2009 6 Minor text updates. 87/87 M58BW16F, M58BW32F Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. 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Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2009, Numonyx, B.V., All Rights Reserved. 88/87