SN74LVC138A . . . RGY PACKAGE
(TOP VIEW)
1 16
8 9
2
3
4
5
6
7
15
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
B
C
G2A
G2B
G1
Y7
A
Y6 V
GND
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54LVC138A . . . J OR W PACKAGE
SN74LVC138A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G2B
G1
B
A
NC
Y6
Y5 V
Y0
Y7
GND
NC
SN54LVC138A . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
SN54LVC138A, SN74LVC138A
www.ti.com
SCAS291V –MARCH 1993–REVISED JANUARY 2013
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
Check for Samples: SN54LVC138A,SN74LVC138A
1FEATURES
• Operate From 1.65 V to 3.6 V • Latch-Up Performance Exceeds 250 mA Per
JESD 17
• Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22
• Max tpd of 5.8 ns at 3.3 V – 2000-V Human-Body Model (A114-A)
• Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA= 25°C – 200-V Machine Model (A115-A)
• Typical VOHV (Output VOH Undershoot) – 1000-V Charged-Device Model (C101)
> 2 V at VCC = 3.3 V, TA= 25°C BRK
BRK
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1993–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN54LVC138A, SN74LVC138A
SCAS291V –MARCH 1993–REVISED JANUARY 2013
www.ti.com
DESCRIPTION/ORDERING INFORMATION
The SN54LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 1.65-V to 3.6-V VCC operation.
The 'LVC138A devices are designed for high-performance memory-decoding or data-routing applications
requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the
effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times
of these decoders and the enable time of the memory usually are less than the typical access time of the
memory. This means that the effective system delay introduced by the decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
TAPACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Reel of 1000 SN74LVC138ARGYR LC138A
QFN – RSV Reel of 3000 SN74LVC138ARSVR ZTP
Tube of 40 SN74LVC138AD
SOIC – D Reel of 2500 SN74LVC138ADR LVC138A
Reel of 250 SN74LVC138ADT
SOP – NS Reel of 2000 SN74LVC138ANSR LVC138A
–40°C to 85°C SSOP – DB Reel of 2000 SN74LVC138ADBR LC138A
Tube of 90 SN74LVC138APW
TSSOP – PW Reel of 2000 SN74LVC138APWR LC138A
Reel of 250 SN74LVC138APWT
TVSOP – DGV Reel of 2000 SN74LVC138ADGVR LC138A
VFBGA – GQN SN74LVC138AGQNR
Reel of 1000 LC138A
VFBGA – ZQN (Pb-free) SN74LVC138AZQNR
CDIP – J Tube of 25 SNJ54LVC138AJ SNJ54LVC138AJ
–55°C to 125°C CFP – W Tube of 150 SNJ54LVC138AW SNJ54LVC138AW
LCCC – FK Tube of 55 SNJ54LVC138AFK SNJ54LVC138AFK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC138A SN74LVC138A
GQN OR ZQN PACKAGE
(TOP VIEW)
1 2 3 4
A
B
C
D
E
B
A
VCC
Y0 Y7
GND
Y6
Y5
SN54LVC138A . . . RSV PACKAGE
C
G2A
G2B
(TOP VIEW)
3
2
1
4
Y1
5
Y2
6
16
7
15
Y3
9
10
11
12
13
G1
Y4
8
14
SN54LVC138A, SN74LVC138A
www.ti.com
SCAS291V –MARCH 1993–REVISED JANUARY 2013
TERMINAL ASSIGNMENTS
1 2 3 4
AB A VCC Y0
BC NC(1) NC(1) Y1
CG2B G2A Y3 Y2
DG1 NC(1) NC(1) Y4
EGND Y7 Y6 Y5
(1) NC - No internal connection
Table 1. SDFGDFGDFG
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X X H X X X H H H H H H H H
L X X X X X H H H H H H H H
H L L L L L L H H H H H H H
H L L L L H H L H H H H H H
H L L L H L H H L H H H H H
H L L L H H H H H L H H H H
H L L H L L H H H H L H H H
H L L H L H H H H H H L H H
H L L H H L H H H H H H L H
HLLHHHHHHHHHHL
Copyright © 1993–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: SN54LVC138A SN74LVC138A
G2B
G2A
G1
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data
Outputs
Select
Inputs
Enable
Inputs
1
2
3
6
4
5
15
14
13
12
11
10
9
7
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
SN54LVC138A, SN74LVC138A
SCAS291V –MARCH 1993–REVISED JANUARY 2013
www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
4Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC138A SN74LVC138A
SN54LVC138A, SN74LVC138A
www.ti.com
SCAS291V –MARCH 1993–REVISED JANUARY 2013
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VIInput voltage range(2) –0.5 6.5 V
VOOutput voltage range(2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
D package(4) 73
DB package(4) 82
DGV package(4) 120
θJA Package thermal impedance GQN/ZQN package(4) 78 °C/W
NS package(4) 64
PW package(4) 108
RGY package(5) 39
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
Copyright © 1993–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN54LVC138A SN74LVC138A
SN54LVC138A, SN74LVC138A
SCAS291V –MARCH 1993–REVISED JANUARY 2013
www.ti.com
Recommended Operating Conditions(1)
SN54LVC138A SN74LVC138A UNIT
MIN MAX MIN MAX
Operating 2 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current mA
VCC = 2.7 V –12 –12
VCC = 3 V –24 –24
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current mA
VCC = 2.7 V 12 12
VCC = 3 V 24 24
Δt/Δv Input transition rise or fall rate 10 10 ns/V
TAOperating free-air temperature –55 125 -40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC138A SN74LVC138A
SN54LVC138A, SN74LVC138A
www.ti.com
SCAS291V –MARCH 1993–REVISED JANUARY 2013
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC138A SN74LVC138A
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP(1) MAX MIN TYP(1) MAX
1.65 V to 3.6 V VCC – 0.2
IOH = –100 μA2.7 V to 3.6 V VCC – 0.2
IOH = –4 mA 1.65 V 1.2
VOH IOH = –8 mA 2.3 V 1.7 V
2.7 V 2.2 2.2
IOH = –12 mA 3 V 2.4 2.4
IOH = –24 mA 3 V 2.2 2.2
1.65 V to 3.6 V 0.2
IOL = 100 μA2.7 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
VOL V
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
IIVI= 5.5 V or GND 3.6 V ±5 ±5 μA
ICC VI= VCC or GND, IO= 0 3.6 V 10 10 μA
One input at VCC – 0.6 V,
ΔICC 2.7 V to 3.6 V 500 500 μA
Other inputs at VCC or GND
CiVI= VCC or GND 3.3 V 5 5 pF
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC138A
FROM TO VCC = 3.3 V
PARAMETER VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.3 V
MIN MAX MIN MAX
A or B or C 7.9 1 6.7
tpd G2A or G2B Y 7.4 1 6.5 ns
G1 6.4 1 5.8
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC138A
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V
MIN MAX MIN MAX MIN MAX MIN MAX
A or B or C 1 22 1 9.9 1 7.9 1 6.7
tpd G2A or G2B Y 1 21 1 9.4 1 7.4 1 6.5 ns
G1 1 20.3 1 8.4 1 6.4 1 5.8
tsk(o) 1 ns
Copyright © 1993–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: SN54LVC138A SN74LVC138A
SN54LVC138A, SN74LVC138A
SCAS291V –MARCH 1993–REVISED JANUARY 2013
www.ti.com
Operating Characteristics
TA= 25°C VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TEST
PARAMETER UNIT
CONDITIONS TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 25 26 27 pF
8Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC138A SN74LVC138A
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE W AVEFORMS
SETUP AND HOLD TIMES
VOLTAGE W AVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE W AVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH − V∆≈0 V
VI
VOLTAGE W AVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
6 V
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
SN54LVC138A, SN74LVC138A
www.ti.com
SCAS291V –MARCH 1993–REVISED JANUARY 2013
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 1993–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: SN54LVC138A SN74LVC138A
SN54LVC138A, SN74LVC138A
SCAS291V –MARCH 1993–REVISED JANUARY 2013
www.ti.com
REVISION HISTORY
Changes from Revision T (July 2005) to Revision U Page
• Added QFN – RSV package option to the ORDERING INFORMATION table. ................................................................... 2
Changes from Revision U (OCTOBER 2012) to Revision V Page
• Changed RSV pinout drawing to drawing with correct pinout. ............................................................................................. 2
10 Submit Documentation Feedback Copyright © 1993–2013, Texas Instruments Incorporated
Product Folder Links: SN54LVC138A SN74LVC138A
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9752601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9752601Q2A
SNJ54LVC
138AFK
5962-9752601QEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9752601QE
A
SNJ54LVC138AJ
5962-9752601QFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9752601QF
A
SNJ54LVC138AW
5962-9752601V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-
9752601V2A
SNV54LVC
138AFK
5962-9752601VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type 5962-9752601VE
A
SNV54LVC138AJ
5962-9752601VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type 5962-9752601VF
A
SNV54LVC138AW
SN74LVC138AD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADBLE OBSOLETE SSOP DB 16 TBD Call TI Call TI -40 to 85
SN74LVC138ADBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138ADBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138ADBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138ADE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC138ADGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138ADGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138ADR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ADTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138AGQNR OBSOLETE BGA
MICROSTAR
JUNIOR
GQN 20 TBD Call TI Call TI -40 to 85 LC138A
SN74LVC138ANSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ANSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138ANSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC138A
SN74LVC138APW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138APWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138APWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138APWLE OBSOLETE TSSOP PW 16 TBD Call TI Call TI -40 to 85
SN74LVC138APWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138APWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC138APWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138APWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138APWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138APWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC138A
SN74LVC138ARGYR ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LC138A
SN74LVC138ARGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LC138A
SN74LVC138ARSVR ACTIVE UQFN RSV 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ZTP
SN74LVC138AZQNR ACTIVE BGA
MICROSTAR
JUNIOR
ZQN 20 1000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 LC138A
SNJ54LVC138AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9752601Q2A
SNJ54LVC
138AFK
SNJ54LVC138AJ ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9752601QE
A
SNJ54LVC138AJ
SNJ54LVC138AW ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9752601QF
A
SNJ54LVC138AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 4
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC138A, SN54LVC138A-SP, SN74LVC138A :
•Catalog: SN74LVC138A, SN54LVC138A
•Automotive: SN74LVC138A-Q1, SN74LVC138A-Q1
•Enhanced Product: SN74LVC138A-EP, SN74LVC138A-EP
•Military: SN54LVC138A
•Space: SN54LVC138A-SP
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 5
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC138ADBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVC138ADGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LVC138ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LVC138APWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74LVC138APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC138APWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC138APWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC138ARGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
SN74LVC138AZQNR BGA MI
CROSTA
R JUNI
OR
ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jul-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC138ADBR SSOP DB 16 2000 367.0 367.0 38.0
SN74LVC138ADGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74LVC138ADR SOIC D 16 2500 333.2 345.9 28.6
SN74LVC138APWR TSSOP PW 16 2000 364.0 364.0 27.0
SN74LVC138APWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74LVC138APWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
SN74LVC138APWT TSSOP PW 16 250 367.0 367.0 35.0
SN74LVC138ARGYR VQFN RGY 16 3000 367.0 367.0 35.0
SN74LVC138AZQNR BGA MICROSTAR
JUNIOR ZQN 20 1000 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Jul-2013
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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