MXOSOTIA CONTENT 1.0 FEATURES 1.1 DIFFERENCE BETWEEN MX93011 and MX93011A 2.0 FUNCTION BLOCK DIAGRAM 3.0 PIN CONFIGURATION 3.1 PIN DESCRIPTIONS 3.2 PIN TYPE SUMMARY 3.3 MULTIPLEX PINS 4.0 FUNCTION DESCRITION 4.1 LOOP 4.2 MODULAR ADDRESSING 4.3 AUXILIARY REGISTERS 4.4 STACK 4.5 HOLD 4.6 MEMORY MAPS 4.7 CLOCK/TIMER/POWER DOWN 4.8 ADDRESSING MODES 4.9 INTERRUPT 5.0 REGISTERS SUMMARY 6.0 REGISTERS DESCRIPTION 7.0 INSTRUCTION SET SUMMARY 8.0 INSTRUCTION SET DESCRIPTION 9.0 DC CHARACTERISICS 10.0 AC TIMING AND CHARACTERISICS 11.0 ORDER INFORMATION 12.0 PACKAGE INFORMATIONM=ic 1.0 FEATURES 1 16-bit, 46.5ns instruction cycle, up to 21MIPS DSP controller for DAM (Digital Answering Machine) ap- plication. 32-bit ALU and 16-bit auxiliary ALU (ARAU) work in parallel. 8 auxiliary registers for indirect addressing work with ARAU. 32-level hardware stack and nestable interrupt sup- port. 32-bit barrel shifter. 8-instruction looped up to 128 times capability. 64k words program ROM space, 32k words may be internal. External ROM option may replace internal 32K for fast prototyping. MXSOSOTIA 64k words SRAM space, 2048 words internal. 32 internal |O address. 1 independent interrupt pin, 1 NMI pin. 8 input pins. 8 bi-direction I/O pins. 19 output pins. Hold or slow system clock for power management. 1/1024 sec orl ms system tick timer for system timing. One Codec interface. Built-in DRAM Controller;1G addressing space, with 1/4/8/16 data bit interface support. 0.6u Single 5V supply, 100 pins PQFP .1 DIFFERENCE BETWEEN MX93011 AND MX93011A . external memory wait state: I/o register(8) MX93011 1 6 5 4 3 2 1 0 | Lo 1] 4 l1 1 | 4 1 1 MMSIZE SRAMWAIT MMWAIT ROMWAIT MX93011A 10 9 8 Z 6 5 4 3 2 1 0 o| 4 1 | 4 { 1 { 1 | 1 { { MMSIZE SRAMWAIT MMWAIT ROMWAIT 2.stack register: MX93011 :16x16 MX93011A:32x16 stack pointer register: MX93011 2 1 0 ee ee ee ee MX93011A | | | | 3 | 2 1 0 0 0 0 0 0 3.internal ROM: MX9301 1 MX93011A 18Kx16 382Kx16 4.SINGLE LOW X' TAL MODE: In MX93011A, high X' TAL is no longer needed. High clock(32.256 MHz) required for DSP running with can be generated from FLL (Frequence Locked Loop) by enabling FLLEN\ pin. X1 and X2 of high X'TAL should be Conpnoctod_to VOD and CN DD racnactiveablyiin thic mada rT fs P/N: PM0402 2 REV. 1.0 , JUL 5, 1996M>= 2.0 FUNCTION BLOCK DIAGRAM MXOSOTIA oO =x wus Qe a = OF oe 5S &x a52c6e2 x Ves xX Sx& xx Zz dose e22 722 8 CLOCK GENERATOR DSP PROGRAM VO PORTS & FLL CONTROL PROGRAM . _ 32x16 ADDRESS UNIT STACK { VO MAPPED 3oKXI6 SECODE REGISTER PROGRAM ROM UNIT A A DATA BUS y ! 1 16x16 texte MUTIPLIER RAM y DATA RAM ADDRESS UNIT LU(S2) _ 1Kx16 RAM hee] ACCUMULATOR(32) +15/-15 SHIFTER MEMORY DRAM CODEC INTERFACE INTERFACE INTERFACE m m mm m m mm 0U QO DBD oO O00 20 =a2U2 8 ZB sxe SD, > aes & B>2R fF BS BL LD 2a 8 ao [3 PROGRAM AUDIO CODEC & DATA DRAMMXOSOTIA 3.0 PIN CONFIGURATION 100 PQFP sdva Z0V4 aNd \NaT14 savas sqva vava edva 2edva Lava odva \HMa \qua \dOd4 \dOd3 Wd10H \C1OH oda aga aNd tds eda eda vada sqa 9qa 404 sda 6qd3 oda HY AH AAG AY AY AY RAY RAY A aerret 2 -2ofx of Bee seh ma seAn oo unwind woO>uzZzz0O00K0000nm ODOAnNOWTYMANTYTOODADANRONTYNNSY HITT ST TTT OMNIAMAANHM bg og eg 62 eg 82 vs Z SG 92 9g ge 4g ve 8g 2 6S 2 og 4 19 02 2g 6L 69 < 8k 9 = Zt gg o SOL 99 ce SL 9 2 vk 8g Ss Sb 69 Zk oz bE bZ OL el 6 ez g bl Z gz 9 gz S ZL v gz 6L Z os L EAMYTMONRARDOL AMY HMORNDADS OOOO DO OO O OP OO) OP : OD OP OD OP OP OD TNPOOY MENG AEFSIESONE ASeSsea SSsehheehah 99 WQS SLOW WSU Houde Ue OU 2Old old yola sold g9old 4018 aNd aga Oldl bLel ldl Eldl vldl Sldl 9ldl Zldl \dx OZEX IZEx OLdO bLdoO ldO LdO vldO SldO 91dO 1dO 8LdO0 61LdO OlldOM=Ic 3.1 PIN DESCRIPTIONS POWER/CLOCK/CONTROL PINS: MXOSOTIA SYMBOL PIN TYPE PIN NUMBER DESCRIPTION VDD 23, 43, 69, 84 5V power source GND 24, 44,53, 70,85 Ground X1/VDD 88 32.256MHZ Crystal input/CONNECT to VDD in single low X'tal mode X2/GND 89 32,256MHZ Crystal output/CONNECT to VDD in single low X'tal mode RSF 1S 96 Pewer-er Reset. XF\ OA 14 External flag if UPMODX=1. This pin can be directly written by one _-!_ T_T _!_#!_|111111 SP instruction Default inactive {5V-output)_H___ HOLD\1867-Ho id DSP clock down and release bus $$$ HOLDAlY___0A/?_se_Aek to HOLB1 Sigtarm|>ds>s4+#$SH HJ EROM IS 97 Disable internal ROM; use external ROM only. NMI IS 41 Non maskable interrupt pin. INTTY iS 40 Interrupt pin X320 t3 32.768KHZ Crystat output. FLLEN\ IS 54 1: Dual X'tal Mode. MEMORY INTERFACE PINS : au Jee Sol eel il n VU. OTNQle TOW A lal WIOUe, SYMBOL PIN TYPE PIN NUMBER DESCRIPTION EADO-EAD15 OA/Z 61-55, 52-45, 42 DSP IO/RAM/ROM external address bus. EADO-EAD14 are for DRAM address. EDO-ED15 IT/OA/ZR 68, 71-83, 86-87. DSP IO/RAM/ROM/DRAM external data bus. With Soft latch feed back current is 250uA. EDCE\ OA/Z 65 External data chip enable. EPCE\ OA/Z 64 External program chip enable. ERD\ OA/Z 63 SRAM/ROM/O external read. EWR\ OA/Z 62 SRAM/ROM/IO external write. CAS\ OA 90 DRAM column address select. RAS\ OA 93 DRAM row address select. DRD\ OA 91 DRAM read. DWR\ OA 92 DRAM write.M=Ic CODEC INTERFACE PINS: MXOSOTIA SYMBOL PIN TYPE PIN NUMBER DESCRIPTION CFS OA 35 Codec frame sync, 8 KHz. (9.6KHz) Output low in power down mode. CMCK OA 36 Codec master clock, 1.536 MHz. Output low in power down mode. CDX0 OA 34 Codec data transmit CDRO IS 38 Codec data receive OPT : Output port SYMBOL PIN TYPE PIN NUMBER DESCRIPTION OPTO-OPT15 OB 11-1,100-98 Output to pin, all output values are registered and may be read back 95,94 when read by IN instruction. OPT16-OPT18 IT/OA/ZR 33,37,39 Output to pin, when UPMODX=1 BIO : Bi-direction I/O SYMBOL PIN TYPE PIN NUMBER DESCRIPTION BIO7-BIOO IT/OA 25-32 Input/output port when UPMODX=1. Direction is controlled by BIO15-BIO8, (see BIOR). IPT : Input port SYMBOL PIN TYPE PIN NUMBER DESCRIPTION IPT4-IPT7 IS 18-15 Input port. IPTO-IPT3 ISH 22-19 Input port with internal pull high resister(R=30k ohm) NOTE: IT TTL level input IS CMOS level schmidt trigger input (hysteresis:2V~3V) ISH CMOS level Schmidt trigger input with internal pull high resistor(~30k ohm) OA 8mA drive level output OB 16mA drive level output Z high impedance state ZR high impedance state with soft latchNM=Iic MX93011A 3.2 PIN TYPE SUMMARY : INPUT : CMOS level schmidt trigger INPUT: IPT7~IPT4,CDRO,INT1\.NMI\,FLLEN\,HOLD\,RST\,EROM CMOS level schmidt trigger INPUT with internal pull high resister: IPT3~IPTO OUTPUT: 8mA drive level output: XF\,CDX0,CFS, CMCK,RAS\,CAS\,DRD\,DWR\ 8mA drive level output/ high impedance state EAD15~EADO,HOLDA\,EPCE\,EDCE\,ERD\,EWR\ 16mA drive level output : OPT15~OPTO BI-DIRECTION: TTL level input/BmA OUTPUT /high impedance state BIO7~BIOO TTL level input/8mA OUTPUT/high impedance state/soft latch ED15~ED0 , OPT18~OPT16 3.3 MULTIPLEX PINS PIN NUMBER PINNAME UPMODX=1 (non_up mode) PIN NAME UPMODX=0(up mode) 25~32 BIO(7:0) Input/output port HDB(7:0) Host data bus 39 OPT18 Output port HILO High low data select 37 OPT17 Output port HRD\ Host read 33 OPT16 Output port HWR\ Host write 14 XF\ External flag ACK\ Acknowledge to host NOTE UPMODX:up mode select bit in CONTROL register,"0" is its power on reset value. PIN NUMBER PIN NAME ~ FLLEN\=1(Dual x'tal) PIN NAME FLLEN\=QO(single xtal) 88 x1 32.256MHZz crystal input VDD Power VDD 89 x2 32.256MHz crystal output GND Power ground NOTE FLLEN\:pin 54.NM=Iic MX93011A 4.0 FUNCTIONAL DESCRIPTION 4.1 LOOP Repeat or loop instruction is important in DSP operation. The MX93011A supports this function by implementing many instructions which are implictly repeated with the number stored in the RCR_ register. Loop up to 8 instructions with specified number of times (can be variable) is also implemented with hardware. Furthermore, flexible usage format is supported which makes the instruction more useful. 4.2 MODULAR ADDRESSING Modular addressing is by modular operation at the output of ARAU. To use modular addressing user must first store non-zero number m which is stored to the MODR register. With this in effect, memory space beginning from k-2"to k-2"+m, where k is an integer greater than or equal to zero and 2" is a power-of-two integer greater than m, will form a circular memory space. Whenever boundary location, 0 or m, is addressed, the next AR content will be set/reset to m/0, independent of the instruction specification. Set MODR to 0 will deactivate modular addressing. For example, if MODR is set to 23, circular memory spaces will start from 32:k to 32:k+23. Any instruction can be indirectly addressed to 55, assuming that using AR1, with increasing operation, will make the next AR1 content to be reset to 32. Likewise, if AR1 content is in decreasing operation and the content of AR1 is set to 0, then the next value of AR1 will be reset to 23. If normal addressing mode is desired, simply output a 0 into the MODR registers. This instruction can help construct data RAM into circular buffer or delay line, thereby eliminating the need of physical data movement in the buffer or delay. However, the pointer need to be kept in the data RAM for easy access to the head/tail of this buffer/delay line. 4.3 AUXILIARY REGISTERS Eight 16 bits auxiliary registers are allocated together with a 16-bit adder/subtractor. The results of adder/ subtractor always go through a modulator to get modular addressing before being stored to the auxiliary registers. The process provides an independent processor to do address calculation and update in parallel with main data path which performs the instruction execution. Of course, AR registers can also be used as temporary registers and as another unsigned adder/subtractor. AR register modification of +(0,1,2,AR0) on the fly is also included. 4.4 STACK Hardware contains 32 deep dedicated stack memories, which support deep hierarchy code. Stack manipulation is transparent to firmware. 4.5 HOLD Hardware hold is supported through pins HOLD\ and HOLDA\. When HOLD\ is activated, the MX93011A will enter hold state after the present instruction cycle is completed(instructions inside Loop and inherent repeat instruction cycles is considered one instruction cycle). At hold state, the MX93011A will release address and data bus to high impedence, stop executing instruction and output HOLDA\. After HOLD\ is invalid the MX93011A will bring HOLDA\ to high and resume normal operation.NM=Iic MX93011A 4.6 MEMORY MAPS: PROGRAM ROM PROGRAM ROM DATA RAM or RAM (ext) or RAM (ext) Oh Oh Oh ON CHIP RAM ON CHIP O7FFh ROM 0800h O7FFh ALL 8000h EXTERNAL EXTERNAL EXTERNAL FFFFh FFFFh FFFFh EROM='0" EROM="1 4.7 CLOCK/TIMER/POWERDOWN High frequency clock(32.256MHz) required for DSP running with can be generated from X'TAL oscillator directly or derived from FLL (FREQUENCY LOCKED LOOP) by enabling FLLEN\ pin. One DSP instruction cycle needs one and half high clock cycle, so the DSP instruction cycle time is 46.5 nano seconds. When PWDN bit in CONTROL register(I/O register 07) is set, high X'TAL and FLL will be disabled, the DSP running clock will switch to be low clock (32768 Hz) to reduce operating power. When this PWDN bit is reset, DSP will keep on slow speed running for 62.5 mili Second, then switch back to normal speed running. LSRUNS bit in CONTROL register will reflect the status of the DSP running speed. Timer interrupt request is generated every one milli second or 1/1024 second depending on HSSRC bit being set or reset. In power down mode, interrupt occurs every 1/32 second. HSSRC bit must be reset prior to high X'TAL shut down. In single low X'TAL mode, clock from FLL output is not prescise enough to be used as timer base. Choosing low clock directly from low X'tal output is better. (HSSRC="0") 32.256 MHz { DSP it 5 : DSP CLOCK CORE $21 > CFS 48 o 4 > CMck FLL (8 KHz) PWDN 32 KHz 1 y~ 239 0 TIMER 32768 H2 0 L 1] INTERRUPT tt $ 32 to DSP HSSRG PWDNNM=Iic MX93011A 4.8 ADDRESSING MODES IMMEDIATE CONSTANT Immediate constant is coded directly in opcode. DIRECT MEMORY ADDRESSING DPR and IOPR are used to completely specify addressing spaces. 4 bits in DPR combined with 7-bits coded in opcode, make direct memory address. (direct memory addressing only for internal 2K WORDS RAM) INDIRECT ADDRESSING The memory address may be pointed by ARs. ARs also has post-addressing execution which provides powerful increment(s)/decrement(s) and modular indexing. It takes only 7 bits to code all these into one opcode to enable program size compact. See AR, ARAU and MODR for more details. MISCELLANEOUS ADDRESSING MODE CALL--Call subroutine at the second word of call instruction. CALA--ACCH indirect call, ACCH=called address BACC-- ACCH indirect branch, ACCH=branch address TRAP-- Always call to hex O00C address 10NM=Iic MX93011A 4.9 INTERRUPT : OPERATIONS The Interrupt source, vectoring address and priority are as follows: NAME VECTORED ADDRESS DESCRIPTIONS RST\ 0000 Power-on reset (top priority) NMK 0002 NMI\non.maskable interrupt, edge-triggered (high to low) Ss 0004 Single-Step, Single step interrupt is for debugging purpose. If set, the MX93011A will be interrupted after every instruction cycle (instructions inside LOOP and inherent repeat instruction cycles is considered as one instruction cycle). User can put debugging service as the interrupt service routine. INT1\ 0006 INT1\ pin interrupt, edge trigged CODEC 0008 Triggered when Codec registers get/send 16 bit data (see Timing diagram) STMR OO00A Triggered by every 1/1024 second or 1milli second depend on the value of HSSRC in normal running, but triggered by 1/32 second in power down mode. TRAP 000C Triggered when executes TRAP Interrupt Process: (Execute by hardware) Release related ISR pending flag Push SSR onto stack Push return-address onto stack Disable global interrupt (same to excuting DINT instruction) If it is in software hold state (See WSTR register and power management), reset SWHOLD 0, and come out of software hold state. ar oNw > Issues of RETI instruction: (Execute by hardware) 1. POP return address to PC 2. POP SSR Note that ACC normally need to be saved. All other registers should also be carefully maintained when doing an in-and-out interrupt. 11M=Ic 5.0 REGISTERS SUMMARY MXOSOTIA NAME BIT CTLR 10 ADDRESS RELATED INSTRUCTIONS DESCRIPTIONS optr 16 oO 0 IN/OUT output register iptr 8 oO 1 IN input port register bior 16 oO 2 IN/OUT bidirectional io register svr 4 3 IN/OUT/SFR/SFL shifter count (scr) and sign imr 4 4 IN/OUT interrupt mask register isr 3 5 IN interrupt status register ctlr 15 7 IN/OUT control register wstr 8 8 IN/OUT wait state register rer 7 12 IN/RPT/LUP repeat counter modr 7 13 IN/MOD modulo register spr 4 15 PSH/POP/IN/PSHH/POPH stack pointer register PSHL,POPL cdrrO 16 16 IN codec 0 receive buffer cdxr0 16 oO 17 OUT codec 0 transmit buffer acch 16 - (many instr.) upper word of DSP accumulator accl 16 - SAL/ADL/SBL lower word of DSP accumulator ar0-7 16x8 - LAR/MAR/SAR for indirect memory access basically; also used in macro instructions accx 32 - SBL, ADL, SFL SFR,multiply acch+accl=accx ssr 16 SSS/OUT/BS/BZ status register INTM : EINT/DINT TB: BIT OVM : ROVM/SOVM ARP : MAR pe 16 - CALL, CALA, TRAP, BS, BZ program counter BAGG, RET, RETI, interrupt, hardware reset 12NM=Iic MX93011A 5.1 TABLE OF 1O MAPPED REGISTERS AND ITS POWER ON VALUES F E D C B A 9 8 7 6 5 4 3 2 1 0 OPTR:(00) Oo Oo 6 6 6 Oo Oo 6 6 Oo 6 6 Oo 6 6 6 RW , OPT15 | opti4 | OPT13 | OPTi2 | OPTi1 | optio | opte | opte | opt7 | opte | opts | opta | OPT3 | opre | opti | opto IPTR:(01) x x x x x x x x RO Piz | pre | pts | pts | iets | pre | teri | pro BIOR:(02) 6 6 a 6 0 0 0 0 6 0 0 a 6 0 a 0 RW , BIOR15 | BIOR14] OPTIS | BIOR18| BIOR11 | BloRt0| BlORe | BIORS | BIOR7 | BiORe | BioRS | BIOR4 | BIORS | Biore | BIOR1 | BIORO . 0 6 6 6 SVR:(03) geualecns RW IMR-(04) ' \ 1 ' RW SSM_|STMRM |CODCM | INTIM ISR:(05) 0 | Ro STMRS | CODCS | INTIS ; o 6 O 0 6 0 0 0 0 6 0 6 O CTLR:(07) oPtis | opti7 | optie | PWON baad uMoo lempRovisruns| ss [HssRc| suse luemoowcesse.| PW ; 1 6 1 i 1 1 j j 1 1 1 WSTR:(08) MM SIZE SRAM WAIT MM Walt ROM WAIT RW . 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 0 MMAC.(09) MMCNT (Mass Memory move Count. 6 bits) iRAUintermal RAM Address. brank one, 10 bits) RW MMAPL:(10) RW MMAPH:(11)|TOIRAM AW RCR:(12) p 8 8 p p 8 8 RO MODR;(13) 8 o 0 e 8 o 0 RO SPR:(15) 0 0 0 Q 0 RO CDRRO:(16) x x x x x x x x x x x x x Xx x x RO CDXRO:(17) |X x X x x x x x x x x x x x x x wo 13NM=Iic MX93011A 6.0 REGISTER DESCRIPTION 10 REGISTERS 6.1 OPTR : Output Register (mapped to IO register 00) F E D Cc B A 9 8 7 6 5 4 3 2 1 0 lOPT15 |OPTO RW Output Register (OPTR:15 ~ OPTR:0) 16 bit, connect to OPT15~OPTO pins. positive Logic, '1' will output 5 Volt on output pin. ('0' for 0 V) 6.2 IPT : Input Port Register (mapped IO address 01) F E D c B A 9 8 7 6 5 4 3 2 1 0 ee ee Bo RO = Input Port (IPT:7~IPT:0) Positive Logic, 5 Volt input will read '1' (OV for '0) IPT:7~IPT:0 connect IPT7~IPTO pins. 6.3 BIOR/CMDR : BI-DIRECTION IO REGISTER (mapped to IO register 02) F E D c B A 9 8 7 6 5 4 3 2 1 0 iBiono | RW When UP MODX=1, used for bidirectional io register. Programable bidirectional 10. BIOR15~BIOR8 control I/O direction of BIOR7~BIORO, respectively (bit 8 control bit 0) BIOR7~BIORO connect to BIO7~BIO0 pins, respectively. 14NM=Iic MX93011A 6.4 SVR : Shift Variable Register (mapped to IO register 03) SVR includes Shift-Count Register (SCR) F E D Cc B A 9 8 7 6 5 4 3 2 4 0 When SFL/SFR instruction gives 0 as shift count, DSP uses the SCR default count as shifting count. This mechanism provides run-time assigned shifting value. 6.5 IMR : Interrupt Mask Register (mapped to IO register 04) F E D Cc B A 9 8 7 6 5 4 3 2 1 0 SSM ff STMRM ficopcm BINT1M RW 6.6 ISR : Interrupt Status Register (mapped to IO register 05) F E D Cc B A 9 8 7 6 5 4 3 2 1 0 RO ISTMRSHCODCSHRINT1S} INT1M - INT1 \ Interrupt Mask 1 STMRM_ -_ System tick Timer interrupt Mask CODCM -_ Codec Interrupt Mask SSM - Single Step Interrupt Mask Note 1: Codec Tx/Rx use this same mask. This is because the 2 events are synchronized and always happen at the same time. Programmers should take care of these 2 events (if necessary) in this interrupt. Note 2: ISR:2~0 will reflect interrupt pending status on IMR:2~0. Note that Single-Step (CTLR:SS, register 07) is directly controlled by the program; no status exists. Note 3: Read ISR will read and clear all pending flags. 15M=Ic 6.7 CTLR: MXOSOTIA CONTROL REGISTER (MAPPED TO IO REGISTER 07) 1: DSP runs at 32768 HZ until 1: It works as external hardware HOLD\ _1: DSP will hold after the current fetched 0: up mode. reset to 0 pin except issued by instructions and instruction has been excuted. 1: non_up mode. 0: normal operation. cleared by interrupt. 0: DSP runs until external bus is 0: normal operation. accessed. 1: 32 KHZ clock is generated from Hi- crystal or FLL 0: 32768 HZ clock is from low crystal E D Cc B A 9 8 7 6 5 4 {3 2 1 0 RW OPT18 MOPT17 JMOPT16 BEPWDN JASWHOLD| ee IHSSRC ESNSEL JUPMODx JICFSSEL| 0: normal operation. 1: single step mode. A interrupt will | 7: select 9.6 KHZ codec It's a status bit. 0: DSP is running at high speed mode. 1: DSP clock is 32768 HZ occur at end of each instruction. | frame sync. 0: select 8 KHZ codec frame syne. In non-yp mode, The statuses of OPT18, OPT17, OPT16 will be reflected to PHILO, PHRDB\, PHWR\ respectively. 0: no sign extension 1: output 5v to PHILO\, PHRDB\ and / 1: MSBs sign extented in ADL, ADLL, PHWRB\ pins in up mode. CMDRDY is cleared by CMDR read. SBL and SBLL instructions. 0: output Ov to PHILO\, PHRDB\ and 1: aenal up writes a command to PHWRB\ pins in up mode. 0: no write operation. 6.8 WSTR: WAIT STATE, AND DRAM SIZE REGISTER (MAPPED TO IO REGISTER 08) F E D c B A 9 8 7 6 5 4 3 2 1 0 IMMSIZE | ISRAMWAIT MMWAIT ROMWAIT RW MASS MEMORY SIZE : Select DRAM configuration 00 -- x1 01 -- x4 10 -- x8 11 -- x16 WAIT STATE: Note: Choose apporiate WAIT_STATE number to meet the following requirement. 1.RAM/ROM(SRAM WAIT,ROM WAIT) TAA or TCS < 31 ns * (1.5 + WAIT_STATE) -20ns 2.DRAM(MM WAIT) TRAC < 15.5ns * (6 + WAIT_STATE) -20ns........ (1) TCAC < 15.5ns * (2+WAIT_STATE)-20ns. ......... (2) Choose the larger WAIT_STATE in (1) and (2) as MM WAIT TAA is the address access time. TCS is the chip select access time. TRAC is the access time from RAS\. TCAC is the access time from CAS\. 16NM=Iic MX93011A 6.9 MMACR : MASS MEMORY ACCESS CONTROL REGISTER (MAPPED TO IO REGISTER 9) F E D c B A 9 8 7 6 5 4 3 2 4 0 6.10 MMAPL : Mass Memory Access Pointer Low register (mapped to IO regsiter 10) F E D Cc B A 9 8 7 6 5 4 3 2 1 0 6.11 MMAPH : Mass Memory Access Pointer High register (mapped to IO register 11) Writing (OUT) a non zero value into MMCNT (REG 9) will start DATA movement between external DRAM and internal data RAM and hold DSP operation till MMCNT=0. The starting address of data RAM and DRAM are pointed by IRA (REG 9) and MMAPH+MMAPL (REG 10 and 11). Data movement will stop when DRAM address reach MMAPH+MMAPL+MMCNT. Total data words being moved depend on what the DRAM configuration is. Only data in RAM bank 1 can be moved around. The direction of movement is decided by TOIRAM(REG 11). TOIRAM=1, DRAM --> INTERNAL RAM TOIRAM=0, DRAM<-- INTERNAL RAM Total 30 bits of MMAPH+MMAPL can address up to 1 Giga DRAM space. 17NM=Iic MX93011A 6.12 RCR: Repeat Counter Register (mapped to IO register 12) * RCR provides repeat count on, LUP RCR must be prepared before macro instructions are being executed. (RPT instruction) Repeat time is RCR+1 6.13 MODR : MODULAR REGISTER (MAPPED TO IO REGISTER 13) F E D Cc B A 9 8 7 6 5 4 3 2 4 0 As MODR=M - 0, 1, 2, ... M-1, M modulo mechanism will be enforced (note: bounded by M --- not M-1) Modular addressing is always performed at the output of ARAU. As MODR=0, modulo addressing is disabled. MOD type instructions are used to load MODR; use IN instruction to read MODR. 6.14 SPR : Stack Pointer Register (mapped to IO register 15) 32-level stack provides nestable interrupt and controller level nested call capabilities. SPR is pointing to 'next-available word, and initialized to 0. As SPR is over address 31, it wraps around to 0. As SPR=0, POP will also wrap SPR to 31. SPR can only be read by IN instructions; no write capability. 6.15 CDRR 0: Codec Data Receive Register (Mapped to IO register 16) 18NM=Iic MX93011A 6.16 CDXR 0: Codec Data Transmit Register (Mapped to IO register 17) 1. Two Codec events from the above registers are always synchronized, so there is only one Codec interrupt for them. 2. These codecs are in 16-bit mechanism; however, 8-bit Codec is also applicable. In 8-bit case, to tx, the data byte to be transmitted must be in bit15~bit8. The received data byte is at bit15~bit8 as read from receive register. 3. MSB (Most-Significant-Bit) is shifted first. 4. Codec registers has shadow registers as buffer. 6.17 ACC:ACCUMULATOR ACC = ACCH + ACCL | | ACCH ACCL * acch+accl=acc * Logic ALU operation is 16 bits and executed on acch. (ACCL is not affected) * ADL/SBL is 32-bit operation. (SVR:SNSEL determine sign-extended) * Lac will put ACCL to 0 19M=Iic MX93011A 6.18 SSR : STATUS REGISTER ssr includes 8 testable status/register bits (ssr:15~8), and 3 arp bits, 2 IOP bits, 4 DP bits SGN and ACZ reflect status of ACCH. (can not be saved) This bit has two functions. It provides an always true" condition for effectively unconditional branch (jump). It's also treat as "INTM", global interrupt 4-bit data page pointer mask status. It can be only set 1 reset by | ACC zero flag overflow mode enable, defines 16 pages, 128 EINT and DINT if INTM=1, interrupt is This bit reflects ACCH used for overflow protection address in each page, of prohibited. current status directly. during +/ -/shift operations. internal RAM so, it is read only. sign flag reflect ACCH directly, read-only ARZ BBESGN | lOPR4~3 wo I testable overflow flag for the last acch Test bit, IOPR define 4 operation the tested memory bit is current active int Pages, 8 address in each page ARZ registering the moved to TB register register rointer.. ; of IO space last operated AR=0 (BIT instructions) neve are 8 16-bit AR registers a conditional test is normally followed but not necessary 6.19 AR (AUXILIARY REGISTER) AND ARAU (AUXILIARY ALU) arO ar1 ar2 AUXILIARY REGISTERS ar3 ar4 ar5 ar6 ar7 ARAU AUXILIARY ALU ee * 16x8 AR registers provide powerful indirect memory access. * Modulo addressing (modulo memory indexing) provides easy implementation of ring buffer or delay line. See modulo register (MODR) for more details. ARAU provides +/ - (0, 1, 2, ARO) post execution after each addressing of ARs. * ARAU works in parallel with main ALU. * ARs may be also used as scratch registers. 20NM=Iic MX93011A 6.20 PC AND PROGRAM FLOW CONTROL PC Program flow is affected by: BS/BZ (branch-if-set/branch-if-zero) conditional branch. BACC - branch indirectly by ACCH. CALA - call indirectly by ACCH, return address is pushed. CALL - call subroutine, see Addressing Modes, Misc. Addressing mode' TRAP - Trapped to call fixed hex 000C address. Power-on reset and interrupt see interrupt Operations ounrwnN> 21NM=Iic MX93011A 7.0 INSTRUCTION SET SUMMARY ABBREVIATIONS a : AR pointer ar : AR acc : accumulator c : short constant d : data memory address dp : data page pointer i : Addressing mode select bit k odd/even address select | loop counter L constant for shift left mr : modulo register 0 : io page pointer pa : port address pc : program counter R : constant for shift right rc : repeat counter Ss : shift right sign extention select bit sp : stack pointer ss : status register SV : shift register Vv : AR arithemetic operation selection x : don't care y : Next AR arithmetic register selection Mnemonic and Description Words & cycles 16-bit opcode MSB LSB 1001 1000 Oxxx = xxxx 0000 0000 iddd_ dddd 0000 0001 Occc cccc 1000 0000 Oxxx = xxxx 0000 0010 iddd = dddd 0000 0011 Oxxx = xxxx 1000 0001 Oxxx = xxxx 0000 1010 iddd = dddd 0000 1011 Occc cccc 1000 0101 Oxxx = xxxx 1111 1010 Oxxx = xxxx 0110 bbbb iddd = dddd abs ; absolute value of accumulator adh ; add to high acc adhk; add to high acc. short immediate adhl ; add to high acc. immediate adl ; add to low acc adlk ; add to low acc. short immediate adil ; add to low acc. immediate and ; and with high acc andk; and short immediate with high acc andl ; and immediate with high acc bacc; branch to address specified by acc bit ; test bit = po = po $] =$ no = + a mS hop 4H U4 Pu Uf UU 22NM=Iic MX93011A Mnemonic and Description Words & cycles 16-bit opcode MSB LSB bs ; branch immediate if bit set 2,3 1101 bbb Oxxx = xxxx bz ; branch immediate if bit reset 2,3 1101 Obbb Oxxx = xxxx cala ; call subroutine indirect specified by acc 1,2 1100 0000 Oxxx XXXX call ; call subroutine 2,3 1111. 1100 0000 90000 dint ; disable interrupt 1,1 1111. 0000 Oxxx = xxxx eint ; enable interrupt 1,1 1111 0001 Oxxx = xxxx in ; input data from port 1,1 1010 pppO iddd = dddd lac ; load acc 1,1 0000 1110 iddd dddd lack ; load acc. short immediate 1,1 0000 1111 Occc cccc lacl ; load acc. immediate 2,2 1000 0111 Oxxx = xxxx lar ; load auxiliary register 1,1 0111 aaaO iddd = dddd lark ; load auxiliary register short immediate 1,1 0111 aaal Occc cccc larl ; load auxiliary register immediate 2,2 1000 1000 Oaaa 0000 Idp ; _ load data page register 1,1 0001 0100 iddd dddd Idpk ; load short immediate to data page 1,1 0001 0101 Oxxx cccc register lip ; load io page register 1,1 0001 0010 iddd dddd lipk ; load io page register with short 1,1 0001 0011 Oxxo Oxxx immediate lup ; loop instruction 1,1 0101 ~=Iild iddd dddd lupk ; load re with 7-bit constant and enable 1,1 0101 sill Occc cccc loop operation mar ; modify auxiliary register 1,1 1111. 0110 1ddd = dddd mod ;_ load modulo register 1,1 0001 0110 iddd dddd modk ; load modulo register short immediate 1,1 0001 0111 Occc cccc nop ; no operation 1,1 1414410061111 -1111 1111 or ; or with high acc 1,1 0000 1000 iddd = dddd ork ; orshort immediate with high acc 1,1 0000 1001 Occc cccc orl ; or immediate with high acc 2,2 1000 0100 Oxxx = xxxx out ; output data to port 1,1 0100 pppO iddd dddd outk ; output short immediate to port 1,1 0100 pppi Occc cccc outl ; output immediate to port 2,2 1000 1111 Oppp 0000 pop ; _ pop top of stack to data memory 1,1 1011. 0101 iddd = dddd poph ; pop top of stack to high accumulator 1,1 1001 0100 Oxxx = xxxx popl| ; pop top of stack to low accumulator 1,1 1001 1011 Oxxx = xxxx psh ; push data memory value onto stack 1,1 1100 1010 iddd dddd pshh ; push high accumulator onto stack 1,1 1100 1000 ivvw ww pshl ; push low accumulator onto stack 1,1 1100 1001 dvvw vw ret ; return from subroutine 1,2 1111. 1000 Oxxx = xxxx reti ; return from interrupt 1,2 1111 1001 Oxxx = xxxx rpt ; load repeat counter 1,1 0001 0000 iddd = dddd rptk =; load rc with 7-bit constant 1,1 0001 0001 Occc cccc rxf ; reset external flag 1,1 1111 0010 Oxxx = xxxx 23NM=Iic MX93011A Mnemonic and Description Words & cycles 16-bit opcode MSB LSB sah ;_ store high acc. 1,1 1011 0000 iddd = dddd sal ; store low acc 1,1 1011 0001 iddd = dddd sar ; store auxiliary register 1,1 1011 taaa iddd = dddd sbh ; subtract from high acc 1,1 0000 0100 iddd = dddd sbhk ; subtract short immediate from high acc1,1 0000 0101 Occc cccc sbhl ; subtract immediate from high acc 2,2 1000 0010 Oxxx = xxxx sbl ; subtract from low acc 2,2 0000 0110 iddd = dddd sblk ; subtract short immediate from low acc 1,1 0000 0111 Occc cccc sbIll ; subtract immediate from low acc 1,1 1000 0011 Oxxx = xxxx sdp ;_ store datapage register 1,1 1011. 0100 iddd = dddd sfl ; shift acc left 1,1 1001 1101 0000 LLLL sfr/sfrs ; shift acc right 1,1 1001 1110 000s RRRR sip ; store iopage register 1,1 1011. 0010 iddd = dddd sss; store ss register 1,1 1011. 0011 iddd = dddd sxf ; set external flag 1,1 1111. 0011 Oxxx = xxxx trap ; software interrupt 1,2 1100 0010 Oxxx = = xxxx xor ; xor with high acc 1,1 0000 1100 iddd = dddd xork ; xor short immediate with high acc 1,1 0000 1101 Occc cccc xorl ; xor immediate with high acc 2,2 1000 0110 Oxxx = xxxx 24M=Ic MXOSOTIA 8.0 INSTRUCTION SET DESCRIPTION abs SYNTAX: EXECUTION: WORDS: CYCLES: adh SYNTAX: EXECUTION: WORDS: CYCLES: Adhk SYNTAX: EXECUTION: WORDS: CYCLES: absolute value of accumulator. Bit: 15 14 13 12 11109 8 7 6 5 4 3 2 1 =9Q 10011 00 0 0 ABS (pc) +1 > pe jJacc(31:16)| > (acc (31:16)) 1 1 add to high acc. direct: 15 14 138 12 11109 8 7 6 5 4 3 2 1 QO 0 0 0 0 0 0 0 OO QO | data memory address indirect: 15 14 138 12 11109 8 7 6 5 4 3 2 1 QO 00 0 0 0 0 0 0 =1 see note 1 adh dma7 adh *(,nar) (pc) + 1 pe (acc(31:16))+(dma) (acc (31:16)) { 1(Dl) 2(DE) add to high acc. Short immediate. BIT: 15 14 138 12 11109 8 7 6 5 4 3 2 1 QO 0 0 0 0 0 0 0 1 =0 7-bit constant adhk cnst 7 (pc) +1 > pe (acc(31:16)) + (7-bit constant) > (acc (31:16)) 1 1 25adhl SYNTAX: EXECUTION: WORDS: CYCLES: adl SYNTAX: EXECUTION: WORDS: CYCLES: NOTE: Cc MX93011A add to high acc. Immediate. BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #90 1 0 0 0 0 0 0 0 0 16-bit constant adhl cnst16 (pc) +2 > pc (acc(31:16))+(16-bit constant) > (acc (31:16)) 2 2 add to low acc. Direct: 15 14 13 12 11109 8 7 6 5 4 32 1 #90 0 0 0 0 0 0 1 0 =O data memory address Indirect: 15 14 13 12 11109 8 7 6 5 4 32 1 #90 0 0 0 0 0 0 1 0 =1 see note 1 adl dma7 adl *(,nar) (pc) +1 > pe (acc)+(dma with optional MSBs sign extension) > (acc) 1 1(Dl) 2(DE) Option is controlled by CTRL: SNSEL bit 26NM=Iic MX93011A adlik add to low acc. Short immediate. BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9 0 0 0 0 0 0 1 14 #90 7-bit constant SYNTAX: adlk cnst7 EXECUTION: (pc) + 1 pc (acc)+(7-bit constant) (acc) WORDS: 1 CYCLES: 1 adil add to low acc. Immediate. BIT: 15 14 13 12 11109 8 7 6 5 4 3 21 #90 1 00 0 0 0 0 1 #0 16-bit constant SYNTAX: adil cnst16 EXECUTION: (pc) +2 > pc (acc)+(16-bit constant with optional MSBs sign extension) (acc) WORDS: 2 CYCLES: 2 Note:option is controlled by CTRL :SENSE bit 27NM=Iic MX93011A and and with high acc. direct: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9Q 0 0 0 01 0 1 0 =O data memory address indirect: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9Q 0 00 0 1 0 1 0 1 see note 1 SYNTAX: and dma7/ and *(,nar) EXECUTION: (pc) + 1 pc (acc(31:16)) .and. (dma) (acc(31:16)) WORDS: 1 CYCLES: 1(Dl) 2(DE) andk and short immediate with high acc. BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9Q 0 0 0 0 1 0 1 +1 =~0 7-bit constant SYNTAX: andk cnst7 EXECUTION: (pc) +1 > pe (acc(23:16) .and. (7-bit constant) > (acc(23:16)) 0 > acc(31:24) WORDS: 1 CYCLES: 1 28andl SYNTAX: EXECUTION: WORDS: CYCLES: bacc SYNTAX: EXECUTION: WORDS: CYCLES: and immediate with high acc. BIT: 15 14 13 12 11109 8 7 MXOSOTIA 6 5 4 3 2 1 #0 1 00 0 0 1 0 1 #40 16-bit constnat andl cnst16 (pc) +2 > pc (acc(31:16)) .and. (16-bit constant) > (acc(31:16)) branch to address specified by acc. BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #0 1 14 1 94 14 0 1 0 0 bacc (acc (31:16)) > pe 1 2 29NM=Iic MX93011A bit test bit. direct: 15 14 13 12 11109 8 7 6 5 4 3 2 1 =O 0 1 1 =#0 bbbb 0 data memory address indirect 15 14 13 12 11109 8 7 6 5 4 3 2 1 QO 0 1 1 40 bbbb 1 see note 1 SYNTAX: bit dma7, bbbb bit * bbbb (,nar) EXECUTION: (pc) +1 > pe (dma) > ss(tb) WORDS: 1 CYCLES: 1(Dl) 2(DE) bs branch immediate if bit set. BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 =O 1 1 01 49 bbb 0 program memory address SYNTAX: bbb, pmai6 EXECUTION: if ss(#1bbb)=1 then (pma) pc else (pc)+2 pc WORDS: 2 CYCLES: 3 30NM=Iic MX93011A bz branch immediate if bit reset. BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #90 1 14 #0 1 #0 bbb 0 program memory address SYNTAX: bz bbb, pmai6 EXECUTION: if ss(#1bbb)=0 then (pma) > pc else (pc)+2 > pc WORDS: 2 CYCLES: 3 cala call subroutine indirect. BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 =0 1 140 0 0 0 0 0; 0 SYNTAX: cala EXECUTION: (pc)+1 (sp) (acc(31:16)) pc WORDS: 1 CYCLES: 2 31NM=Iic MX93011A call subroutine . BIT: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9Q 1 141 947 14 7 0 0 0 0 0 0 0 0 0 0 16-bit constant SYNTAX: call pmai6 EXECUTION: (pc)+1 (sp) (16-bit constant) pc WORDS: 2 CYCLES: 3 dint disable interrupt. Bit: 15 14 13 12 11109 8 7 6 5 4 3 2 1 QO 11414 1 00 0 0 0 SYNTAX: dint EXECUTION: (pc) +1 > pe 1 (INTM) status bit WORDS: 1 CYCLES: 1 32eint SYNTAX: EXECUTION: WORDS: CYCLES: SYNTAX: EXECUTION: WORDS: CYCLES: enable interrupt. MXOSOTIA Bit: 15 14 13 12 11 10 9 7 6 5 4 3 2 1 =O 1 1 14 1 0 0 #0 0 eint (pc) + 1 pe 0 (INTM) status bit { { input data from port. direct: 15 14 13 12 11 10 9 7 6 5 4 3 2 1 #0 1 0 1 O | port address 0 data memory address indirect: 15 14 13 12 11 10 9 7 6 5 4 3 2 1 #0 1 0 1 O | port address 1 see note 1 in dma7,port in * port(,nar) (pc) + 1 > pe port address a2-a0 (IOPR(4:3)) > a4-a3 0 > a15-a6 (IOR) > dma 1 1; note:only for internal memory 33NM=Iic MX93011A lac load acc. direct: 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 14 141 0 =O data memory address indirect: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9Q 0 0 0 0 1 1 14 0 = =1 see note 1 SYNTAX: lac dma7 lac *(,nar) EXECUTION: (pc) +1 > pe (dma) acc(31:16) 0 > acc(15:0) WORDS: 1 CYCLES: 1(DI) 2(DE) lack load acc. short immediate. Bit: 15 14 13 12 11109 8 7 6 5 4 3 2 1 90 0 0 0 0 1 14 41 +14 ~=0 7-bit sonstant SYNTAX: lack cnst7 EXECUTION: (pc) +1 > pe (7-bit constant) > acc(23:16) 0 > acc(31 :24) 0 > acc(15:0) WORDS: 1 CYCLES: 1 lacl load acc. Immediate Bit: 15 14 13 12 11109 8 7 6 5 4 3 2 1 90 1 0O 0 0 0 1 1 1 =0 16-bit constant SYNTAX: lacl cnst16 EXECUTION: (pc) +2 > pc (16-bit constant) acc(31:16) 0 > acc(15:0) WORDS: 2 CYCLES: 2 34NM=Iic MX93011A lar load auxiliary register. direct: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #0 0 1 1 41 arp 0 0 data memory address indirect: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9Q 0 1 1 41 arp 0 1 see note 1 SYNTAX: lar dma/7, arp lar * arp(,nar) EXECUTION: (pc) +1 > pe (dma)- (ar) WORDS: 1 CYCLES: 1(DI) 2(DE) ; no manipulation on ars lark load auxiliary register short immediate. Bit: 15 14 13 12 11109 8 7 6 5 4 3 2 1 =9Q 0 1 1 1 arp 1 O 7-bit constant SYNTAX: lark cnst7, arp EXECUTION: (pc) +1 > pe (7-bit constant) (ar(6:0)) 0 ar(15:7) WORDS: 1 CYCLES: 1 35NM=Iic MX93011A larl load auxiliary register immediate. Bit: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #90 1 00 0 1 0 0 0 0 arp 0 0 0 0 15 14 13 12 11109 8 7 6 5 4 3 2 1 =9Q 16-bit constant SYNTAX: larl cnst16, arp EXECUTION: (pc) + 2 > pc (16-bit constant) ar (15:0) WORDS: 2 CYCLES: 2 Idp load data-page register. direct: 15 14 13 12 11109 8 7 6 5 4 3 2 1 =O 0 0 0 1 0 1 0 0 0 data memory address indirect: 15 14 13 12 11109 8 7 6 5 4 3 2 1 #9Q 0 00 1 0 1 0 0 1 see note 1 SYNTAX: Idp dma7 Idp *(,nar) EXECUTION: (pc) +1 > pe (dma(3:0)) (dp(3:0)) WORDS: 1 CYCLES: 1(DI) 2(DE) Idpk load short immediate to data page register. Bit: 15 14 13 12 11109 8 7 6 5 4 3 2 1 =9Q 0 0 0 1 0 1 0 +14 +#O;| x x x] 4-bit constant SYNTAX: Idpk cnst4 EXECUTION: (pc) +1 > pe (4-bit constant) (dp(3:0)) WORDS: 1 CYCLES: 1 36NM=Iic MX93011A lip load io page register direct: 15 141312 11109 8 7 6 5 4 3 2 1 #0 0 0 0 1 0 0 1 =O O} data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 0001 00 1 0 1 see note 1 SYNTAX: lip dma7 lip *(,nar) EXECUTION: (pc) + 1 >pc (dma) (iop(1:0)) WORDS: 1 CYCLES: 1(Dl) 2(DE) lipk load io page register with short immediate. Bit: 15 14131211109 8 7 6 5 4 3 2 1 =O 000% 0 0 1 4 0 x x}]st sO}x x x SYNTAX: lipk cnst2 EXECUTION: (pc) + 1 pc s1i iop(1), sO > iop(0) WORDS: 1 CYCLES: 1 37MXOSOTIA lup SYNTAX: EXECUTION: WORDS: CYCLES: lupk SYNTAX: EXECUTION: WORDS: CYCLES: loop instruction. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0O 0 1 O 1 | loop number} 0 O | data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0O 0 1 O 1 | loop number} 0 1 see note 1 lup dma, lic lup * lic(,nar) (pc) + 1 > pe (dma)- (rc) (loop number) > (loop counter) 1 1(DI) 2(DE); the next (loop number+1) words will be repeat (rc+1) times load re with 7-bit constant and enable loop operation. 15 1413 12 11109 8 7 6 5 4 3 2 1 #0 1 loop number 1 0 7-bit constant Bit: 0 1 0 lupk cnst7, lic (pc) +1 > pc (7-bit constant) (rc) (loop number) > (loop counter) 1 1 38NM=Iic MX93011A mar modify auxiliary register. indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1 41447 1 0 1 14 0 41 see note 1 SYNTAX: MAR *(,nar) EXECUTION: (pc) +1 > pe modifies arp, ar(arp) as specified by the indirect addressing field WORDS: 1 CYCLES: 1 mod load modulo register. direct: 15 14131211109 8 7 6 5 4 3 2 1 #0 0 00 1 0 1 1 0 0 data memory address indirect 15 1413 12 11109 8 7 6 5 4 3 2 1 90 000% 01 1 0 1 see note 1 SYNTAX: mod dma7 mod *(,nar) EXECUTION: (pc) +1 > pe (dma(6:0)) mr(6:0) WORDS: 1 CYCLES: 1(Dl) 2(DE) modk load modulo register short immediate. Bit: 15 14131211109 8 7 6 5 4 3 2 1 =O 000% 0 1 41 41 +0 7-bit constant SYNTAX: modk cnst7 EXECUTION: (pc) +1 > pe (7-bit constant) mr(6:0) WORDS: 1 CYCLES: 1 39NM=Iic MX93011A nop no operation. Bit: 15 141312 11109 8 7 6 5 43 2 1 0 147474 47 4 747 447 4 +4 4 +4 ~4~714 ~4 SYNTAX: nop EXECUTION: (pc) + 1 > pe WORDS: 1 CYCLES: 1 or or with high acc. direct: 15 141312 11109 8 7 6 5 4 3 2 1 #0 0 00 01 0 0 0 0 data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 00001 0 0 0 =4 see note 1 SYNTAX: or dma7 or *(,nar) EXECUTION: (pc) +1 > pe (acc(31:16)).or. (dma) (acc(31:16)) WORDS: 1 CYCLES: 1(Dl) 2(DE) 40MXOSOTIA ork SYNTAX: EXECUTION: WORDS: CYCLES: orl SYNTAX: EXECUTION: WORDS: CYCLES: or short immediate with high acc. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 00001 0 0 1 +0 7-bit constant ork cnst7 (pc) +1 > pe (acc(23:16) ).or. (7-bit constant) (acc(23:16) (acc(31:24)) > acc(31:24) 1 1 or immediate with high acc. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 100 00 1 0 0 0 16-bit constant orl cnst16 (pc) +2 > pc (acc(31:16)) .or. (16-bit constant) (acc(31:16) 2 2 4NM=Iic MX93011A out output data to port. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 0 1 O O | port address|O O | data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 0 1 0 O | portaddressjO 1 see note 1 SYNTAX: out dma7, port out port *(,nar) EXECUTION: (pc) +1 > pc (pa) address bus a1-a0 (LOPR)(4:3) > a4-a0 0 > a15-a5 WORDS: 1 CYCLES: 1;note: For internal memory only outk output short immediate to port. Bit: 151413 12 11109 8 7 6 5 43 2 1 0 0 1 O 0O | port address}1 0 7-bit constant SYNTAX: outk cnst7, port EXECUTION: (pc) +1 > pc (pa) address bus a2-a0 (IOPR)(4:3) > a4-a3 0 > a15-a5 (7-bit constant ) IOR (addressed by a4-a0) WORDS: 1 CYCLES: 1; note: For internal memory only 42outl SYNTAX: EXECUTION: WORDS: CYCLES: poph SYNTAX: EXECUTION: WORDS: CYCLES: MXOSOTIA output immediate to port. direct: 15 141312 11109 8 7 6 5 4 3 2 1 #0 1 0 0 0 1 #1 #14 +#1 +O} portaddess0 0 0 O 16-bit constant outl cnst16, port pc) +1> pc ( (pa) address bus a2-a0 (IOPR)(4:3) > a4-a3 0 > a15-a5 (16-bit constant) lOR(addressed by a4-a0) 1 1;note: for internal memory only pop top of stack to high accumulator. Bit: 15 14131211109 8 7 6 5 4 3 2 1 =O 1001 01 0 0 0 poph (pc) + 1 pe (tos) > acc(31:16) 1 1 43NM=Iic MX93011A popl pop top of stack to low accumulator. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 100 1 7 0 141 1 ~=90 SYNTAX: popl EXECUTION: (pc) +1 > pe (tos) > acc(15:0) WORDS: 1 CYCLES: 1 pop pop top of stack to data memory. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0O 1 0 1 1 0 1 =O 1 Of data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1014 1 01 0 14 41 see note 1 SYNTAX: pop dma pop *(,nar) EXECUTION: (pc) +1 > pe (tos) > dma WORDS: 1 CYCLES: 1(Dl) 2(DE) 44NM=Iic MX93011A psh push data memory value onto stack. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1 1001 0 1 0 0 data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1 100141 01 0 4 see note 1 SYNTAX: psh dma psh *(,nar) EXECUTION: (pc) +1 > pe dma -> (tos) WORDS: 1 CYCLES: 1 pshh push high accumulator onto stack. Bit: 151413 12 11109 8 7 6 5 43 2 1 0 1 1001 000 4 see note 1 SYNTAX: pshh EXECUTION: (pc) +1 > pe acc(31:16) (tos) WORDS: 1 CYCLES: 1 45NM=Iic MX93011A pshl push low accumulator onto stack. Bits: 15 141312 11109 8 7 6 5 4 3 2 1 #0 1 100141 001 4 see note 1 SYNTAX: pshl EXECUTION: (pc) +1 > pe acc(15:0) > (tos) WORDS: 1 CYCLES: 1 ret return from subroutine. Bits: 15 14131211109 8 7 6 5 4 3 2 1 0 1 11 147 1 0 0 0 #0 SYNTAX: ret EXECUTION: (sp) > pc sp-1 > sp WORDS: 1 CYCLES: 2 46reti SYNTAX: EXECUTION: WORDS: CYCLES: rpt SYNTAX: EXECUTION: WORDS: CYCLES: rptk SYNTAX: EXECUTION: WORDS: CYCLES: return from interrupt. MXOSOTIA Bit: 15 14131211109 8 7 6 5 4 3 2 1 =O 1 414147 1474 1 0 0 1 +0 reti (sp) pe (sp)-1 sp (sp) > ss sp-1 sp { 2 load repeat counter. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =O 000 1 0 0 0 0 0 data memory address indirect!L 15 14 18 12 11109 8 7 6 5 4 3 2 1 QO 0001 00 0 0 1 see note rpt dma 7 rpt *(,nar) (pc) + 1 pe (dma) > (rc) { 1(Dl) 2(DE) load rc with 7-bit constant. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0O 0001 00 0 1 =0 7-bit constant rptk cnst7 (pc) + 1 pe (7-bit constant) (rc) 1 1 47NM=Iic MX93011A rxf reset external flag. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 1 $417 1 00 1 0 #0 SYNTAX: rxf EXECUTION: (pc) +1 > pe 0 (XF) pin and status bit. WORDS: 1 CYCLES: 1 sah store high acc. direct: 15 141312 11109 8 7 6 5 4 3 2 1 #0 1 0 1 1 0 0 0 O Of data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 101 1 00 0 0 1 see note 1 SYNTAX: sah dma7 sah *(,nar) EXECUTION: (pc) +1 > pe (acc(31:16)) (dma) WORDS: 1 CYCLES: 1(Dl) 2(DE) 48NM=Iic MX93011A sal store low acc. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1014 1 0 0 0 1 =0 data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 101 1 00 0 1 41 see note 1 SYNTAX: sal dma7 sal *(,nar) EXECUTION: (pc) +1 > pe (acc(15:0)) (dma) WORDS: 1 CYCLES: 1(Dl) 2(DE) sar store auxiliary register. direct: 15 141312 11109 8 7 6 5 4 3 2 1 #0 1 0 17 1 4 ar 0 data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1 0 1 1 =1 ar 1 see note 1 SYNTAX: sar dma/7, arp sar * arp (,nar) EXECUTION: (pc)+1 pc (ar) > (dma) WORDS: 1 CYCLES: 1(Dl) 2(DE) 49sbh SYNTAX: EXECUTION: WORDS: CYCLES: sbhk SYNTAX: EXECUTION: WORDS: CYCLES: subtract from high acc. direct: 15 1413 12 11109 8 7 MXOSOTIA 6 5 4 3 2 1 0 000001 0 0 0 data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 0 0000 01 00 4 see note 1 sbh dma7 sbh *(,nar) (pc) +1 > pce (acc(31:16)) - (dma) > (acc(31:16)) 1 1(Dl) 2(DE) subtract short immediate from high acc. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 0 000001 0 1 0 7-bit constant sbhk cnst7 (pc)+1 pc (acc(31:16)) - (7-bit constant) > (acc(31:16)) 50sbhl SYNTAX: EXECUTION: WORDS: CYCLES: sbl SYNTAX: EXECUTION: WORDS: CYCLES: MXOSOTIA subtract immediate from high acc. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 100 00 0 1 0 0 16-bit constant sbhl cnst16 (pc)+2 pc (acc(31:16)) - (16-bit constant) (acc(31:16)) subtract from low acc. direct: 15 14131211109 8 7 6 5 4 3 2 1 #0 0 0 0 0 0 1 +1 =O O | data memory address indirect: 15 141312 11109 8 7 6 5 4 3 2 1 #0 0 00 001 1 0 4 see note 1 sbl dma7 sbl *(,nar) (pc)+1 pc (acc) - (dma with optional MSBs sign extension*) (acc) 1 1(Dl) 2(DE) ; note : Option is controlled by CTRL : SENSE bit 51sblk SYNTAX: EXECUTION: WORDS: CYCLES: sbll SYNTAX: EXECUTION: WORDS: CYCLES: MXOSOTIA subtract short immediate from low acc. Bit: 15 14131211109 8 7 6 5 4 3 2 1 #90 0 00001 1 1 =0 7-bit constant sblk cnst7 (pc)+1 pc (acc) - (7-bit constant) > (acc) subtract immediate from low acc. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 100 00 0 1 141 =0 16-bit constant sbll cnst16 (pc)+2 > pc (acc) - (16-bit constant with optional MSBs sign extension*) > (acc) 2 2 ; note:Option is controlled by CTRL: SENSE bit 52NM=Iic MX93011A sdp store data_page register. direct: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1014 1 01 0 0 0 data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 1014 17 0 1 0 0 =1 see note 1 SYNTAX: sdp dma7 sdp *(,nar) EXECUTION: (pc)+1 pc (dp) > (dma) WORDS: 1 CYCLES: 1(Dl) 2(DE) sfl shift acc left. Bit: 15 14131211109 8 7 6 5 4 3 2 1 #0 1001411 1 0 1 0 0 0 QO} shift SYNTAX: sfl cnst4 EXECUTION: (pc)+1 pc if (shift>< 0) then acc * (2** shift) acc else acc*(2**(sv(3:0))) > acc WORDS: 1 CYCLES: 1; note 53MXOSOTIA str/sfrs SYNTAX: EXECUTION: WORDS: CYCLES: sip SYNTAX: EXECUTION: WORDS: CYCLES: shift acc right. Bit: 15 14131211109 8 7 6 5 4 3 2 1 #0 100141 1 141 14 0 0 0 0O- | shift sfr cnst4 sfrs cnst4 (pc)+1 pc if (shift>< 0) then acc * (2**( -shift)) acc else acc*(2**(-sv(3:0)) > acc * s=0 the msbs zero-filled *s=1 the msbs sign-extended 1 1 store io_page register direct: 15 14131211109 8 7 6 5 4 3 2 1 #0 1014 1 0 0 1 0 0 data memory address indirect: 15 141312 11109 8 7 6 5 4 3 2 1 #0 101 1 0 0 1 0 1 see note 1 sip dma7 sip *(,nar) (pc)+1 pc IOPR(4:3)> (dma (1:0)) 1 1(Dl) 2(DE) 54sss SYNTAX: EXECUTION: WORDS: CYCLES: sxf SYNTAX: EXECUTION: WORDS: CYCLES: MXOSOTIA store ss register. direct: 15 141312 11109 8 7 6 5 4 3 2 1 #0 1014 1 0 0 1 14 +0 data memory address indirect: 15 141312 11109 8 7 6 5 4 3 2 1 #0 1014 1 0 0 1 14 41 see note 1 sss dma7 sss *(,nar) (pc)+1 pc (ss) (dma) 1 1(DI) 2(DE) set external flag. Bit: 15 141312 11109 8 7 6 5 4 3 2 4 1 $417 141 0 0 1 71 ~=90 sxf (pc)+1 > pc 1 (XF) pin and status bit. 55NM=Iic MX93011A trap software interrupt. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 1 1 000 0 1 0 0 SYNTAX: trap EXECUTION: (pc)+1 sp Oc > pc WORDS: 1 CYCLES: 2 xor xor with high acc. direct: 15 141312 11109 8 7 6 5 4 3 2 1 #0 0 00 01 1 0 0 0 data memory address indirect: 15 1413 12 11109 8 7 6 5 4 3 2 1 =0 0000141 1 0 0 =4 see note 1 SYNTAX: xor dma7 xor *(,nar) EXECUTION: (pc)+1 pc (acc(31:16)) .xor. (dma) > (acc(31:16) WORDS: 1 CYCLES: 1(Dl) 2(DE) 56MXOSOTIA xork SYNTAX: EXECUTION: WORDS: CYCLES: xorl SYNTAX: EXECUTION: WORDS: CYCLES: xor short immediate with high acc. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 00001 1 0 1 =0 7-bit constant xork cnst7 :16)) .xor. (7-bit constant) > (acc(23:16)) :24)) > acc(31:24) xor short immediate with high acc. Bit: 15 1413 12 11109 8 7 6 5 4 3 2 1 90 100 00 1 1 0 0 16-bit constant xorl cnst16 (pc)+2 pc (acc(31:16)) .xor. (16-bit constant) > (acc(31:16)) 57note 1 15 14 13 12 14 10 9 8 TO epeede 4 y operation: case(vvvv) ; 0000: no manipulation of ars/arp operand: 0001: y arp + 0 0010: ar(arp) - arO ar(arp) t ARO 0011: ar(arp) - arO0 ar(arp), y > arp - ARO 0100: ar(arp) + arO ar(arp) + ARO 0101: ar(arp) + arO > ar(arp), y > arp ARO 1000: ar(arp) +1 > ar(arp) + 1001: ar(arp) +1 ar(arp), y > arp + 1010: ar(arp) - 1 > ar(arp) ty 1011: ar(arp) -1 > ar(arp), y > arp " 1100: ar(arp) +2 ar(arp) oy 1101: ar(arp) +2 ar(arp), y > arp +t 1110: ar(arp) -2 ar(arp) thoy 1111: ar(arp) -2 ar(arp), y > arp ~ y 58 MXOSOTIANM=Iic MX93011A 9.0 DC CHARACTERISTICS: TA = 0 to 70C, VCC = 5V + 10% Storage temperature range : -55C - 150C SYMBOL PARAMETER CONDITION MIN TYPE MAX UNIT vcc Supply voltage 4.5 5 5.5 Vv GND Ground 0 Vv TTL LEVEL INPUT(IT) VIH Input high voltage 2.0 Vv VIL Input low voltage 0.8 Vv SCHMITT TRIGGER INPUT(IS) VIH Input high voltage 0.7*VCC Vv VIL Input low voltage 0.3*VCC V 8mA OUTPUT(OA) VOH Output high voltage IOH=-8mA 2.4 Vv VOL Output low voltage IOL= 8mA 0.4 Vv 16mA OUTPUT(OB) VOH Output high voltage IOH=-16mMA 2.4 Vv VOL Output low voltage IOL=16mA 0.4 Vv SUPPLY CERRENT Icc NORMAL 45 70 mA Icc HOLD MODE 10 mA ICC POWER DOWN 3 6 mA 59NM=Iic MX93011A 10.AC TIMING AND CHARACTERISTICS: RESET TIMING se aM $$ T(r tt) Aaa RST = EAD15~EADO x PC=0000 x 0001 x ED15-ED0 ald val CONTROL (inactive) SIGNALS OPT18~OPTO x 0000 A, BIO7~BIOO ;? Note: Control Signals HOLDA\EDCE\EPCE\ERD\EWR\ CAS\RAS\DRD\DWR\ RESET TIMING SYMBOL PARAMETER MIN NOM MAX UNIT Tw (rst) Reset low pulse width 2*46.5ns OUTPUT PORT AND EXTERNAL FLAG(XF\) TIMING AD15-ADO | | t-Td(a-o) OPT18~OPTO BIO7~BIOO XF\ OUTPUT PORTS AND EXTERNAL FLAG (XF\) TIMING SYMBOL PARAMETER MIN NOM MAX UNIT Td (a-o) Address to output ports delay time 0 10 ns 60NM=Iic MX93011A CODEC TRANSMIT AND RECEIVE TIMING ~ ana CMCK Td(ch-fs) ae Td(ch-fs) <>! Tip <) Thar) CFS CDRO + N=1 x N=2 x N=3 x N=4 X sauune sas CDXO ____ N=1 x N=2 xX N=3 x N=4 OX crass ears SYMBOL PARAMETER MIN NOM MAX UNIT Te CMCK cycle time 650 ns Tlpd CMCK low pulse duration 315 335 ns Thpd CMCK high pulse duration 315 335 ns Td (ch-fs) CMCK to CFS delay time 20 ns Td (ch-dx) CMCK rising edge to Dx valid 10 ns Ts (dr) DR set-up time before CMCK falling edge 10 ns Th (dr) DR hold time before CMCK falling edge 10 ns INTERRUPT TIMING INTO\ <_ wo INT1\ INT2\ AD15-ADO x fetch N+0 x fetch N+1 x fetch N+1 x fetch N+1 x fetch | x SYMBOL PARAMETER MIN NOM MAX UNIT Tw INT\ low pulse duration 3Q* ns NOTE:Q=15.5 ns 61NM=Iic MX93011A SRAM/ROM READ TIMING tS$}7r7 Ss St EDCE\,EPCE\ <__ TAA | EAD15-EADO ERD\ \ TOH = TDR >|+- fo ED15-EDO 54 DATA IN , SRAM WRITE TIMING EDCE\ / EAD15-EADO j~< TAS e| TWR ~t- EWR\ TDW |< TDH] ED15-EDO < DATA OUT SYMBOL PARAMETER MIN NOM MAX UNIT TCS Chip select access time 26.54+WxT ns TAA Address access time 26.54+WxT ns TDR Data read setup time 12 ns TOH Data hold from end of read 0 ns TAS Address setup time 0 5 ns TDW Data to EWR\ low overlap 12 ns TDH Data hold from end of write 0 ns TWR Write recovery time 0 ns *NOTE : T=31ns W:wait state number 62MXOSOTIA M=Ic HOLD TIMING EAD15-EADO NX net Xe + Nea Ned ~| | Ten(ah-a) EDIS-EDa L\ NLT c LN \_/ \_/ \_/S \_/S EPCE\ Oe XX) =X ERD\ my) pe Ts(ah) an Td(hh-ha) HOLD\ TCT 5 HOLDA\ \ SYMBO PARAMETER MIN NOM MAX UNIT Ts (a-h) Address set-up time before HOLD\ low 5 3Q-10 ns Td (hh-ha) HOLD\ high to HOLDA\ high 0 1Q 1Q+10 ns Ten (ah-a) Address driven after HOLDA\ high 1Q-10 1Q 2Q ns * NOTE : Q=15.5n CAS\ BEFORE RAS\ REFRESH TIMING TRP >< TRAS TRP > RAS\ < TRPC \+ TcsR < Tcp TCHR CAS\ SYMBO PARAMETER MIN NOM MAX UNIT TRP RAS\ precharge time 77.5 ns TRPC RAS\ to CAS\ precharge time 62 ns TcP CAS\ precharge time 31 ns TCSR CAS\ set-up time (CBR cycle) 15.5 ns TCHR CAS\ hold time (CBR cycle) 62 ns TRAS RAS\ pulse width 108.5 ns 63M=Ic DRAM READ/WRITE TIMING MXOSOTIA RAS\ sie -t Tred Teas Tep CAS\ Tasr pw Tan a Taso | Tach EAD15-EADO ROW ADDRESS COLUMN ADDRESS A. COLUMN ADDRESS DRD\ t Td(rd-c) ] [ Ts(qas) |---| Th(cas) READ CYGLE { onta ny) aan) DWR\ pe Tater) [ Ts(w-ca) t+ Th(w-ca) ED15-EDO WRITE CYCLE DATA OUT SYMBO PARAMETER MIN NOM MAX UNIT Trp RAS\ precharge time 77.5 ns Tred RAS\ to CAS\ delay time 62 ns Tcas CAS\ low pulse duration 31+W*Q ns Tep CAS\ precharge time 31 ns Tasr Row address set-up time 0 ns Trah Row address hold time 31 ns Tasc Column address setup time 0 ns Tach Column address hold time 31 ns Td(rd-c) DRD\ low to CAS\ low ns Td(wr-c) DWR\ low to CAS\low ns Ts(cas) Data set-up time before CAS\ high 20 ns Th(cas) Data hold time after CAS\high 0 ns Ts(w-ca) Data set-up time before CAS\low 0 ns Th(w-ca) Data hold time after CAS\low 46.5 ns *NOTE: W:Wait state number of DRAM Q:15.5ns 64M=Ic 12.0 ORDERING INFORMATION PART NO. PACKAGE MX93011A PQFP MX 93 011A MXIC | COMPONY PREFIX FAMILY PREFIX MXOSOTIA L COMMERCIAL 0 ~ 70C PACKAGE TYPE F : PQFP PRODUCT NUMBER 65NM=Iic MX93011A 13.0 PACKAGE INFORMATION 100-PIN PQFP A ITEM MILLIMETERS INCHES A 24.80 + .40 976 + .016 8 B 20.00 + .13 787 + .005 1400413 551+ .005 HHABH ARERR AHA AH RR AH D 18.80 + .40 740 + .016 ae "0 Cry fT E 12.35 [REF] .486 [REF] | Le F .83 [REF] .033 [REF] = ES Cry [1 G 58 [REF] .023 [REF] == ES . H .30 [Typ.] .012 [Typ.] = - 7 a I 65 [Typ] .026 [Typ.] oo Lo Cry fT J 2.40 [Typ.] .094 [Typ.] 4 HE K 1.20 [Typ.] 047 [Typ.] | = C) ES ee L 15 [Typ] 006 [Typ.] . ==} 190 at = Joh Mo tomax. 004 max. t a #o N 2.754 .15 -108 + .006 LL oO 10 min. .004 min. rl 6 N P 3.30 max. -130 max. NOTE: Each lead centerline is located within .25mm[.01 inch] of its true position [TP] ata N maximum material condition. [ K 66