1
DSC-6157/1
JUNE 2003
PRELIMINARY
IDT72T55248
IDT72T55258
IDT72T55268
2.5V QUADMUX DDR FLOW-CONTROL DEVICE
WITH MUX/DEMUX/BROADCAST FUNCTIONS
8,192 x 40 x 4
16,384 x 40 x 4
32,768 x 40 x 4
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
8,192 x 40
16,384 x40
32,768 x 40
8,192 x 40
16,384 x40
32,768 x 40
8,192 x 40
16,384 x40
32,768 x 40
8,192 x 40
16,384 x40
32,768 x 40
FF0/IR0
PAF0
FF1/IR1
PAF1
FF2/ IR2
PAF2
FF3/IR3
PAF3
WEN0
WCS0
WEN1
WCS1
WEN2
WCS2
WEN3
WCS3
WCLK0
WCLK1
WCLK2
WCLK3
10
10
10
10
D[9:0]
D[19:10]
D[29:20]
D[39:30]
EF0/OR0
PAE0
EF1/OR1
PAE1
EF2/OR2
PAE2
EF3/OR3
PAE3
CEF/COR
Q[39:0]
x10,x20,x40
REN0
RCS0
RCLK0
OE0
Read Control
Queue 0
Queue 1
Queue 2
Queue 3
OS[1:0]
Read Port
Flag Outputs
Write Port
Flag Outputs
Mux Mode
6157 drw01
Queue 0
Data In
Queue 1
Data In
Queue 2
Data In
Queue 3
Data In
Data Out
2
FEATURES
••
••
•Choose from among the following memory organizations:
IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential
Queues total
IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential
Queues total
IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 Sequential
Queues total
••
••
•User Selectable Mux / Demux / Broadcast Write Modes
••
••
•Mux Mode offers 4:1 architecture
- Five discrete clock domains, four write clocks and one read clock
- Four separate write ports, writes data to four independent Queues
- One single read port, capable of reading from any four Queues
- Selectable single or double data rate (SDR/DDR) on read and write
ports
- 10-bit wide write ports in single data rate, doubles internally in double
data rate
- 40-bit wide read port, doubles internally in double data rate,
selectable between the four independent Queues
- Bus Matching on the Read Port x10/x20/x40 (SDR/DDR)
- Fully independent status flags for every Queue
- Composite Empty/Output Ready Flag monitors currently selected
Queue
- Dedicated partial reset for every Queue
••
••
•Demux Mode offers 1:4 architecture
- Five discrete clock domains, one write clock and four read clocks
- Four separate read ports, read data from four independent Queues
- One single write port, capable of writing to any four Queues
- Selectable single or double data rate on read and write ports
- 10-bit wide read ports in single data rate, doubles internally in double
data rate
- 40-bit wide write port, doubles internally in double data rate,
selectable between the four independent Queues
- Bus Matching on the Write Port x10/x20/x40 (SDR/DDR)
- Fully independent status flags for every Queue
- Composite Full/Input Ready Flag monitors currently selected Queue
- Dedicated partial reset for every Queue
••
••
•Broadcast Write Mode offers, 1:4 architecture (with simultaneous
writes to all Queues)
- Five discrete clock domains, one write clock and four read clocks
- Four separate read ports, read data from four independent Queues
- One single write port, writes to all four independent Queues
simultaneously
- 10-bit wide read ports in single data rate, doubles internally in double
data rate
- 40-bit wide write port, doubles internally in double data rate
- Selectable single or double data rate on read and write ports
- Bus-Matching on the write port x10/x20/x40 (SDR/DDR)
(See next page for Demux and Broadcast modes)
FUNCTIONAL BLOCK DIAGRAMS
2
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
8,192 x 40
16,384 x40
32,768 x 40 10
REN0
RCS0
RCLK0
Q[9:0]
Queue 0
OE0
8,192 x 40
16,384 x40
32,768 x 40 10
REN1
RCS1
RCLK1
Q[19:10]
Queue 1
OE1
8,192 x 40
16,384 x40
32,768 x 40 10
REN2
RCS2
RCLK2
Q[29:20]
Queue 2
OE2
8,192 x 40
16,384 x40
32,768 x 40 10
FF0/ IR0
PAF0
FF1/ IR1
PAF1
FF2/ IR2
PAF2
FF3/ IR3
PAF3
REN3
RCS3
RCLK3
Q[39:30]
Write Port
Flag Outputs
EF0/ OR0
PAE0
EF1/ OR1
PAE1
EF2/ OR2
PAE2
EF3/ OR3
PAE3
CFF/ CIR
Data In
x10,x20,x40
WEN0
WCS0
WCLK0
Write Control
Queue 3
IS[1:0]
Read Port
Flag Outputs
Demux Mode
6157 drw02
D[39:0]
OE3
Queue 0
Data Out
Queue 1
Data Out
Queue 2
Data Out
Queue 3
Data Out
2
- Fully independent status flags for every Queue
- Composite Full/Input Ready Flag monitors currently selected Queue
- Dedicated partial reset for every Queue
••
••
•Up to 200MHz operating frequency, 8Gbps (SDR) and 16Gbps
(DDR)
••
••
•User selectable Single Data Rate (SDR) or Double Data Rate
(DDR) modes on both the write port(s) and read port(s)
••
••
•All I/O are LVTTL/ HSTL/ eHSTL user selectable
••
••
•3.3V tolerant inputs in LVTTL mode
••
••
•ERCLK and EREN Echo outputs on all read ports
••
••
•Write Chip Select WCS input for each write port
••
••
•Read Chip Select RCS input for each read port
••
••
•User Selectable IDT Standard mode (using EF and FF flags) or
FWFT mode (using IR and OR flags)
••
••
•Composite Full/ Input Ready Flag in Demux and Broadcast
mode
••
••
•Composite Empty/ Output Ready flag in Mux mode
••
••
•Independent Programmable Almost Empty and Almost Full flags
per Queue
••
••
•Dedicated Serial Port for flag programming
••
••
•Dedicated Partial Reset for each individual Queue
••
••
•Power Down pin minimizes power consumption
••
••
•2.5V Supply Voltage
••
••
•Available in a 324-pin Plastic Ball Grid Array (PBGA)
19mm x 19mm, 1mm Pitch
••
••
•IEEE 1149.1 compliant JTAG port provides boundary scan
function, or flag programming
••
••
•Low Power, High Performance CMOS technology
••
••
•Industrial temperature range (-40°°
°°
°C to +85°°
°°
°C)
FUNCTIONAL BLOCK DIAGRAMS (CONTINUED)
FEATURES (CONTINUED)
3
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
8,192 x 40
16,384 x40
32,768 x 40
8,192 x 40
16,384 x40
32,768 x 40
8,192 x 40
16,384 x40
32,768 x 40
8,192 x 40
16,384 x40
32,768 x 40
FF0/ IR0
PAF0
FF1/ IR1
PAF1
FF2/ IR2
PAF2
FF3/ IR3
PAF3
Write Port
Flag Outputs
EF0/ OR0
PAE0
EF1/ OR1
PAE1
EF2/ OR2
PAE2
EF3/ OR3
PAE3
CFF/ CIR
Data In
x10,x20,x40
WEN0
WCS0
WCLK0
Write Control
Queue 0
Queue 1
Queue 2
Queue 3
Read Port
Flag Outputs
Broadcast Mode
6157 drw03
10
REN0
RCS0
RCLK0
Q[9:0]
OE0
10
REN1
RCS1
RCLK1
Q[19:10]
OE1
10
REN2
RCS2
RCLK2
Q[29:20]
OE2
10
REN3
RCS3
RCLK3
Q[39:30]
OE3
Queue 0
Data Out
Queue 1
Data Out
Queue 2
Data Out
Queue 3
Data Out
D[39:0]
FUNCTIONAL BLOCK DIAGRAMS (CONTINUED)
4
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION
The IDT72T55248/72T55258/72T55268 QuadMux flow-control devices
are ideal for many applications where data stream convergence and parallel
buffering of multiple data paths are required. These applications may include
communication and networking systems such as terabit routers, quality of
service (QOS) and packet prioritization routing systems, data bandwidth
aggregation, data acquisition systems, WCDMA baseband systems, and
medical equipments. The QuadMux replaces traditional methods of muxing
multiple data paths at different data rates, in essence reducing external glue
logic. The QuadMux offers three modes of operation, Mux, Demux and
Broadcast. Regardless of the mode of operation there are four internal
Sequential Queues built using IDT FIFO technology and five discrete clock
domains. All four Queues have the same density, and the read and write ports
can operate independently in Single Data Rate (SDR) or Double Data Rate
(DDR). See Figure 1, QuadMux Block Diagram or an outline of the functional
blocks within the device.
The QuadMux device is capable of up to 200MHz operation of all five clock
inputs, all clocks being totally independent of each other. Along with this high
speed of operation the input and output ports are independently selectable
between Single Data Rate, SDR mode, and Double Data Rate, DDR mode.
If Double Data Rate mode is selected data can be written into or read out of a
Queue on every rising and falling edge of the respective clock. For example,
if the write clock is running at 200MHz and the write port(s) is/are setup for DDR
mode, a data input pin has a bandwidth of 400Mbps. So for a 40-bit wide bus
a total bandwidth of 16Gbps can be achieved.
In Mux mode operation a 4:1 architecture is setup, (four input ports to one
output port). Here there are four internal Sequential Queues each with a
dedicated write port. Data can be written into each of the dedicated write ports
totally independent of any other port, each port has its own write clock input and
control enables. There is a single read port that can access any one of the four
Queues. Data is read out of a specific Queue based on the address present
on the output select pins. Only one Queue can be selected and read from at
a time. All input ports are 10 bits wide and the output port has a selectable Bus
Matching x10, x20 or x40 bus widths. A full set of flag outputs per Queue are
available in this mode providing the user with continuous status of each
individual Queue levels.
In Demux mode operation a 1:4 architecture is setup, (one input port to four
output ports). Here there is a single write port that can write data into any one
of four internal Queues. Data is written into a specific Queue based on the
address present on the input select pins. Only one Queue can be selected and
written into at a time. There are four dedicated read ports, one port for each
Queue. Data can be read out of the four Queues through the read port totally
independent of any other port. Each port has its own read clock input and control
enables. The input port has a selectable Bus Matching x10, x20 or x40 bus width
and all the output ports are 10-bits. A full set of flag outputs per Queue are
available in this mode providing the user with continuous status of each individual
Queue levels.
In the Broadcast Write mode the architecture is similar to the Demux mode,
1:4 (one input port to four output ports). However, there is no Queue select
operation in Broadcast mode. Instead data written into the write port is written
to all four internal Queues simultaneously. Again there are four independent
read ports, one port per Queue. In Broadcast mode write operations to all
Queues will be prevented when any one or more of the four Queues are full
or being partially reset. A full set of flag outputs is available in this mode providing
the user with continuous status of each individual Queue levels.
As is typical with most IDT Queues, two types of data timing modes are
available, IDT Standard mode and First Word Fall Through (FWFT) mode. This
affects the device’s operation and also the flag outputs. The device provides four
flag outputs, for each internal Queue. The device also provides composite flags
that represent the full and empty status of the currently selected Queue.
All read ports provide the user with a dedicated Echo Read Enable, EREN
and an Echo Read Clock, ERCLK output. These outputs aid in high-speed
applications where synchronization of the input clock and data of a receiving
device is critical. Otherwise known as “Source Synchronous clocking” the echo
outputs provide tighter synchronization of the data transmitted from the Queue
to the read clock interfacing the Queue outputs.
A master reset input is provided and all setup and configuration pins are
latched with respect to a Master Reset. A Partial Reset is provided for each
internal Queue. When a Partial Reset is performed on a Queue the read and
write pointers of that Queue only are reset to the first memory location. The flag
offset values, timing modes, and initial configurations are retained.
The QuadMux device has the capability of operating its I/Os at either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, VREF input
is provided for HSTL and eHSTL interfaces. The type of I/O is selected by the
IOSEL pin. There are certain inputs that are CMOS based and must be tied to
either VCC or GND. The core supply voltage of the device, VCC is always 2.5V,
however the output pins have a separate supply, VDDQ which can be 2.5V, 1.8V
or 1.5V. The device also offers significant power savings, achieved through the
use of the Power Down input, PD in HSTL/eHSTL mode.
A JTAG test port is provided on the QuadMux device. The Boundary Scan
is fully compliant with IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture. The JTAG port can also be used to program the flag offsets.
5
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Res et
Logic
Input
6157 drw04
Input Mux IW[1:0]
8080
80
8080
RAM
ARRAY 0
8,192 x 40
16,384 x 40
32,768 x 40
RAM
ARRAY 2
8,192 x 40
16,384 x 40
32,768 x 40
RAM
ARRAY 1
8,192 x 40
16,384 x 40
32,768 x 40
RAM
ARRAY 3
8,192 x 40
16,384 x 40
32,768 x 40
Output Mux
OE0/1/2/3
Q[39:0] (x10, x20, x40)
4
OW[1:0]
RCS0/1/2/3
JTAG Control
(Boundary Scan)
Status Flag
Logic
Read Control
Logic
Write Control
Logic
Read Control
Logic
Write Control
Logic
Status Flag
Logic
WDDR
WEN2
WCS2
WCLK2
RDDR
REN2
RCS2
RCLK2
WDDR
WEN3
WCS3
WCLK3
RDDR
REN3
RCS3
RCLK3
PAF2
FF2/IR2
PAE2
EF2/OR2
PAF3
FF3/IR3
PAE3
EF3/OR3
TCK
TRST
TMS
TDI
TDO
Composite
Flags
CEF/
COR
CFF/
CIR
MRS PRS0/1/2/3
4
Status Flag
Logic
Read Control
Logic
Write Control
Logic
Read Control
Logic
Write Control
Logic
Status Flag
Logic
Programmable
Flag Control
WDDR
WEN0
WCS0
WCLK0
RDDR
REN0
RCS0
RCLK0
WDDR
WEN1
WCS1
WCLK1
RDDR
REN1
RCS1
RCLK1
PAF0
FF0/IR0
PAE0
EF0/OR0
PAF1
FF1/IR1
PAE1
EF1/OR1
D[39:0] (x10, x20, x40)
SCLK
SWEN
SREN
SDO
FWFT/SI
FSEL[1:0]
PFM
Figure 1. QuadMux Block Diagram
NOTES:
1. This block diagram only shows the architecture for Queue 0. There are a total of four Queues inside this device all with the identical architecture.
2. *Denotes dedicated signal for each internal Queue inside the device.
6
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PRELIMINARY
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
WEN2
WCS3
GND
GND
VCC
VCC
VCC
D39 Q33
Q36
PAF3 OS0 Q35REN2RCS1
VDDQ
VCC VCC
VCC GND VDDQ
VDDQ VDDQ VDDQ
D0 D1
D6
D3
D13
WCLK0
WCLK1
D38
MD0
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
PRS0
PD
VCC
GND
VDDQ OE3
OE0
PRS3VREF MRS
D23
OE1OE2
FWFT/SI
Q9
Q12
Q15
12 34 56 78 910111213141516
A1 BALL PAD CORNER
OW1
MD1
D24
D27
D30
D33
D36
GND
VDDQ
WCLK2
WCLK3
D26
D29
D32
D35
D7
D11
D14
D16
D18
D20
D25
D22
D28
D31
D34
D37 Q30
Q18
EREN1
EREN2
Q21
Q24
Q27
TDI SREN
SCLK
D12
D15
D17
D19
D21
D4 D5 FSEL0
WDDR
D9 OW0
FSEL1 VDDQ
IW0 GND
VCC TRST
IW1 TMS
TCK
GND
PFM VCC
IOSEL VDDQ
GND GND
VCC VDDQVDDQ VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D2
SWEN
Q6
D10
RDDR VCC
PRS1PRS2
D8
6157 drw05
U
V
IS1
GND
GND
VCC
VCC
Q38
RCLK1
OS1 RCS2RCLK2RCLK3
REN3
RCS0
PAE3RCS3REN1REN0
17 18
ERCLK0
ERCLK1
Q37
Q34
Q1
Q0
Q2
Q7
Q10
Q13
Q32
Q16
Q19
Q20
Q23
Q26
Q29
TDO
SDO
Q5
EREN0
EREN3
Q22
Q25
Q28
Q31
Q8
Q11
Q14
Q17
Q3
Q4
ERCLK2
ERCLK3
RCLK0
Q39
VCCVCC
VCC VDDQ
VCC GND
VCC VDDQ VDDQ
VDDQ
GNDGND
VCC GNDGND GND
GND GND VDDQ
GND
GNDGND
VCC GNDGND GND
GND GND VDDQ
GND
GND
GND
GND
GND GND
GND
VCC GND GND GND GND VDDQGND
GND
GND
VCC GND GND
GND VDDQ
GNDVCCVCC VDDQ
VCC
VCC GND VDDQ
VDDQ VDDQ
GNDGND
VCC
GNDGND
VCC
GNDGND
VCC
GNDGND
VCC
GND VDDQ
GND
GND VDDQ
GND
GND VDDQ
GND
GND VDDQ
GND
WEN3
WEN0WEN1
WCS0WCS1WCS2
IS0 PAE0EF0/OR0PAE1PAE2
PAF0CEF/
COR
FF0/IR0PAF1CFF/CIR PAF2FF2/IR2
FF3/IR3
FF1/IR1
EF1/OR1EF2/OR2
EF3/OR3
PBGA (BB324-1, order code: BB)
TOP VIEW
PIN CONFIGURATION
7
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CEF/COR Composite Empty/ HSTL-LVTTL If Mux mode is selected this flag will represent the exact status of the current Queue being read
(U6) Composite Output OUTPUT(2) without the user having to observe the empty flag corresponding to the current Queue.
Ready Flag If Demux or Broadcast mode is selected this output is not used and can be left floating.
CFF/CIR Composite Full/ HSTL-LVTTL If Mux mode is selected this output is not used and can be left floating.
(T6) Composite Input OUTPUT(2) If Demux mode is selected this flag will represent the exact status of the current Queue being written
Ready flag without the user having to observe the full flag corresponding to the current Queue.
If Broadcast mode is selected this flag goes active when any one of the four Queues goes full and
inactive when all four Queues are not full.
D[39:0] Data Input Bus HSTL-LVTTL These are the data inputs for the device. Data is written into the part using the respective write port
(See Pin No. INPUT clock(s) and enable(s). If Demux or Broadcast mode is selected this is a single data input bus providing
table for details) Bus-Matching of x10, x20 or x40 bits. If Mux mode is selected these inputs become four separate
busses to the four separate Queues. D[9:0] is Queue[0], D[19:10] is Queue[1], D[29:20] is Queue[2],
D[39:30] is Queue[3]. Any unused inputs should be tied to GND. Note the inputs are 3.3V tolerant
in LVTTL mode.
EF0/1/2/3/- Empty Flags 0/1/2/3 HSTL-LVTTL This is the Empty Flag (Standard IDT mode) or Output Ready Flag (FWFT mode) corresponding
OR0/1/2/3 or Output Ready OUTPUT(2) to each of the four Queues on the read port. EF indicates whether or not the Queue is empty.
(See Pin No. Flags 0/1/2/3 OR indicates whether or not there is valid data available at the outputs. These flags always represent
table for details) the status of the corresponding Queue at all times in every mode.
ERCLK0 Echo Read Clock 0 HSTL-LVTTL If Mux mode is selected this is the only echo clock output available for the read port.
(R18) OUTPUT(2) If Demux or Broadcast mode is selected this is the echo read clock output for Queue 0.
Echo read clock always follows RCLK0 with an associated delay.
ERCLK1/2/3 Echo Read Clock HSTL-LVTTL If Mux mode is selected these clock outputs are inactive and can be left floating.
(ERCLK1-T18 1/2/3 OUTPUT(2) If Demux or Broadcast mode is selected these are the echo read clock outputs for Queues 1, 2, and
ERCLK2-U18 3 respectively.
ERCLK3-V18) ERCLK1, ERCLK2 and ERCLK3 always follow RCLK1, RCLK2 and RCLK3 respectively.
EREN0 Echo Read Enable 0 HSTL-LVTTL If Mux mode is selected this is the echo read enable output for the read port.
(J17) OUTPUT(2) If Demux or Broadcast mode is selected this is the echo read enable input for Queue 0.
Echo Read Enable is synchronous to the RCLK input and is active when a read operation has occurred
and a new word has been placed onto the data output bus.
EREN1/2/3 Echo Read Enable HSTL-LVTTL If Mux mode is selected these outputs are inactive and can be left floating.
(EREN1-J16 1/2/3 OUTPUT(2) If Demux or Broadcast mode is selected these are the echo read enable outputs for Queues 1, 2 and
EREN2-K16 3 respectively.
EREN3-K17) Echo Read Enable is synchronous to the RCLK input and is active when a read operation has occurred
and a new word has been placed onto the data output bus.
FF0/1/2/3- Full Flags 0/1/2/3 or HSTL-LVTTL This is the Full Flag (Standard IDT mode) or Input Ready Flag (FWFT mode) corresponding to
IR0/1/2/3 Input Ready Flags OUTPUT(2) each of the four Queues on the write port. FF indicates whether or not the Queue is full.
(See Pin table) 0/1/2/3 IR indicates whether or not there is valid space for writing data onto the Queue.
FSEL [1:0] Flag Select HSTL-LVTTL During master reset, the FSEL pins are used to select one of four default PAE and PAF offsets.
(FSEL1-C5 INPUT All four internal Queues are programmed to the same PAE/PAF offset value. Values are: 00 = 7;
FSEL0-B6) 01 = 63; 10 = 127; 11 = 1023
FWFT/SI First Word Fall HSTL-LVTTL During master reset, FWFT is HIGH then the First Word Fall Through mode is selected. If FWFT
(B16) Through/ Serial INPUT is LOW the IDT Standard mode is selected. After master reset this pin is used for the serial data
Input input for the programming of the PAE and PAF flags offset registers.
IOSEL I/O Select CMOS(1) This input determines whether the inputs will operate in LVTTL or HSTL/eHSTL mode. If IOSEL
(D5) INPUT pin is HIGH, then all inputs and outputs that are designated "LVTTL or HSTL" in this section will be
set to LVTTL format. If IOSEL is LOW then HSTL/eHSTL format is selected. This signal must be
tied to either VCC or GND for proper operation.
IS[1:0] Input Select HSTL-LVTTL If Mux or Broadcast mode is selected these inputs are not used and should be tied to GND.
(IS1-V1 INPUT If Demux mode is selected these inputs select one of the four Queues to be written into on the write
IS0-V2) port. The address on the input select pins is setup with respect to the rising edge of WCLK0.
PIN DESCRIPTIONS
Symbol & Name I/O TYPE Description
Pin No.
8
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
IW[1:0] Input Width CMOS(1) In Demux or Broadcast, these pins are used during master reset to select the input bus size for the
(IW1-C12 INPUT device. The values are: 00 = x10; 01 = x20; 10 = x40. 11 = Restricted. In Mux mode these pins must
IW0-C8) be tied to GND.
MD[1:0] Mode Pin CMOS(1) This mode selection pin used during Master Reset to select the mode of the Queue. The values are:
(MD1-B5 INPUT 00 = Demux; 10 = Mux; 01 = Broadcast Write; 11 = Restricted.
MD0-B4)
MRS Master Reset HSTL-LVTTL This input provides a full device reset. All set-up pins are sampled based on a master reset operation.
(A5) INPUT Read and write pointers will be reset to the first location memory. All flag offsets are cleared and
reset to default values determined by FSEL[1:0].
OE0 Output Enable 0 HSTL-LVTTL If Mux mode is selected this is the Output Enable for the read port. All data output pins will be placed
(A13) INPUT into High Impedance if this pin is HIGH.
If Demux or Broadcast mode is selected this is the output enable pin for Queue 0. All data output
pins of Queue 0 will be placed into High Impedance if this pin is HIGH. This input is asynchronous.
OE1-(A14) Output Enable 1/2/3 HSTL-LVTTL If Mux mode is selected these inputs are ignored and can be tied HIGH.
OE2-(A15) INPUT If Demux or Broadcast mode is selected these are the output enable pins Queues 1, 2 and 3
OE3-(A16) respectively. All data outputs on Queue 1, Queue 2 and Queue 3 will be in High-Impedance if the
respective output enable pin is High. These inputs are asynchronous.
OS[1:0] Output Select HSTL-LVTTL If Mux mode is selected these inputs select one of the four Queues to be read from on the read port.
(OS1-V11 INPUT The address on the output select pins is setup with respect to the rising edge of RCLK0.
OS0-T12) If Demux or Broadcast mode is selected these inputs are not used and should be tied to GND.
OW[1:0] Output Width HSTL-LVTTL If Mux mode is selected, this pin is used during master reset to select the output word width bus
(OW1-B8 INPUT size for the device. The values are: 00 = x10; 01 = x20; 10 = x40; 11 = Restricted.
OW0-C6) If Demux or Broadcast mode is selected the output word width will be x10. These pins are not used
and must be tied to GND.
PAE0-(V3) Programmable HSTL-LVTTL This is the programmable almost empty flag that can be used to pre-indicate the empty boundary
PAE1-(V5) Almost Empty Flag OUTPUT(2) of each Queue. The PAE flags can be set to one of four default offsets determined by the state of
PAE2-(V7) 0/1/2/3 FSEL0 and FSEL1 during master reset. The PAE offset values can also be written and read from
PAE3-(U10) serially by either the JTAG port or the serial programming pins (SCLK, FWFT/SI, SDO, SWEN,
SREN). This flag can operate in synchronous or asynchronous mode depending on the state of the
PFM pin during master reset.
PAF0-(U4) Programmable HSTL-LVTTL This is the programmable almost full flag that can be used to pre-indicate the full boundary of each
PAF1-(T5) Almost Full Flag OUTPUT(2) Queue. The PAF flags can be set to one of four default offsets determined by the state of FSEL0 and
PAF2-(T7) 0/1/2/3 FSEL1 during master reset. The PAF offset values can also be written and read from serially by
PAF3-(T11) either the JTAG port or the serial programming pins (SCLK, FWFT/SI, SDO, SWEN, SREN). This
flag can operate in synchronous or asynchronous mode depending on the state of the PFM pin
during master reset.
PD Power Down HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input
(B12) INPUT level translators for all the data input pins, clocks and non-essential control pins are turned off.
When PD is brought high, power-up sequence timing will have to be followed to before the inputs
will be recognized. It is essential that the user respect these conditions when powering down the
part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks
are free running. PD does not provide any power consumption savings when the inputs are
configured for LVTTL
PFM Programmable Flag CMOS(1) During master reset, a HIGH on PFM selects synchronous PAE/PAF flag timing, a Low during
(D4) Mode INPUT master reset selects asynchronous PAE/PAF flag timing. This pin controls all PAE/PAF flag outputs.
PRS0-(A6) Partial Reset HSTL-LVTTL These are the partial reset inputs for each internal Queue. The read, write, flag pointers, and output
PRS1-(A7) 0/1/2/3 registers will all be set to zero when partial reset is activated. During partial reset, the existing mode
PRS2-(A8) (IDT or FWFT), input/output bus width and rate mode, and the programmable flag settings are all
PRS3-(A12) retained.
Symbol & Name I/O TYPE Description
Pin No.
9
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Q[39:0] Data Output Bus HSTL-LVTTL These are the data outputs for the device. Data is read from the part using the respective read
See Pin No. OUTPUT(2) port clock(s) and enable(s). If Mux mode is selected this is a single data output bus providing Bus-
table for details) Matching of x10, x20 or x40 bits. If Demux or Broadcast mode is selected these outputs become four
separate busses from the four separate Queues. Q[9:0] is Queue[0], Q[19:10] is Queue[1], Q[29:20]
is Queue[2], Q[39:30] is Queue[3]. Any unused outputs should be left floating. Note, that the outputs
are NOT 3.3V tolerant.
RCLK0 Read Clock 0 HSTL-LVTTL If Mux mode is selected this is the clock input for the read port. All read port operations will be
(V17) INPUT synchronous to this clock input.
If Demux or Broadcast mode is selected this is the read clock input for Queue 0. All read port operations
on Queue 0 will be synchronous to this clock input.
RCLK1-(V16) Read Clock 1/2/3 HSTL-LVTTL If Mux mode is selected these clock inputs are ignored and if unused can be tied to GND.
RCLK2-(V15) INPUT If Demux or Broadcast mode is selected these are the read clock inputs for Queues 1, 2, and 3
RCLK3-(V14) respectively. All read port operations on Queue 1, Queue 2 and Queue 3 will be synchronous to clock
inputs RCLK1, RCLK2 and RCLK3 respectively.
RCS0 Read Chip Select 0 HSTL-LVTTL If Mux mode is selected this is the read chip select input for the read port. All read operations will occur
(U13) INPUT synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.
If Demux or Broadcast mode is selected this is the read chip select input for Queue 0. All read operations
on Queue 0 will occur synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.
RCS1-(T13) Read Chip Select HSTL-LVTTL If Mux mode is selected these inputs are ignored and can be tied HIGH.
RCS2-(V12) 1/2/3 INPUT If Demux or Broadcast mode is selected these are the read chip select inputs for Queues 1, 2 and
RCS3-(U12) 3 respectively. All read operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the
RCLK1, 2 and 3 input respectively, provided that the corresponding read enable and read chip
select inputs are LOW.
RDDR Read Port DDR CMOS(1) During master reset, this pin selects the output port to operate in DDR or SDR format. If RDDR is HIGH,
(B7) INPUT then a word is read on the rising and falling edge of the appropriate RCLK0, 1, 2 and 3 input. If RDDR
is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs.
REN0 Read Enable 0 HSTL-LVTTL If Mux mode is selected this is the read enable input for the read port. All read operations will occur
(U15) INPUT synchronous to the RCLK0 clock input provided that REN0 and RCS0 are LOW.
If Demux or Broadcast mode is selected this is the read enable input for Queue 0. All read operations
on Queue 0 will occur synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.
REN1-(U14) Read Enable 1/2/3 HSTL-LVTTL If Mux mode is selected these inputs are ignored and can be tied HIGH.
REN2-(T14) INPUT If Demux or Broadcast mode is selected these are the read enable inputs for Queues 1, 2 and 3
REN3-(V13) respectively. All read operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the
RCLK0, 1, 2 and 3 inputs respectively, provided that the corresponding read enable and read chip
select inputs are LOW.
SCLK Serial Clock HSTL-LVTTL Serial clock for writing and reading the PAE and PAF offset registers. On the rising edge of each
(B14) INPUT SCLK, when SWEN is LOW, one bit of data is shifted from the FWFT/SI pin into the PAE and PAF offset
registers. On the rising edge of each SCLK, when SREN is LOW, one bit of data is shifted out of the
PAE and PAF offset registers. The reading of the PAE and PAF offset registers are non-destructive.
If programming of the PAE/PAF offset registers is done via the JTAG port, this input must be tied to VCC.
SDO Serial Data Output LVTTL This output is used to read data from the programmable flag offset registers. It is used in conjunction
(C17) OUTPUT(2) with the SREN and SCLK signals.
SREN Serial Read Enable HSTL-LVTTL When SREN is brought LOW before the rising edge of SCLK, the contents of the PAE and PAF
(B15) INPUT offset registers are copied to a serial shift register. While SREN is maintained LOW, on each rising
edge of SCLK, one bit of data is shifted out of this serial shift register through the SDO output pin.
If programming of the PAE/PAF offset registers is done via the JTAG port, this input must be tied to VCC.
SWEN Serial Write Enable HSTL-LVTTL On each rising edge of SCLK when SWEN is LOW, data from the FWFT/SI pin is serially loaded
(C16) INPUT into the PAE and PAF registers. If programming of the PAE/PAF offset registers is done via the
JTAG port, this input must be tied to VCC. On each clock, data is shifted into and through the actual
PAE and PAF registers, so the value of the registers is changed on each clock
Symbol & Name I/O TYPE Description
Pin No.
10
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TCK(3) JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
(C13) INPUT operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the
rising edge of TCK and output TDO change on the falling edge of TCK. If the JTAG function is not used
this signal needs to be tied to GND.
TDI(3) JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(B13) Input INPUT operation, test data is serially loaded via the TDI on the rising edge of TCK to either the Instruction
Register, ID Register, Bypass Register or Boundary Scan chain. An internal pull-up resistor forces
TDI HIGH if left unconnected.
TDO(3) JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(B17) Output OUTPUT operation, test data is scanned to the TDO output on the falling edge of TCK from either the Instruction
Register, ID Register, Bypass Register and Boundary Scan chain. This output is high impedance
except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS(3) JTAG Mode Select HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs
(C14) INPUT the device through its TAP controller states sampled on the rising edge of TCK. An internal pull-up
resistor forces TMS HIGH if left unconnected.
TRST(3) JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller is automatically
(C15) INPUT reset upon power-up. If the TAP controller is not properly reset then the Queue outputs will always
be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST
can be tied with MRS to ensure proper Queue operation. If the JTAG function is not used then this
signal needs to be tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected.
WCLK0 Write Clock 0 HSTL-LVTTL If Mux mode is selected this is the clock input for Queue 0. All write port operations to Queue 0 will
(F1) INPUT be synchronous to this clock input.
If Demux or Broadcast mode is selected this is the clock input for the write port. All write port operations
will be synchronous to this clock input. Sampled on the rising edge of WCLK and independent of WDDR.
WCLK1-(G1) Write Clock 1/2/3 HSTL-LVTTL If Mux mode is selected these are the clock inputs for Queues 1, 2, and 3 respectively. All write
WCLK2-(H1) INPUT port operationson Queue1, Queue 2 and Queue 3 will be synchronous to clock inputs WCLK1,
WCLK3-(J1) WCLK2 and WCLK3 respectively.
If Demux or Broadcast mode is selected these clock inputs are ignored and can be tied to GND.
WCS0 Write Chip Select 0 HSTL-LVTTL If Mux mode is selected this is the write chip select input for Queue 0. All write operations on Queue 0
(U1) INPUT will occur synchronous to the WCLK0 input provided that WEN0 and WCS0 are LOW.
If Demux or Broadcast mode is selected this is the write chip select input for the write port. All write
operations will occur synchronous to the WCLK0 input provided that WEN0 and WCS0 are LOW.
Sampled on the rising edge of WCLK and independent of WDDR.
WCS1-(U2) Write Chip Select HSTL-LVTTL If Mux mode is selected these are the write chip select inputs for Queues 1, 2 and 3 respectively. All
WCS2-(U3) 1, 2, 3 INPUT write operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the WCLK1, 2 and 3
WCS3-(T1) respectively, provided that the corresponding write enable and write chip select inputs are LOW.
Sampled on the rising edge of WCLK and independent of WDDR.
If Demux or Broadcast mode is selected these inputs are ignored and can be tied HIGH.
WDDR Write Port DDR CMOS(1) During master reset, this pin selects the input port to operate in DDR or SDR format. If WDDR is HIGH,
(C7) INPUT then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.
If WDDR is LOW, then a word is written only on the rising edge of the appropriate WCLK1, 1, 2 and
3 inputs.
WEN0 Write Enable 0 HSTL-LVTTL If Mux mode is selected this is the write enable input for Queue 0. All write operations on Queue 0 will
(T2) INPUT occur synchronous to the WCLK0 input provided that WEN0 and WCS0 are LOW.
If Demux or Broadcast mode is selected this is the write enable input for the write port. All write
operations will occur synchronous to the WCLK0 clock input provided that WEN0 and WCS0 are LOW.
WEN1-(T3) Write Enable 1/2/3 LVTTL If Mux mode is selected these are the write enable inputs for Queues 1, 2 and 3 respectively. All write
WEN2-(R1) operations on Queue 1, Queue 2 and Queue 3 will occur synchronous to the WCLK1, 2 and 3 inputs
WEN3-(R2) respectively, provided that the corresponding write enable and write chip select inputs are LOW.
If Demux or Broadcast mode is selected these inputs are ignored and can be tied HIGH.
PIN DESCRIPTIONS (CONTINUED)
Symbol & Name I/O TYPE Description
Pin No.
11
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol & Name I/O TYPE Description
Pin No.
VCC +2.5V Supply Power These are VCC core power supply pins and must all be connected to a +2.5V supply rail.
(See Pin table)
VDDQ Output Rail Voltage Power This pin should be tied to the desired voltage rail for providing to the output drivers. Nominally 1.5V
(See Pin table) or 1.8V for HSTL, 2.5V for LVTTL.
GND Ground Pin Ground These ground pins are for the core device and must be connected to the GND rail.
(See Pin table)
Vref Reference voltage Analog This is a Voltage Reference input and must be connected to a voltage level determined in the Voltage
(A4) Recommended DC Operating Conditions section. This provides the reference voltage when using
HSTL class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.
PIN NUMBER TABLE
Symbol Name I/O TYPE Pin Number
D[39:0] Data Input Bus HSTL-LVTTL D39-R3, D(38-36)-P(1-3), D(35-33)-N(1-3), D(32-30)-M(1-3), D(29-27)-L(1-3), D(26-24)-K(1-3),
INPUT D(23,22)-J(3,2), D(21,20)-H(3,2), D(19,18)-G(3,2), D(17,16)-F(3,2), D(15-13)-E(3-1),
D(12-10)-D(3-1), D(9-6)-C(4-1), D(5-3)-B(3-1), D(2-0)-A(3-1)
EF0/1/2/3- Empty Flags0-3 or HSTL-LVTTL EF0/OR0-V4, EF1/OR1-U5, EF2/OR2-U7, EF3/OR3-V10
OR0/1/2/3 Output Ready Flags 0-3 OUTPUT(2)
FF0/1/2/3- Full Flags0-3 or HSTL-LVTTL FF0/IR0-T4, FF1/IR1-V6, FF2/IR2-T10, FF3/IR3-U11
IR0/1/2/3 Input Ready Flags 0-3 OUTPUT(2)
Q[39:0] Data Output Bus HSTL-LVTTL Q(39,38)-U(17,16), Q(37-35)-T(17-15), Q(34,33)-R(17,16), Q(32-30)-P(18-16), Q(29-27)-N(18-16),
OUTPUT(2) Q(26-24)-M(18-16), Q(23-21)-L(18-16), Q20-K18, Q19-J18, Q(18-16)-H(16-18), Q(15-13)-G(16-18),
Q(12-10)-F(16-18), Q(9-7)-E(16-18), Q(6-4)-D(16-18), Q3-C18, Q2-B18, Q(1-0)-A(18-17)
VCC +2.5V Supply Power A9, B9, C9, D(6,9), E(4-9), F(4,5), G(4,5), H(4,5), J(4,5), K(4,5), L(4,5), M(4,5), N(4,5), P(4-8),
R(4-8), T8, U8, V8
VDDQ O/P Rail Voltage Power A11, B11, C11, D(11-15), E(11-15), F(14,15), G(14,15), H(14,15), J(14,15), K(14,15), L(14,15),
M(14,15), N(14,15), P(11-15), R(11-15)
GND Ground Pin Ground A10, B10, C10, D(7,8,10), E10, F(6-13), G(6-13), H(6-13), J(6-13), K(6-13), L(6-13), M(6-13),
N(6-13), P(9,10), R(9,10), T9, U9, V9
NOTES:
1. All CMOS pins should remain unchanged. CMOS format means that the pin is intended to be tied directly to VCC or GND and these particular pins are not tested for VIH
or VIL.
2. All unused outputs may be left floating.
3. These pins are for the JTAG port. Please refer to pages 35-38, Figure 4-6 for JTAG information.
12
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SET-UP, CONFIGURATION & RESET PINS
Regardless of the mode of operation, (Mux, Demux or Broadcast), the
following inputs must always be used. These inputs must be set-up with respect
to master reset as they are latched during master reset.
WDDR – Write Port DDR/SDR selection
RDDR – Read Port DDR/SDR selection
MD[1:0] – Mode Selection
OW[1:0] – Output width
IW[1:0] – Input Width
FSEL[1:0] – Flag offset default values
IOSEL – I/O Level Selection
PFM – Programmable Flag Mode
FWFT/SI – First word Fall Through or Standard IDT mode flag timing selection
MUX MODE
The following inputs/ outputs should be used when Mux mode is selected
by the user:
INPUTS:
WCLK0, WCLK1, WCLK2, WCLK3 – Four write port clocks
WEN0, WEN1, WEN2, WEN3 – Four write port enables
WCS0, WCS1, WCS2, WCS3 – Four write port chip selects
OS[1:0] - Output Select
RCLK0 – Read port clock
REN0 – Read port enable
RCS0 – Read port chip select
OE0 – Read port output enable
OUTPUTS:
ERCLK0 – Read port echo read clock
EREN0 – Read port echo read enable
EF0/OR0, EF1/OR1, EF2/OR2, EF3/OR3 – Four read port empty/output
ready flags
PAE0, PAE1, PAE2, PAE3 – Four read port programmable almost empty flags
PAF0, PAF1, PAF2, PAF3 – Four write port programmable almost full flags
FF0/IR0, FF1/IR1, FF2/IR2, FF3/IR3 – Four write port full/ input ready flags
CEF/COR – Composite empty/output ready flag on read port
SERIAL PORT
The following pins are used for writing and reading the Programmable Flag
Offsets values:
SCLK – Serial Clock
SWEN – Serial Write Enable
SREN – Serial Read Enable
FWFT/SI – Serial Data In
SDO – Serial Data Out
DEMUX OR BROADCAST MODE
The following inputs/outputs should be used when Demux or Broadcast
Write mode is selected by the user:
INPUTS:
IS[1:0] - Input Select, Demux mode only, not used in broadcast mode.
WCLK0 – Write port clock
WEN0 – Write port enable
WCS0 – Write port chip select
RCLK0, RCLK1, RCLK2, RCLK3 – Four read port clocks
REN0, REN1, REN2, REN3 – Four read port enables
RCS0, RCS1, RCS2, RCS3 – Four read port chip selects
OE0, OE1, OE2, OE3 – Four read port output enables
OUTPUTS:
ERCLK0, ERCLK1, ERCLK2, ERCLK3 – Four read port echo read clock
outputs
EREN0, EREN1, EREN2, EREN3 – Four read port echo read enable outputs
EF0/OR0, EF1/OR1, EF2/OR2, EF3/OR3 – Four read port empty/output
ready flags
FF0/IR0, FF1/IR1, FF2/IR2, FF3/IR3 – Four write port full/input ready flags
PAF0, PAF1, PAF2, PAF3 – Four write port programmable almost full flags
PAE0, PAE1, PAE2, PAE3 – Four read port programmable almost empty flags
CFF/CIR – Composite full/ input ready flag on write port
QUADMUX I/O USAGE SUMMARY
13
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
Symbol Parameter(1) Conditions Max. Unit
CIN(2,3) Input VIN = 0V 10(3) pF
Capacitance
COUT(1,2) Output VOUT = 0V 10 pF
Capacitance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 2.375 2.5 2.625 V
VDDQ Output Supply Voltage LVTTL 2.375 2.5 2.625 V
eHSTL 1. 7 1. 8 1. 9 V
HSTL(2) 1.4 1.5 1.6 V
VREF Voltage Reference Input eHSTL 0. 8 0 . 9 1. 0 V
HSTL(2) 0.68 0.75 0.9 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage LVTTL 1.7 — 3.45 V
eHSTL VREF+0.1 — VDDQ+0.3 V
HSTL(2) VREF+0.1 — VDDQ+0.3 V
VIL Input Low Voltage LVTTL — — 0.7 V
eHSTL VREF-0.3 — VREF-0.1 V
HSTL(2) VREF-0.3 — VREF-0.1 V
TAOperating Temperature Commercial 0 — +70 °C
TAOperating Temperature Industrial -40 — +85 °C
RECOMMENDED DC OPERATING CONDITIONS
NOTES:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. Compliant with JEDEC JESD8-6.
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Com'l & Ind'l Unit
VTERM Terminal Voltage –0.5 to +3.6(2) V
with respect to GND
TSTG Storage Temperature –55 to +125 °C
IOUT DC Output Current –? to +? mA
14
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol Parameter Min. Max. Unit
ILI Input Leakage Current –10 +10 µA
ILO Output Leakage Current –10 +10 µA
VOH(7) Output Logic “1” Voltage, IOH = –8 mA @LVTTL VDDQ -0.4 — V
IOH = –8 mA @eHSTL VDDQ -0.4 — V
IOH = –8 mA @HSTL VDDQ -0.4 — V
VOL Output Logic “0” Voltage, IOL = 8 mA @LVTTL — 0. 4 V
IOL = 8 mA @eHSTL — 0.4 V
IOL = 8 mA @HSTL — 0.4 V
ICC1(1,2,3) Active VCC Current -- LVTTL — 239 mA
(See Note 8 and 9 for test conditions) -- eHSTL — 336 mA
-- HSTL — 3 32 mA
ICC3(1,2,3) Standby VCC Current (Mux mode) -- LVTTL — 112 mA
(See Note 10 and 11 for test conditions) -- eHSTL — 188 mA
-- HSTL — 1 86 mA
ICC5(1,2,3) Power Down VCC Current (Mux mode) -- LVTTL — 9 mA
(See Note 12 and 13 for test conditions) -- eHSTL — 2 6 mA
-- HSTL — 24 mA
NOTES:
1. Both WCLK and RCLK toggling at 20MHz.
2. Data inputs toggling at 10MHz.
3. Typical ICC1 calculation:for LVTTL I/O ICC1 (mA) = 10 x fS, fS = WCLK frequency = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 72+ (10 x fS), fS = WCLK frequency = RCLK frequency (in MHz)
4. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.78 x fS
With Data Outputs in Low-Impedance: IDDQ (mA) = CL x VDDQ x fS x N /2000
fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL
tA = 25°C, CL = capacitive load (pf), N = Number of bits switching
5. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)]. IOH = -8mA for all voltage levels.
6. IOH ≥ 8mA, IOL ≥ -8mA.
7. Outputs are not 3.3V tolerant.
8. VCC = 2.5V, WCLK0-3 = RCLK0 = 20MHz, WEN0-3 = REN0 = LOW, WCS0-3 = RCS0 = LOW, OE = LOW, PD = HIGH.
9. VCC = 2.5V, WCLK0 = RCLK0-3 = 20MHz, WEN0 = REN0-3 = LOW, WCS0 = RCS0-3 = LOW, OE0-3 = LOW, PD = HIGH.
10. VCC = 2.5V, WCLK0-3 = RCLK0 = 20MHz, WEN0-3 = REN0 = HIGH, WCS0-3 = RCS0 = HIGH, OE = LOW, PD = HIGH.
11. VCC = 2.5V, WCLK0 = RCLK0-3 = 20MHz, WEN0 = REN0-3 = HIGH, WCS0 = RCS0-3 = HIGH, OE0-3 = LOW, PD = HIGH.
12. VCC = 2.5V, WCLK0-3 = RCLK0 = 20MHz, WEN0-3 = REN0 = HIGH, WCS0-3 = RCS0 = HIGH, OE = LOW, PD = LOW.
13. VCC = 2.5V, WCLK0 = RCLK0-3 = 20MHz, WEN0 = REN0-3 = HIGH, WCS0 = RCS0-3 = HIGH, OE0-3 = LOW, PD = LOW.
15
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
P R E L I M I N A R Y
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, T A = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial & Industrial Commercial & Industrial
IDT72T55248L5 IDT72T55248L6-7
IDT72T55258L5 IDT72T55258L6-7
IDT72T55268L5 IDT72T55268L6-7
Symbol Parameter Min. Max. Min. Max. Unit
fSClock Cycle Frequency (WCLK & RCLK) — 200 — 150 MHz
tAData Access Time 0.6 3.6 0.6 3.8 ns
tCLK Clock Cycle Time 5 — 6.7 — ns
tCLKH Clock High Time 2. 3 — 2 .8 — n s
tCLKL Clock Low Time 2. 3 — 2. 8 — ns
tDS Data Setup Time 1.5 — 2.0 — ns
tDH Data Hold Time 0.5 — 0.5 — ns
tENS Enable Setup Time 1.5 — 2.0 — ns
tENH Enable Hold Time 0.5 — 0.5 — ns
fCClock Cycle Frequency (SCLK) — 10 — 10 M Hz
tASO Serial Output Data Access Time — 20 — 20 ns
tSCLK Serial Clock Cycle 100 — 100 — ns
tSCKH Serial Clock High 45 — 45 — ns
tSCKL Serial Clock Low 45 — 45 — ns
tSDS Serial Data In Setup 15 — 15 — ns
tSDH Serial Data In Hold 5 — 5 — n s
tSENS Serial Enable Setup 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — ns
tRS Reset Pulse Width 200 — 200 — ns
tRSS Reset Setup Time 15 — 15 — ns
tRSR Reset Recovery Time 10 — 10 — ns
tRSF Reset to Flag and Output Time — 12 — 15 ns
tOLZ (OE - Qn)(2) Output Enable to Output in Low-Impedance 0.6 3.6 0.8 3.8 ns
tOHZ(2) Output Enable to Output in High-Impedance 0.6 3.6 0.8 3.8 ns
tOE Output Enable to Data Output Valid 0.6 3.6 0.8 3.8 ns
tWFF Write Clock to FF or IR — 3.6 — 3.8 ns
tREF Read Clock to EF or OR — 3.6 — 3.8 ns
tCEF Read Clock to Composite EF or OR — 3.6 — 3.8 ns
tCFF Write Clock to Composite FF or IR — 3.6 — 3.8 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.6 — 3.8 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.6 — 3.8 ns
tPAFA Write Clock to Asynchronous Programmable Almost-Full Flag — 10 — 12 ns
tPAEA Read Clock to Asynchronous Programmable Almost-Empty Flag — 10 — 12 ns
tERCLK RCLK to Echo RCLK Output — 4. 0 — 4. 3 ns
tCLKEN RCLK to Echo REN Output — 3. 6 — 3.8 n s
tDTime Between Data Switching and ERCLK edge 0.4 — 0.5 — ns
tRCSLZ RCLK to Active from High-Impedance — 3.6 — 3.8 ns
tRCSHZ RCLK to High-Impedance — 3.6 — 3.8 ns
tSKEW1(3) SKEW time between RCLK and WCLK for EF/OR and FF/IR 4— 5—ns
tSKEW2 SKEW time between RCLK and WCLK for EF/OR and FF/IR in5— 7—ns
DDR mode
tSKEW3 SKEW time between RCLK and WCLK for PAE and PAF 5— 7—ns
NOTES:
1. Values guaranteed by design, not currently tested.
2. This applies to both DDR and SDR modes of operation.
16
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC TEST LOADS
Figure 2a. AC Test Load
6157 drw06
50
Ω
V
DDQ
/2
I/O Z
0
= 50
Ω
Input Pulse Levels 0.25 to 1.25V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.75
Output Reference Levels VDDQ/2
HSTL
1.5V AC TEST CONDITIONS
Input Pulse Levels GND to 2.5V
Input Rise/Fall Times 1ns
Input Timing Reference Levels VCC/2
Output Reference Levels VDDQ/2
LVTTL
2.5V AC TEST CONDITIONS
NOTE:
1. VDDQ = 1.5V.
NOTE:
1. For LVTTL, VCC = VDDQ = 2.5V.
Input Pulse Levels 0.4 to 1.4V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.9
Output Reference Levels VDDQ/2
EXTENDED HSTL
1.8V AC TEST CONDITIONS
NOTE:
1. VDDQ = 1.8V.
Figure 2b. Lumped Capacitive Load, Typical Derating
6157 drw06a
6
5
4
3
2
1
20 30 50 80 100 200
Capacitance (pF)
∆t
CD
(Typical, ns)
17
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE & DISABLE TIMING
VIH
OE
VIL
t
OE &
t
OLZ
100mV
100mV
t
OHZ
100mV
100mV
Single Output
Normally
LOW
Single Output
Normally
HIGH
VOL
VOH
V
DDQ
/2
6157 drw07
Output
Enable
Output
Disable
V
DDQ
/2
V
DDQ
/2
V
DDQ
/2
t
OLZ
Current data in output register
t
OE
V
DDQ
/2
Output Bus V
DDQ
/2
t
OHZ
READ CHIP SELECT ENABLE & DISABLE TIMING
NOTES:
1. REN is HIGH.
2. OE is LOW.
V
IH
RCS
V
IL
tENS
tENH
tRCSLZ
RCLK
VDDQ
2
VDDQ
2
100mV
100mV
tRCSHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
VDDQ
2
VDDQ
2
6157 drw08
NOTES:
1. REN is HIGH.
2. RCS is LOW.
18
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
MASTER RESET & DEVICE CONFIGURATION - MRS
During Master Reset the device operation is determined, this includes the
following:
1.Mux, Demux or Broadcast mode
2.IDT Standard or First Word Fall Through (FWFT) flag timing mode
3.Single or Double Data Rates on both the Write and Read ports
4. Programmable flag mode, synchronous or asynchronous timing
5.Write and read port bus widths, x10, x20 or x40
6.Default offsets for the programmable flags, 7, 63, 127 or 1023
7.LVTTL or HSTL I/O level selection
8. Input and output Queue selection
The state of the configuration inputs during a master reset will determine which
of the above modes are selected. A Master Reset comprises of pulsing the MRS
input ping from high to low for a period of time (tRS) with the configuration inputs
held in their respective states. Table 1 summarizes the configuration modes
available doing master reset. The are described as follows:
Mux/Demux/Broadcast. This mode is selected using the MD[1:0] inputs.
If during master reset, MD1 is HIGH and MD0 is LOW then Mux mode is selected.
If MD1 and MD2 are LOW then Demux is selected. If MD1 is LOW and MD0
is HIGH then Broadcast mode is selected.
IDT Standard or FWFT Mode. The two available flag timing modes are
selected using the FWFT/SI input. If FWFT/SI is LOW during Master Reset then
IDT Standard mode is selected, if it is high then FWFT mode is selected.
Single Data Rate (SDR) or Double Data Rate (DDR). The input/output
data rates are port selectable. This is a versatile feature that allows the user to
select either SDR or DDR on the write port(s) and/or read(s) port using the
WDDR and/or RDDR inputs. If WDDR is LOW during master reset then the write
port(s) will function in SDR mode, if it is high then the write port will be DDR mode.
If RDDR is LOW during master reset then the read port(s) will function in SDR
mode, if it is high then the read port will be DDR mode. Note that WDDR will select
the data rate mode for the single write port in Demux and Broadcast mode and
all four write ports in Mux mode. Likewise, RDDR will select the data rate mode
for the single read port in Mux mode and all four read ports in Demux and
Broadcast mode.
Programmable Almost Empty/Full Flags. These flags can operate in
either synchronous or asynchronous timing mode. If the programmable flag
input, PFM is HIGH during master reset then all programmable flags will operate
in a synchronous manner, meaning the PAE flags are double buffered and
updated based on the rising edge of its respective read clocks. The PAF flags
are also double buffered and updated based on the rising edge of its respective
write clocks. If it is LOW then all programmable flags will operate in an
asynchronous manner, meaning the PAE and PAF flags are not double buffered
and will update through the internal counter after a nominal delay.
Selectable Bus Width. The bus width can be selected on the write port in
Demux and Broadcast mode and on the read port in Mux mode. In Demux and
Broadcast mode the write port width is selected using the IW[1:0] inputs. If IW0
and IW1 are LOW then the write port will be 10 bits wide, if IW0 is LOW and IW1
is HIGH then the write port will be 20 bits wide, if IW0 is HIGH and IW1 is LOW
then the write port will be 40 bits wide. Note, in Demux and Broadcast mode all
read ports are 10 bits wide. In Mux mode the read port width is selected using
the OW[1:0] inputs. If OW0 and 0W1 are LOW then the read port will be 10 bits
wide, if OW0 is LOW and OW1 are HIGH then the read port will be 20 bits wide,
if OW0 is HIGH and OW1 are LOW then the read port will be 40 bits wide. Note,
in Mux mode all write ports are 10 bits wide.
Programmable Flag Offset Values. These offset values can be user
programmed or they can be set to one of four default values during a master
reset. For default programming, the state of the FSEL[1:0] inputs during master
TABLE 1 — DEVICE CONFIGURATION
PINS VALUES CONFIGURATION
MD[1:0] 00 Demux
10 Mux
01 Broadcast Write
11 Restricted
FWFT/SI 0 IDT Standard
1 FWFT
WDDR 0 Single Data Rate write port
1 Double Data Rate write port
RDDR 0 Single Data Rate read port
1 Double Data Rate read port
PFM 0 Asynchronous operation of PAE and PAF outputs
1 Synchronous operation of PAE and PAF outputs
IW[1:0] 0 0 Write port is 10 bits wide
0 1 Write port is 20 bits wide
1 0 Write port is 40 bits wide
11 Restricted
OW[1:0] 0 0 Read port is 10 bits wide
0 1 Read port is 20 bits wide
1 0 Read port is 40 bits wide
11 Restricted
FSEL[1:0] 00 Programmable flag offset registers value = 7
01 Programmable flag offset registers value = 63
10 Programmable flag offset registers value = 127
11 Programmable flag offset registers value = 1023
IOSEL 0 All applicable I/Os (except CMOS) are LVTTL
1 A ll applicable I/Os (except CMOS) are HSTL/eHSTL
IS[1:0] Mux/Broadcast Mode Demux Mode
00 not used Queue0
01 not used Queue1
10 not used Queue2
11 not used Queue3
OS[1:0] Mux Mode Demux/Broadcast Mode
00 Queue0 not used
01 Queue1 not used
10 Queue2 not used
11 Queue3 not used
IDT72T55248
IDT72T55258
IDT72T55268
FSEL1 FSEL0 Offsets n,m
00 7
0163
1 0 127
1 1 1,023
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. In default programming, the offset value selected applies to all internal Queues.
2. To program different offset values for each Queue, serial programming must be used.
19
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
reset will determine the value. Table 1 lists the four offset values and how to select
them. For programming the offset values to a specific number, use the serial
programming signals (SCLK, SWEN, SREN, FWFT/SI) to load the value into
the offset register. You may also use the JTAG port on this device to load the
offset value. Keep in mind that you must disable the serial programming signals
if you plan to use the JTAG port for loading the offset values. To disable the serial
programming signals, tie SCLK, SWEN, SREN, and SI to VCC. A thorough
explanation of the serial and JTAG programming of the flag offset values is
provided in the next section.
I/O Level Selection. The I/Os can be selected for either 2.5V LVTTL levels
or 1.5V HSTL / 1.8V eHSTL levels. The state of the IOSEL input will determine
which I/O level will be selected. If IOSEL is HIGH then the applicable I/Os will
be 1.5V HSTL or 1.8V eHSTL, depending on the voltage level applied to VDDQ
and VREF. For HSTL, VDDQ and VREF = 0.75V and for eHSTL VDDQ and VREF
= 0.9V. If IOSEL is LOW then the applicable I/Os will be 2.5V LVTTLVREF =
0. As noted in the Pin Description section, IOSEL is a CMOS input and must be
tied to either VCC or GND for proper operation.
Input and Output Selection. During master reset, the value of IS[1:0] and
OS[1:0] will be held constant and indicates which internal Queue the read and
write port will select for initial operation. Data will be written to or read from this
internal Queue on the first valid write and read operation after master reset.
SERIAL WRITING AND READING OF OFFSET REGISTERS
These offset registers can be loaded with a default value or they can be user
programmed with another value. One of four default values are detected based
on the state of the FSEL[1:0] inputs, discussed in the Functional Description
section earlier. User programming of the offset values can be performed by
SCLKTDI*
0008
TCK* SWEN
0
SREN
1
No Operation
IW/OW = x40
Serial read from registers:
104 bits for the IDT72T55248
112 bits for the IDT72T55258
120 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
IDT72T55258
IDT72T55268
IDT72T55278
Serial write into register:
104 bits for the IDT72T55248
112 bits for the IDT72T55258
120 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
6157 drwAA
IW/OW = x20
Serial write into register:
112 bits for the IDT72T55248
120 bits for the IDT72T55258
128 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
0007
11
Serial read from registers:
112 bits for the IDT72T55248
120 bits for the IDT72T55258
128 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
No Operation
Don’t
care
except
0008 &
0007
10
XX
IW/OW = x10
Serial write into register:
120 bits for the IDT72T55248
128 bits for the IDT72T55258
136 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
Serial read from registers:
120 bits for the IDT72T55248
128 bits for the IDT72T55258
136 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
No Operation
NOTES:
* Programming done using the JTAG port.
1. The programming methods apply to both IDT Standard mode and FWFT mode.
2. Parallel programming is not featured in this device.
3. The number of bits includes programming to all four dedicated PAE/PAF offset registers.
Figure 3. Programmable Flag Offset Programming Methods
either the dedicated serial programming port or the JTAG port. The dedicated
serial port can be used to load or read the contents of the offset registers. The
offset registers are programmed and read sequentially and behave similar to
a shift register.
The serial read and write operations are performed by the dedicated SCLK,
FWFT/SI, SWEN, SREN, and SDO pins. The total number of bits per device
is listed in Figure? Programmable Flag Offset Programming Sequence. These
bits account for all four PAE/PAF offset registers in the device. To write to the
offset registers, set the serial write enable signal active (LOW), and on each rising
edge of SCLK one bit from the FWFT/SI pin is serially shifted into the flag offset
register chain. Once the complete number of bits has been programmed into all
four registers, the programming sequence is complete. The programming
sequence is listed in Figure ? To read values from the offsets registers, set the
serial read enable active (LOW). Then on each rising edge of SCLK, one bit
is shifted out to the serial data output. The serial read enable must be kept LOW
throughout the entire read operation. To stop reading the offset register, disable
the serial read enable (HIGH). There is serial read enable to SCLK time for
reading the offset registers, as the offset register data for each Queue is
temporarily stored in a scan chain. When data has been completely read out
of the offset registers, any additional read operations to the offset register will
result in zeros as the output data.
Reading and writing of the offset registers can also be accomplished using
the JTAG port. To write to the offset registers using JTAG, set the instructional
register to the offset write command (Hex Value = 0x0008). The JTAG port will
load data into each of the offset registers in a similar fashion as the serial
programming described above. To read the values from the offset registers, set
the instructional register to the offset read command (Hex Value = 0x0007). The
20
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TDO of the JTAG port will output data in a similar fashion as the serial
programming described above.
The number of bits required to load the offset registers is dependent on the
size of the device selected. Each offset register requires different total number
of bits depending on input and output bus width configuration. This total must be
programmed into the device in order for all the flags to be programmed correctly.
To change values of one or more offset register, all of the registers must be
reprogrammed serially again. See Figure? Offset Registers Serial Bit Se-
quence.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T55248/72T55258/72T55268 support two different timing modes
of operation: IDT Standard mode or First Word Fall Through (FWFT) mode.
The selection of which mode will operate is determined during master reset, by
the state of the FWFT input.
During master reset, if the FWFT pin is LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (EF) to indicate whether or not there
are any words present in the Queue. It also uses the Full Flag (FF) to indicate
whether or not the Queue has any free space for writing. In IDT Standard mode,
every word read from the Queue, including the first, must be requested using
the Read Enable (REN) and RCLK.
If the FWFT pin is HIGH during master reset, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs. It also uses Input Ready (IR) to indicate whether
or not the Queue has any free space for writing. In the FWFT mode, the first word
written to an empty Queue goes directly to output bus after three RCLK rising
edges, applying RCS = LOW is not necessary. However, subsequent words
must be accessed using the (RCS) and RCLK. Various signals, in both inputs
and outputs operate differently depending on which timing mode is in effect. The
timing mode selected affects all internal Queues equally.
IDT STANDARD MODE
In this mode, the status flags FF, PAF, PAE, and EF operate in the manner
outlined in Table 3. To write data into the Queue, Write Enable (WEN) and WCS
must be LOW. Data presented to the DATA IN lines will be clocked into the Queue
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH after three clock latency.
Subsequent writes will continue to fill up the Queue. The Programmable Almost-
Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the
Queue, where n is the empty offset value. The default setting for these values
are listed in Table ?. This parameter is also user programmable as described
in the serial writing and reading of offset registers section.
Continuing to write data into the Queue without performing read operations
will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no
reads are performed, the PAF will go LOW after (8,192-m) writes for the
IDT72T55248, (16,384-m) writes for the IDT72T55258, and (32,768-m) writes
for the IDT72T55268. This is assuming the I/O bus width is configured to x40.
If the I/O is x20, then PAF will go LOW after (16,384-m) writes for the
IDT72T55248, (32,768-m) writes for the IDT72T55258, and (65,536-m) writes
for the IDT72T55268. If the I/O is x10, then PAF will go LOW after (32,768-m)
writes for the IDT72T55248, (65,536-m) writes for the IDT72T55258, and
(131,072-m) writes for the IDT72T55268. The offset “m” is the full offset value.
The default setting for these values are listed in Table 3. This parameter is also
user programmable. See the section on serial writing and reading of offset
registers for details.
When the Queue is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the Queue. If the I/O bus width is configured to x40, then D = 8,192 writes for
the IDT72T55248, 16,384 writes for the IDT72T55258, and 32,768 writes for
the IDT72T55268. If the I/O is x20, then D = 16,384 writes for the IDT72T55248,
32,768 writes for the IDT72T55258, and 65,536 writes for the IDT72T55268.
If the I/O is x10, then D = 32,768 writes for the IDT72T55248, 65,536 writes
for the IDT72T55258, and 131,072 writes for the IDT72T55268.
6157 drwAB
Offset
Register
PAE3
PAF3
PAE2
PAF2
PAE1
PAF1
PAE0
PAF0
14 - 26
27 - 39
40 - 52
53 - 65
66 - 78
1 - 13
79 - 91
92 - 104
Serial Bits
IDT72T55248
IW/OW = x20
or
IDT72T55258
IW/OW = x40
IDT72T55248
IW/OW = x20
or IDT72T55258
IW/OW = x20
or IDT72T55268
IW/OW = x40
IDT72T55248
IW/OW = x40
IDT72T55268
IW/OW = x10
IDT72T55258
IW/OW = x10
or
IDT72T55268
IW/OW = x20
15 - 28
29 - 42
43 - 56
57 - 70
71 - 84
1 - 14
85 - 98
99 - 112
16 - 30
31 - 45
46 - 60
61 - 75
76 - 90
1 - 15
91 - 105
106 - 120
17 - 32
33 - 48
49 - 64
65 - 80
81 - 96
1 - 16
97 - 112
113 - 128
18 - 34
35 - 51
52 - 68
69 - 85
86 - 102
1 - 17
103 - 119
120 - 136
Figure 4. Offset Registers Serial Bit Sequence
21
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If the Queue is full, the first read operation will cause FF to go HIGH after two
WCLKS. Subsequent read operations will cause PAF to go HIGH at the
conditions described in Table ?. If further read operations occur, without write
operations, PAE will go LOW when there are n words in the Queue, where n
is the empty offset value. Continuing read operations will cause the Queue to
become empty. Then the last word has been read from the Queue, the EF will
go LOW inhibiting further read operations. REN is ignored when the Queue is
empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs. IDT Standard mode is available when the device is
configured in both Single Data Rate and Double Data Rate mode. Relevant
timing diagrams for IDT Standard mode can be found in Figures 14, 15, 16.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags OR, IR, PAE, and PAF operate in the manner
outlined in Table 4. To write data into to the Queue, WCS must be LOW. Data
presented to the DATA IN lines will be clocked into the Queue on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOWafter 3rd rising edge of RCLK. Subsequent writes will continue
to fill up the Queue. PAE will go HIGH after n + 2 words have been loaded into
the Queue, where n is the empty offset value. The default setting for these values
are listed in Table 4. This parameter is also user programmable as described
in the serial writing and reading of offset registers section.
Continuing to write data into the Queue without performing read operations
will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no
reads are performed, the PAF will go LOW after (8,193-m) writes for the
IDT72T55248, (16,385-m) writes for the IDT72T55258, and (32,769-m) writes
for the IDT72T55268. This is assuming the I/O bus width is configured to x40.
If the I/O is x20, then PAF will go LOW after (16,385-m) writes for the
IDT72T55248, (32,769-m) writes for the IDT72T55258, and (65,537-m) writes
for the IDT72T55268. If the I/O is x10, then PAF will go LOW after (32,769-m)
writes for the IDT72T55248, (65,537-m) writes for the IDT72T55258, and
(131,073-m) writes for the IDT72T55268. The offset “m” is the full offset value.
The default setting for these values are listed in Table ?. This parameter is also
user programmable. See the section on serial writing and reading of offset
registers for details.
When the Queue is full, the Input Ready (IR) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, IR will go LOW after
D writes to the Queue. If the I/O bus width is configured to x40, then D = 8,193
writes for the IDT72T55248, 16,385 writes for the IDT72T55258, and 32,769
writes for the IDT72T55268. If the I/O is x20, then D = 16,385 writes for the
IDT72T55248, 32,769 writes for the IDT72T55258, and 65,537 writes for the
IDT72T55268. If the I/O is x10, then D = 32,769 writes for the IDT72T55248,
65,537 writes for the IDT72T55258, and 131,073 writes for the IDT72T55268.
If the Queue is full, the first read operation will cause IR to go HIGH after two
WCLKs after RCLK. Subsequent read operations will cause PAF to go HIGH
at the conditions described in Table ? If further read operations occur, without
write operations, PAE will go LOW when there are n words in the Queue, where
n is the empty offset value. Continuing read operations will cause the Queue to
become empty. Then the last word has been read from the Queue, the OR will
go HIGH inhibiting further read operations. RCS is ignored when the Queue
is empty.
When configured in FWFT mode, the OR flag output is triple register-buffered
and the IR flag output is double register-buffered. Relevant timing diagrams for
FWFT mode can be found in Figures 17, 18, 19.
6157 drwSFT
TABLE 4 STATUS FLAGS FOR FWFT MODE
TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE
0
1 to n
(1)
(n+1) to (8,192 - m)
8,192
FF PAF PAE EF
HHLL
HHLH
HLHH
LLHH
IDT72T55248 IDT72T55258
IDT72T55258
IDT72T55248
IDT72T55248
OW = x20
Number of
Words in
Queue
OW = x10
IDT72T55268OW = x40
IDT72T55268
IDT72T55258 IDT72T55268
0
1 to n
(1)
(n+1) to (16,384 - m)
16,384
0
1 to n
(1)
(n+1) to (32,768 - m)
32,768
0
1 to n
(1)
(n+1) to (65,536 - m)
65,536
0
1 to n
(1)
(n+1) to (131,072 - m)
131,072
0
1 to n+1
(1)
(n+2) to (8,193 - m)
8,193
FF PAF PAE EF
HHLL
HHLH
HLHH
LLHH
IDT72T55248 IDT72T55258
IDT72T55258
IDT72T55248
IDT72T55248
OW = x20
Number of
Words in
Queue
OW = x10
IDT72T55268OW = x40
IDT72T55268
IDT72T55258 IDT72T55268
0
1 to n+1
(1)
(n+2) to (16,385 - m)
16,385
0
1 to n+1
(1)
(n+2) to (32,769 - m)
32,769
0
1 to n+1
(1)
(n+2) to (65,537 - m)
65,537
0
1 to n+1
(1)
(n+2) to (131,073 - m)
131,073
NOTE:
1. n, m = 7 if FSEL[1:0] = 00, n, m = 63 if FSEL[1:0] = 01, n, m = 127 if FSEL[1:0] = 10, n, m = 1023 if FSEL[1:0] = 11.
NOTE:
1. n, m = 7 if FSEL[1:0] = 00, n, m = 63 if FSEL[1:0] = 01, n, m = 127 if FSEL[1:0] = 10, n, m = 1023 if FSEL[1:0] = 11.
22
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HSTL/LVTTL I/O
The inputs and outputs of this device can be configured for either LVTTL or
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels. To select between HSTL or eHSTL VREF must be
driven to 0.75V or 0.9V respectively. Typically a logic HIGH in HSTL would
be VREF ±300mV and a logic LOW would be VREF ±300mV. If the IOSEL pin
is LOW during master reset, then all applicable LVTTL or HSTL signals will be
configured for LVTTL operating voltage levels. In this configuration VREF must
be set to the static core voltage of 2.5V. Table ? illustrates which pins are and
are not associated with this feature. Note that all “Static Pins” must be tied to VCC
or GND. These pins are CMOS only and are purely device configuration pins.
Note the IOSEL pin should be tied HIGH or LOW and cannot toggle before and
after master reset.
BUS MATCHING
The write and read port has bus-matching capability such that the input and
output bus can be either 10 bits, 20 bits or 40 bits wide, depending on which
operating mode the device is configured to. The bus width of both the input and
output port is determined during master reset using the input and output width
setup pins (IW[1:0], OW[1:0]). The selected port width is applied to all four Queue
ports, such that all four Queues will be configured for either x10, x20 or x40 bus
widths. When writing or reading data from a Queue the number of memory
locations available to be written or read will depend on the bus width selected
and the density of the device.
If the write/read port is 10 bits wide, this provides the user with a Queue depth
of 32,768 x 10 for the IDT72T55248, 65,536 x 10 for the IDT72T55258, or
131,072 x 10 for the IDT72T55268. If the write/read port is 20 bits wide, this
provides the user with a Queue depth of 16,384 x 20 for the IDT72T55248,
32,768 x 20 for the IDT72T55258, or 65,536 x 20 for the IDT72T55268. If the
write/read port is 40 bits wide, this provides the user with a Queue depth of 8,192
x 40 for the IDT72T55248, 16,384 x 40 for the IDT72T55258, or 32,768 x 40
for the IDT72T55268. The Queue depths will always have a fixed density of
327,680 bits for the IDT72T55248, 655,360 bits for the IDT72T55258 and
1,310,072 bits for the IDT72T55268 regardless of bus-width configuration on
the write/read port.
When the device is operating in double data rate, the word is twice as large
as in single data rate since one word written or read on both the rising and falling
edge of clock. Therefore in DDR, the Queue depths will be half of what it is
mentioned above. For instance, if the write/read port is 10 bits wide, the depth
of each Queue is 16,384 x 10 for the IDT72T55248, 32,768 x 10 for the
IDT72T55258, or 65,536 x 10 for the IDT72T55268.
See Figure 5, Bus-Matching Byte Arrangement for more information.
LVTTL/HSTL/eHSTL STATIC CMOS SIGNALS
Write Port Read Port JTAG Control Pins Serial Port Static Pins
D[39:0] CEF/COR TCK FSEL[1:0] SCLK IOSEL
WCLK0/1/2/3 EF0/1/2/3 TRST IS[1:0] SREN IW[1:0]
WEN0/1/2/3 OR0/1/2/3 TMS OS[1:0] SWEN MD[1:0]
FF0/1/2/3 ERCLK0/1/2/3 TDI PD FWFT/SI OW[1:0]
WCS0/1/2/3 OE0/1/2/3 TDO MRS SDO PFM
CFF/CIR PAE0/1/2/3 PRS0/1/2/3 RDDR
PAF0/1/2/3 Q[39:0] FWFT/SI WDDR
RCLK0/1/2/3
RCS0/1/2/3
REN0/1/2/3
EREN[3:0]
TABLE 5 — I/O VOLTAGE LEVEL CONFIGURATION
23
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 5. Bus-Matching Byte Arrangement (Mux Mode)
6157 drw09
x10 INPUT to x40 OUTPUT for Queue0
2nd: Write to Queues
L
OS1 OS0 OW1
LH
BYTE ORDER ON OUTPUT PORT:
D39-D30 D29-D20 D19-D10 D9-D0
A
1st: Write to Queues
MUX MODE
BYTE ORDER ON INPUT PORT:
B
4th: Write to Queues
C
3rd: Write to Queues
D
Queue0
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
A
1st: Read from Queues
BCD
1st: Read from Queues
A
C
2nd: Read from Queues
x10 INPUT to x20 OUTPUT for Queue0
2nd: Read from Queues
A
1st: Read from Queues
B
4th: Read from Queues
C
3rd: Read from Queues
D
x10 INPUT to x10 OUTPUT for Queue0
OW0
L
B
D
L
OS1 OS0 OW1
LL
BYTE ORDER ON OUTPUT PORT:
OW0
H
L
OS1 OS0 OW1
LL
OW0
L
BYTE ORDER ON OUTPUT PORT:
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
Queue1Queue2Queue3
NOTES:
= High-Z outputs.
= Inputs set to GND.
24
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 5. Bus-Matching Byte Arrangement (Demux Mode) (Continued)
6157 drw10
x40 INPUT to x10 OUTPUT for Queue1
1st: Read from Queues
D39-D30 D29-D20 D19-D10 D9-D0
A
1st: Write to Queues
A
3rd: Read from Queues
B
2nd: Read from Queues
C
1st: Write to Queues
A
x20 INPUT to x10 OUTPUT for Queue1
x10 INPUT to x10 OUTPUT for Queue1
B
LHLH
L
IS1 IS0 IW1
HH
IW0
L
4th: Read from Queues
D
IS1 IS0 IW1 IW0
1st: Read from Queues
A
2nd: Read from Queues
B
1st: Write to Queues
A
1st: Read from Queues
A
LHLL
IS1 IS0 IW1 IW0
DEMUX MODE
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON INPUT PORT:
X
BCD
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
X
X
X
X
X
X
X
X
X
X
X
Note:
X is data in the output register.
D39-D30 D29-D20 D19-D10 D9-D0
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
Q39-Q30 Q29-Q20 Q19-Q10 Qn-Q0
D39-D30 D29-D20 D19-D10 D9-D0
Queue0Queue1Queue2Queue3
X
X
X
X
X
X
X X X
25
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 5. Bus-Matching Byte Arrangement (Broadcast Mode) (Continued)
6157 drw11
x40 INPUT to x10 OUTPUT for Every Queue
1st: Read from Queues
A1st: Write to Queues
BROADCAST MODE
BYTE ORDER ON INPUT PORT:
3rd: Read from Queues
B
2nd: Read from Queues
C
1st: Write to Queues
A
x20 INPUT to x10 OUTPUT for Every Queue
x10 INPUT to x10 OUTPUT to Every Queue
B
4th: Read from Queues
D
1st: Read from Queues
2nd: Read from Queues
1st: Write to Queues
A
1st: Read from Queues
L L
IW1 IW0
AAAA
BBBB
CCCC
DDDD
AAAA
BBBB
AAAA
L H
IW1 IW0
H L
IW1 IW0
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON INPUT PORT:
D39-D30 D29-D20 D19-D10 D9-D0
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
D39-D30 D29-D20 D19-D10 D9-D0
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
D39-D30 D29-D20 D19-D10 D9-D0
Q39-Q30 Q29-Q20 Q19-Q10 Q9-Q0
26
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SELECTABLE MODES
The device is capable of operating in three different modes, Mux, Demux,
and Broadcast Write. Each of these three modes can be selected based on the
MD[1:0] bits. These bits should be tied directly to VCC or GND as they are latched
in during master reset. The state of the MD pins for each mode is summarized
in Table 1 – Device Configuration.
Each mode has access to four dedicated Queues internally, with each Queue
having densities of 327,680 bits for the IDT72T55248, 655,360 bits for the
IDT72T55258 and 1,310,072 bits for the IDT72T55268. The density of each
Queue is fixed and cannot be programmed. Also, the density does not change
when the device is operating in single or double data rate, or when the device
is utilizing the bus-matching feature.
The QuadMux flow-control device accommodates for all of the timing issues
associated with converging multiple data rates onto one path. Such issues
include clock skew, race conditions, and meeting setup and hold times. These
issues are difficult to address when performing mux operations from external
logic or within an FPGA, especially at higher frequencies. The complexity of the
design makes it difficult to implement within an FPGA, where speed degradations
occur as the circuit becomes more complicated.
MUX MODE
In Mux mode the device is configured as shown in the Mux mode block
diagram on page 1. The device in this mode consists of four separate Queues:
Queue 0, Queue 1, Queue 2 and Queue 3. The four Queues all have the same
common read port, and the read control selecting which Queue to read from.
The Mux mode can be used in applications where multiple incoming data rates
from different data paths are being buffered to one common data rate and data bus.
WRITE PORT OPERATION
In Mux mode there are four independent write port controls for each individual
Queue. Data can be written to any of the four Queues using its corresponding
write clock, write enable, and write chip select. A data word will be written on
the rising (and falling in DDR) edge of write clock provided WEN and write chip
select are active. Note in double data rate the setup and hold times of the write
enables and write chip selects are sampled with respect to the rising edge of its
respective write clock only. The falling edge of WCLK does not sample the write
enable and write chip select.
In FWFT mode the first word written to any Queue will automatically be placed
onto the output bus of that respective Queue when selected on the read port via
the OS[1:0] pins. There is a two cycle input pipeline and a two cycle output
pipeline. It will take two cycles or three rising edges of the WCLK to move data
from the write port to the queue and two cycles or those rising edges of RCLK
to move data from the queue to the data outlines. This is regardless of the state
of the corresponding read enable and read chip select, provided that the
selected Queue was empty. This is not true in IDT Standard mode, where the
first word written to a selected Queue must be accessed by setting REN and RCS
are LOW on the rising edge of RCLK.
READ PORT OPERATION
In Mux mode the output select pins (OS[1:0]) determine which one of the four
Queues the output bus will read data from. The output select pins are sampled
on the rising edge of every RCLK, and may change on every clock edge. Thus
there is no latency switching from one Queue to another. Note that in Mux mode
only the RCLK0 is active, all other output read clocks are not used. The same
applies to the read enable (REN0) and read chip select (RCS0). Data will be
read on the rising (and falling in DDR) edge of read clock provided read enable
and read chip select are active (LOW). When selecting a Queue for read
operations the new word read from that Queue will be available immediately on
the next clock edge after the new Queue is selected. For example, if OS[1:0]
is set to 01 (Queue1) on RCLK edge 0, then on RCLK edge 1 (next read clock
edge) data can be read from Queue1 if REN0 and RCS0 are enabled.
In FWFT mode, the first word written to a selected Queue will automatically
be placed onto the output bus of that respective Queue regardless of the state
of the corresponding read enable, provided that the selected Queue was empty
and its corresponding output ready flag was inactive. This occurs due to the
nature of the FWFT flag timing. There is a two cycle input pipeline and a two cycle
output pipeline. It will take two cycles or three rising edges of the WCLK to move
data from the write port to the queue and two cycles or those rising edges of RCLK
to move data from the queue to the data outlines. Subsequent writes to the Queue
that is not empty will not fall through to the output bus. Note in FWFT mode, during
a Queue selection the next word available in the Queue will automatically fall
through to the output bus regardless of the read enable and read chip select.
In IDT Standard mode, every word including the first word must be accessed
by the read enable and read chip select. Unlike FWFT mode, during a Queue
selection the next word available in the Queue will not automatically fall through
to the output bus. The previous word that was read out of the read port will remain
on the output bus if the REN and RCS select are HIGH.
DEMUX MODE
In Demux mode the device is configured as shown in the Demux mode block
diagram on page 2. The device in this mode consists of four separate Queues:
Queue 0, Queue 1, Queue 2 and Queue 3. The four Queues all have the same
common write port, and the read control selecting which Queue to read from.
The Demux mode can be used in applications where a single incoming data
rate is being buffered to multiple outgoing data rates.
WRITE PORT OPERATION
In Demux mode the input select pins (IS[1:0]) determine which one of the four
Queues the input bus will write data into. The input select pins are sampled on
the rising edge of every WCLK, and may change on every clock edge. Thus
there is no latency switching from one Queue to another. Note that in Demux
mode only the WCLK0 is active, all other input write clocks are not used. The
same applies to the write enable (WEN0) and write chip select (WCS0). Data
will be written on the rising (and falling in DDR) edge of write clock provided WEN
and WCS are active on the rising edge of the WCLK. Note in double data rate
the setup and hold times of the WEN and WCS selects are sampled with respect
to the rising edge of the write clock only. The falling edge of WCLK does not
sample the write enable and write chip select. When selecting a Queue for write
operations the next word can be written to that Queue immediately on the next
clock edge after the new Queue is selected. For example, if IS[1:0] is set to 01
(Queue1) on WCLK edge 0, then on WCLK edge 1 (next read clock edge) data
can be written to Queue1 if WEN0 and WCS0 are enabled.
In FWFT mode the first word written to a selected Queue will automatically
be placed onto the output bus regardless of the state of the corresponding read
enable, provided that the selected Queue was empty and its corresponding
output ready flag was inactive. There is a two cycle input pipeline and a two cycle
output pipeline. It will take two cycles or three rising edges of the WCLK to move
data from the write port to the queue and two cycles or those rising edges of RCLK
to move data from the queue to the data outlines. This occurs due to the nature
of the FWFT flag timing. Subsequent writes to the Queue that is not empty will
not fall through to the output bus. In IDT Standard mode, every word including
the first word must be accessed by the read enable and read chip select.
READ PORT OPERATION
In Demux mode there are four independent read port controls for each
individual Queue. Data can be read from any of the four Queues using its
27
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
corresponding read clock, read enable, and read chip select. A data word will
be read on the rising (and falling in DDR) edge of read clock provided read
enable and read chip select are active. There are also four individual output
enables that will take the output bus to high-impedance. Note that data will be
read from memory regardless of the state of the output enable OE[3:0] pins.
As explained above, in FWFT mode the first word written to each Queue will
automatically be placed onto the output bus regardless of the of the state of the
corresponding read enable. There is a two cycle input pipeline and a two cycle
output pipeline. It will take two cycles or three rising edges of the WCLK to move
data from the write port to the queue and two cycles or those rising edges of
RCLK to move data from the queue to the data outlines.
BROADCAST WRITE MODE
In Broadcast Write mode the device is configured as shown in the Broadcast
Write mode block diagram on page 2. The device in this mode consists of four
separate Queues: Queue 0, Queue 1, Queue 2 and Queue 3. The four Queues
all have one common write port which will write data into all four Queues
simultaneously when a write operation is initiated, there is no write selection
to write data into a specific Queue. The Broadcast Write mode can be used in
applications where a single incoming data bus needs to be sent to multiple data
paths simultaneously.
WRITE PORT OPERATION
In Broadcast Write mode there are no input or output select pins to select the
individual Queues separately. The write port will write data into all four Queues
simultaneously. Note that in Broadcast mode only the WCLK0 is active, all other
input clocks are not used. The same applies to the write enable (WEN0) and
write chip select (WCS0). Data will be written on the rising (and falling in DDR)
edge of write clock provided write enable and write chip select are active (LOW)
on the rising edge of write clock. Write operations are prohibited if any of the
four Queues are being partially reset or any of their full flag status full (FF =
LOW).
In FWFT mode, the first word written to a selected Queue will automatically
be placed onto the output bus of that respective Queue regardless of the state
of the corresponding read enable, provided that the selected Queue was empty
and its corresponding output ready flag was inactive. There is a two cycle input
pipeline and a two cycle output pipeline. It will take two cycles or three rising
edges of the WCLK to move data from the write port to the queue and two cycles
or those rising edges of RCLK to move data from the queue to the data outlines.
This occurs due to the nature of the FWFT flag timing. Subsequent writes to
the Queue that is not empty will not fall through to the output bus. In IDT Standard
mode, every word including the first word must be accessed by the read enable
and read chip select.
READ PORT OPERATION
In Broadcast Write mode there are four independent read port controls for
each individual Queue. Data can be read from any of the four Queues using
its corresponding read clock, read enable, and read chip select. A data word
will be read on the rising (and falling in DDR) edge of read clock provided read
enable and read chip select are active. There are also four individual output
enables that will take the output bus to high-impedance. Note that data will be
read from memory regardless of the state of the output enable OE[3:0] pins.
28
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT BUS (D[39:0])
The data input bus can be 40, 20, or 10 bits wide in Demux and Broadcast
mode. D[39:0] are data inputs for the 40-bit wide data bus, D[19:0] are data
inputs for 20-bit wide data bus, and D[9:0] are data inputs for the 10-bit wide
data bus. In Mux mode the input bus will be 10 bits wide for each of the four
internal Queues. D[9:0] are dedicated to Queue 0, D[19:10] are dedicated to
Queue 1, D[29:20] are dedicated to Queue 2, and D[39:30] are dedicated to
Queue 3. Data can be written into each of the four Queues on every WCLK
cycle. There is a two cycle input pipeline and a two cycle output pipeline. It will
take two cycles or three rising edges of the WCLK to move data from the write
port to the queue and two cycles or those rising edges of RCLK to move data
from the queue to the data outlines.
MASTER RESET (MRS)
There is a single master reset available for all internal Queues in this device.
A master reset is accomplished whenever the MRS input is taken to a LOW state.
This operation sets the internal read and write pointers of all Queues to the first
location in memory. The programmable almost empty flag will go LOW and the
almost full flags will go HIGH.
If FWFT/SI signal is LOW during master reset then IDT Standard mode is
selected. This mode utilizes the empty and full status flags from the EF/OR and
FF/IR dual-purpose pin. During master reset, all empty flags will be set to LOW
and all full flags will be set to HIGH.
If FWFT/SI signal is HIGH during master reset, then the First Word Fall
Through mode is selected. This mode utilizes the input read and output ready
status flags from the EF/OR and FF/IR dual-purpose pin. During master reset,
all input ready flags will be set to LOW and all output ready flags will be set to
HIGH.
All device configuration pins such as MD[1:0], OW[1:0], IW[1:0], IS[1:0],
OS[1:0], WDDR, RDDR, IOSEL, PFM, FSEL[1:0] and FWFT/SI needs to be
defined before the master reset cycle. During a master reset the output register
is initialized to all zeros. If the output enable(s) are LOW during master reset,
then the output bus will be LOW. If the output enable(s) are HIGH during master
reset, then the output bus will be in High-impedance. RCS has no affect on the
data outputs during master reset. If the output width OW[1:0] is configured to
x10 or x20, then the unused outputs will be in high-impedance. A master reset
is required after power up before a write operation to any Queue can take place.
Master reset is an asynchronous signal and thus the read and write clocks can
be free-running or idle during master reset. See Figure 10, Master Reset
Timing, for the associated timing diagram.
PARTIAL RESET (PRS0/1/2/3)
A partial reset is a means by which the user can reset both the read and write
pointers of each individual Queue inside the device without changing the
Queue’s configuration. There are four dedicated partial reset signals that each
correspond to an individual Queue. There are restrictions as to when partial
reset can be performed that apply to each operating modes.
In Mux mode, partial reset may not be performed on the two Queues involved
during Queue selection on the read port. For instance, if OS[1:0] is switching
from 00 to 01 then PRS0 and PRS1 may not be enabled from the first rising RCLK
edge with OS[1:0]=01 until three more rising RCLK edges have been received.
In other words, partial reset may not be performed for a minimum of three RCLK
cycles from the time a new Queue is selected. Also, if Queue0 or Queue1 are
partially reset before the switch, the appropriate PRS signal must return HIGH
at least tRSR (reset recovery time) before the first RCLK edge with OS[1:0]=01.
Any Queues not involved in the selection can be partially reset.
In Demux mode, partial reset may not be performed on the two Queues
involved during Queue selection on the write port. For instance, if IS[1:0] is
switching from 11 to 10 then PRS3 and PRS2 may not be enabled from the first
rising WCLK edge with OS[1:0]=01 until three more rising WCLK edges have
been received. In other words, partial reset may not be performed for a minimum
of three WCLK cycles from the time a new Queue is selected. Also, if Queue0
or Queue1 are partially reset before the switch, the appropriate PRS signal must
be HIGH at least tRSR (reset recovery time) before the first WCLK edge with
IS[1:0]=10. Any Queues not involved in the selection can be partially reset.
In Broadcast mode, partial reset may not be performed during write
operations. The write enable and write chip select must be HIGH with respect
to the rising edge of WCLK0 for a minimum of tRSS before partial reset can be
performed. If the device is operating in DDR mode, partial reset of any Queue
must be initiated after the falling edge of WCLK0 to ensure data from the falling
edge are written into all four Queues in memory. This maintains the data integrity
of all four Queues in the device.
See Figures 11, 12, 13, Partial Reset Timing, for the associated timing
diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
input determines whether the device will operate in IDT Standard mode or First
Word Fall Through (FWFT) mode.
If FWFT/SI is LOW before the falling edge of master reset, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the Queues memory. It also uses the
Full Flag function (FF) to indicate whether or not the Queues memory has any
free space for writing. In IDT Standard mode, every word read from the
Queues, including the first, must be requested using the Read Enable (REN),
Read Chip Select (RCS) and RCLK.
If FWFT/SI is HIGH before the falling edge of master reset, then FWFT mode
will be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the Queues have any free space for writing. In the
FWFT mode, the first word written to an empty Queue goes directly to Qn after
three RCLK rising edges, provided that the first RCLK meets tSKEW param-
eters. There will be a one RCLK cycle delay if tSKEW is not met. REN and RCS
do not need to be enabled. Subsequent words must be accessed using the
REN, RCS, and RCLK. RCS must be LOW or the outputs will be in a High-
state.
The state of the FWFT/SI input must be kept at the present state for the
minimum of the reset recovery time (tRSR) after master reset. After this time, the
FWFT/SI acts as a serial input for loading PAE and PAF offsets into the
programmable offset registers. The serial input is used in conjunction with
SCLK, SWEN, SREN, and SDO to access the offset registers. Serial program-
ming using the FWFT/SI pin functions the same way in both IDT Standard and
FWFT modes.
WRITE CLOCK (WCLK0/1/2/3)
There are a possible total of four write clocks available in this device
depending on the mode selected, each corresponding to the individual Queues
in memory. A write cycle is initiated on the rising and/or falling edge of the WCLK
input. If the write double data rate (WDDR) mode pin is tied HIGH during master
reset, data will be written on both the rising and falling edge of WCLK0/1/2/3,
provided that WEN0/1/2/3 and WCS0/1/2/3 are enabled. If WDDR is tied LOW,
data will be written only on the rising edge of WCLK0/1/2/3 provided that WEN0/
1/2/3 and WCS0/1/2/3 are enabled. The four write clocks are completely
independent of one another.
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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
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TEMPERATURE RANGES
Data setup and hold times must be met with respect to the LOW-to-HIGH (and
HIGH-to-LOW in DDR) transition of the write clock(s). It is permissible to stop
the write clock(s). Note that while the write clocks are idle, the FF/IR0/1/2/3 and
PAF0/1/2/3 flags will not be updated unless it is operating in asynchronous
timing mode (PFM=00). The write clocks can either be independent or
coincident of one another.
In Demux and Broadcast Write mode, only the WCLK0 input is available.
All other write clocks inputs should be tied to GND.
WRITE ENABLE (WEN0/1/2/3)
There are a possible total of four write enables available in this device
depending on the mode selected, one for each individual Queues in memory.
When the write enable input is LOW on the rising edge of WCLK in single data
rate, data is loaded on the rising edge of every WCLK cycle, provided the
device is not full and the write chip select (WCS) is enabled. The setup and
hold times are referenced with respect to the rising edge of WCLK only. When
the write enable input is LOW on the rising edge of WCLK in double data rate,
data is loaded into the selected Queue on the rising and falling edge of every
WCLK cycle, provided the device is not full and the write chip select (WCS)
is enabled. In this mode, the data setup and hold times are referenced with
respect to the rising and falling edge of WCLK. Note that WEN and WCS are
sampled only on the rising edge of WCLK in either data rate modes.
Data is stored in the Queues sequentially and independently of any ongoing
read operation. When the write enable(s) and write chip select(s) are HIGH,
no new data is written into the corresponding Queue on each WCLK cycle. The
four write enables operate independent of one another.
In Demux and Broadcast mode, only the WEN0 input is available. All other
write enables should be tied to VCC.
WRITE CHIP SELECT (WCS0/1/2/3)
There are a possible total of four write chip selects available in this device
depending on the mode selected, one for each individual Queues in memory.
The write chip selects disables all Write Port inputs for each individual Queue
if it is held HIGH. To perform normal write operations for each individual Queue,
the write chip select must be enabled, held LOW. The four write chip selects
are completely independent of one another.
When the write chip select is LOW on the rising edge of WCLK in single data
rate, data is loaded on the rising edge of every WCLK cycle, provided the
device is not full and the write enable (WEN) of the corresponding Queue is
LOW. When the write chip select is LOW on the rising edge of WCLK in double
data rate, data is loaded into the selected Queue on the rising and falling edge
of every WCLK cycle, provided the device is not full and the write enable (WEN)
of the corresponding Queue is LOW.
When the write chip select is HIGH on the rising edge of WCLK in single data
rate, the write port is disabled and no words are written on the rising edge of
WCLK into the Queue, even if WEN is LOW. If the write chip select is HIGH on
the rising edge of WCLK in double data rate, the write port is also disabled and
no words are written on the rising and falling edge of WCLK into the Queue,
even if WEN is LOW. Note that WCS is sampled on the rising edge of WCLK
only in either data rate modes.
In Demux and Broadcast mode, only the WCS0 input is available. All other
write chip selects should be tied to VCC.
WRITE DOUBLE DATA RATE (WDDR)
When the write double data rate (WDDR) pin is HIGH prior to master reset,
the write port will be set to double data rate mode. In this mode, all write
operations are based on the rising and falling edge of the write clocks, provided
that write enables and write chip selects are LOW for the rising clock edges.
In double data rate the write enable signals are sampled with respect to the rising
edge of write clock only, and a word will be written on both the rising and falling
edge of write clock regardless of whether or not the write enables are active
on the falling edge of write clock.
When WDDR is LOW, the write port will be set to single data rate mode. In
this mode, all write operations are based on only the rising edge of the write
clocks, provided that write enables and write chip selects are LOW during the
rising edge of write clock. This pin should be tied HIGH or LOW and cannot
toggle before or after master reset.
READ CLOCK (RCLK0/1/2/3)
There are a possible total of four read clocks available in this device
depending on the mode selected, each corresponding to the individual Queues
in memory. A read cycle is initiated on the rising and/or falling edge of the RCLK
input. If the read double data rate (RDDR) mode pin is tied HIGH, data will be
read on both the rising and falling edge of RCLK0/1/2/3, provided that REN0/
1/2/3 and RCS0/1/2/3 are enabled. If RDDR is tied LOW, data will be read
only on the rising edge of RCLK0/1/2/3 provided that REN0/1/2/3 and RCS0/
1/2/3 are enabled. The four read clocks are completely independent of one
another.
There is an associated data access time (tA) for the data to be read out of
the Queues. It is permissible to stop the read clocks. Note that while the read
clocks are idle, the EF/OR0/1/2/3 and PAE0/1/2/3 flags will not be updated
unless it is operating in asynchronous timing mode (PFM=0). The write and
read clocks can either be independent or coincident.
In Mux mode, only the RCLK0 input is available. All other read clock inputs
should be tied to GND.
READ ENABLE (REN0/1/2/3)
There are a possible total of four read enables available in this device
depending on the mode selected, one for each individual Queue in memory.
When the read enable input is LOW on the rising edge of RCLK in single data
rate, data will be read on the rising edge of every RCLK cycle, provided the
device is not empty and the read chip select (RCS) is enabled. The associated
data access time (tA) is referenced with respect to the rising edge of RCLK.
When the read enable input is LOW on the rising edge of RCLK in double data
rate, will be read on the rising and falling edge of every RCLK cycle, provided
the device is not empty and RCS is enabled. In this mode, the data access times
are referenced with respect to the rising and falling edges of RCLK. Note that
REN is sampled only on the rising edge of RCLK in either data rate modes.
Data is stored in the Queues sequentially and independently of any ongoing
write operation. When the read enable(s) and read chip select(s) are HIGH,
no new data is read on each RCLK cycle. The four read enables operate
independent of one another.
To prevent reading from an empty Queue in the IDT Standard mode, the
empty flag of each Queue will go LOW with respect to RCLK, when the total
number of words in the Queue has been read out, thus inhibiting further read
operations. Upon the completion of a valid write cycle, the empty flag will go
HIGH with respect to RCLK two cycles later, thus allowing another read to
occur, providing tSKEW of WCLK to RCLK is met.
In Mux mode, only the REN0 input is available. All other read enables should
be tied to VCC.
READ CHIP SELECT (RCS0/1/2/3)
There are a possible total of four read chip selects available in this device,
each corresponding to the individual Queue in memory. The read chip select
inputs provides synchronous control of the read port for each individual Queue.
When the read chip select is held LOW, the next rising edge of the correspond-
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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ing RCLK will enable the output bus. When the read chip select goes HIGH,
the next rising edge of RCLK will send the output bus into high-impedance and
prevent that RCLK from initiating a read, regardless of the state of REN. During
a master or partial Reset the read chip select input has no effect on the output
bus, output enable (OE[3:0]) is the only input that provides high-impedance
control of the output bus. If output enable is LOW, the data outputs will be active
regardless of read chip select until the first rising edge of RCLK after a reset is
complete. Afterwards if read chip select is HIGH the data outputs will go to high-
impedance. The four read chip selects are completely independent of one
another.
The read chip select inputs do not affect the updating of the flags. For example,
when the first word is written to any/all empty Queues, the empty flag(s) will still
go from LOW to HIGH based on a rising edge of the RCLK(s), regardless of
the state of the read chip select inputs. Also, when operating the Queue in FWFT
mode the first word written to any/all empty Queues will still be clocked through
to the output bus on the third rising edge of RCLK(s), regardless of the state of
read chip select inputs, assuming that the tSKEW parameter is met. For this reason
the user should pay extra attention to the read chip selects when a data word
is written to any/all empty Queues in FWFT mode. If the read chip select inputs
are HIGH when an empty Queue is written into, the first word will fall through
to the output register but will not be available on the outputs because they are
in high-impedance. The user must enable the read chip selects on the next rising
edge of RCLK to access this first word.
In Mux mode, only the RCS0 input is available. All other read chip select inputs
should be tied to VCC.
READ DOUBLE DATA RATE (RDDR)
When the read double data rate (RDDR) pin tied HIGH, the read port will be
set to double data rate mode, sampled during master reset. In this mode, all read
operations are based on the rising and falling edge of the read clocks, provided
that read enables and read chip selects are LOW. In double data rate mode,
the read enable signals are sampled with respect to the rising edge of read clock
only, and a word will be read from both the rising and falling edge of read clock
regardless of whether or not read enable and read chip select are active on
the falling edge of read clock.
When RDDR is tied LOW at master reset, the read port will be set to single
data rate mode. In this mode, all read operations are based on only the rising
edge of the read clocks, provided that read enables and read chip selects are
LOW during the rising edge of read clock. This pin should be tied HIGH or LOW
and cannot toggle before and after master reset.
OUTPUT ENABLE (OE0/1/2/3)
There are a possible total of four asynchronous output enables available in
this device, each corresponding to the individual Queues in memory. When the
output enable inputs are LOW, the output bus of each individual Queue become
active and drives the data currently in the output register. When the output enable
inputs (OE[3:0]) are HIGH, the output bus of each individual Queue goes into
high-impedance. During master or partial Reset the output enable is the only
input that can place the output data bus into high-impedance. During reset the
read chip select input has no effect on the output data bus. The four output enable
inputs are completely independent of one another.
In Mux mode, only the OE0 input is available. All other output enable inputs
should be tied to GND.
I/O SELECT (IOSEL)
The inputs and outputs of this device can be configured for either LVTTL or
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels. To select between HSTL or eHSTL VREF must be
driven to 0.75V or 0.9V respectively.
If the IOSEL pin is LOW during master reset, then all applicable LVTTL or
HSTL signals will be configured for LVTTL operating voltage levels. In this
configuration VREF should be set to the static core voltage of 2.5V.
This pin should be tied HIGH or LOW and cannot toggle before or after master
reset. Please refer to table ? for a list of applicable LVTTL/HSTL/eHSTL signals.
POWER DOWN (PD)
This device has a power down feature intended for reducing power
consumption for HSTL/eHSTL configured inputs when the device is idle for a
long period of time. By entering the power down state certain inputs can be
disabled, thereby significantly reducing the power consumption of the part. All
WEN and REN signals must be disabled for a minimum of four WCLK and RCLK
cycles before activating the power down signal. The power down signal is
asynchronous and needs to be held LOW throughout the desired power down
time. During power down, the following conditions for the inputs/outputs signals
are:
•All data in Queue(s) are retained.
•All data inputs become inactive.
•All write and read pointers maintain their last value before power down.
•All enables, chip selects, and clock input pins become inactive.
••
••
•All data outputs become inactive and enter high-impedance state.
••
••
•All flag outputs will maintain their current states before power down.
••
••
•All programmable flag offsets maintain their values.
••
••
•All echo clocks and enables will become inactive and enter
high-impedance state.
••
••
•The serial programming and JTAG port will become inactive and enter
high-impedance state.
••
••
•All setup and configuration CMOS static inputs are not affected, as these
pins are tied to a known value and do not toggle during operation.
All internal counters, registers, and flags will remain unchanged and maintain
their current state prior to power down. Clock inputs can be continuous and free-
running during power down, but will have no affect on the part. However, it is
recommended that the clock inputs be low when the power down is active. To
exit power down state and resume normal operations, disable the power down
signal by bringing it HIGH. There must be a minimum of 1µs waiting period before
read and write operations can resume. The device will continue from where it
had stopped, no form of reset is required after exiting power down state. The
power down feature does not provide any power savings when the inputs are
configured for LVTTL operation. However, it will reduce the current for I/Os that
are not tied directly to VCC or GND. See Figure ?, for the associated timing
diagram.
SERIAL CLOCK (SCLK)
The serial clock is used to load data and read data from in the programmable
offset registers. Data from the serial input signal (FWFT/SI) can be loaded into
the offset registers on the rising edge of SCLK provided that the serial write
enable (SWEN) signal is LOW. Data can be read from the offset registers via
the serial data output (SDO) signal on the rising edge of SCLK provided that
SREN is LOW. The serial clock can operate at a maximum frequency of 10MHz.
The read operation is non-destructive. However, the write operation will
change the flag offsets on each SCLK rising edge as data shifts into the registers.
SERIAL WRITE ENABLE (SWEN)
The serial write enable input is an enable used for serial programming of the
programmable offset registers. It is used in conjunction with the serial input
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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
(FWFT/SI) and serial clock (SCLK) when programming the offset registers.
When the serial write enable is LOW, data at the serial input is loaded into the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
write enable is HIGH, the offset registers retain the previous settings and no
offsets are loaded. Serial write enable functions the same way in both IDT
Standard and FWFT modes.
SERIAL READ ENABLE (SREN)
The serial read enable input is an enable used for reading the value of the
programmable offset registers. It is used in conjunction with the serial data output
(SDO) and serial clock (SCLK) when reading the offset registers. When the
serial read enable is LOW, data at the serial data output can be read from the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
read enable is HIGH, the reading of the offset registers will stop. Whenever serial
read enable (SREN) is activated values in the offset registers are read starting
from the first location in the offset registers. The SREN HIGH to LOW transition
copies the values in the offset registers directly into a serial scan out register.
SREN must be kept LOW in order to read the entire contents of the offset register.
If at any point SREN is toggled HIGH to LOW, another copy function from the
offset register to the serial scan out register will occur. Serial read enable
functions the same way in both IDT Standard and FWFT modes.
OUTPUTS:
DATA OUTPUT BUS (Q[39:0])
The data output bus can be 40, 20, or 10 bits wide in Mux mode. Q[39:0] are
data outputs for the 40-bit wide data bus, Q[19:0] are data outputs for 20-bit wide
data bus, and Q[9:0] are data outputs for the 10-bit wide data bus. In Demux
and Broadcast mode the output bus will be 10 bits wide for each of the four internal
Queues. Q[9:0] are dedicated to Queue 0, Q[19:10] are dedicated to Queue
1, Q[29:20] are dedicated to Queue 2, and Q[39:30] are dedicated to Queue
3. In FWFT mode, when switching from one Queue to another, the data of the
newly selected Queue will always be present on the output bus two cycles after
the next RCLK cycle after OS[1:0] is selected providing RCS is LOW regardless
of whether or not REN is active. Thus each of the four Queues can be accessed
on every RCLK cycle.
EMPTY/OUTPUT READY FLAG (EF/OR0/1/2/3)
There are four empty/output ready flags available in this device, each
corresponding to the individual Queues in memory. This is a dual-purpose pin
that is determined based on the state of the FWFT/SI pin during master reset
for selecting one of the two timing modes of this device. In the IDT Standard mode,
the empty flags are selected. When an individual Queue is empty, its empty flag
will go LOW, inhibiting further read operations from that Queue. When the empty
flag is HIGH, the individual Queue is not empty and valid read operations can
be applied. See Figures 24, 25, Read Cycle, Empty Flag and First Word
Latency Timing (IDT Standard Mode), for the relevant timing information. Also
see Table 3 “Status Flags for IDT Standard Mode” for the truth table of the empty
flags.
In FWFT mode, the output ready flags are selected. Output ready flags (OR)
go LOW at the same time that the first word written to an empty Queue appears
on the outputs, which is a minimum of three read clock cycles provided the RCLK
and WCLK meets the tSKEW parameter. OR stays LOW after the RCLK LOW-
to-HIGH transitions that shifts the last word from the Queue to the outputs. OR
goes HIGH when an enabled read operation is performed to an empty queue.
The previous data stays at the outputs, indicating the last word was read. Further
data reads are inhibited until a new word is on the bus when OR goes LOW again.
See Figures 21, 22, 23, Read Timing (FWFT Mode), for the relevant timing
information. Also see Table 4 “Status Flags for FWFT Mode” for the truth table
of the empty flags.
The empty/output ready flags are synchronous and updated on the rising
edge of RCLK. In IDT Standard mode, the flags are double register-buffered
outputs. In FWFT mode, the flags are triple register-buffered outputs. The four
empty flags operate independent of one another and always indicate the
respective Queue’s status.
COMPOSITE EMPTY/OUTPUT READY FLAG (CEF/COR)
This status pin is used to determine the empty state of the current Queue
selected. The composite empty/output ready flag represents the state of the
Queue selected on the read port, such that the user does not have to monitor
each individual Queues’ empty/output ready flags. The composite empty/output
ready flag is only available in Mux mode, since the output select bits (OS[1:0])
are used to select any one of the four Queues to read from.
The timing of the composite empty/output ready flag differs in IDT Standard
and FWFT modes. In IDT Standard mode, when switching from one Queue to
another, the composite empty flag will update to the status of the newly selected
Queue one RCLK cycle after the rising edge of RCLK that made the new Queue
selection. In FWFT mode, the composite output ready flag will update to the status
of the newly selected Queue on two clock cycles after the rising edge of RCLK
that made the new Queue selection. See Figures 26, 27 for the associated timing
diagram. See Table 3 and 4 “Status Flags for IDT Standard and FWFT Mode
“ for the truth table of the composite empty flag.
FULL/INPUT READY FLAG (FF/IR0/1/2/3)
There are four full/input ready flags available in this device, each corresponding
to the individual Queues in memory. This is a dual-purpose pin that is determined
based on the state of the FWFT/SI pin during master reset for selecting the two
timing modes of this device. In the IDT Standard mode, the full flags are selected.
When an individual Queue is full, its full flags will go LOW after the rising edge
of WCLK that wrote the last word, thus inhibiting further write operations to the
Queue. When the full flag is HIGH, the individual Queue is not full and valid write
operations can be applied. See Figures 14, 15, 16, Write Cycle, Full Flag and
First Word Latency Timing (IDT Standard Mode), for the associated timing
diagram. Also see Table 3 “Status Flags for IDT Standard Mode” for the truth
table of the full flags.
In FWFT mode, the input ready flags are selected. Input ready flags go LOW
when there is adequate memory space in the Queues for writing in data. The
input ready flags go HIGH after the rising edge of WCLK that wrote the last word,
when there are no free spaces available for writing in data. See Figures 17,
18, 19, Write Timing (FWFT Mode), for the associated timing information. Also
see Table 4 “Status Flags for FWFT Mode” for the truth table of the full flags. The
input ready status not only measures the depth of the Queues memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to make IR HIGH is one greater than needed
to set FF = LOW in IDT Standard mode.
In Broadcast mode, when any one of the four full flags becomes asserted,
all write operations to every Queue will be disabled. This maintains data integrity
throughout all four Queues for comparison. In all other modes, the full flag will
only disable write operations to its corresponding Queue.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs. The four full flags operate independent of one
another, except in Broadcast mode.
To prevent data overflow in the IDT Standard mode, the full flag of each Queue
will go LOW with respect to WCLK, when the maximum number of words has
been written into the Queue, thus inhibiting further write operations. Upon the
32
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
completion of a valid read cycle, the full flag will go HIGH with respect to WCLK
two cycles later, thus allowing another write to occur, provided tSKEW has been
met.
To prevent data overflow in the FWFT mode, the input ready flag of each
Queue will go HIGH with respect to WCLK, when the maximum number of words
has been written into the Queue, thus inhibiting further write operations. Upon
the completion of a valid read cycle, the input ready flag will go LOW with respect
to WCLK two cycles later, thus allowing another write to occur, provided tSKEW
has been met.
COMPOSITE FULL/INPUT READY FLAG (CFF/CIR)
This status pin is used to determine the full state of the current Queue selected.
The composite full/input ready flag represents the state of the Queue selected
on the write port, such that the user does not have to monitor each individual
Queues’ full/input ready flags. The composite full/input ready flag is only
available in both Demux and Broadcast modes. When switching from one
Queue to another, the composite full/input ready flag will update to the status of
the newly selected Queue one WCLK cycle after the rising edge of WCLK that
made the new Queue selection, regardless of which timing mode the device is
operating in. See Figure ? for the relevant associated timing diagram. See Table
? and ? “Status Flags for IDT Standard and FWFT Mode “ for the truth table
of the composite full flag
PROGRAMMABLE ALMOST EMPTY FLAG (PAE0/1/2/3)
There are four programmable almost empty flags available in this device,
each corresponding to the individual Queues in memory. The programmable
almost empty flag is an additional status flag that notifies the user when the Queue
is near empty. The user may utilize this feature as an early indicator as to when
the Queue will become empty. In IDT Standard mode, PAE will go LOW when
there are n words or less in the Queue. In FWFT mode, the PAE will go LOW
when there are n-1 words or less in the Queue. The offset “n” is the empty offset
value. The default setting for this value is stated in Table ?. Since there are four
internal Queues hence four PAE offset values, n0, n1, n2, and n3.
There are two timing modes available for the PAE flags, selectable by the state
of the Programmable Flag Mode (PFM) pin during master reset. If PFM is tied
HIGH, then synchronous timing mode is selected. If PFM is tied LOW, then
asynchronous timing mode is selected. In synchronous PAE configuration, the
PAE flag is updated on the rising edge of RCLK. In asynchronous PAE
configuration, the PAE flag is asserted LOW on the LOW-to-HIGH transitions of
the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transitions
of the Write Clock (WCLK). See Figure ? and ?, Synchronous and Asynchronous
Programmable Almost-Empty Flag Timing (IDT Standard and FWFT mode),
for the relevant timing information.
The four programmable almost empty flags operate independent of one
another.
PROGRAMMABLE ALMOST FULL FLAG (PAF0/1/2/3)
There are four programmable almost full flags available in this device, each
corresponding to the individual Queues in memory. The programmable almost
full flag is an additional status flag that notifies the user when the Queue is nearly
full. The user may utilize this feature as an early indicator as to when the Queue
will not be able to accept any more data and thus prevent data from being
dropped. In IDT Standard mode, if no reads are performed after master reset,
PAF will go LOW after (D-m) (D meaning the density of the particular device)
words are written to the Queue. In FWFT mode, PAF will go LOW after (D+1-
m) words are written to the Queue. The offset “m” is the full offset value. The default
setting for this value is stated in Table 2. Since there are four internal Queues
hence four PAF offset values, m0, m1, m2, and m3.
There are two timing modes available for the PAF flags, selectable by the state
of the Programmable Flag Mode (PFM) pin during master reset. If PFM is tied
HIGH, then synchronous timing mode is selected. If PFM is tied LOW, then
asynchronous timing mode is selected. In synchronous PAF configuration, the
PAF flag is updated on the rising edge of WCLK. In asynchronous PAF
configuration, the PAF flag is asserted LOW on the LOW-to-HIGH transitions
of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH
transitions of the Read Clock (RCLK). See Figures 35 and 37, Synchronous
and Asynchronous Programmable Almost-Full Flag Timing (IDT Standard
and FWFT mode), for the relevant timing information.
The four programmable almost full flags operate independent of one
another.
TABLE 6 — TSKEW MEASUREMENT
Data Port Status Flags TSKEW Measurement Datasheet
Configuration Parameter
DDR Input EF/OR Negative Edge WCLK to tSKEW2
t o Positive Edge RCLK
DDR Output FF/IR Negative Edge RCLK to tSKEW2
Positive Edge WCLK
PAE Negative Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Negative Edge RCLK to tSKEW3
Positive Edge WCLK
DDR Input EF/OR Negative Edge WCLK to tSKEW2
t o Positive Edge RCLK
SDR Output FF/IR Positive Edge RCLK to tSKEW1
Positive Edge WCLK
PAE Negative Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Positive Edge RCLK to tSKEW3
Positive Edge WCLK
SDR Input EF/OR Positive Edge WCLK to tSKEW1
t o Positive Edge RCLK
DDR Output FF/IR Negative Edge RCLK to tSKEW2
Positive Edge WCLK
PAE Positive Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Negative Edge RCLK to tSKEW3
Positive Edge WCLK
SDR Input EF/OR Positive Edge WCLK to tSKEW1
t o Positive Edge RCLK
SDR Output FF/IR Positive Edge RCLK to tSKEW1
Positive Edge WCLK
PAE Positive Edge WCLK to tSKEW3
Positive Edge RCLK
PAF Positive Edge RCLK to tSKEW3
Positive Edge WCLK
33
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ECHO READ CLOCK (ERCLK0/1/2/3)
There are four echo read clock outputs available in this device, each
corresponding to their respective input read clocks in the Queue. The echo
read clock is a free-running clock output, that will always follow the RCLK input
regardless of the read enables and read chip selects. The ERCLK output
follows the RCLK input with an associated delay. This delay provides the user
with a more effective read clock source when reading data from the output bus.
This is especially helpful at high speeds when variables within the device may
cause changes in the data access times. These variations in access time may
be caused by ambient temperature, supply voltage, or device characteristics.
Any variations effecting the data access time will also have a corresponding
effect on the echo read clock output produced by the device, therefore the echo
read clock output level transitions should always be at the same position in time
relative to the data outputs. Note, that echo read clock is guaranteed by design
to be slower than the slowest data outputs. Refer to Figure 6, Echo Read Clock
and Data Output Relationship, Figure 27, Echo Read Clock and Read Enable
Operation in Double Data Rate Mode and Figure 28, Echo RCLK and Echo
REN
Operation for timing information. The four echo read clock outputs operate
independent of one another and are direct copies of their respective RCLK
inputs.
ECHO READ ENABLE (EREN0/1/2/3)
There are four echo read enable outputs available in this device, each
corresponding to the individual Queues in memory. The echo read enable
output is provided to be used in conjunction with the echo read clock and
provides the device receiving data from the Queue with a more effective
scheme for reading the Queues’ data. The echo read enable output is
controlled by internal logic that becomes active for the read clock cycle that a
new word is read out of the Queue. That is, a rising edge of read clock will cause
echo read enable to go LOW, if both read enable and read chip select are active
and the Queue is not empty. In other words, every cycle puts data on the output
bus and drives EREN output to the LOW.
Figure 6. Echo Read Clock and Data Output Relationship
NOTES:
1. REN is LOW. OE is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
5. DDR mode clocks data on rising and falling edge of RCLK.
6157 drw12
ERCLK
t
A
t
D
Q
SLOWEST
(3)
RCLK
t
ERCLK
t
A
(5)
34
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
4
t
3
TDO
TDO
TDI/
TMS
TCK
TRST
t
DO
Notes to diagram:
t1 = t
TCKLOW
t2 = t
TCKHIGH
t3 = t
TCKFALL
t4 = t
TCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
6157 drw13
t
5
t
6
t
1
t
2
t
TCK
t
DH
t
DS
Figure 7. Standard JTAG Timing
Parameter Symbol Test
Conditions Min. Max. Units
JTAG Clock Input Period tTCK - 100 - ns
JTAG Clock HIGH tTCKHIGH -40-ns
JTAG Clock Low tTCKLOW -40-ns
JTAG Clock Rise Time tTCKRISE --5
(1) ns
JTAG Clock Fall Time tTCKFALL --5
(1) ns
JTAG Reset tRST -50-ns
JTAG Reset Recovery tRSR -50-ns
JTAG
AC ELECTRICAL CHARACTERISTICS
(vcc = 3.3V ± 5%; Tambient (Industrial) = 0°C to +85°C)
NOTE:
1. 50pf loading on external output signals. NOTE:
1. Guaranteed by design.
SYSTEM INTERFACE PARAMETERS
IDT72T55248
IDT72T55258
IDT72T55268
Parameter Symbol Test Conditions Min. Max. Units
Data Output tDO(1) -20ns
Data Output Hold tDOH(1) 0-ns
Data Input tDS trise=3ns 10 - ns
tDH tfall=3ns 10 -
35
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAG TIMING SPECIFICATIONS
(IEEE 1149.1 COMPLIANT)
The JTAG test port in this device is fully compliant with the IEEE Standard
Test Access Port (IEEE 1149.1) specifications. Five additional pins (TDI, TDO,
TMS, TCK and TRST) are provided to support the JTAG boundary scan
interface. Note that IDT provides appropriate Boundary Scan Description
Language program files for these devices.
The Standard JTAG interface consists of seven basic elements:
•Test Access Port (TAP)
•TAP controller
•Instruction Register (IR)
•Data Register Port (DR)
•Bypass Register (BYR)
•ID Code Register
•Flag Programming
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 8. JTAG Architecture
TEST ACCESS PORT (TAP)
The TAP interface is a general-purpose port that provides access to the
internal JTAG state machine. It consists of four input ports (TCLK, TMS, TDI,
TRST) and one output port (TDO).
THE TAP CONTROLLER
The TAP controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and updating of data passed through the TDI
serial input.
In Pad
In Pad
Incell
Incell
Core
Logic
Outcell
Outcell
Out Pad
Out Pad
All outputs
All inputs
Eg: Dins, Clks
(BSDL file
describes the
chain order)
ID
Bypass
Instruction
Register
TA P
TMS
TDI
TCK
TRST
Instruction
Select
Enable
TDO
6157 drw14
Flag Offset Chain
36
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the Queue operation and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling the
normal operation of the IC. The TAP controller state machine is designed in such
a way that, no matter what the initial state of the controller is, the Test-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idle otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
Figure 9. TAP Controller State Diagram
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising
edge of TCK. The instruction available on the TDI pin is also shifted in to the
instruction register. TDO changes on the falling edge of TCK.
Exit1-IR This is a controller state where a decision to enter either the Pause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register
scan chain is latched in to the register of the Instruction Register on every falling
edge of TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
Test-Logic
Reset
Run-Test/
Idle
1
0
0
Select-
DR-Scan
Select-
IR-Scan
111
Capture-IR
0
Capture-DR
0
0
Exit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
10
1
1
1
6157 drw15
0
Shift-DR
0
0
0
Shift-IR
0
0
Pause-IR
0
1
Input is
TMS
0
0
1
NOTES:
1. Five consecutive 1's at TMS will reset the TAP.
2. TAP controller resets automatically upon power-up.
37
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
THE INSTRUCTION REGISTER
The instruction register (IR) is eight bits long and tells the device what
instruction is to be executed. Information contained in the instruction includes the
mode of operation (either normal mode, in which the device performs its normal
logic function, or test mode, in which the normal logic function is inhibited or
altered), the test operation to be performed, which of the four data registers is
to be selected for inclusion in the scan path during data-register scans, and the
source of data to be captured into the selected data register during Capture-DR.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in the serial
path. When the bypass register is selected by an instruction, the shift register
stage is set to a logic zero on the rising edge of TCLK when the TAP controller
is in the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The boundary-scan register (BSR) is 48 bits long. It contains one
boundary-scan cell (BSC) for each normal-function input pin and one BSC for
each normal-function I/O pin (one single cell for both input data and output data).
The BSR is used 1) to store test data that is to be applied externally to the device
output pins, and/or 2) to capture data that appears internally at the outputs of
the normal on-chip logic and/or externally at the device input pins.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the device to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT72T55248/72T55258/72T55268, the Part Number field con-
tains the following values:
IDT72T55248/258/268 JTAG Device Identification Register
31(MSB) 28 27 12 11 1 0(LSB)
V ersion (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0000 0033 (hex) 1
JTAG INSTRUCTION REGISTER
The Instruction register allows an instruction to be serially input into the
device when the TAP controller is in the Shift-IR state. The instruction is decoded
to perform the following:
•Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
•Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
Hex Instruction Function
Value
0000 EXTEST Test external pins
0001 SAMPLE/PRELOAD Select boundary scan register
0002 IDCODE Selects chip identification register
0003 CLAMP Fix the output chains to scan chain values
0004 HIGH-IMPEDANCE Puts all outputs in high-impedance state
0007 OFFSET READ Read PAE/PAF offset register values
0008 OFFSET WRITE Write PAE/PAF offset register values
000F BYPASS Select bypass register
Private Several combinations are private (for IDT
internal use). Do not use codes other than
those identified above.
JTAG INSTRUCTION REGISTER DECODING
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the device into an external
boundary-test mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register is
accessed to drive test data off-chip via the boundary outputs and receive test
data off-chip via the boundary inputs. As such, the EXTEST instruction is the
workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint
opens/shorts and of logic cluster function.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the device to remain in
a normal functional mode and selects the boundary-scan register to be
connected between TDI and TDO. During this instruction, the boundary-scan
register can be accessed via a data scan operation, to take a sample of the
functional data entering and leaving the device. This instruction is also used to
preload test data into the boundary-scan register before loading an EXTEST
instruction.
IDCODE
The optional IDCODE instruction allows the device to remain in its functional
mode and selects the optional device identification register to be connected
between TDI and TDO. The device identification register is a 32-bit shift register
containing information regarding the device manufacturer, device type, and
version code. Accessing the device identification register does not interfere with
the operation of the device. Also, access to the device identification register
should be immediately available, via a TAP data-scan operation, after power-
up of the device or after the TAP has been reset using the optional TRST pin
or by otherwise moving to the Test-Logic-Reset state.
Device Part# Field
IDT72T55248 04C9 (hex)
IDT72T55258 04CA (hex)
IDT72T55268 04CB (hex)
38
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CLAMP
The optional CLAMP instruction sets the outputs of an device to logic levels
determined by the contents of the boundary-scan register and selects the one-
bit bypass register to be connected between TDI and TDO. Before loading this
instruction, the contents of the boundary-scan register can be preset with the
SAMPLE/PRELOAD instruction. During this instruction, data can be shifted
through the bypass register from TDI to TDO without affecting the condition of
the outputs.
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an device to a disabled (high-impedance) state
and selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the device outputs.
OFFSET READ
This instruction is an alternative to serial reading the offset registers for the
PAE/PAF flags. When reading the offset registers through this instruction, the
dedicated serial programming signals must be disabled.
OFFSET WRITE
This instruction is an alternative to serial programming the offset registers for
the PAE/PAF flags. When writing the offset registers through this instruction, the
dedicated serial programming signals must be disabled.
BYPASS
The required BYPASS instruction allows the device to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the device.
39
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
EF/OR
0/1/2/3
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
t
RSF
PAF0/1/2/3
t
RSF
t
RSF
Q[39-0]
t
RSF
OE = HIGH
OE = LOW
6157 drw16
OW[1:0]
(4)
,
IW[1:0]
(4)
FSEL[1:0]
(4)
PFM
(4)
HIGH = Synchronous PAE/PAF Timing
LOW = Asynchronous PAE/PAF Timing
MD[1:0]
(4)
t
RSS
HIGH = FWFT Mode
LOW = IDT Standard Mode
RDDR
(4)
,
WDDR
(4)
FWFT/SI
(4)
IOSEL
(4)
HIGH = Read/Write Double Data Rate
LOW = Read/Write Single Data Rate
HIGH = HSTL I/Os
LOW = LVTTL I/Os
t
RSS
t
RSS
t
RSS
t
RSS
t
RSS
t
RSS
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
0/1/2/3
PAE0/1/2/3
IS[1:0]
(4)
,
OS[1:0]
(4)
t
RSS
t
RS
MRS
WEN
REN
t
RSS
SWEN,
SREN
t
RSS
t
RSR
t
RSR
Figure 10 . Master Reset
NOTES:
1. OE can be toggled during this period.
2. PRS should be HIGH during a MRS.
3. RCLK(s), WCLK(s) and SCLK(s) can be free running or idle.
4. The state of these pins are latched when the master reset pulse is LOW.
5. JTAG clock should not toggle during master reset.
6. RCS and WCS can be HIGH or LOW until the first rising edge of RCLK after master reset is complete.
7. EREN wave form is identical to REN, ERCLK wave form is identical to RCLK.
40
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WEN0/1,
REN0/1
t
RSS
PRS2/3
(1)
6157 drw17
FF/IR0/1
t
RSF
Current State
Current State
FF/IR2/3
t
RSF If FWFT = HIGH, FF = HIGH
If FWFT = LOW, IR = LOW
If FWFT = HIGH, CFF = HIGH
If FWFT = LOW, CIR = LOW
PAE0/1
t
RSF
Current State
PAE2/3
t
RSF
PAF0/1
t
RSF
Current State
PAF2/3
t
RSF
Q[39-0]
(2,4)
t
RSF OE = HIGH
OE = LOW
Current State
Current State
t
RSS
t
RSR
WEN2/3,
REN2/3
t
RSS
t
RSR
OS[1:0]
t
ENS
00 = Queue 0 01 = Queue 1
EF/OR0/1
t
RSF
Current State
Current State
EF/OR2/3
t
RSF If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
RCLK0
123
PRS0/1
(1)
t
RS
t
RS
CEF/COR
t
RSF
Current State
If FWFT = HIGH, COR = HIGH
If FWFT = LOW, CEF = LOW
4
Output Data Queue 0 Output Data Queue 1
Figure 11 . Partial Reset for Mux mode
NOTES:
1 . During the output selection of two Queues, partial reset of the two Queues involved are prohibited.
2. During partial reset the high-impedance control of the output is provided by OE only.
3. PRS0/1 must go LOW after the fourth rising edge of RCLK0.
4. This is the output data from Queue0 and Queue1.
41
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WEN0,
REN0/1
t
RSS
PRS2/3
(1)
6157 drw18
Current State
t
RSF If FWFT = HIGH, FF = HIGH
If FWFT = LOW, IR = LOW
t
RSF
Current State
PAE2/3
t
RSF
PAF0/1
t
RSF
Current State
PAF2/3
t
RSF
Q[9-0]
(2,4)
Q[19-10]
(2,5)
t
RSF
OE = HIGH
OE = LOW
Current State
Current State
t
RSS
t
RSR
REN2/3
t
RSS
t
RSR
IS[1:0]
t
DS
00 = Queue 0 01 = Queue 1
EF/OR0/1
t
RSF
Current State
Current State
EF/OR2/3
t
RSF If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
FF/IR0/1
t
RSF
Current State
FF/IR2/3
If FWFT = HIGH, FF = HIGH
If FWFT = LOW, IR = LOW
PAE0/1
WCLK0
123
PRS0/1
(1)
t
RS
t
RS
4
CFF/CIR
t
RSF
Current State
If FWFT = HIGH, FF = HIGH
If FWFT = LOW, IR = LOW
Q[29-20]
(2,6)
Q[39-30]
(2,7)
t
RSF OE = HIGH
OE = LOW
Figure 12 . Partial Reset for Demux mode
NOTES:
1 . During the output selection of two Queues, partial reset of the two Queues involved are prohibited.
2. During partial reset the high-impedance control of the output is provided by OE only.
3. PRS0/1 must go LOW after the fourth rising edge of WCLK0.
4. This is the output data from Queue0.
5. This is the output data from Queue1.
6. This is the output data from Queue2.
7. This is the output data from Queue3.
42
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 13. Partial Reset for Broadcast mode
WCLK0
REN
(2)
0/1/2/3
tRSS
PRS0/1/2/3
6157 drw19
(1)
WEN0
EF/OR0/1/2/3
tRSF If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
tRSS
FF/IR0/1/2/3
tRSF If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
PAE0/1/2/3
tRSF
PAF0/1/2/3
tRSF
Q[39-0]
(3,4)
tRSF OE = HIGH
OE = LOW
CFF/CIR
tRSF If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
NOTES:
1. If the write port is configured in double data rate, partial reset must be initiated after the falling edge of WCLK0 to ensure falling edge data is written into memory.
2. Only the read enable of the Queue involved in partial reset need to be HIGH.
3. During partial reset the high-impedance control of the outputs is provided by OE only.
4 . Only affects the output of the Queue partial reset is applied to.
43
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 14. Write Cycle and Full Flag Timing (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out
OS[1:0]
00=Queue 0
t
A
Previous Word+1 Queue 0
6157 drw20
12
RCLK0
3
REN0
01=Queue 1
Q[39:0]
(4) Previous Word Queue 0
t
A
Word 0 Queue 1
t
A
Word 0 Queue 2
t
A
Word 1 Queue 2
t
A
t
ENS
t
ENS
t
ENH
10=Queue 2
WCLK1
WEN0
12
D[9:0]
t
SKEW
(3)
t
ENS
No Write
WD-1
WCLK0
No Write
No Write
WEN1
FF0
t
WFF
t
WFF
FF1
t
DH
t
DS
WD
D[19:10]
WD-1
t
DS
t
DS
WD
t
DH
t
DH
t
ENH
t
ENH
t
WFF
t
WFF
t
DH
t
SKEW
(2)
NOTES:
1. WCS0, WCS1 are LOW.
2. This is the skew between RCLK0 and WCLK0 for Queue0.
3. This is the skew between RCLK0 and WCLK1 for Queue1.
4 . There is a two-stage pipeline so each read appears in the data bus two cycles or three rising edges of RCLK later.
44
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK2
t
SKEW1
Din[9:0]
WEN0
NO WRITE
WCLK0
NO WRITE
t
ENS
t
DH
Word D
t
DH
t
DS
Word D-1 Word D+1
t
DH
t
DS
Word D+2
Word 1
Q[29:20]
6157 drwA
t
A
Previous Data in Output Register
FF2
t
WFF
t
WFF
t
WFF
t
WFF
FF1
t
WFF
FF0
t
SKEW1
REN2
t
ENS
RCLK1
REN1
t
ENS
RCLK0
REN0
t
ENS
t
A
Word 2
t
A
Word 3
t
A
Word 4
t
A
Word 5
t
A
Word 6
t
A
Word 7
Word 1
t
A
t
A
Word 2
t
A
Word 3
t
A
Word 4
Q[19:10]
Previous Data in Output Register
Word 1
t
A
Q[9:0]
Previous Data in Output Register
1212
Figure 15. Write Cycle and Full Flag Timing (Broadcast Write mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out
NOTE:
1. WCS0, RCS0/1/2, and OE0/1/2 are LOW.
45
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK2
t
SKEW1
Din[9:0]
(2)
t
DH
Word X Queue X
t
DH
t
DS
Word X-1 Queue X
Q[29:20]
6157 drwB
Previous Data in Output Register
FF2
t
WFF
t
WFF
t
WFF
t
WFF
FF1
FF0
REN2
t
ENS
RCLK1
REN1
t
ENS
RCLK0
REN0
t
ENS
t
A
Word 1
t
A
Word 2
t
A
Word 3
t
A
Word 4
t
A
Word 5
Word 2
t
A
t
A
Word 3
t
A
Word 4
Q[19:10]
Previous Data in Output Register
Q[9:0]
Previous Data in Output Register
WEN0
WCLK0
NO WRITE
10 = Queue 2
IS[1:0]
01 = Queue 1 00 = Queue 0 10 01 00
t
ENH
t
ENS
10 01
Word 0 Queue 2 Word 0 Queue 1
t
WFF
t
WFF
t
SKEW1
t
SKEW1
Word 1
t
A
Word 2
t
A
t
A
Word 3Word 1
t
A
t
ENH
12 12
Word 1 Queue 1 Word 0 Queue 0
Figure 16. Write Cycle and Full Flag Timing (Demux mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out
NOTES:
1. WCS0, RCS0/1/2, and OE0/1/2 are LOW.
2. There is a two-stage pipeline so each read appears in the queue two cycles or three rising edges of WCLK later.
46
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK0
t
SKEW1
Word 1
Q[9:0]
6157 drwC
t
A
Previous Data in Output Register
t
A
Word 2
t
A
Word 3 Word 4
Q[19:10]
REN0
t
ENS
OR0t
WFF
OR1
Din[9:0]
WEN0
WCLK0
t
ENS
Word 2
t
DH
t
DS
Word 1
t
ENH
Word 3 Word 4
D[19:10]
WEN1
WCLK1
t
ENS
Word 2
t
DH
t
DS
Word 1
t
ENH
Word 3 Word 4
12 3
00 = Queue 0
OS[1:0]
01 = Queue 1
t
ENS
Word 1
t
A
Previous Data in Output Register Word 2
t
A
t
DH
t
DH
Figure 17. Write Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out
NOTE:
1. WCS0/1, and OE0/1 are LOW.
47
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK3
t
SKEW1
Word 1
Q[39:30]
6157 drwD
t
A
Previous Data in Output Register
t
A
Word 2
t
A
Word 3 Word 4
Q[9:0]
REN3
t
ENS
12 3
Word 1
t
A
Previous Data in Output Register Word 2
t
A
OR3t
REF
OR0
Din[9:0]
WEN0
WCLK0
t
ENS
Word 2
t
DH
t
DS
Word 1 Word 3 Word 4 Word 5 Word 6 Word 7
t
REF
RCLK0
t
SKEW1
REN0
t
ENS
12 3
t
A
Figure 18. Write Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out
NOTE:
1. WCS0, RCS0/3, and OE0/3 are LOW.
48
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK2
t
SKEW1
6157 drwE
Word 2
t
A
Word 3
t
A
Q[29:20]
Previous Data in Output Register
Q[19:10]
Previous Data in Output Register
Word 1
t
A
Word 2
t
A
t
A
Word 3Word 1
t
A
REN2
RCLK1
REN1
12 3
Din[9:0]
(2)
OR2
OR1
t
ENS
WEN0
WCLK0
10 = Queue 2
IS[1:0]
01 = Queue 1 10 01 10 01
t
ENS
10 01
t
REF
Word X Queue X
t
DH
t
DS
t
ENH
Word 0 Queue 2 Word 0 Queue 1 Word 1 Queue 2 Word 1 Queue 1 Word 2 Queue 2 Word 2 Queue 1
t
REF
t
SKEW1
12 3
Figure 19. Write Timing (Demux mode, FWFT mode, SDR to SDR) x10 In to x10 Out
NOTES:
1. WCS0, RCS1/2, and OE1/2 are LOW.
2. There is a two-stage pipeline so each read appears in the queue two cycles or three rising edges of WCLK later.
49
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK0
REN0
12
EF
t
REF
t
REF
t
REF
WEN3
D[39:30]
Q[39:0]
t
ENS
Wx-3
t
A
No Read No Read
Wx-1
t
A
Wx
CEF
t
REF
t
REF
t
REF
WCLK3
t
SKEW
t
ENS
t
ENH
t
DH
Wx (Byte 0)
6157 drw22
t
A
Wx-2
t
DS
t
DS
t
DH
Wx (Byte 1)
t
DS
t
DH
Wx (Byte 2)
t
DS
t
DH
Wx (Byte 3)
Figure 20. Read Cycle, Empty Flag and First Word Latency (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out
NOTES:
1. RCS0, WCS3, OE3 are LOW.
2. OS[1:0] = 11.
3. Wx (Byte 0) = Q[9:0], Wx (Byte 1) = Q[19:10], Wx (Byte 2) = Q[29:20], Wx (Byte 3) = Q[39:30].
50
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK1
t
SKEW1
6157 drwF
W4
t
A
Q[19:10] W1 W2
t
A
REN1
12
Din[9:0]
IR0
WEN0
WCLK0
W
D
t
DH
t
DS
t
WFF
t
WFF
W3
t
A
RCLK0
W2
Q[9:0] W1
REN0
t
A
t
REF
t
REF
Figure 21. Read Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out
NOTES:
1. WCS0, RCS0/1, and OE0/1 are LOW.
2. Q[39:10] = 0.
51
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK0
6157 drwG
W4
t
A
Q[9:0]
W1 W2
t
A
REN0
IR0
t
WFF
t
WFF
W3
t
A
t
ENS
t
SKEW1
12
D[9:0]
WEN0
WCLK0
W
D
t
ENH
t
ENS
t
A
W5
6157 drwH
t
A
W1 Byte D
t
A
t
ENS
t
A
RCLK0
Q[9:0]
REN0
IR0
t
WFF
t
WFF
t
SKEW1
12
D[19:0]
WEN0
WCLK0
W
D
t
ENH
t
ENS
t
DH
t
DS
W1 Byte 1 W2 Byte D W2 Byte 1
Figure 23. Read Timing (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out
NOTES:
1. WCS0, RCS0, and OE0 are LOW.
2. IS[1:0] = 00. Q[39:10] = 0.
3. WD is a 20-bit word. Q[9:0] = Byte 0, Q[19:10] = Byte 1.
Figure 22. Read Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out
NOTES:
1. WCS0, RCS0, and OE0 are LOW.
2. OS[1:0] = 00.
3. Q[39:10] = 0.
52
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK0
REN0
EF1
Q[19:10]
WCLK0
WEN0
D[19:0]
IS[1:0]
REN1
RCLK1
EF0
Q[9:0]
t
SKEW1
12
t
REF
6157 drwI
Previous Data in Output Register
t
A
W
X
Byte 0
t
A
01 = Queue 1 00 = Queue 0 01
t
ENS
t
ENH
WX Byte 0 - Byte 1
t
DS
t
ENS
t
SKEW1
12
W
X
Byte 1
t
ENS
t
REF
Previous Data in Output Register
t
A
W
X
Byte 0
t
A
W
X
Byte 1
t
ENS
t
ENS
t
DH
WX Byte 0 - Byte 1
t
DS
t
DH
Figure 24. Read Cycle, Empty Flag and First Word Latency (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out
NOTES:
1. WCS0, RCS0/1, and OE0/1 are LOW.
2. WX is a 20-bit word. LSB = Byte 0, MSB = Byte 1.
53
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK1
REN1
EF2
Q[29:20]
WCLK0
WEN0
D[39:0]
6157 drwJ
WX Byte 0 - Byte 3
t
DS
t
DH
REN2
RCLK2
EF1
Q[19:10]
t
SKEW1
12
t
REF
Previous Data in Output Register
t
A
WX Byte 0
t
A
t
ENS
12
WX Byte 3
t
ENS
t
REF
Previous Data in Output Register
t
A
WX Byte 0
t
A
WX Byte 1
t
ENS
t
REF
t
A
WX Byte 2
t
A
WX Byte 1
t
A
t
ENS
NO READ
Figure 25. Read Cycle, Empty Flag and First Word Latency (Broadcast Write mode, IDT Standard mode, SDR to SDR) x40 In to x10 Out
NOTES:
1. WCS0, RCS1/2, and OE1/2 are LOW.
2. WX is a 40-bit word. LSB = Byte 0-Byte 1, MSB = Byte 2-Byte 3.
54
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
REN0
EF
RCLK0
tA
6157 drw23
12 3
Q[39:0](3) Word D-1 Queue 1
OS[1:0] 01 = Queue 1 11 = Queue 3
Word D Queue 1
tENS
tA
Next Word Queue 3
tREF
CEF
tREF tREF
No Read
tDS
Figure 26. Composite Empty Flag (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out
NOTES:
1. RCS0 and OE0 are LOW.
2. EF3 is HIGH.
3. Word D-1 is the second and last word in Queue 1. Word D is the last word in Queue 1.
REN0
OR1
RCLK0
tA
6157 drw24
12 3
Q[39:0]
(3)
Word
D-1
Queue 1
OS[1:0] 01 = Queue 1 11 = Queue 3
Word D Queue 1
tENS
tENS
tA
Next Word Queue 3
tREF
COR
tREFtREF
Figure 27. Composite Output Ready Flag (Mux mode, FWFT mode, SDR to SDR) x10 In to x40 Out
NOTES:
1. RCS0 and OE0 are LOW.
2. OR3 is LOW.
3. Word D-1 is the second and last word in Queue 1. Word D is the last word in Queue 1.
55
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WEN0
WCLK0
6157 drw25
CFF
tWFF
tWFF
12 3
IS[1:0] 01 = Queue 1 11 = Queue 3
tENS
No Write
D[19:0] Word D Queue 1
tDS tDH
tDH
Word D Queue 3 Word D+1 Queue 3
FF
tWFF
tDS tDH tDS
Figure 28. Composite Full Flag (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out
NOTES:
1. WCS0 is LOW.
2. FF3 is HIGH.
WEN0
WCLK0
6157 drw26
CIR
t
WFF
12 3
IS[1:0]
t
ENS
No Write
D[19:10]
(3)
t
DH
IR1
t
WFF
Word D+1 Queue 1
t
DS
t
DH
Word D Queue 3 Word D+1 Queue 3
01 = Queue 1 11 = Queue 3
t
DS
t
DH
t
DS
t
WFF
Figure 29. Composite Input Ready Flag (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out
NOTES:
1. WCS0 is LOW.
2. IR3 is LOW.
3. Word D is the first word written and fell through to output (FWFT).
56
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 30. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, DDR to DDR) x10 In to x10 Out
NOTES:
1. The EREN0 output is “or gated” to RCS0 and REN0 and will follow these inputs provided that the Queue is not empty. If the Queue is empty, EREN0 will go HIGH to indicate that there is no new word available.
2. The EREN0 output is synchronous to RCLK0.
3. OE0 = LOW, WDDR = HIGH, and RDDR = HIGH.
4. Q[39:10] = 0.
5. The truth table for EREN is shown below:
RCLK0
REN0
EREN0
ERCLK0
EF0
RCS0
tENS
tREF
tERCLK
tENH
Q[9:0]
tENS
tENH
tCLKEN tCLKEN tCLKEN tCLKEN
tOLZ tA
tA
tCLKEN
tAtOLZ
tOLZ tA
tAtAtA
tA
WD-10 WD-9 WD-8 WD-6 WD-5 WD-4 WD-3 WD-2 Last Word W
D
6157 drw27
tCLKEN
tA
WD-7 WD-6
tA
WD-1
tENS
NO Read NO Read
RCLK EF RCS REN EREN
↑1000
↑1011
↑1101
↑1111
↑0XX1
57
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 31. Echo RCLK and Echo Read Enable Operation (Mux/Demux/Broadcast mode, FWFT mode, SDR to SDR)
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS0 and OE0 are both active, LOW, that is the bus is not in
High-Impedance state.
2. OE0 is LOW.
3. Q[39:10] = 0.
Cycle:
a&b. At this point the Queue is empty, OR0 is HIGH.
RCS0 and REN0 are both disabled, the output bus is High-Impedance.
c. Word Wn+1 falls through to the output register, OR0 goes active, LOW.
RCS0 is HIGH, therefore the Qn outputs are High-Impedance. EREN0 goes LOW to indicate that a new word has been placed into the output register.
d. EREN0 goes HIGH, no new word has been placed on the output register into this cycle.
e. No Operation.
f. RCS0 is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode it is important to take RCS0 active LOW at least one cycle ahead of REN0, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle, otherwise Wn+1 will overwritten by Wn+2.
g. REN0 goes active LOW, this reads out the second word, Wn+2.
EREN0 goes active LOW to indicate a new word has been placed into the output register.
h. Word Wn+3 is read out, EREN0 remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the Queue.
i. This is the next enabled read after the last word, Wn+3 has been read out. OR0 flag goes HIGH and EREN0 goes HIGH to indicate that there is no new word available.
4. OE0 is LOW, WDDR = LOW, and RDDR = LOW.
5. The truth table for EREN is shown below:
Q[9:0]
O/P
(1)
Reg.
t
A
t
REF
OR0
6157 drw28
t
RCSLZ
REN0
t
ENS
t
ENH
RCS0
t
ENS
RCLK0
abcdefghi
W
n+1
WCLK0
WEN0
D[9:0]
t
SKEW1
t
ENS
t
DS
t
ENH
W
n+2
W
n+3
ERCLK0
EREN0
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
W
n+1
W
n+2
W
n+3
t
A
t
REF
W
n+1
W
n+2
W
n+3
W
n
Last Word
t
DH
t
DH
t
DH
t
DS
t
DS
12
t
ERCLK
HIGH-Z
t
ENH
RCLK OR RCS REN EREN
↑0000
↑0011
↑0101
↑0111
↑1XX1
58
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
6157 drw29
RCLK0
REN0
t
ERCLK
ERCLK0
RCS0
t
ENS
EREN0
t
CLKEN
t
CLKEN
t
CLKEN
EF0
t
REF
Q[9:0]
t
OLZ
t
A
t
A
t
A
t
A
t
A
W
D-1
W
D Last Word
W
D-2
W
D-3
W
D-4
Figure 32. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out
NOTES:
1. The EREN0 output is “or gated” to RCS0 and REN0 and will follow these inputs provided that the Queue is not empty. If the Queue is empty, EREN0 will go HIGH to indicate that
there is no new word available.
2. The EREN0 output is synchronous to RCLK0.
3. OE0 = LOW, WDDR = HIGH, and RDDR = HIGH.
4. Q[39:10] = 0.
5. The truth table for EREN is shown below:
RCLK EF RCS REN EREN
↑1000
↑1011
↑1101
↑1111
↑0XX1
59
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 33. Loading of Programmable Flag Registers (IDT Standard and FWFT modes)
t
SENH
t
SDH
SCLK
SWEN
FWFT/SI
6157 drw30
EMPTY OFFSET 3 FULL OFFSET 3
t
SENS
t
SDS
BIT
X
(1)
8
BIT 1
t
SCL
K
t
SCKH
t
SCKL
BIT 1
(LSB)
EMPTY OFFSET 0 FULL OFFSET 0
BIT 1
BIT 1
(LSB)
BIT
X
(1)
8
BIT
X
(1)
8
BIT
X
(1)
8
(MSB)(MSB)
Figure 34. Reading of Programmable Flag Registers (IDT Standard and FWFT modes)
SCLK
SREN
SDO
6157 drw31
EMPTY OFFSET 3 FULL OFFSET 3
t
SENS
t
SOA
t
SEN
H
BIT X
(1)
t
SENH
t
SCLK
t
SCKH
t
SCKL
BIT 0 BIT 0 BIT X
(1)
BIT X
(1)
t
SOA
BIT 0
EMPTY OFFSET 0 FULL OFFSET 0
BIT 0
(LSB)
BIT X
(1)
(MSB) (LSB) (MSB)
NOTE:
1 . If IW/OW = x40, X = 104 for the IDT72T55248, X = 112 for the IDT72T55258, X = 120 for the IDT72T55268.
If IW/OW = x20, X = 112 for the IDT72T55248, X = 120 for the IDT72T55258, X = 128 for the IDT72T55268.
If IW/OW = x10, X = 120 for the IDT72T55248, X = 128 for the IDT72T55258, X = 136 for the IDT72T55268.
NOTE:
1 . If IW/OW = x40, X = 104 for the IDT72T55248, X = 112 for the IDT72T55258, X = 120 for the IDT72T55268.
If IW/OW = x20, X = 112 for the IDT72T55248, X = 120 for the IDT72T55258, X = 128 for the IDT72T55268.
If IW/OW = x10, X = 120 for the IDT72T55248, X = 128 for the IDT72T55258, X = 136 for the IDT72T55268.
60
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
WEN0
PAF0
RCLK0
REN0
6157 drw32
1212
D - m0 words in Queue(1)
D - (m0 +1) words in Queue(1)
t
ENH
t
ENS
t
PAFS
t
ENS
t
ENH
t
CLKL
t
SKEW2
(3)
t
PAFS
t
CLKL
WCLK0
WEN0
PAE0
RCLK0
12 12
REN06157 drw33
n0 words in Queue
t
ENS
t
SKEW2(4)
t
ENH
t
PAES
n0 + 1 words in Queue
(2)
,
n0 + 2 words in Queue
(3)
t
ENS
t
ENH
t
CLKH
t
CLKL
NOTES:
1. m0 = PAF0 offset .
2. D = maximum Queue depth. For density of Queue with bus-matching, refer to the bus-matching section on page 19.
3. tSKEW2 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that PAF0 will go HIGH (after one WCLK0 cycle plus tPAFS). If the time
between the rising edge of RCLK0 and the rising edge of WCLK0 is less than tSKEW2, then the PAF0 deassertion time may be delayed one extra WCLK0 cycle.
4. PAF0 is asserted and updated on the rising edge of WCLK0 only.
5. Select this mode by setting PFM HIGH during Master Reset.
6. RCS0 = LOW, WCS0 = LOW, WDDR = LOW, and RDDR = LOW.
Figure 35. Synchronous Programmable Almost-Full Flag Timing
(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out
NOTES:
1. The timing diagram shown is for Queue0. Queues1-3 exhibit the same behavior.
2 . n0 = PAE0 offset.
3. For IDT Standard mode
4. For FWFT mode.
5.
tSKEW2 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE
0
will go HIGH (after one RCLK0 cycle plus tPAES). If the time between
the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW2, then the PAE
0
deassertion may be delayed one extra RCLK0 cycle.
6. PAE0 is asserted and updated on the rising edge of WCLK0 only.
7. Select this mode by setting PFM HIGH during Master Reset.
8. RCS0 = LOW, WCS0 = LOW, WDDR = LOW, and RDDR = LOW.
Figure 36. Synchronous Programmable Almost-Empty Flag Timing
(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out
61
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK0
WEN0
PAF0D - (m0 + 1) words
in Queue
RCLK0
tPAFA
REN0
6157 drw34
D - m0 words
in Queue
D - (m0 + 1) words in Queue
tENS
tPAFA
tENH
tENS
tCLKLtCLKH
WCLK0
WEN0
PAE0
n0 words in Queue
(2)
,
n0 + 1 words in Queue
(3)
RCLK0
REN0
6157 drw35
t
PAEA
n0 + 1 words in Queue
(2)
,
n 0+ 2 words in Queue
(3)
t
PAEA
t
ENS
t
ENS
t
ENH
t
CLKL
t
CLKH
n0 words in Queue
(2)
,
n0 + 1 words in Queue
(3)
NOTES:
1. m0 = PAF0 offset.
2. D = maximum Queue depth. For density of Queue with bus-matching, refer to the bus-matching section on page 19.
3. PAF0 is asserted to LOW on WCLK0 transition and reset to HIGH on RCLK0 transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS0 is LOW, WCS0 is LOW, WDDR = LOW, and RDDR = LOW.
Figure 37. Asynchronous Programmable Almost-Full Flag Timing
(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out
NOTES:
1 . n0 = PAE0 offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE0 is asserted LOW on RCLK0 transition and reset to HIGH on WCLK0 transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS0 is LOW, WCS0 is LOW, WDDR = LOW, and RDDR = LOW.
Figure 38. Asynchronous Programmable Almost-Empty Flag Timing
(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out
62
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 39. Power Down Operation
6157 drw36
WCLK
WEN
D[39:0]
t
DS
t
DH
t
DH
W
D10
W
D11
t
DS
t
DH
t
DS
W
D13
RCLK
REN
t
A
t
A
t
A
t
ERCLK
t
PDHZ
(7)
t
PDLZ
(2)
t
PDL
t
PDH
(2)
t
PDH
(2)
W
DH
(8)
Hi-Z
Hi-Z
W
D4
W
D3
W
D2
W
D1
Hi-Z
t
EREN
Q[39:0]
PD
ERCLK
EREN
1234
(1)
t
DS
1µs
t
A
t
EREN
W
DS
W
D12
NOTES:
1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
All input and output signals will also resume after this time period.
3. Set-up and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
63
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1533
Santa Clara, CA 95054 fax: 408-492-8674 email: Flow-Controlhelp@idt.com
www.idt.com
Plastic Ball Grid Array (PBGA, BB324-1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Low Power
6157 drwlast
Commercial and Industrial
Commercial and Industrial
IDT XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
I(1)
72T55248 8,192 x 40 x 4 2.5V QuadMux DDR Flow-Control Device
72T55258 16,384 x 40 x 4 2.5V QuadMux DDR Flow-Control Device
72T55268 32,768 x 40 x 4 2.5V QuadMux DDR Flow-Control Device
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
BB
5
6-7
L
ORDERING INFORMATION
