ADS8320EB/2K5G4 - Texas Instruments

ADS8320

DESCRIPTION

The ADS8320 is a 16-bit, sampling analog-to-digital (A/D)

converter with ensured specifications over a 2.7V to 5.25V

supply range. It requires very little power even when operat-

ing at the full 100kHz data rate. At lower data rates, the high

speed of the device enables it to spend most of its time in the

power-down mode—the average power dissipation is less

than 100mW at 10kHz data rate.

The ADS8320 also features operation from 2.0V to 5.25V, a

synchronous serial (SPI/SSI compatible) interface, and a

differential input. The reference voltage can be set to any

level within the range of 500mV to VCC.

Ultra-low power and small size make the ADS8320 ideal

for portable and battery-operated systems. It is also a

perfect fit for remote data acquisition modules, simulta-

neous multi-channel systems, and isolated data acquisi-

tion. The ADS8320 is available in an MSOP-8 package.

16-Bit, High-Speed, 2.7V to 5V

micro

Power Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●100kHz SAMPLING RATE

●

micro

POWER:

1.8mW at 100kHz and 2.7V

0.3mW at 10kHz and 2.7V

●POWER-DOWN: 3µA max

●MSOP-8 PACKAGE

●PIN-COMPATIBLE TO ADS7816 AND ADS7822

●SERIAL (SPI™/SSI) INTERFACE

SAR Control

Serial

Interface

DOUT

Comparator

S/H Amp CS/SHDN

DCLOCK

+In

VREF

–In CDAC

APPLICATIONS

●BATTERY-OPERATED SYSTEMS

●REMOTE DATA ACQUISITION

●ISOLATED DATA ACQUISITION

●SIMULTANEOUS SAMPLING,

MULTICHANNEL SYSTEMS

●INDUSTRIAL CONTROLS

●ROBOTICS

●VIBRATION ANALYSIS

SBAS108D – MAY 2000 – REVISED MARCH 2007

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.

ADS8320

2SBAS108D

www.ti.com

SPECIFICATIONS: +VCC = +5V

At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified.

ADS8320E ADS8320EB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 16 ✻Bits

ANALOG INPUT

Full-Scale Input Span +In – (–In) 0 VREF ✻✻V

Absolute Input Range +In –0.1

VCC + 0.1

✻✻V

–In –0.1 +1.0 ✻✻V

Capacitance 45 ✻pF

Leakage Current 1✻nA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits

Integral Linearity Error ±0.008 ±0.018 ±0.006 ±0.012

% of FSR

Offset Error ±1±2±0.5 ±1mV

Offset Temperature Drift ±3✻µV/°C

Gain Error ±0.05 ±0.024 %

Gain Temperature Drift ±0.3 ✻ppm/°C

Noise 20 ✻µVrms

Power-Supply Rejection Ratio +4.7V < VCC < 5.25V 3 ✻LSB(1)

SAMPLING DYNAMICS

Conversion Time 16 ✻

Clk Cycles

Acquisition Time 4.5 ✻

Clk Cycles

Throughput Rate 100 ✻kHz

Clock Frequency Range 0.024 2.4 ✻✻MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion VIN = 5VPP at 10kHz –84 –86 dB

SINAD VIN = 5VPP at 10kHz 82 84 dB

Spurious-Free Dynamic Range VIN = 5VPP at 10kHz 84 86 dB

SNR 90 92 dB

REFERENCE INPUT

Voltage Range 0.5 VCC ✻✻V

Resistance

CS = GND, fSAMPLE = 0Hz

5✻GΩ

CS = VCC 5✻GΩ

Current Drain 40 80 ✻✻µA

fSAMPLE = 10kHz 0.8 ✻µA

CS = VCC 0.1

✻µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻

Logic Levels:

VIH IIH = +5µA 3.0

VCC + 0.3

✻✻V

VIL IIL = +5µA–0.3 0.8 ✻✻V

VOH IOH = –250µA 4.0 ✻V

VOL IOL = 250µA 0.4 ✻V

Data Format Straight Binary ✻

POWER-SUPPLY REQUIREMENTS

VCC Specified Performance 4.75 5.25 ✻✻V

VCC Range(2) 2.0 5.25 ✻✻V

Quiescent Current 900 1700 ✻✻µA

fSAMPLE = 10kHz(3, 4) 200 ✻µA

Power Dissipation 4.5 8.5 ✻✻mW

Power-Down CS = VCC 0.3 3 ✻✻µA

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Specifications same as ADS8320E.

NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 0.076mV.

(2) See

Typical Performance Curves

for more information.

(3) fCLK = 2.4MHz, CS = VCC for 216 clock cycles out of every 240.

(4) See the Power Dissipation section for more information regarding lower sample rates.

ADS8320 3

SBAS108D www.ti.com

SPECIFICATIONS: +VCC = +2.7V

At –40°C to +85°C, VREF = 2.5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified.

ADS8320E ADS8320EB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 16 ✻Bits

ANALOG INPUT

Full-Scale Input Span +In – (–In) 0 VREF ✻✻V

Absolute Input Range +In –0.1

VCC + 0.1

✻✻V

–In –0.1 +0.5 ✻✻V

Capacitance 45 ✻pF

Leakage Current 1✻nA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits

Integral Linearity Error ±0.008 ±0.018 ±0.006 ±0.012

% of FSR

Offset Error ±1±2±0.5 ±1mV

Offset Temperature Drift ±3✻µV/°C

Gain Error ±0.05 ±0.024 % of FSR

Gain Temperature Drift ±0.3 ✻ppm/°C

Noise 20 ✻µVrms

Power-Supply Rejection Ratio +2.7V < VCC < +3.3V 3 ✻LSB(1)

SAMPLING DYNAMICS

Conversion Time 16 ✻

Clk Cycles

Acquisition Time 4.5 ✻

Clk Cycles

Throughput Rate 100 ✻kHz

Clock Frequency Range 0.024 2.4 ✻✻MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion VIN = 2.7Vp-p at 1kHz –86 –88 dB

SINAD VIN = 2.7Vp-p at 1kHz 84 86 dB

Spurious-Free Dynamic Range VIN = 2.7Vp-p at 1kHz 86 88 dB

SNR 88 90 dB

REFERENCE INPUT

Voltage Range 0.5 VCC ✻✻V

Resistance

CS = GND, fSAMPLE = 0Hz

5✻GΩ

CS = VCC 5✻GΩ

Current Drain 20 50 ✻✻µA

CS = VCC 0.1

✻✻µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻

Logic Levels:

VIH IIH = +5µA 2.0

VCC + 0.3

✻✻V

VIL IIL = +5µA–0.3 0.8 ✻✻V

VOH IOH = –250µA 2.1 ✻V

VOL IOL = 250µA 0.4 ✻V

Data Format Straight Binary ✻

POWER-SUPPLY REQUIREMENTS

VCC Specified Performance 2.7 3.3 ✻✻V

VCC Range(3) 2.0 5.25 ✻✻V

See Note 2 2.0 2.7 ✻✻V

Quiescent Current 650 1300 ✻✻µA

fSAMPLE = 10kHz(4,5) 100 ✻µA

Power Dissipation 1.8 3.8 ✻✻mW

Power-Down CS = VCC 0.3 3 ✻✻µA

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Specifications same as ADS8320E.

NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 0.038mV.

(2) The maximum clock rate of the ADS8320 is less than 2.4MHz in this power supply range.

(3) See the

Typical Performance Curves

for more information.

(4) fCLK = 2.4MHz, CS = VCC for 216 clock cycles out of every 240.

(5) See the Power Dissipation section for more information regarding lower sample rates.

ADS8320

4SBAS108D

www.ti.com

ELECTROSTATIC

DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from

performance degradation to complete device failure. Texas

Instruments recommends that all integrated circuits be handled

and stored using appropriate ESD protection methods.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

ABSOLUTE MAXIMUM RATINGS(1)

VCC ....................................................................................................... +6V

Analog Input..............................................................–0.3V to (VCC + 0.3V)

Logic Input ...............................................................................–0.3V to 6V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +125°C

External Reference Voltage .............................................................. +5.5V

Input current to any pin except supply ............................................ ±10mA

NOTE: (1) Stresses above these ratings may permanently damage the device.

PIN NAME DESCRIPTION

REF Reference Input.

2 +In Noninverting Input.

3–In Inverting Input. Connect to ground or to remote

ground sense point.

4 GND Ground.

5 CS/SHDN Chip Select when LOW, Shutdown Mode when

HIGH.

OUT The serial output data word is comprised of 16

bits of data. In operation the data is valid on the

falling edge of DCLOCK. The

second clock pulse after the falling edge of CS

enables the serial output. After one null bit the

data is valid for the next 16 edges.

7 DCLOCK Data Clock synchronizes the serial data transfer

and determines conversion speed.

8+V

CC Power Supply.

PIN ASSIGNMENTS

PIN CONFIGURATION

Top View MSOP

DCLOCK

OUT

CS/SHDN

REF

+In

–In

GND

ADS8320

PACKAGE/ORDERING INFORMATION(1)

MAXIMUM NO

INTEGRAL MISSING

LINEARITY CODE SPECIFICATION

ERROR ERROR PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT (%) (LSB) PACKAGE DESIGNATOR RANGE MARKING(2) NUMBER(3) MEDIA

ADS8320E 0.018 14 MSOP-8 DGK –40°C to +85°C A20 ADS8320E/250 Tape and Reel

ADS8320E "" " " " "ADS8320E/2K5 Tape and Reel

ADS8320EB 0.012 15 MSOP-8 DGK –40°C to +85°C A20 ADS8320EB/250 Tape and Reel

ADS8320EB "" " " " "ADS8320EB/2K5 Tape and Reel

NOTES: (1) For the most current product and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website

at www.ti.com.

(2) Performance Grade information is marked on the reel.

(3) Models with a slash(/) are available only in tape and reel in quantities indicated (for example, /250 indicates 250 units per reel, /2K5 indicates

2500 devices per reel). Ordering 2500 pieces of ”ADS8320E/2K5“ will get a single 2500-piece tape and reel.

ADS8320 5

SBAS108D www.ti.com

TYPICAL PERFORMANCE CURVES

At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified.

INTEGRAL LINEARITY ERROR vs CODE (+25°C)

2 0

1.0

0.0

–1.0

–2.0

–3.0

–4.0

–5.0

–6.0

Integral Linearity Error (LSB)

0000H8000HC000H

4000HFFFFH

Hex Code

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

3.0

2.0

1.0

0.0

–1.0

–2.0

–3.0

Differential Linearity Error (LSB)

0000H8000HC000H

4000HFFFFH

Hex Code

SUPPLY CURRENT vs TEMPERATURE

1200

1000

800

600

400

200

Supply Current (µA)

–50 –25 0 25 50 75 100

Temperature (°C)

2.7V

POWER-DOWN SUPPLY CURRENT

vs TEMPERATURE

600

500

400

300

200

100

Supply Current (nA)

–50 –25 0 25 50 75 100

Temperature (°C)

QUIESCENT CURRENT vs V

1200

1000

800

600

400

200

Quiescent Current (µA)

12345

(V)

MAXIMUM SAMPLE RATE vs VCC

1000

100

Sample Rate (kHz)

12345

VCC (V)

ADS8320

6SBAS108D

www.ti.com

TYPICAL PERFORMANCE CURVES (Cont.)

At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified.

CHANGE IN OFFSET vs REFERENCE VOLTAGE

–1

–2

–3

Change in Offset (LSB)

12345

Reference Voltage (V)

= 5V

CHANGE IN OFFSET vs TEMPERATURE

−1

−2

−3

Delta from +25 C (LSB)

−50 −250 255075100

Temperature (°C)

2.7V

CHANGE IN GAIN vs REFERENCE VOLTAGE

–1

–2

Change in Gain (LSB)

12345

Reference Voltage (V)

VCC = 5V

FREQUENCY SPECTRUM

(8192 Point FFT, FIN = 10.120kHz, –0.3dB)

–20

–40

–60

–80

–100

–120

–140

Amplitude (dB)

0 102030 4050

Frequency (kHz)

PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE

Peak-to-Peak Noise (LSB)

0.1 1 10

Reference Voltage (V)

VCC = 5V

CHANGE IN GAIN vs TEMPERATURE

–2

–4

–6

Delta from 25°C (LSB)

–50 –25 0 25 50 75 100

Temperature (°C)

2.7V

ADS8320 7

SBAS108D www.ti.com

TYPICAL PERFORMANCE CURVES (Cont.)

At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified.

TOTAL HARMONIC DISTORTION vs FREQUENCY

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Total Harmonic Distortion (dB)

1 10 100

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY

100

Signal-to-(Noise + Distortion) (dB)

1 10 50 100

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL

Signal-to-(Noise + Distortion) (dB)

–40 –35 –30 –25 –20 –15 –10 –50

Input Level (dB)

REFERENCE CURRENT vs SAMPLE RATE

Reference Current (µA)

0 20 40 60 80 100

Sample Rate (kHz)

2.7V

REFERENCE CURRENT vs TEMPERATURE

Reference Current (µA)

–50 –25 0 25 50 75 100

Temperature (°C)

2.7V

SPURIOUS-FREE DYNAMIC RANGE AND

SIGNAL-TO-NOISE RATIO vs FREQUENCY

100

Spurious-Free Dynamic Range

and Signal-to-Noise Ratio (dB)

1 10 10050

Frequency (kHz)

Signal-to-Noise Ratio

Spurious-Free Dynamic Range

ADS8320

8SBAS108D

www.ti.com

THEORY OF OPERATION

The ADS8320 is a classic successive approximation register

(SAR) analog-to-digital (A/D) converter. The architecture is

based on capacitive redistribution, which inherently includes

a sample/hold function. The converter is fabricated on a 0.6µ

CMOS process. The architecture and process allow the

ADS8320 to acquire and convert an analog signal at up to

100,000 conversions per second while consuming less than

4.5mW from +VCC.

The ADS8320 requires an external reference, an external

clock, and a single power source (VCC). The external refer-

ence can be any voltage between 500mV and VCC. The value

of the reference voltage directly sets the range of the analog

input. The reference input current depends on the conversion

rate of the ADS8320.

The external clock can vary between 24kHz (1kHz through-

put) and 2.4MHz (100kHz throughput). The duty cycle of

the clock is essentially unimportant, as long as the minimum

high and low times are at least 200ns (VCC = 2.7V or

greater). The minimum clock frequency is set by the leakage

on the capacitors internal to the ADS8320.

The analog input is provided to two input pins: +In and –In.

When a conversion is initiated, the differential input on these

pins is sampled on the internal capacitor array. While a

conversion is in progress, both inputs are disconnected from

any internal function.

The digital result of the conversion is clocked out by the

DCLOCK input and is provided serially, most significant bit

first, on the DOUT pin. The digital data that is provided on the

DOUT pin is for the conversion currently in progress—there

is no pipeline delay. It is possible to continue to clock the

ADS8320 after the conversion is complete and to obtain the

serial data least significant bit first. See the digital timing

section for more information.

ANALOG INPUT

The +In and –In input pins allow for a differential input

signal. Unlike some converters of this type, the –In input is

not re-sampled later in the conversion cycle. When the

converter goes into the hold mode, the voltage difference

between +In and –In is captured on the internal capacitor

array.

The range of the –In input is limited to –0.1V to +1V (–0.1V

to +0.5V when using a 2.7V supply). Because of this, the

differential input can be used to reject only small signals that

are common to both inputs. Thus, the –In input is best used

to sense a remote signal ground that may move slightly with

respect to the local ground potential.

The input current on the analog inputs depends on a number

of factors: sample rate, input voltage, source impedance, and

power-down mode. Essentially, the current into the ADS8320

charges the internal capacitor array during the sample pe-

riod. After this capacitance has been fully charged, there is

no further input current. The source of the analog input

voltage must be able to charge the input capacitance (45pF)

to a 16-bit settling level within 4.5 clock cycles. When the

converter goes into the hold mode or while it is in the power-

down mode, the input impedance is greater than 1GΩ.

Care must be taken regarding the absolute analog input

voltage. To maintain the linearity of the converter, the –In

input should not drop below GND – 100mV or exceed

GND + 1V. The +In input should always remain within the

range of GND – 100mV to VCC + 100mV. Outside of these

ranges, the converter linearity may not meet specifications.

To minimize noise, low bandwidth input signals with low-

pass filters should be used.

REFERENCE INPUT

The external reference sets the analog input range. The

ADS8320 operates with a reference in the range of 500mV

to VCC. There are several important implications of this.

As the reference voltage is reduced, the analog voltage

weight of each digital output code is reduced. This is often

referred to as the Least Significant Bit (LSB) size and is

equal to the reference voltage divided by 65,536. This means

that any offset or gain error inherent in the A/D converter

will appear to increase, in terms of LSB size, as the reference

voltage is reduced.

The noise inherent in the converter also appears to increase

with lower LSB size. With a +5V reference, the internal

noise of the converter typically contributes only 1.5 LSB

peak-to-peak of potential error to the output code. When the

external reference is 500mV, the potential error contribution

from the internal noise will be 10 times larger—15 LSBs.

The errors due to the internal noise are gaussian in nature

and can be reduced by averaging consecutive conversion

results.

For more information regarding noise, consult the typical

performance curve “Peak-to-Peak Noise vs Reference Volt-

age.” Note that the Effective Number of Bits (ENOB) figure

is calculated based on the converter’s signal-to-(noise +

distortion) ratio with a 1kHz, 0dB input signal. SINAD is

related to ENOB as follows:

SINAD = 6.02 • ENOB + 1.76

With lower reference voltages, extra care should be taken to

provide a clean layout including adequate bypassing, a clean

power supply, a low-noise reference, and a low-noise input

signal. Because the LSB size is lower, the converter is also

more sensitive to external sources of error such as nearby

digital signals and electromagnetic interference.

ADS8320 9

SBAS108D www.ti.com

NOISE

The noise floor of the ADS8320 itself is extremely low, as

can be seen from Figures 1 and 2, and is much lower than

competing A/D converters. It was tested by applying a low-

noise DC input and a 5.0V reference to the ADS8320 and

initiating 5000 conversions. The digital output of the A/D

2510

2490

Code

0000

FIGURE 1. Histogram of 5000 Conversions of a DC Input

at the Code Transition.

FIGURE 2. Histogram of 5000 Conversions of a DC Input

at the Code Center.

4864

Code

64 000

converter varies in output code due to the internal noise of

the ADS8320. This is true for all 16-bit SAR-type A/D

converters. Using a histogram to plot the output codes, the

distribution should appear bell-shaped with the peak of the

bell curve representing the nominal code for the input value.

The ±1σ, ±2σ, and ±3σ distributions represents the 68.3%,

95.5%, and 99.7%, respectively, of all codes. The transition

noise can be calculated by dividing the number of codes

measured by 6 and this yields the ±3σ distribution or 99.7%

of all codes. Statistically, up to 3 codes could fall outside the

distribution when executing 1000 conversions. The

ADS8320, with < 3 output codes for the ±3σ distribution,

yields a < ±0.5LSB transition noise. Remember, to achieve

this low noise performance, the peak-to-peak noise of the

input signal and reference must be < 50µV.

AVERAGING

The noise of the A/D converter can be compensated by

averaging the digital codes. By averaging conversion re-

sults, transition noise is reduced by a factor of 1/√n, where

n is the number of averages. For example, averaging four

conversion results reduces the transition noise by 1/2 to

±0.25 LSBs. Averaging should only be used for input

signals with frequencies near DC.

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging; for every decimation by 2, the signal-

to-noise ratio improves 3dB.

DIGITAL INTERFACE

SIGNAL LEVELS

The digital inputs of the ADS8320 can accommodate logic

levels up to 5.5V regardless of the value of VCC. Thus, the

ADS8320 can be powered at 3V and still accept inputs from

logic powered at 5V.

The CMOS digital output (DOUT) swings 0V to VCC. If VCC

is 3V and this output is connected to a 5V CMOS logic

input, then that IC may require more supply current than

normal and may have a slightly longer propagation delay.

ADS8320

10 SBAS108D

www.ti.com

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tSMPL Analog Input Sample Time 4.5 5.0

Clk Cycles

tCONV Conversion Time 16

Clk Cycles

tCYC Throughput Rate 100 kHz

tCSD CS Falling to 0 ns

DCLOCK LOW

tSUCS CS Falling to 20 ns

DCLOCK Rising

thDO DCLOCK Falling to 5 15 ns

Current DOUT Not Valid

tdDO DCLOCK Falling to Next 30 50 ns

DOUT Valid

tdis CS Rising to DOUT Tri-State 70 100 ns

ten DCLOCK Falling to DOUT 20 50 ns

Enabled

tfDOUT Fall Time 5 25 ns

trDOUT Rise Time 7 25 ns

FIGURE 3. ADS8320 Basic Timing Diagrams.

TABLE I. Timing Specifications (VCC = 2.7V and above,

–40°C to +85°C.

DESCRIPTION ANALOG VALUE

Full-Scale Range VREF

Least Significant VREF/65,536

Bit (LSB) BINARY CODE HEX CODE

Full-Scale VREF – 1 LSB 1111 1111 1111 1111 FFFF

Midscale VREF/2 1000 0000 0000 0000 8000

Midscale – 1LSB VREF/2 – 1 LSB 0111 1111 1111 1111 7FFF

Zero 0V 0000 0000 0000 0000 0000

DIGITAL OUTPUT

STRAIGHT BINARY

TABLE II. Ideal Input Voltages and Output Codes.

SERIAL INTERFACE

The ADS8320 communicates with microprocessors and other

digital systems via a synchronous 3-wire serial interface, as

shown in Figure 3 and Table I. The DCLOCK signal syn-

chronizes the data transfer with each bit being transmitted on

the falling edge of DCLOCK. Most receiving systems will

capture the bitstream on the rising edge of DCLOCK. How-

ever, if the minimum hold time for DOUT is acceptable, the

system can use the falling edge of DCLOCK to capture each

bit.

A falling CS signal initiates the conversion and data transfer.

The first 4.5 to 5.0 clock periods of the conversion cycle are

used to sample the input signal. After the fifth falling

DCLOCK edge, DOUT is enabled and outputs a LOW value

for one clock period. For the next 16 DCLOCK periods,

DOUT outputs the conversion result, most significant bit first.

After the least significant bit (B0) has been output, subse-

quent clocks repeat the output data but in a least significant

bit first format.

After the most significant bit (B15) has been repeated, DOUT

will tri-state. Subsequent clocks will have no effect on the

converter. A new conversion is initiated only when CS has

been taken HIGH and returned LOW.

DATA FORMAT

The output data from the ADS8320 is in Straight Binary

format, as shown in Table II. This table represents the ideal

output code for the given input voltage and does not include

the effects of offset, gain error, or noise.

POWER DISSIPATION

The architecture of the converter, the semiconductor fabrica-

tion process, and a careful design allow the ADS8320 to

convert at up to a 100kHz rate while requiring very little

power. Still, for the absolute lowest power dissipation, there

are several things to keep in mind.

The power dissipation of the ADS8320 scales directly with

conversion rate. Therefore, the first step to achieving the

lowest power dissipation is to find the lowest conversion

rate that satisfies the requirements of the system.

In addition, the ADS8320 is in power-down mode under two

conditions: when the conversion is complete and whenever

CS is HIGH (as shown in Figure 3). Ideally, each conversion

should occur as quickly as possible, preferably at a 2.4MHz

clock rate. This way, the converter spends the longest

possible time in the power-down mode. This is very impor-

tant as the converter not only uses power on each DCLOCK

transition (as is typical for digital CMOS components), but

also uses some current for the analog circuitry, such as the

comparator. The analog section dissipates power continu-

ously, until the power-down mode is entered.

CS/SHDN

DOUT

DCLOCK

Complete Cycle

Power Down

ConversionSample

Use positive clock edge for data transfer

tSUCS

tCONV

tSMPL

NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.

If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.

B15

(MSB)B14 B13 B12 B11 B10 B9 B8 B0

(LSB)

B7 B1B6 B2B5 B3B4

Hi-Z 0Hi-Z

tCSD

ADS8320 11

SBAS108D www.ti.com

FIGURE 4. Timing Diagrams and Test Circuits for the Parameters in Table I.

OUT

1.4V

Test Point

3kΩ

100pF

LOAD

Load Circuit for t

dDO

, t

, and t

Voltage Waveforms for D

OUT

Rise and Fall Times, t

, t

Voltage Waveforms for D

OUT

Delay Times, t

dDO

Voltage Waveforms for t

dis

NOTES: (1) Waveform 1 is for an output with internal conditions such that the output

is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with

internal conditions such that the output is LOW unless disabled by the output control.

Voltage Waveforms for t

Load Circuit for t

dis

and t

OUT

Test Point

dis

Waveform 2, t

dis

Waveform 1

100pF

LOAD

3kΩ

dis

CS/SHDN

OUT

Waveform 1

(1)

OUT

Waveform 2

(2)

90%

10%

B11

CS/SHDN

DCLOCK

OUT

dDO

OUT

DCLOCK

hDO

ADS8320

12 SBAS108D

www.ti.com

Figure 5 shows the current consumption of the ADS8320

versus sample rate. For this graph, the converter is clocked

at 2.4MHz regardless of the sample rate—CS is HIGH for

the remaining sample period. Figure 6 also shows current

consumption versus sample rate. However, in this case, the

DCLOCK period is 1/24th of the sample period—CS is

HIGH for one DCLOCK cycle out of every 16.

There is an important distinction between the power-down

mode that is entered after a conversion is complete and the

full power-down mode which is enabled when CS is HIGH.

CS LOW will shut down only the analog section. The digital

section is completely shut down only when CS is HIGH.

Thus, if CS is left LOW at the end of a conversion and the

converter is continually clocked, the power consumption

will not be as low as when CS is HIGH. Figure 7 shows

more information.

Power dissipation can also be reduced by lowering the

power-supply voltage and the reference voltage. The

ADS8320 operates over a VCC range of 2.0V to 5.25V.

However, at voltages below 2.7V, the converter will not run

at a 100kHz sample rate. See the typical performance curves

for more information regarding power supply voltage and

maximum sample rate.

SHORT CYCLING

Another way of saving power is to utilize the CS signal to

short cycle the conversion. Because the ADS8320 places the

latest data bit on the DOUT line as it is generated, the

converter can easily be short cycled. This term means that

the conversion can be terminated at any time. For example,

if only 14 bits of the conversion result are needed, then the

conversion can be terminated (by pulling CS HIGH) after

the 14th bit has been clocked out.

This technique can be used to lower the power dissipation

(or to increase the conversion rate) in those applications

where an analog signal is being monitored until some con-

dition becomes true. For example, if the signal is outside a

predetermined range, the full 16-bit conversion result may

not be needed. If so, the conversion can be terminated after

the first n bits, where n might be as low as 3 or 4. This results

in lower power dissipation in both the converter and the rest

of the system, as they spend more time in the power-down

mode.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS8320 circuitry. This is particu-

larly true if the reference voltage is low and/or the conver-

sion rate is high. At a 100kHz conversion rate, the ADS8320

makes a bit decision every 416ns. That is, for each subse-

quent bit decision, the digital output must be updated with

the results of the last bit decision, the capacitor array

appropriately switched and charged, and the input to the

comparator settled to a 16-bit level all within one clock

cycle.

FIGURE 5. Maintaining fCLK at the Highest Possible Rate

Allows Supply Current to Drop Linearly with

Sample Rate.

FIGURE 6. Scaling fCLK Reduces Supply Current Only

Slightly with Sample Rate.

FIGURE 7. Shutdown Current with CS HIGH is 50nA

Typically, Regardless of the Clock. Shutdown

Current with CS LOW Varies with Sample

Rate.

1000

800

600

400

200

0.0

0.00

Supply Current (µA)

0.1 1 10 100

Sample Rate (kHz)

= 25°C

= 5.0V

REF

= 5.0V

CLK

= 24 • f

SAMPLE

CS LOW (GND)

CS HIGH (V

)

0.250

1000

100

Supply Current (µA)

0.1 1 10 100

Sample Rate (kHz)

= 25°C

= 5.0V

REF

= 5.0V

CLK

= 24 • f

SAMPLE

1000

100

Supply Current (µA)

0.1 1 10 100

Sample Rate (kHz)

VCC = 5.0V

VREF = 5.0V VCC = 2.7V

VREF = 2.5V

TA = 25°C

fCLK = 2.4MHz

ADS8320 13

SBAS108D www.ti.com

The basic SAR architecture is sensitive to spikes on the

power supply, reference, and ground connections that occur

just prior to latching the comparator output. Thus, during

any single conversion for an n-bit SAR converter, there are

n “windows” in which large external transient voltages can

easily affect the conversion result. Such spikes might origi-

nate from switching power supplies, digital logic, and high

power devices, to name a few. This particular source of error

can be very difficult to track down if the glitch is almost

synchronous to the converter DCLOCK signal—as the phase

difference between the two changes with time and tempera-

ture, causing sporadic misoperation.

With this in mind, power to the ADS8320 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the ADS8320 package as possible. In

addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series

resistor may be used to low-pass filter a noisy supply.

The reference should be similarly bypassed with a 0.1µF

capacitor. Again, a series resistor and large capacitor can be

used to low-pass filter the reference voltage. If the reference

voltage originates from an op amp, be careful that the op

amp can drive the bypass capacitor without oscillation (the

series resistor can help in this case). Keep in mind that while

the ADS8320 draws very little current from the reference on

average, there are still instantaneous current demands placed

on the external input and reference circuitry.

Texas Instruments' OPA627 op amp provides optimum

performance for buffering both the signal and reference

inputs. For low-cost, low-voltage, single-supply applica-

tions, the OPA2350 or OPA2340 dual op amps are recom-

mended.

Also, keep in mind that the ADS8320 offers no inherent

rejection of noise or voltage variation in regards to the

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise and

ripple from the supply will appear directly in the digital

results. While high-frequency noise can be filtered out as

described in the previous paragraph, voltage variation due to

the line frequency (50Hz or 60Hz), can be difficult to

remove.

The GND pin on the ADS8320 should be placed on a clean

ground point. In many cases, this will be the “analog”

ground. Avoid connecting the GND pin too close to the

grounding point for a microprocessor, microcontroller, or

digital signal processor. If needed, run a ground trace di-

rectly from the converter to the power-supply connection

point. The ideal layout includes an analog ground plane for

the converter and associated analog circuitry.

APPLICATION CIRCUITS

Figure 8 shows a basic data acquisition system. The ADS8320

input range is 0V to VCC, as the reference input is connected

directly to the power supply. The 5Ω resistor and 1µF to

10µF capacitor filter the microcontroller “noise” on the

supply, as well as any high-frequency noise from the supply

itself. The exact values should be picked such that the filter

provides adequate rejection of the noise.

FIGURE 8. Basic Data Acquisition System.

ADS8320

OUT

DCLOCK

REF

+In

–In

GND

5Ω

1µF to

10µF

1µF to

10µF

0.1µF

Microcontroller

+2.7V to +5.25V

ADS8320

14 SBAS108D

www.ti.com

DATE REVISION PAGE SECTION DESCRIPTION

4 Absolute Max Ratings Added last row,

Input current to any pin except supply...

10mA

6 Typ Performance Curves Changed

CHANGE IN OFFSET vs TEMPERATURE

plot

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

3/07

7/06

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS8320E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS