
Sample-and-Hold Amplifiers
SHM-4860
®
PHYSICAL/ENVIRONMENTAL
Operating T emperature Ranges
SHM-4860MC 0 to +70°C (ambient)
SHM-4860MM, 883 –55 to +125°C (case)
Storage T emperature Range –65 to +150°C
Package Type 24-pin ceramic DDIP
Footnotes:
➀
Input signal should not exceed the supply voltage.
➁
The SHM-4860’s output is current limited at approximately ±65mA. The device
can withstand a sustained short to ground. However, shor ts from the output to
either supply will cause permanent damage. For normal operation, the load
current should not exceed ±40mA.
➂
Full Scale (FS) = 10V. Full Scale Range (FSR) = 20V.
➃
Sample-to-Hold Offset Error (Pedestal) is constant regardless of input/output
level.
➄
Units are ppm of FSR/°C.
ABSOLUTE MAXIMUM RATINGS
±15V Supply Voltag es, Pins 24, 22 ±18V
+5V Supply Voltage, Pin 9 –0.5V to +7V
Analog Input, Pin 13
➀
±18V
Digital Inputs, Pins 11, 12 –0.5V to +7V
Output Current
➁
±65mA
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C with ±15V and +5V supplies unless otherwise noted.)
ANALOG INPUT/OUTPUT MIN. TYP. MAX. UNITS
Input/Output Voltage Range
➀
±10.25 ±11.25 — V
Input Impedance —1—k
Ω
Output Current
➁
— — ±40 mA
Output Impedance 0.1 — k
Ω
Maximum Capacitive Load — 250 — pF
DIGIT AL INPUT
Input Logic Level
Logic "1" +2.0 — +5.0 V
Logic "0" 0 — +0.8 V
Loading
Logic "1" — — +40 µA
Logic "0" — — –1.6 mA
TRANSFER CHARACTERISTICS
Gain — –1 — V/V
Gain Accuracy — ±0.05 ±0.1 %
Gain Linearity Error
➂
— ±0.005 ±0.01 %FS
Sample-Mode Offset Voltage — ±0.5 ±5 mV
Sample-to-Hold Offset Error
➃
(Pedestal) — ±2.5 ±20 mV
Gain T empco (Dr ift) — ±0.5 ±5 ppm/°C
Sample-Mode Offset Drift — ±3 ±15
➄
Sample-to-Hold Offset Drift —±4—
➄
DYNAMIC CHARACTERISTICS
Acquisition Time
10V to ±0.01%FS — 160 200 ns
10V to ±0.1%FS — 100 170 ns
10V to ±1%FS — 90 — ns
1V to ±1%FS — 75 — ns
Sample-to-Hold Settling Time
10V to ±0.01%FS — 60 100 ns
10V to ±0.1%FS — 40 — ns
Sample-to-Hold Transient — 180 — mV p-p
Aperture Delay Time —6—ns
Aperture Uncer tainty (Jitter) — ±50 — ps
Output Slew Rate — ±300 —
µ
V/
µ
s
Small Signal Bandwidth (–3dB) — 16 — MHz
Droop: +25°C — ±0.5 ±5
µ
V/
µ
s
+70°C — ±15 —
µ
V/
µ
s
+125°C — ±1.2 — mV/
µ
s
Feedthrough Attenuation —74—dB
Overload Recovery Time
Positive — 200 — ns
Negative — 700 — ns
POWER REQUIREMENTS
Voltag e Range: ±15V Supplies — ±3 — %
+5V Supply — ±5 — %
Power Supply Rejection Ratio — ±0.5 — mV/V
Quiescent Current Drain
+15V Supply — +21 +25 mA
–15V Supply — –22 –25 mA
+5V Supply — +17 +25 mA
Power Consumption — 730 875 mW
TECHNICAL NOTES
1. All ground pins (10, 15, 21, 23) should be tied together and
connected to system analog ground as close to the package
as possible. It is recommended to use a ground plane
under the device and solder all four ground pins directly to
it. Care must be taken to ensure that no ground potentials
can exist between Pin 10 and the other ground pins.
2. Although the power supply pins (9, 22, 24) are internally
bypassed to ground with 0.01µF ceramic capacitors,
additional external 0.1µF to 1µF tantalum bypass
capacitors may be required in critical applications.
3. A logic "0" on the HOLD COMMAND input (Pin 11), or a
logic "1" on the HOLD COMMAND input (Pin 12), will put
the device in the sample mode. In this mode, the device
acts as an inverting unity-gain amplifier, and its output will
track its input. A logic "1" on Pin 11 (logic "0" on Pin 12)
will put the device in the hold mode, and the output will be
held constant at the last input level present when the hold
command was given.
If the HOLD COMMAND input (Pin 11) is used to control the
device, Pin 12 must be tied to digital ground. If HOLD
COMMAND input (Pin 12) is used to control the device, Pin
11 must be tied to +5V.
4. The maximum capacitive load to avoid oscillation is typically
250pF. Recommended resistive load is 500Ω, although
values as low as 250Ω may be used. Acquisition and
sample-to-hold settling times are relatively unaffected by
resistive loads down to 250Ω and capacitive loads up to
50pF. However, higher capacitances will affect both
acquisition and settling time.