TECHNICAL NOTES
1. Rated performance requires using good high-frequency circuit board layout
techniques. The analog and digital grounds are not connected to each other
internally. Avoid ground-related problems by connecting the digital and
analog grounds to one point, the ground plane beneath the converter. Due
to the inductance and resistance of the power supply return paths, return
the analog and digital ground separately to the power supplies.
2. Bypass the analog and digital supplies and the +10V REF. OUT (pin 1) to
ground with a 4.7μF, 25V tantalum electrolytic capacitor in parallel with a
0.1μF ceramic capacitor.
3. CODING SELECT (pin 8) is compatible with CMOS/TTL logic levels for those
users desiring logic control of this function. The device has an internal pull-
up resistor on this pin, allowing pin 8 to be connected to +5V or left open
when a logic 1 is needed. See the Calibration Procedure for selecting an
output coding.
4. To enable the three-state outputs, connect ENABLE (pin 9) to a logic "0"
(low). To disable, connect pin 9 to a logic "1" (high).
CALIBRATION PROCEDURE
1. Connect the converter per Figure 3 and Table 1 for the appropriate input
range. Apply a pulse of 50 nanoseconds minimum to START CONVERT (pin
32) at a rate of 200kHz. This rate is chosen to reduce fl icker if LED's are
used on the outputs for calibration purposes.
2. Zero Adjustments
Apply a precision voltage reference source between ANALOG INPUT (pin 3)
and SIGNAL GROUND (pin 4), then adjust the reference source output per
Table 2. For unipolar operation, adjust the zero trimpot so that the output
code fl ickers equally between 00 0000 0000 0000 and 00 0000 0000 0001
with CODING SELECT (pin 8) tied low (straight binary) or between 11 1111
1111 1111 and 11 1111 1111 1110 with pin 8 tied high (complementary
binary). For bipolar operation, adjust the trimpot until the code fl ickers
equally between 10 0000 0000 0000 and 10 0000 0000 0001 with pin 8
tied low (offset binary) or between 01 1111 1111 1111 and 01 1111 1111
1110 with pin 8 tied high (complementary offset binary). Two's complement
coding requires using BIT 1 OUT (MSB) (pin 31). With pin 8 tied low, adjust
the trimpot until the code fl ickers between 00 0000 0000 0000 and 00
0000 0000 0001.
3. Full-Scale Adjustment
Set the output of the voltage reference used in step 2 to the value shown
in Table 2. Adjust the gain trimpot until the output code fl ickers equally be-
tween 11 1111 1111 1110 and 11 1111 1111 1111 with pin 8 tied low for
straight binary/offset binary or between 00 0000 0000 0000 and 00 0000
0000 0001 with pin 8 tied high for complementary binary/complementary
offset binary. Two's complement coding requires using pin 31. With pin
8 tied low, adjust the gain trimpot until the output code fl ickers equally
between 01 1111 1111 1110 and 01 1111 1111 1111.
4. To confi rm proper operation of the device, vary the precision reference volt-
age source to obtain the output coding listed in Table 3.
THERMAL REQUIREMENTS
All DATEL sampling A/D converters are fully characterized and speci-
fi ed over operating temperature (case) ranges of 0 to +70°C and –55
to +125°C. All room-temperature (TA = +25°C) production testing is
performed without the use of heat sinks or forced-air cooling. Thermal
impedance fi gures for each device are listed in their respective specifi ca-
tion tables.
These devices do not normally require heat sinks, however, standard pre-
cautionary design and layout procedures should be used to ensure devices
do not overheat. The ground and power planes beneath the package, as
well as all pcb signal runs to and from the device, should be as heavy as
possible to help conduct heat away from the package. Electricallyinsulating,
thermally-conductive "pads" may be installed underneath the package. De-
vices should be soldered to boards rather than "socketed", and of course,
minimal air fl ow over the surface can greatly help reduce the package
temperature.
Removing System Errors
Use external potentiometers to remove system errors or to reduce the small
initial errors to zero. Use a 100W trimpot in series with the analog input for
gain adjustment. Use a fi xed 50W resistor instead of the trimpot for opera-
tion without adjustment. Use a 20kW trimpot with the wiper tied to OFFSET
ADJUST (pin 5) for zero/offset adjustment. Connect pin 5 to ANALOG
GROUND (pin 6) for operation without zero/offset adjustment.
Table 2. Zero and Gain Adjustments
INPUT RANGE ZERO ADJUST
+½ LSB
GAIN ADJUST
FS –1½ LSB
0 to +10V +305μV +9.999085V
±5V +305μV +4.999085V
Table 1. Input Connections
INPUT RANGE INPUT PIN TIE TOGETHER
0 +10V Pin 3 Pins 2 and 4
±5V Pin 3 Pins 1 and 2
Scale is approximatel
50ns per division.
START
CONVERT
INTERNAL S/H
NN+1
35ns max.
EOC
10ns typ.
Conversion Time
600ns typ.
OUTPUT
DATA DATA N VALID
Hold
DATA N-1 VALID
30ns max.
50ns min., 100ns max
350ns max.
Aquisition Time
INVALID DATA
600ns min.
400ns max.
Figure 2. ADS-941 Timing Diagram
ADS-941
14-Bit, 1MHz Sampling A/D Converters
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
01 Apr 2011 MDA_ADS-941.B02 Page 3 of 5