73S8023C
Smart Card Interface
Simplifying System Integrati on™ DATA SHEET
April 2009
Rev. 1.5 © 2009 Teridian Semiconductor Co rpora ti on 1
DESCRIPTION
The Teridian 73S8023C is a low-power, high effici ency,
single smart card interface IC suitabl e for 3V and 5V
cards. It provides full electr ical compliance with IS O-
7816-3 and EMV 4.0 (EMV2000) sp ecifications.
Hardware support for any type of synchronous cards
(memory cards) is provided.
Interfacing with the system controller is done t hr ough the
control bus; composed of dig ital inputs to co ntrol the
interface, an d one interrupt output to inform the system
controller of the card presence and faults. Data exchang e
with the card is managed from the system controller usin g
the I/O line (and eventually the auxiliary I/O lines).
A chip select input allows multiple 73S8023C ICs to share
the same contr ol bus. When chip select is set low, the
host microco ntroller inputs are latched and outputs are
taken to a high impedance state.
The card clock signal can be generated by an on-chip
oscillator using an external crystal or by connectin g an
external clock signal.
The 73S8023C device incorporates an I S O-7816-3
activation/deactiva tion sequen ce r that controls the card
signals. Emergency card deactivation is initiated upon
card extraction or upon an y f ault generated by the
protection circuitry.
The 73S8023C requi res only a single 2.7 V to 3.6 V power
supply, and features a high-efficiency embe dded DC-DC
converter. This architecture, plus a Power Down digit al
input that allow placing t he IC in a very low-power mode
making the 73S 8023C particularly suitab l e for low-power
applications ( cell-phones, PDAs, payphones, hand-held
POS terminals…).
ADVANTAGES
• Supports both synchronous and asynchronous sm ar t
cards
• Replacement for TDA8002, with up to 600 mW in
power savings (@ EMV ICCmax condition) !
• The inductor-based DC-DC converter provides higher
current and efficiency
Ideal for battery-powered applications
Suitable for high current ca rds and SAMs: (100 mA
max)
Single 2.7 V to 3.6 V power suppl y a l lows removal
of 5 V from the system
• Power do wn mode: 2 µA typical
• Package: Small Format (5x5mm) 32-QFN
FEATURES
• Card Interface:
Complies wit h ISO-7816-3, EMV 4.0
A DC-DC Converter provides 3V / 5V to the card
from an extern al power suppl y input
High-efficiency converter: > 80% @ VDD=3.3 V,
VCC=5 V and ICC
Up to 100 mA supp l ied to the card
= 65 mA
ISO-7816-3 Activation / Deactiva tion sequen cer
with emergency automated deactivation
Protection i ncludes 2 volt age supervisor s which
detect volta ge drops on card VCC and on VDD
The V
power supply
DD
True over-cur rent detecti on (150 mA max.)
voltage supervi so r threshol d va lue can be
externally adjusted
2 card detection inputs, 1 for either possible switch
configuration
Full support of synchronous cards
• System Cont roller Int erface:
3 Digital input s control the ca rd activation /
deactivation, card reset and card voltage
3 Digital input s control the ca rd clock (division rate
and card clock source selection)
1 Digital out put, interrupt to the system controller,
allows the s ystem controller to monitor the card
presence and faults
1 Power do wn digital input (places the 73S8023C
in a very low-power mode (card deactivated)
1 Chip select d igi tal input f or parallel operation of
several 73S8023C ICs.
1 External clock input (STROBE), used f or
synchronous o perat i on
1 Digital out put clock, buffered versi on of signal on
XTALIN
Crystal oscillator or host clock (XTALIN), up to
27 MHz
• Power Supply: VDD
• 6 kV ESD Protection on the card interface
2.7 V to 3.6 V
APPLICATIONS
• Point of Sales and Transaction Terminals
• Payphones
• Set-Top-Boxes, DVD / HDD Recor ders
• Payment card i nterfaces in portable device s (PDAs,
mobile phones…)
73S8023C Data Sheet DS_8023C_019
2 Rev. 1.5
FUNCTIONAL DIAGRAM
Figure 1: 73S8023 C Blo ck Diagram
ICC I/O BUFFERS
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
XTAL
OSC CLOCK
GENERATION
DIGITAL
CIRCUITRY
&
FAULT LOGIC
VDD FAULT VCC FAULT
Int_Clk
VDD VDD
VCC
RST
CLK
PRES
PRES
XTALIN
XTALOUT
CLKDIV1
CLKDIV2
GND
TEMP FAULT
NC
29
30
31
2 6
4
6
7
9
10
11
12
13
15
14
20
19
18
17
26
24
23
22
28
27
ISO-7816-3
SEQUENCER
R-C
OSC.
DC-DC
CONVERTER
ICC RESET
BUFFER
ICC CLOCK
BUFFER
OVER
TEMP
PWRDN
I/O
AUX1
AUX2
IOUC
AUX1UC
AUX2UC
VDDF_ADJ
RSTIN
CMDVCC
5V/3V
OFF
5
GND
1
3
LIN
6
21
GND
ICC FAULT
CLKOUT 32
8
CS
CLKSEL
16 STROBE
25
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 3
Table of Contents
1 Pin Description .................................................................................................................................... 5
1.1 Card Interface ............................................................................................................................... 5
1.2 Miscellaneous Inputs a nd Outputs ................................................................................................ 5
1.3 Power Supply and Ground ............................................................................................................ 5
1.4 Microcontroller Interf ace ............................................................................................................... 6
2 System Controller Interface ............................................................................................................... 7
3 Oscillator .............................................................................................................................................. 8
4 DC-DC Converter – Card Power Supply .......................................................................................... 8
5 Voltage Supervision ........................................................................................................................... 9
6 Power Down ....................................................................................................................................... 10
7 Over-Temperature Monit or ............................................................................................................... 10
8 Activation and Deactivation ............................................................................................................. 11
8.1 Activation Sequence (Sy nchronous Mode) ................................................................................ 11
8.2 Deactivation Sequence (Sy nchrono us Mode ) ............................................................................ 11
8.3 Activation Sequence (Asynchronous Mode) ............................................................................... 12
8.4 Deactivation Sequence (Asy nchro nous M ode) .......................................................................... 14
9 OFF and Fault Detection .................................................................................................................. 14
10 I/O Circuitry and Timing ................................................................................................................... 15
11 Typical Application Schematic ........................................................................................................ 17
12 Electrical Specification ..................................................................................................................... 18
12.1 Absolute M aximum Ratings ........................................................................................................ 18
12.2 Recommend ed Operat ing Con dition s ......................................................................................... 18
12.3 Package Thermal Parameters .................................................................................................... 18
12.4 Card Interf ace Characteristics .................................................................................................... 19
12.5 Digital Signals ............................................................................................................................. 22
12.6 DC Charact er ist ics ...................................................................................................................... 23
12.7 Voltage / Tem perature Fault Detection Circuit s .......................................................................... 23
13 Mechanical Drawing (32-QFN) ......................................................................................................... 24
14 Package Pin Desi gn ation (32-QFN) ................................................................................................. 25
15 Ordering Information ........................................................................................................................ 26
16 Related Documentation .................................................................................................................... 26
17 Contact Informati o n .......................................................................................................................... 26
Revision History ........................................................................................................................................ 27
73S8023C Data Sheet DS_8023C_019
4 Rev. 1.5
Figures
Figure 1: 73S8023C B l ock Diagram ............................................................................................................. 2
Figure 2: Power Do wn M ode Operation: CS = high .................................................................................... 10
Figure 3: Activ ation Sequence – Synchronous Mode ................................................................................. 11
Figure 4: Synchronous Deactivat ion Operation – CKSEL = High ............................................................... 12
Figure 5: Asynchronous Activation Sequence – RSTIN Low When CMDVCC Goes Low ......................... 13
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2 ......................................................... 13
Figure 7: Asynchronous Deactivation Sequence ........................................................................................ 14
Figure 8: Timing Diagram – Management of the Interrupt Line OFF .......................................................... 15
Figure 9: I/O and I/OUC State Diagram ...................................................................................................... 16
Figure 10: I/O – I/OUC Delays Timing Diagram .......................................................................................... 16
Figure 11: 73S8023C – Typical Application Schematic .............................................................................. 17
Figure 12: DC – DC Co nverter efficien cy (VCC = 5 V) ................................................................................ 20
Figure 13: DC – DC Converter Eff i ci ency (VCC = 3 V) ................................................................................ 20
Figure 14: 32-QFN Mechanical Drawing ..................................................................................................... 24
Figure 15: 32-QFN 73S8023C Pin Out ....................................................................................................... 25
Table
Table 1: Choice of V CC Pin Capacitor .......................................................................................................... 8
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 5
1 Pin Description
1.1 Card Interface
Name Pin Description
I/O 9 Card I/O: Data signal to/from card. Includes a pull-u p resistor to V
CC.
AUX1 11 AUX1: Auxiliary data sign al to/from card. Includes a pull-up resistor to VCC.
AUX2 10 AUX2: Auxiliary data signal to/from card. Includes a pul l-up resistor to VCC.
RST 14 Card reset: Provi des reset (RST) signal to card.
CLK 13 Card clo ck: Provides clock (CLK ) signal to card. The rate of this clock i s
determined by cry st al oscillator frequency and CLKDIV select ions.
PRES 7 Card Presence switch: Active high indicates card i s present. Includes a
pull-down current source.
PRES 6 Card Presence swit ch: Active low indicates card is pre sent . Includes a pull-up
current source.
VCC 15 Card power suppl y: Logically cont roll ed by sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
GND 12 Card ground.
1.2 Miscellaneous Inputs and O utputs
Name Pin Description
XTALIN 23 Crystal oscillator input: can ei ther be connected t o cr ystal or driven as a
source for the card clock.
XTALOUT 24 Crystal oscillator output: conne ct ed to crystal. Left open if XTALIN is being
used as external clo ck input.
VDDF_ADJ 17 VDD fault threshold adjustment i nput: this pin can be used to adjust VDDF
value (that controls deactivation of the card). Must be left open if unused.
NC 4 Non-connected pi n. Must be left open.
1.3 Power Supply and Ground
Name Pin Description
VDD 3, 20 System controller i nterface supply voltage: Supply voltage for internal power
supply and DC-DC conve rter power supply source.
GND 1 DC-DC convert er ground.
GND 21 Digital ground.
LIN 2 External inductor. Connect ext ernal inductor from pin 2 to VDD. Keep the
inductor close t o pi n 2.
73S8023C Data Sheet DS_8023C_019
6 Rev. 1.5
1.4 Microcontroller Interface
Name Pin Description
CMDVCC 18 Command VCC (negative assertion): Logic low o n this pin causes the DC-DC
converter to ramp the VCC supply to the card and initiates a card activat i on
sequence.
5V/#V 31 5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card
interface, logic low selects 3 volt operation. When the part is to be used with
a single card voltage, this pin should b e tied to either GND or VDD. However,
it includes a high im pedance pull-up resistor to defa ul t this pin high (select i on
of 5V card) when unconnected
PWRDN 5 Power Down control input: Active High. When Power Down (PD) mode i s
activated, all int ernal analog function s are disabled to place the 73S8023C i n
its lowest power consumption mode. The P D m ode is allowed only out of a
card session (PW RDN high is ignored when CMDVCC = 0). Must be tied to
ground when power down function i s not used.
CLKDIV1
CLKDIV2 29
30 Sets the divide ratio from the X TALIN oscillator (or external clock input) to the
card clock. These pins include pull-do wn resistors.
CLKDIV1 CLKDIV2 Clock Rate
0
0
XTALIN/8
0
1
XTALIN/4
1
1
XTALIN/2
1
0
XTALIN
OFF 22 Interrupt signal to the processor: Active Low. Multi-function indicating fault
conditions and car d presence. Open dra i n output configuration; it includes an
internal 20 kΩ pull-up to V
DD.
RSTIN 19 Reset Input: This signal controls the RST signal to the card.
I/OUC 26 System controller data I/O to/from the card. Includes internal p ull-up resistor
to VDD.
AUX1UC 27 System controller auxiliary dat a I/O to/from the card. Includes inter nal pul l-up
resistor to VDD.
AUX2UC 28 System controller auxiliary dat a I/O to/from t he car d. Include s internal pull-up
resistor to V
DD.
CS 8 When CS = 1, the cont rol and signal pins are configured normally. When CS
is set low, signals CMDVCC, RSTIN, PWRDN, 5V/#V, CLKDIV1, CLKDIV2,
CLKSEL are latched. I/OUC, AUX1UC, and AUX2UC are set to high
impedance pull-up mode and won’t pass data to or from the smart card. OFF
output is tri-stated.
CLKSEL 16 Selects CLK and RS T operational m ode. When CLKSEL is low (default), the
circuit is confi gured for asynchron ous card operation and the sequencer
manages the contr ol of CLK and RST. Whe n CLK SEL is high, the signal
CLK is a buffered copy of STROBE and the signal RST is directl y controlled
by RSTIN.
STROBE 25 When CLKSEL = 1, the signal CLK is cont rol l ed directly by STROBE.
CLKOUT 32 CLKOUT is the buffered version of the signal on pin XT A LIN.
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 7
2 System Controller Interface
• The CS (chip select) i nput allows multi ple devices to operate in parallel. When CS i s high, the system
interface sign al s operate as describe d. When CS is take n low, the system int erface signals are
latched internally. The pins I/OUC, A UX1UC, and AUX2UC are weakly pulled up and the OFF signal
is put into a high impedance state.
• The CLKSEL signal selects betwee n sy nchronous and asy nchronous operation. When CLKSEL i s
low, asynchronous operation is sel ect ed. When CLKSEL is high, synch ronous operation is selected.
• Digital inputs al l ow direct control of the card interface from the host as follo ws:
Pin CMDVCC: When set low, st arts an activati on sequence if a card i s present.
Pin 5V/#V: Defines the card voltage.
• The card I/O and Res et signals have their correspondi ng controller I/Os to be co nnected directly to
the host:
Pin RSTIN: controls the card RST signal. When enabled by the sequencer, RST is equal to
RSTIN for both synchronous and asyn chronous modes.
Pin I/OUC: d ata transfer to card I/O contact.
Pins AUX1UC and A UX2UC (auxiliary I/O lines associated to the auxiliary I/Os which ar e
connected to the C4 and C8 card connect or contacts).
• Two digital inputs c ontrol the card clock frequency di vision rate: CLKDI V 1 and CLKDIV2 define the
card clock frequency from the input clock frequency (crystal or external clock). The division rate is
defined as foll ows:
CLKDIV2 CLKDIV1 CLK
0 0 ⅛ XTAL
0 1 XTAL
1 0 ¼ XTAL
1 1 ½ XTAL
When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the
card clock depends on the duty-cycle and waveform o f the signal applied on the pin XTALIN.
When other division rat es are used, the 73S8023C circuitry guarantees a duty-cycle in the
range 45% to 55% , conforming to ISO-7816-3 and EMV 4.1 specifications.
• Interrupt output to the host: A s l ong as the card is not act i vated, the OFF pin inf orms the host a bout
the card presence only (low = no card in the reader). When CMDVCC is set low (C ard activation
sequence requested from the host), a low l evel on OFF means a fault has been detected (e.g. card
removedl during a card session, or voltage fault, or therm al / over-current fault) that automatically
initiates a deactiv ation sequence.
• Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8023C i n
its Power Do wn state. This pin can only be activated outside of a card session.
• The CLKOUT signal is a buffered output of the signal appl ied to the XTALIN pin whether it is an
external clock sour ce or it is configured as a crystal oscillator. CLKOUT c an be used when using
multiple 73S8023 C devices to share a single clock sig nal .
• The STROBE input directly drives the smart card CLK signal when operating in synchronous m ode.
STROBE is ignored in asynchronous mode.
73S8023C Data Sheet DS_8023C_019
8 Rev. 1.5
3 Oscillator
The 73S8023C devi ce has an on-chip oscillator that can generat e the smart card clock using an external
crystal (connected between the pins X TALIN and XTA LOUT) to set the oscillator frequency . When the
card clock signal is av ai l able from another so urce, it can be connected to the pi n XTALIN, and t he pi n
XTALOUT should be left unconnected. Signal CLKO UT i s t he buffered versi on of the signal on XTALIN.
4 DC-DC Converter – Card Power Supply
An internal DC-DC converter provides t he car d power supply. This conve rter is able to prov i de either 3 V
or 5 V card voltage from the power suppl y applied on the VDD pin. The digital ISO-7816-3 s equencer
controls the converte r. Card voltage selection i s ca rried out by the digital input 5V/#V.
The circuit is an inductive step-up conv erter/regulat or. The external components required are 2 fil ter
capacitors on the power-supply input VDD (next to the LIN pin, 100 nF + 10 µF), an induct or, and an
output filter capacitor on the card power supply VCC. The circuit performs regul ation by activating the
step-up operation when VCC is below a set point of 5. 0 or 3.0 volts minus a comparator hysteresis voltage
and the input sup pl y VDD is less than the set point for VCC. When VDD is greater than the set point for VCC
(VDD = 3.6 V, VCC =3 V) the circuit operates as a li near regulator.
Depending on the i nductor values, the voltage convert er can provide current on VCC as high as 100 mA.
The circuit prov i des over-current protection and limits ICC to 150 mA. When an over-current con di tion is
sensed, the circuit i nitiates a deactivation sequence from the control l ogic and reports back t o the host
controller a fault on the interrupt output OFF.
Choice of the inductor
The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between LIN (pin 2)
and the VDD supply voltage. The inductor value can be opt i m i zed to meet a particular configur ation
(ICC_MAX). The inductor should be located on the PCB as close as possible t o the LIN pin of the IC.
Choice of the VCC
Depending on the applications, the requirements in terms of both the V
capacitor
CC Table 1
minimum voltage and the
transient current s t hat the interface mu st provide to the card are di fferent. shows the
recommended capacitors for each VCC
Table 1: Choice of V CC Pin Capacitor
power supply conf i guration and applicable specification.
Specification Requirement Application
Specification
Min VCC Max Transient
Current Charge
Voltage
Allowed During
Transient Current
Capacitor
Type Capacitor
Value
EMV 4.1 4.6 V 30 nAs X5R/X7R w/
ESR < 100 mΩ
3.3 µF
ISO-7816-3 4.5 V 20 nAs 1 µF
NDS 4.65 V 40 nAs 3.3 µF
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 9
5 Voltage Supervision
Two voltage supervi sors constantly check the presen ce of the voltages VDD and VCC. A card deactivation
sequence is trigge red upon a fault det ect ed by these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage
range for the int erface with the syst em controller. The VDD Voltage supervisor is also us ed to initialize the
ISO-7816-3 sequenc er at power-on, and al so t o deactivate t he card at power-off or upon a fault. The
voltage threshol d of the VDD voltage supervisor is internally s et by default to 2.3 V nominal. Howev e r, it
may be desirable, i n some applications, to modify this threshold value. The pin VDDF_ADJ (pin 17) i s
used to connect an external resisto r REXT to ground to raise the VDD fault voltage to another value, VDDF.
The resistor v alue is defined as follows:
REXT = 180 kΩ /(VDDF
An alternative (more ac cur ate) metho d of adjusting the V
- 2.33)
DD Figure 11: 73S8023C – Typical Application
Schematic
fault voltage is to use a resistive network of
R3 from the pin to supply and R1 from t he pin to ground (see
). In order to set the new threshold voltage, the equi valent resistan ce must be deter m ined.
This resistance value will be designat ed Kx. Kx is defined as R1/(R1+R3). K x is calculated as:
Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage.
To determine t he values of R1 and R3, use t he following formulas:
R3 = 72000 / Kx R1 = R3*(Kx / (1 – Kx))
Taking the example ab ove, where a VDD fault threshold voltage of 2.7 V is desired, solvi ng for Kx gives:
Kx = (2.649 / 2.7) - 0.6042 = 0. 377
Solving for R3 giv es: R3 = 72000 / 0.377 = 191 kΩ.
Solving for R1 gives: R1 = 191000 * (0. 377 / (1 – 0.377)) = 115.6 kΩ.
Using standard 1 % resistor values give s R3 = 191 kΩ and R1 = 115 kΩ. These values give an
equivalent resist ance of Kx = 0.376, a 0.3% error.
Using 1% external resistors and a parallel resistance of 72 k ohms will result in a +/- 6% tolerance in the
value of VDD Fault . The sources of vari ation due to integrat ed circuit process variations and m i smatches
include the internal reference voltage (less than +/- 1%), the intern al comparator hyst eresis and offset
(less than +/- 1.7% for part-to-part, processi ng and environment), the internal resistor value mismatch and
value variations (less than 1.8% ), and the external r esistor values (1% ).
If the 2.3 V default threshold is ac ceptable, this pin m ust be left unconnected.
73S8023C Data Sheet DS_8023C_019
10 Rev. 1.5
6 Power Down
A power down funct i on is provided via t he PWRDN pin (active high). When activated, the P ower Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC convert er, to put the 73S8023C in its lowest power con sumption mode. PD mode is only
allowed in the deacti vated condition (out of a card ses sion, when the CMDVCC si gnal i s driven high from
the host controller).
The host controlle r invokes the power do wn st at e when it is desirable to save power. The sig nals PRES
and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller
must then set P WRDN low and wait for the internal stabi l ization time prio r to starting any car d session
(prior to turning CMDVCC low).
Resumption of t he norm al mode occurs approximately 10 ms (stabilizati on of the internal oscillators and
reset of the circuitry) after P WRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, OFF can be used as an indicat i on that the circuit has complet ed i ts
recovery from power-down state. OFF will go high at the end of the stabil ization period. Should
CMDVCC go low during PWR DN = 1, or within t he 10 ms internal stabilizat i on / reset time, i t will not be
taken into account and the card interface will remai n inactive. Since CMDVCC is t aken into account on
its edges, it should be toggled high and low again after the 10 ms to activate a card.
Figure 2 illust rates the sequencing of the PD and Normal m odes. PWRDN must be connected to GND if
the power down fun ct i on i s not used.
Figure 2: Power Do wn Mode Oper ation: CS = high
7 Over-temperature Monitor
A built-in detector monitors die tempe rature. When an over-temperature condition occurs, a card
deactivation sequence is initiated, and an error or fault condition is reported to the sy st em controller.
PRES
OFF
PWRDN
Internal RC OSC
CMDVCC
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
CMDVCC=0
EMV / ISO deactivation
time ~= 100 uS
~10ms
PWRDN has effect when
the cardi s deactivated
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 11
8 Activation and Deactivation
8.1 Activation Sequence (Synchron ous Mode)
The 73S8023C smart card interface I C has an internal ~10 ms delay at power-on reset or on applic ation
of VDD > VDDF
1. CMDVCC is set low.
. No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to
activate the card.
The following steps list the activation s equence and the t i m i ng of the card control signals when t he
system controller sets CMDVCC low:
2. Turn on VCC and I/O (AUX1, AUX2) to reception mode at the end of (tACT
3. RST is a copy of RSTIN and CLK is a copy of STROBE after (t ).
1
).
Figure 3: Activation Sequence – Synchronous Mode
8.2 Deactivation Sequence ( Synchronous Mode)
Deactivation i s i ni tiated either by the system controlle r by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-cur rent, overheating, VDD
1. RST goes low at time t
fault and card ext ract ion
during the session and are indicated to the system controll er by the fall of OFF.
The following steps list the deactivat i on sequence and the timing of the card c ontrol signals wh en the
system controller sets the CMDVCC high or a f ault condition set s OFF low:
1
2. CLK stops low at time t .
2
3. I/O goes low at time t .
3
4. V . Out of recepti on m ode.
CC is shut down at time t4. After a delay t5 (discharge of the VCC capacitor), VCC
is low.
CMDVCC
VCC
IO
CLK
RSTIN
tACT t1
RST
STROBE
t
ACT
~= 500µs
t1 > 0.5
µ
s after tACT, RST = RSTIN, CLK = STROBE
73S8023C Data Sheet DS_8023C_019
12 Rev. 1.5
CMDVCC
VCC
IO
OFF
RSTIN
RST
STROBE
CLK
t
0
- Deactivation starts after CMDVCC is set high or OFF falls due to card removal or fault
t
4
- VCC is shut down
(Note: Host should set STROBE low when CMDVCC is set high, otherwise CLK may be truncated.
CLK truncation may occur if an OFF event is triggered)
t
3
- IO falls approx 2us after CLK falls
t
1
- RST falls approx. 0.5us after deactivation begins
t
2
- CLK falls approx. 7.5us after RST falls
-- OR --
t
0
t
1
t
2
t
3
t
5
t
4
t
5
- VCC goes to 0 after discharge of VCC capacitor, approx 100us after deactivation begins
Figure 4: Synchronous Deactivation Operation – CKSEL = High
8.3 Activation Sequence (Asynchronous Mode)
The 73S8023C smart card interface I C has an internal 10 ms delay at power-on reset or upon appli cation
of VDD > VDDF
1. CMDVCC is set low.
or upon exit of Power Down mode. The card interface may only be act i vated when OFF is
high which indicate s a card is present. No a ct i vation is allowed at this time. CMDVCC (edge trigge red )
must then be set low t o activate the card.
The following steps list the activation s equence and the t i m i ng of the card control signals when t he
system controller sets CMDVCC low while the RST IN is low:
2. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In norm al operation,
the voltage VCC to the card becomes valid during t1. If VCC does not become valid, then OFF goes
low to report a f aul t to the system contr oll er, and the power VCC
3. Turn I/O (AUX1, AUX2) to reception mode at the end of t to the card is turned off.
2
4. CLK is applied to the card at the end of t.
3
5. RST is a copy of RSTIN after t.
4. RSTIN may be set high before t4, however the sequencer won’t set
RST high until 42000 clock cycles aft er the start of CLK.
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 13
Figure 5: Asynchronous Activation S equ ence – RSTIN Low When CMDVCC Goes Low
The following steps list the activation sequence and the timing of the card control signals when the
system controller pul ls the CMDVCC low while the RSTIN is high:
1. CMDVCC is set low.
2. Next, the internal VCC control circuit checks the presence of VCC at t1. In normal operation, the
voltage V CC to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power VCC
3. Due to the fal l of RSTIN at t to the car d i s t urned off.
2
4. CLK is applied to the card at the end of t
, turn I/O (AUX1, A UX2) to reception mode.
3
5. RST is to be a copy of RSTIN after t after I/O is in reception mode.
4. RSTIN may be set high before t4
, however the sequencer
won’t set RST high unt i l 42000 clock cycle s after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
t1t2t3t4
RST
t1 = 0.510 ms (timing by 1.5MHz int er nal Oscillator )
t2 = 1.5µs, I/O goes to reception state
t3 = > 0.5µs, CLK active
t4
Figure 6: Asynchronous Activation S equ ence – Timing Diagram #2
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
CMDVCC
VCC
IO
CLK
RSTIN
t1t2t3t4
RST
t
1
= 0.510 ms (timing by 1.5 MHz internal Oscillator)
t2 = 1.5 µs, I/O goes to rec eption state
t3 ≥ 0.5 µs, CLK starts
t4 ≥ 42000 card clo ck cycles. Time for RST to become the copy of RSTIN
73S8023C Data Sheet DS_8023C_019
14 Rev. 1.5
8.4 Deactivation Sequence (Asynchronous Mode)
Deactivation i s i ni tiated either by the system cont roll er by setting CMDVCC high, or aut om atically in the
event of hardware faults. Hardware faults are over-curr ent, overheating, VDD fault, VCC
1. RST goes low at the end of time t
fault, and card
extraction during the session.
The following steps list the deactivat i on sequence and the timing of the card c ontrol signals wh en the
system controller sets the CMDVCC high or OFF goes low due to a f aul t or card removal:
1
2. CLK stops low at the end of time t .
2
3. I/O goes low at the end of time t .
3
4. V . Out of reception m ode.
CC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC
is low.
RST
CLK
I/O
VCC
t1t2t3t4t5
CMDVCC -- OR --
OFF
Figure 7: Asynchronous Deactivati on Sequence
9 OFF and Fault Detection
There are two case s for which the syste m cont roller can monit or the OFF signal: to query regarding t he
card presence outside card sessi ons, or for fault det ect i on during card sessions.
Monitoring Outside a Card Session
In this condition, CMDVCC is always high, OFF is low if the card is not present, and hi gh i f the card is
present. Because it i s out side a card session, any fault detection will not act upon t he OFF signal. No
deactivation is req ui red during this time.
Monitoring During a Card Session
CMDVCC is always low, and OFF falls low if the card is extracted or i f any fault is detect ed. A t the same
time that OFF is set low, the sequencer starts the deact i vation process.
Figure 8 shows t he timing diagram for the signals CMDVCC, PRES, and OFF during a card session and
outside the card session:
t1 ≥ 0.5 µs, t iming by 1.5 MHz internal Oscillator
t2 ≥ 7.5 µs t3 ≥ 0.5 µs t4 ≥ 0.5 µs
t5 = depends on VCC f i lter capacitor.
t1 + t2 + t3 + t4 + t5 ~= 100 µs
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 15
Figure 8: Timing Diagram – Management of the Interrupt Line OFF
10 I/O Circuitry and Timing
The I/O, AUX1, and AUX2 pins are in the low state after power-on reset and they are in the high state
when the activation sequencer turns on the I/O reception state. See Section 8 Activat i on and
Deactivation for m ore details on when the I/O recept i on is on.
The state of the I/OUC, AUX1UC, and AUX2UC pins is high after power-on reset. Within a card session
and when the I/ O recept ion state is on, the first I/O line on which a falling edge i s detected becomes t he
input I/O line and t he other becomes the output I/O li ne. When the i nput I/O line rising edge is detected,
both I/O lines ret urn to their neutral st ate.
Figure 9 shows t he state diagram of how the I/O and I/OUC lines are managed to become input or output.
The delay between the I/O signals i s shown in Figure 10.
In order to be compliant to the NDS specif icatio ns, a 27 pF c apacitor must be ad ded between pins
I/O (C7) and GN D (C5) at the smart ca rd connector.
PRES
OFF
CMDVCC
VCC
outside card session within card session
OFF is low by
card extracted OFF is low by
any fault
within card
session
73S8023C Data Sheet DS_8023C_019
16 Rev. 1.5
Neutral
State
I/OUC
in
I/O
reception
I/OICC
in
No
Yes
No No
No
Yes
No
Yes
I/O
&
not I/OUC
I/OUC
&
not I/O
I/OUC I/O
yesyes
Figure 9: I/O and I/OUC State Diagram
IO
IOUC
t
IO_HL tIO_LH tIOUC_HL tIOUC_LH
Delay from I/ O to I/OUC: tIO_HL = 100ns tIO_LH = 25ns
Delay from I/OUC to I/O: tI/OUC_HL = 100ns tI/OUC_LH
Figure 10: I/O – I/OUC Delays Timing Diagram
= 25ns
73S8023C Data Sheet DS_8023C_019
Rev. 1.5 17
11 Typical Application Schematic
32QFN
73S8023C
1
4
3
8
6
7
12
13
14
15
24
23
GND
NC
VDD
PRES
PRES
GND
CLK
RST
VCC
XTALOUT
XTALIN
2LIN
5PWRDN
CS
16 CLKSEL
29
30
31
28
27
26
CLKDIV1
CLKDIV2
5V/3V
AUX2UC
AUX1UC
I/OUC 25
STROBE
32
CLKOUT
17
18
19
20
21
22
VDDF_ADJ
CMDVCC
RSTIN
VDD
GND
OFF
10
9
11 AUX2
I/O
AUX1
See NOTE 4
VDD
PWRDN_from_uC
Y1
CRYSTAL
C2
22pF
C1
SO7816=1uF,
NDS/EMV=3.3uF
See NOTE 5
RSTIN_from_uC
CLKDIV2_from_uC
CLK track should be routed
far from RST, I/O, C4 and
C8.
I/OUC_to/from_uC
R1
Rext1
See NOTE 1
VDD
C9
100nF
External_clock_from uC
C4
100nF
C3
22pF
AUX1UC_to.from_uC See NOTE 6
C5
10uF
AUX2UC_to/from_uC
See NOTE 3
See NOTE 1
CLKOUT_to_uC
VDD
CLKDIV1_from_uC
CMDVCC_from_uC
5V/3V_select_from_uC
OFF_interrupt_to_uC
R3
Rext2
- OR -
See note 7
Smart Card Connector
1
2
3
4
5
6
7
8
9
VCC
RST
CLK
C4
GND
VPP
I/O
C8
SW-1
SW-2
VDD
L1 10uH
CS_from_uC
CLKSEL_from_uC
STROBE_from_uC
See note 2
NOTES:
1) VDD supply must be = 2.7V to 3.6V DC).
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Pin can not float. Must be driven or connected to GND if
power down function is not used.
6) Internal pull-up allows it to be left open if unused.
7) Rext1 and Rext2 are external resistors to ground and
VDD to modify the VDD fault voltage. Can be left open.
2) Keep L1 close to pin 2. VDD
R2
20K
10
Card detection
switch is
normally
closed.
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
C8C7
C6
27pF 27pF 27pF
8) Capacitors C7 and C8 are optional. C6 is mandatory for NDS.
Figure 11: 73S8023 C – Typical Application Schematic
73S8023C Data Sheet DS_8023C_019
18 Rev. 1.5
12 Electrical Specification
12.1 Absolute Maximum Ratings
Operation outside these rating limits may cause permanent damage to the device.
Parameter Rating
Supply Voltage V -0.5 to 4.0 VDC
DD
Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC
Storage Temperat ure -60 °C to 150 °C
Pin Voltage (ex cept LIN and card interf ace) -0.3 to (VDD +0.5) VDC
Pin Voltage (LI N) -0.3 to 6.0 VDC
Pin Voltage (card interface) -0.3 to (VCC + 0.5) VDC
ESD Tolerance – C ard i nterface pins +/- 6 kV
ESD Tolerance – Ot her pins +/- 2 kV
ESD testing on Card pins uses the HBM condit i on, 3 pulses, ea ch polarity referenced to ground.
The smart card pins are protected a gai nst shorting between a ny combination of smart card pins.
12.2 Recommended Operati ng Condi tions
Parameter Rating
Supply Voltage VDD 2.7 to 3.6 VDC
Ambient Operating T emperature -40 °C to +85 °C
Input Voltage for Digital Inputs 0 V to VDD + 0.3 V
12.3 Package Thermal Parameter s
Package Rating
32QFN 47 °C / W (with bottom pad soldered)
32QFN 78 °C / W (without bott om pad soldered)
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 19
12.4 Card Interface Characteristics
Symbol Parameter Condition Min Typ Max Unit
Card Power Supply (VCC) DC-DC Converter
General conditions, -40
°
C < T < 85
°
C, 2.7 V < VDD < 3.6 V
V Card supply volt age
including ripple and noise
CC
Inactive mode -0.1 0.1 V
Inactive mode
ICC -0.1
=1 mA 0.4 V
Active mode
ICC 4.75
< 65 mA; 5 V 5.25 V
Active mode
ICC 2.8
< 65 mA; 3 V 3.2 V
Active mode
single pulse of 100 mA
for 2 µs; 5 V,
fixed load = 25 mA
4.65 5.25 V
Active mode
single pulse of 100 mA
for 2 µs; 3 V,
fixed load = 25 mA
2.76 3.2 V
Active mode
current pulses of 40 nAs
with peak |ICC 4.65
| < 200 mA,
t < 400 ns; 5 V
5.25 V
Active mode
current pulses of 40 nAs
with peak |ICC 2.76
| < 200 mA,
t < 400 ns; 3 V
3.2 V
VVCC Ripple
CCR 350 mV
IMaximum supply current
to the card
CCmax Static load current
VCC 100 > 4.6 or 2.7 V as
selected, L=10 µH mA
I I
CCF CC fault current 100 125 180 mA
VV
SR CC C
slew rate – Rise rate
on activate F on VCC 0.05 = 1 uF 0.15 0.25 V/µs
VV
SF CC C
slew rate – Fall rate
on deactivate F on VCC 0.1 = 1 uF 0.3 0.5 V/µs
CExternal filter capacitor
(V
F CC
to GND) 0.47 3.3 4.7 µF
L Inductor (LIN to VDD ) 10 µH
Limax Imax in inductor VCC = 5 V, ICC = 65 mA,
VDD
= 2.7 V 400 mA
η Efficiency VCC = 5 V, ICC = 65 mA,
VDD
= 3.3 V 87 %
73S8023C Data Sheet DS_8023C_019
20 Rev. 1.5
1011B01 Converter efficiency (VCC 5V)
50
55
60
65
70
75
80
85
90
95
100
020 40 60 80 100
Icc [mA]
Efficiency [%]
2.7V
3.0V
3.3V
3.6V
Figure 12: DC – DC Co n verter efficien cy (VCC = 5 V)
Output current on Vcc at 5 V. Input voltage on VDD
1011B01 Converter efficiency (VCC 3V)
50
55
60
65
70
75
80
85
90
95
100
020 40 60 80 100
Icc [mA]
Efficiency [%]
2.7V
3.0V
3.3V (Linear)
3.6V (Linear)
at 2.7, 3.0, 3.3 and 3.6 v olts.
Figure 13: DC – DC Converter Efficiency (VCC = 3 V)
Output current on Vcc at 3 V. Input voltage on VDD at 2. 7, 3.0, 3.3 and 3.6 volts.
Converter Efficiency (VCC 3 V)
Converter Efficiency (VCC 5 V)
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 21
Symbol Parameter Condition Min Typ Max Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC. ISHORTL, ISHORTH, and VINACT requireme nts do not pertain to I//OUC, AUX1UC, and AUX2UC.
VOutput level, high (I /O, AUX1,
AUX2)
OH IOH = 010.9 V
CC VCC V + 0.1
IOH 0.75 V
= -40 µA
CC VCC V + 0.1
VOutput level, high (I/OUC,
AUX1UC, AUX2UC)
OH IOH 0.9 V = 0
DD VDD V + 0.1
IOH 0.75 V
= -40 µA
DD VDD V + 0.1
VOutput level, low
OL IOL =1 mA 0.3 V
VInput level, high (I /O, AUX1,
AUX2)
IH 1.8 VCC V + 0.30
VInput level, high (I/OUC,
AUX1UC, AUX2UC)
IH 1.8 VDD V + 0.30
VInput level, low
IL -0.3 0.8 V
VOutput voltag e when outside
of session
INACT IOL = 0 0.1 V
IOL = 1 mA 0.3 V
IInput leakage
LEAK VIH = V
CC 10 µA
I
Input current, low (I/OUC,
AUX1UC, AUX2UC)
IL
VIL = 0, CS = 1 0.65 mA
VIL = 0, CS = 0 5 µA
Input current, low (I/O, AUX1,
AUX2) VIL = 0 2 mA
IShort circuit out put current
SHORTL For output low,
shorted to VCC
through 33 Ω 15 mA
IShort circuit out put current
SHORTH For output high,
shorted to ground
through 33 Ω 15 mA
tR, t Output rise time, fall times
F
CL = 80 pF, 10% to
90%. For I/OUC,
AUX1UC, AUX2UC,
CL
= 50 pF
100 ns
tIR, t Input rise, fall times
IF 1 µs
RInternal pull-up resistor
PU Output stable for
> 200 ns 8 11 14 kΩ
Ipuhiz Pull-up current, Hi-Z state For pins IOU C,
AUX1UC, AUX2UC
when CS = 0 5 µA
FD Maximum data rate
MAX 1 MHz
T
Delay, I/O to I/OUC,
I/OUC to I/O
(falling edge to fal l i ng edge)
FDIO
100 Started
ns
Delay, I/O to I/OUC,
I/OUC to I/O
(rising edge to rising edge) 10
CInput capacitance
IN 10 pF
1 NDS applications require a 27 pF capacitor on I/O pla ced at the smart card c onnector.
73S8023C Data Sheet DS_8023C_019
22 Rev. 1.5
Symbol Parameter Condition Min Typ Max Unit
Reset and Clock for card interface, RST, CLK
VOutput level, high
OH IOH 0.9 V
= -200 µA
CC V V
CC
VOutput level, low
OL IOL 0
= 200 µA 0.2 V
VOutput voltag e when outside
of a session
INACT IOL = 0 0.1 V
IOL = 1 mA 0.3 V
IOutput current limit, RST
RST_LIM 30 mA
IOutput current limit, CLK
CLK_LIM 70 mA
tR, t Output rise time, fal l time
F
CL
= 35 pF for
CLK, 10% to 90% 8 ns
CL
= 200 pF for
RST, 10% to 90% 100 ns
Td Delay time STROBE to CLK,
RSTIN to RST
CLKSEL = 1, Cap.
load on CLK and
RST is minimal,
else rise, fall times
are a factor
20 ns
δ Duty cycle for CLK CL = 35 pF,
48% < δIN 45
< 52% 55 %
12.5 Digital Signals
Symbol Parameter Condition Min Typ Max Unit
Digital I/O Except for OSC I/O
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 1.8 VDD + 0.3 V
VOL Output Low Voltage IOL = 2 mA 0.45 V
VOH Output High Voltage IOH = -1 mA VDD - 0.45 V
ROUT Pull-up resistor, OFF 20 kΩ
tSL Time from CS going high to
interface active 50 ns
tDZ Time from CS going low t o
interface inac tive, Hi-Z 50 ns
tIS Set-up time, control signals
to CS rising edge 50 ns
tSI Hold time, control signals
from CS rising edge 50 ns
tID Set-up time, control signals
to CS fall 50 ns
tDI Hold time, control signals
from CS fall 50 ns
|IIL1| Input Leakage Current GND < VIN < VDD -5 5 μA
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 23
Symbol Parameter Condition Min Typ Max Unit
Oscillator (XTALIN) I/O Parameters
VILXTAL Input Low Voltage - XTALIN -0.3 0.3 VDD V
VIHXTAL Input High Voltage - XTALIN 0.7 VDD VDD+0.3 V
IILXTAL Input Current - XTALIN GND < VIN < VDD -30 30 μA
fMAX Max freq. Osc or exter nal clock 27 MHz
δin External input duty cycle limit tR/F < 10% fIN,
45% < δCLK < 55% 48 52 %
12.6 DC Characteristics
Symbol Parameter Condition Min Typ Max Unit
ISupply Current on V
DD
Linear mode, I CC = 0
I/O, AUX1, AUX2 = high
DD 4.9 mA
Step up mode, I CC = 0
I/O, AUX1, AUX2 = high 4.7 mA
ISupply Current on V
DD_PD DD
PWRDN = 1,
Start/stop bit = 0
All digital inputs driven
with a true logical 0 or 1
in
Power Down mode 0.11 2.5 µA
12.7 Voltage / Temperature Fault Detecti on Ci rcuits
Symbol Parameter Condition Min Typ Max Unit
VV
DDF DD fault – VDD No external resistor on
VDDF_ADJ
Voltage
supervisor thresh ol d) 2.15 2.4 V
VV
CCF CC fault – VCC V
Voltage
supervisor thresh ol d CC 4.20 = 5 V 4.6 V
VCC 2.5 = 3 V 2.7 V
TDie over temperatu re fault
F 115 145 °C
ICard over current f aul t
CCF 100 150 mA
73S8023C Data Sheet DS_8023C_019
24 Rev. 1.5
13 Mechanical Drawing (32-QFN)
2.5
5
2.5
5
TOP VIEW
1
2
3
Figure 14: 32-QFN Mechanical Drawing
0.85 NOM.
/
0.9MAX. 0.00 / 0.005
0.20 REF.
SEATING
PLANE
SIDE VIEW
0.2 MIN.
0.35 / 0.45
1.5 / 1.875
3.0 / 3.75
0.18 / 0.3
BOTTOM VIEW
1
2
3
0.25
0.5
0.5
0.25
3.0 / 3.75
1.5 / 1.875
0.35 / 0.45
CHAMFERED
0.30
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 25
14 Package Pin Designation (32-QFN)
Use handling procedures necessary for a static sensitive component.
(Top View)
Figure 15: 32-QFN 73S8023C Pin Out
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
GND
LIN
VDD
NC
PRDWN
PRES
PRES
I/O
XTALOUT
XTALIN
OFF
GND
VDD
RSTIN
CMDVCC
VDDF_ADJ
AUX2
AUX1
GND
CLK
RST
VCC
CLKSEL
TERIDIAN
73S8023C
STROBE
CLKOUT
5V/3V
CLKDIV2
CLKDIV1
AUX2UC
AUX1UC
I/OUC
CS
73S8023C Data Sheet DS_8023C_019
26 Rev. 1.5
15 Ordering Information
Part Description Order Number Packaging Mark
73S8023C-QFN 32-pin Le ad-F ree QF N 73S8023C-IM/F 73S8023C
73S8023C-QFN 32-pin Le ad-Free QFN Tape / Reel 73S8023C-IMR/F 73S8023C
16 Related Documentation
The following 73S8023C documents are available from Teridian Semiconductor Corpor ation:
73S8023C Data Sheet (t his document)
73S8023C QFN Demo Board User’s Guide
17 Contact Information
For more informat i on about Teridian S em i conductor products or to check the availability of the
73S8023C, contact us at:
6440 Oak Canyon Ro ad
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: scr.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
DS_8023C_019 73S8023C Data Sheet
Rev. 1.5 27
Revision History
Revision Date Description
1.0
6/13/2005
First publication.
1.1
7/15/2005
Converted to Teridian format.
1.2
12/5/2007
Add EMV and ISO logo, remove leaded package option, change 32QFN
punched to SAWN p ackage.
1.3
1/17/2008
Changed dimension of bottom expos ed pad on 32QFN mec hanical package
figure.
1.4
1/8/2009
Added NDS logo to page 1 and assigned document number.
1.5
4/3/2009
Removed all references to VPC as VPC must be tied t o V DD.
© 2009 Teridian Semic onduct or Corpo rat ion. All rights reserved.
Teridian Semiconductor Corporation is a register ed trademark of Teridian Semiconductor Corporation.
Simplifying System Integrati on i s a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respecti ve owners.
Teridian Semiconductor Corporation makes no warr anty for the use of it s products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporat i on standard Terms
and Conditions. T he company assumes no responsibil i ty for any errors which may appear i n this
document, reserves the right to change devices or sp ecifications d etailed herein at any time without
notice and does not make any commitment to update the information contained herein. Ac cordingly, the
reader is cautioned t o verify that this document is current by comparing it t o the latest version on
http://www.teridian.com or by checking wit h your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd. , Suite 100, Irv ine, CA 92618
TEL (714) 508-8800, F A X (714) 508-8877, http://www.Teri di an.com
