SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
•Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
•Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ′ALS139 are dual 2-line to 4-line
decoders/demultiplexers designed for use in
high-performance memory-decoding or data-
routing applications requiring very short
propagation delay times. In high-performance
memory systems, these devices can minimize the
effects of system decoding. When employed with
high-speed memories utilizing a fast-enable
circuit, the delay times of these decoders and the
enable time of the memory are usually less than
the typical access time of the memory. Therefore,
the effective system delay introduced by the
Schottky-clamped system decoder is negligible.
The ′ALS139 comprise two individual 2-line to
4-line decoders in a single package. The
active-low enable (G) input can be used as a data
line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its
driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and
simplify system design.
The SN54ALS139 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS139 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE SELECT
OUTPUTS
ENABLE
GB A Y0 Y1 Y2 Y3
H X X H H H H
L L LLHHH
L LHHLHH
L HLHHLH
L HHHHHL
SN54ALS139 ...J PACKAGE
SN74ALS139 ...D OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2A
2B
NC
2Y0
2Y1
1B
1Y0
NC
1Y1
1Y2
SN54ALS139 . . . FK PACKAGE
(TOP VIEW)
1A
1G
NC
2Y3
2Y2 2G
1Y3
GND
NC
NC – No internal connection
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
GND
VCC
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols (alternatives)†
X/Y
1
2
1A 3
1B
13
2B
EN
1
15
14
2A
1Y0
4
0
1Y1
5
1
1Y2
6
2
1Y3
7
3
2Y0
12
2Y1
11
2Y2
10
2Y3
9
G3
0
1G
2G
DMUX
0
2
1A
1
3
1B
13
2B
1
15
14
2A
1Y0
4
0
1Y1
5
1
1Y2
6
2
1Y3
7
3
2Y0
12
2Y1
11
2Y2
10
2Y3
9
1G
2G
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
Select
Inputs
Select
Inputs 2B
2A
Enable 2G
1B
1A
Enable 1G
Data
Outputs
2Y3
2Y2
2Y1
2Y0
1Y3
1Y2
1Y1
1Y0
1
2
3
15
14
13
4
5
6
7
12
11
10
9
Pin numbers shown are for the D, J, and N packages.
SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54ALS139 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS139 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
SN54ALS139 SN74ALS139
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.7 0.8 V
IOH High-level output current –0.4 –0.4 mA
IOL Low-level output current 4 8 mA
TAOperating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS139 SN74ALS139
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VOH VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 V
VOL
VCC =45V
IOL = 4 mA 0.25 0.4 0.25 0.4
V
V
OL
V
CC =
4
.
5
V
IOL = 8 mA 0.35 0.5
V
IIVCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA
IO§VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
ICC VCC = 5.5 V 8 13 8 13 mA
‡All typical values are at VCC = 5 V, TA = 25°C.
§The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX¶UNIT
(INPUT)
(OUTPUT)
SN54ALS139 SN74ALS139
MIN MAX MIN MAX
tPLH
AorB
Y
317 3 14
ns
tPHL
A
or
B
Y
3 17 3 14
ns
tPLH
G
Y
317 3 14
ns
tPHL
G
Y
3 18 3 15
ns
¶For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B)
[
0 V
VOH
VOL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-87683012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87683012A
SNJ54ALS
139FK
5962-8768301EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768301EA
SNJ54ALS139J
5962-8768301FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768301FA
SNJ54ALS139W
SN54ALS139J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54ALS139J
SN74ALS139D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139DRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS139N
SN74ALS139N3 OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70
SN74ALS139NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74ALS139N
SN74ALS139NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SN74ALS139NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 ALS139
SNJ54ALS139FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87683012A
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SNJ54ALS
139FK
SNJ54ALS139J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768301EA
SNJ54ALS139J
SNJ54ALS139W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768301FA
SNJ54ALS139W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALS139DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74ALS139NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALS139DR SOIC D 16 2500 333.2 345.9 28.6
SN74ALS139NSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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