2012 Microchip Technology Inc. Preliminary DS41634A
PIC12F529T48A
Data Sheet
14-Pin, 8-Bit Flash Microcontrollers
DS41634A-page 2 Preliminary 2012 Microchip Technology Inc.
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Printed on recycled paper.
ISBN: 9781620762424
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2012 Microchip Technology Inc. Preliminary DS41634A-page 3
PIC12F529T48A
High-Performance RISC CPU:
• Only 34 Single-Word Instructions
• All Single-Cycle Instructions Except for Program
Branches which are Two-Cycle
• Four-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
for Data and Instructions
• Operating Speed:
- DC – 8 MHz internal clock
- DC – 500 ns instruction cycle
S pecial Microcontroller Features:
• 8 MHz Precision Internal Oscillator
- Factory calibrated to ±1%
• In-Circuit Serial Programming™ (ICSP™)
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with Dedicated On-Chip
RC Oscillator for Reliable Operation
• Programmable Code Protection
• Multiplexed MCLR Input Pin
• Internal Weak Pull-Ups on I/O Pins
• Power-Saving Sleep mode
• Wake-up from Sleep on Pin Change
• Selectable Oscillator Options:
- INTRC: 4 MHz or 8 MHz precision internal
RC oscillator
- EXTRC: External low-cost RC oscillator
- XT: Standard crystal/resonator
- LP: Power-saving, low-frequency crystal
Low-Power Features/CMOS Technology:
• Standby Current:
- 250 nA @ 2.0V, RF Sleep, typical
• Operating Current:
- 170 µA @ 4 MHz, 2.0V, RF Sleep, typical
- 9.17 mA @ 4 MHz, 2.0V, RF on at +0 dBm,
typical
- 16.67 mA @ 4 MHz, 2.0V, RF on at +10 dBm,
typical
• Watchdog Timer Current:
- 1 µA @ 2.0V, typical
• High Endurance Program and Flash Data
Memory Cells
- 100,000 write Flash program memory
endurance
- 1,000,000 write Flash data memory
endurance
- Program and Flash data retention: >40 years
• Fully Static Design
• Operating Voltage Range: 2.0V to 3.7V
- Industrial temperature range: -40°C to +85°C
RF Transmitter:
• Fully Integrated Transmitter
• FSK Operation up to 100 kbps
• OOK Operation up to 10 kbps
• Operation in 418, 434 and 868 MHz Bands:
- 8 selectable center frequencies
• Configurable Output Power: +10 dBm, 0 dBm
Peripheral Feat ures:
• 6 I/O Pins:
- 5 I/O pins with individual direction control
- 1 input-only pin
- High-current sink/source for direct LED drive
• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
14-Pin, 8-Bit Flash Microcontroller
PIC12F529T48A
DS41634A-page 4 Preliminary 2012 Microchip Technology Inc.
FIGURE 1: 14-PIN DIAGRAM, PIC12F529T48A
PIC12F529T48A
1
2
10
9
8
3
4
5
7
6
VDD
GB5/OSC1/CLKIN
GB4/OSC2
GB3/MCLR/VPP
Vss
GB0/ICSPDAT
GB1/ICSPCLK
GB2/T0CKI
XTAL
VDDRF
14
13
12
11
CTRL
RFOUT
DATA
VSSRF
TSSOP
Device
Program
Memory Data Memory
I/O RF Transmitter Compa rators Timers (8-bit) 8-bit A/D
Channels
Flash
(words) SRAM
(bytes) Flash
(bytes)
PIC12F529T48A 1536 201 64 6 1 0 1 0
2012 Microchip Technology Inc. Preliminary DS41634A-page 5
PIC12F529T48A
Table of Contents
1.0 General Description .................................................................................................................................................................. 7
2.0 PIC12F529T48A Device Varieties ........................................................................................................................................... 9
3.0 Architectural Overview............................................................................................................................................................ 11
4.0 Memory Organization ............................................................................................................................................................. 15
5.0 Flash Data Memory ................................................................................................................................................................ 23
6.0 I/O Port ................................................................................................................................................................................... 25
7.0 Timer0 Module and TMR0 Register ........................................................................................................................................ 33
8.0 Special Features Of The CPU ................................................................................................................................................ 39
9.0 RF Transmitter ........................................................................................................................................................................ 51
10.0 Instruction Set Summary ........................................................................................................................................................ 55
11.0 Development Support ............................................................................................................................................................. 63
12.0 Electrical Characteristics ........................................................................................................................................................ 67
13.0 DC and AC Characteristics Graphs and Charts ..................................................................................................................... 79
14.0 Packaging Information ............................................................................................................................................................ 87
Index ................................................................................................................................................................................................... 93
The Microchip Web Site ...................................................................................................................................................................... 95
Customer Change Notification Service ............................................................................................................................................... 95
Customer Support ............................................................................................................................................................................... 95
Reader Response ............................................................................................................................................................................... 96
Product Identification System ............................................................................................................................................................. 97
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PIC12F529T48A
DS41634A-page 6 Preliminary 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. Preliminary DS41634A-page 7
PIC12F529T48A
1.0 GENERAL DESCRIP T ION
The PIC12F529T48A device from Microchip
Technology is a low-cost, high-performance, 8-bit, fully-
static, Flash-based CMOS microcontroller. It employs a
RISC architecture with only 34 single-word/single-cycle
instructions. All instructions are single cycle except for
program branches, which take two cycles. The
PIC12F529T48A device delivers performance an order
of magnitude higher than their competitors in the same
price category. The 12-bit wide instructions are highly
symmetrical, resulting in a typical 2:1 code
compression over other 8-bit microcontrollers in its
class. The easy-to-use and easy to remember
instruction set reduces development time significantly.
The PIC12F529T48A product is equipped with special
features that reduce system cost and power
requirements. The Power-on Reset (POR) and Device
Reset Timer (DRT) eliminate the need for external
Reset circuitry. There are four oscillator configurations
to choose from including INTRC Internal Oscillator
mode and the power-saving LP (Low-power) Oscillator
mode. Power-Saving Sleep mode, Watchdog Timer
and code protection features improve system cost,
power and reliability.
The PIC12F529T48A device is available in the cost-
effective Flash programmable version, which is
suitable for production in any volume. The customer
can take full advantage of Microchip’s price leadership
in Flash programmable microcontrollers, while
benefiting from the Flash programmable flexibility.
The PIC12F529T48A product is supported by a full-
featured macro assembler, a software simulator, a low-
cost development programmer and a full-featured
programmer. All the tools are supported on PC and
compatible machines.
1.1 Applications
The PIC12F529T48A device fits in applications ranging
from personal care appliances and security systems to
low-power remote transmitters/receivers. The Flash
technology makes customizing application programs
(transmitter codes, appliance settings, receiver
frequencies, etc.) extremely fast and convenient. The
small footprint packages, for through hole or surface
mounting, make these microcontrollers perfect for
applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC12F529T48A device very versatile even
in areas where no microcontroller use has been
considered before (e.g., timer functions, logic and
programmable logic devices (PLDs) in larger systems
and coprocessor applications).
TABLE 1-1: FEATURES AND MEMORY OF PIC12F529T48A
PIC12F529T48A
Clock Maximum Frequency of Operation (MHz) 8
Memory Flash Program Memory 1536
SRAM Data Memory (bytes) 201
Flash Data Memory (bytes) 64
Peripherals Timer Module(s) TMR0
Wake-up from Sleep on Pin Change Yes
Features I/O Pins 5
Input Pins 1
Internal Pull-ups Yes
In-Circuit Serial Programming™ Yes
Number of Instructions 34
Packages 14-pin TSSOP
Note 1: The PIC12F529T48A device has Power-on Reset, selectable Watchdog Timer, selectable code-protect,
high I/O current capability and precision internal oscillator.
2: The PIC12F529T48A device uses serial programming with data pin GP0 and clock pin GP1.
PIC12F529T48A
DS41634A-page 8 Preliminary 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. Preliminary DS41634A-page 9
PIC12F529T48A
2.0 PIC12F529T48A DEVICE
VARIETIES
When placing orders, please use the PIC12F529T48A
Product Identification System at the back of this data
sheet to specify the correct part number. Depending on
application and production requirements, the proper
device option can be selected using the information in
this section.
2.1 Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for factory
production orders. This service is made available for
users who choose not to program medium-to-high
quantity units and whose code patterns have stabilized.
The devices are identical to the Flash devices but with
all Flash locations and fuse options already
programmed by the factory. Certain code and prototype
verification procedures do apply before production
shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.2 Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where a
few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
PIC12F529T48A
DS41634A-page 10 Preliminary 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. Preliminary DS41634A-page 11
PIC12F529T48A
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC12F529T48A device
can be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC12F529T48A device uses a Harvard
architecture in which program and data are accessed
on separate buses. This improves bandwidth over tra-
ditional von Neumann architectures where program
and data are fetched on the same bus. Separating
program and data memory further allows instructions
to be sized differently than the 8-bit wide data word.
Instruction opcodes are 12 bits wide, making it possi-
ble to have all single-word instructions. A 12-bit wide
program memory access bus fetches a 12-bit instruc-
tion in a single cycle. A two-stage pipeline overlaps
fetch and execution of instructions. Consequently, all
instructions (34) execute in a single cycle (500 ns @
8MHz, 1s @ 4 MHz) except for program branches.
Table 3-1 below lists memory supported by the
PIC12F529T48A device.
TABLE 3-1: PIC12F52 9T48 A MEMO RY
The PIC12F529T48A device can directly or indirectly
address its register files and data memory. All Special
Function Registers (SFR), including the PC, are
mapped in the data memory. The PIC12F529T48A
device has a highly orthogonal (symmetrical) instruc-
tion set that makes it possible to carry out any opera-
tion, on any register, using any addressing mode. This
symmetrical nature and lack of “special optimal situa-
tions” make programming with the PIC12F529T48A
device simple, yet efficient. In addition, the learning
curve is reduced significantly.
The PIC12F529T48A device contains an 8-bit ALU and
working register. The ALU is a general purpose arith-
metic unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
The ALU is 8 bits wide and capable of addition,
subtraction, shift and logical operations. Unless other-
wise mentioned, arithmetic operations are two’s
complement in nature. In two-operand instructions, one
operand is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-2 .
Device
Program
Memory Data Memory
Flash
(words) SRAM
(bytes)
Flash
Data
(bytes)
PIC12F529T48A 1536 201 64
PIC12F529T48A
DS41634A-page 12 Preliminary 2012 Microchip Technology Inc.
FIGURE 3-1: PI C12F52 9T48A ARCHITECTURAL BLOCK DIAGRAM
CP
PA
M/N
PFD
Sigma/
Delta
DATA
Control LogicCTRL
RF
OUT
V
DDRF
V
SSRF
XTAL
Flash
Program
Memory
11 Data Bus 8
12
Program
Bus
Instruction reg
Program Counter
RAM
GPR
Direct Addr
0-4
RAM Addr 8
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Device Reset
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2
MCLR
VDD, VSS
Timer0
PORTB
8
8
GB4/OSC2
GB3/MCLR/VPP
GB2/T0CKI
GB1/ICSPCLK
0-7
3
GB5/OSC1/CLKIN
STACK1
STACK2
201
Internal RC
Clock
1.5K x 12
bytes
Timer
Self-write
64x8
STACK3
STACK4
BSR 5-7
3
GB0/ICSPDAT
Note 1: 201-byte GPR in PIC12F529T48A, including linear RAM.
2: FSR and direct addressing differs from standard baseline parts.
2012 Microchip Technology Inc. Preliminary DS41634A-page 13
PIC12F529T48A
TABLE 3-2: PIC12F529T48A PINOUT DESCRIPTION
Name Function Type Input Type Output Type Description
GP0/ICSPDAT GP0 I/O TTL CMOS Bidirectional I/O port with weak pull-up.
ICSPDAT I/O ST CMOS ICSP™ mode Schmitt Trigger.
GP1/ICSPCLK GP1 I/O TTL CMOS Bidirectional I/O port with weak pull-up.
ICSPCLK I ST — ICSP™ mode Schmitt Trigger.
GP2/T0CKI GP2 I/O TTL CMOS Bidirectional I/O port.
T0CKI I ST — Timer0 clock input.
GP3/MCLR/VPP GP3 I TTL — Standard TTL input with weak pull-up.
MCLR IST —MCLR input (weak pull-up always enabled in
this mode).
VPP I High Voltage — Test mode high voltage pin.
GP4/OSC2 GP4 I/O TTL CMOS Bidirectional I/O port.
OSC2 O — XTAL XTAL oscillator output pin.
GP5/OSC1/
CLKIN
GP5 I/O TTL CMOS Bidirectional I/O port.
OSC1 I XTAL — XTAL oscillator input pin.
CLKIN I ST — EXTRC Schmitt Trigger input.
VDD VDD P — — Positive supply for logic and I/O pins.
VSS VSS P — — Ground reference for logic and I/O pins.
VDDRF VDDRF P Power — RF Power Supply.
CTRL CTRL I CMOS — Configuration Selection and Configuration
Clock.
RFOUT RFOUT — — RF Transmitter RF output.
VSSRF VSSRF P Power — RF Power Supply.
DATA DATA I/O CMOS CMOS Configuration Data and Transmit Data.
XTAL XTAL — XTAL — Crystal Oscillator.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog Voltage
PIC12F529T48A
DS41634A-page 14 Preliminary 2012 Microchip Technology Inc.
3.1 Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2 and Example 3-1.
3.2 Instruction Flow/Pipel ining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO), then two cycles
are required to complete the instruction (Example 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC PC PC + 1 PC + 2
Fetch INST (PC)
Execute INST (PC - 1) Fetch INST (PC + 1)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 1)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 03H Fetch 1 Execute 1
2. MOVWF GPIO Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF GPIO, 1 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
2012 Microchip Technology Inc. Preliminary DS41634A-page 15
PIC12F529T48A
4.0 MEMORY ORGANIZATION
The PIC12F529T48A memory is organized into
program memory and data memory (SRAM). The self-
writable portion of the program memory called Flash
data memory, is located at addresses 600h-63Fh. As
the device has more than 512 bytes of program
memory, a paging scheme is used. Program memory
pages are accessed using STATUS register bit, PA0.
For the PIC12F529T48A, with data memory register
files of more than 32 registers, a banking scheme is
used. Data memory banks are accessed using the File
Select Register (FSR).
4.1 Program Memory Orga nization for
the PIC12F529T48A
The PIC12F529T48A device has an 11-bit Program
Counter (PC) capable of addressing a 2K x 12 program
memory space.
Only the first 1.5K x 12 (0000h-05FFh) are physically
implemented (see Figure 4-1). Accessing a location
above these boundaries will cause a wrap-around
within the 1.5K x 12 space. The effective Reset vec-
tor is a 0000h (see Figure 4-1). Location 05FFh con-
tains the internal clock oscillator calibration value.
This value should never be overwritten.
FIGURE 4-1: MEMORY MAP
CALL, RETLW
PC<11:0>
Stack Level 1
Stack Level 2
User Memory
Space
10
0000h
07FFh
01FFh
0200h
On-chip Program
Memory
Reset Vector(1)
Note 1: Address 0000h becomes the effective
Reset vector. Location 05FFh contains
the MOVLW XX internal oscillator
calibration value.
2: Flash data memory is non-executable.
512 Word
512 Word 03FFh
0400h
On-chip Program
Memory
Flash Data Memory(2)
063Fh
0640h
Flash Data Memory
Space
Stack Level 3
Stack Level 4
512 Word
On-chip Program
Memory
05FFh
0600h
PIC12F529T48A
DS41634A-page 16 Preliminary 2012 Microchip Technology Inc.
4.2 Data Memory (SRAM and FSRs)
Data memory is composed of registers or bytes of
SRAM. Therefore, data memory for a device is
specified by its register file. The register file is divided
into two functional groups: Special Function Registers
(SFR) and General Purpose Registers (GPR).
The Special Function Registers include the TMR0
register, the Program Counter Low (PCL), the STATUS
register, the I/O register (port) and the File Select
Register (FSR). In addition, the EECON, EEDATA and
EEADR registers provide for interface with the Flash
data memory.
The PIC12F529T48A register file is composed of 10
Special Function Registers and 201 General Purpose
Registers.
4.2.1 GENERAL PURPOSE REGISTER
FILE
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.8 “Indirect Data Addressing:
INDF and FSR Registers”.
FIGURE 4-2: REGISTER FILE MAP
File Address
00h
01h
02h
03h
04h
05h
06h
1Fh
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTB
10h
Bank 0 Bank 1 Bank 2 Bank 3
3Fh
30h
20h
5Fh
50h
40h
7Fh
70h
60h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
Note 1: Not a physical register.
BSR<2:0> 000 001 010 011
2Fh 4Fh 6Fh
0Fh
INDF(1)
EECON
PCL
STATUS
FSR
EEDATA
EEADR
Addresses map back to
addresses in Bank 0.
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTB
INDF(1)
EECON
PCL
STATUS
FSR
EEDATA
EEADR
9Fh
Linear
General
Purpose
Registers
100 101 110
80h A0h C0h
BFh DFh
Bank 4 Bank 5 Bank 6
Linear
General
Purpose
Registers
Linear
General
Purpose
Registers
Linear
General
Purpose
Registers
E0h
FFh
Bank 7
111
07h
2012 Microchip Technology Inc. Preliminary DS41634A-page 17
PIC12F529T48A
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (Table 4-1).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
4.2.3 LINEAR RAM
The last four banks, addresses 0x80 to 0xFF, are
general purpose RAM registers, unbroken by SFRs.
This region is ideal for indirect access using the FSR
and INDF registers.
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Note: Unlike other baseline devices, the FSR
register does not contain bank bits and,
therefore, does not affect direct
addressing schemes. The FSR/INDF
registers have full access to RAM.
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
Power-on
Reset
N/A TRISGPIO —— TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 --11 1111
N/A OPTION Contains Control Bits to Configure Timer0 and Timer0/WDT Prescaler 1111 1111
N/A BSR — — — — — BSR<2:0> ---- -000
00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx
01h TMR0 Timer0 Module Register xxxx xxxx
02h(1) PCL Low Order 8 bits of PC 1111 1111
03h STATUS GPWUF PA1 PA0 TO PD ZDCC0001 1xxx
04h FSR Indirect Data Memory Address Pointer xxxx xxxx
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —1111 111-
06h GPIO —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx
21h EECON — — — FREE WRERR WREN WR RD ---0 x000
25h EEDATA EEDATA7 EEDATA6 EEDATA5 EEDATA4 EEDATA3 EEDATA2 EEDATA1 EEDATA0 xxxx xxxx
26h EEADR —— EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 --xx xxxx
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused
Note 1: The upper byte of the Program Counter is not directly accessible. See Sect ion 4.6 “Progr am Cou nter ” for an explanation of how to
access these bits.
PIC12F529T48A
DS41634A-page 18 Preliminary 2012 Microchip Technology Inc.
4.3 STATUS register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF instructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, DC or C bits
from the STATUS register. For other instructions which
do affect Status bits, see Section 10.0 “Instruction
Set Summary”.
REGISTER 4-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
GPWUF PA1 PA0 TO PD ZDCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GPWUF: Wake-up From Sleep on Pin Change bit
1 = Reset due to wake-up from Sleep on pin change
0 = After power-up or other Reset
bit 6-5 PA<1:0>: Program Page Preselect bits(1)
00 = Page 0 (000h-1FFh)
01 = Page 1 (200h-3FFh)
10 = Page 2 (400h-5FFh)
11 = Reserved. Do not use.
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF: SUBWF: RRF or RLF:
1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred
Note 1: Do not set both PA0 and PA1.
2012 Microchip Technology Inc. Preliminary DS41634A-page 19
PIC12F529T48A
4.4 OPTION Register
The OPTION register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION regis-
ter. A Reset sets the OPTION<7:0> bits.
Note: If the T0SC bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-2: OPTION: OPTION REGISTER
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 GPWU: Enable Wake-up On Pin Change bit
1 = Disabled
0 = Enabled
bit 6 GPPU: Enable Weak Pull-Ups bit
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
PIC12F529T48A
DS41634A-page 20 Preliminary 2012 Microchip Technology Inc.
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used
to calibrate the 8 MHz internal oscillator macro. It
contains seven bits of calibration that uses a two’s
complement scheme for controlling the oscillator speed.
See Register 4-3 for details.
REGISTER 4-3: OSCCAL: OSCILLATOR CALIBRATION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0
CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 CAL<6:0>: Oscillator Calibration bits
0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 = Minimum frequency
bit 0 Unimplemented: Read as ‘0’
2012 Microchip Technology Inc. Preliminary DS41634A-page 21
PIC12F529T48A
4.6 Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits <8:0> of the PC are pro-
vided by the GOTO instruction word. The Program
Counter (PCL) is mapped to PC<7:0>. Bits 5 and 6 of
the STATUS register provide page information to bits 9
and 10 of the PC. (Figure 4-3).
For a CALL instruction, or any instruction where the
PCL is the destination, bits <7:0> of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-3).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PCL, ADDWF PCL
and B SF PCL,5.
FIGURE 4-3: LOADING OF PC
BRANCH INSTRUCTIONS
4.6.1 EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
The STATUS register page preselect bits are cleared
upon a Reset, which means that page 0 is pre-selected.
Therefore, upon a Reset, a GOTO instruction will
automatically cause the program to jump to page 0 until
the value of the page bits is altered.
4.7 Stack
The PIC12F529T48A device has a four-deep, 12-bit
wide hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack
1 into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than four
sequential CALLs are executed, only the most recent
four return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into Stack Level 1. If more than four sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2. Note that
the W register will be loaded with the literal value
specified in the instruction. This is particularly useful for
the implementation of data look-up tables within the
program memory.
Note: Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
PA<1:0>
Status
PC
87 0
PCL
910
Instruction Word
70
GOTO Instruction
CALL or Modify PCL Instruction
PA<1:0>
Status
PC
87 0
PCL
910
Instruction Word
70
Reset to ‘0’
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
PIC12F529T48A
DS41634A-page 22 Preliminary 2012 Microchip Technology Inc.
4.8 Indirect Data Addressing: INDF
and FSR Registers
The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although Status bits may be affected).
The FSR is an 8-bit wide register. It is used in conjunc-
tion with the INDF Register to indirectly address the
data memory area.
EXAMPLE 4-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
FIGURE 4-4: DIRECT/INDI RECT ADDRE SS ING
4.9 Direct Data Addressing
Banking when using direct addressing methods is
accomplished using the MOVLB instruction to write to the
BSR. The BSR, like the OPTION register, is not
mapped to user-accessable memory. The value in BSR
has no effect on indirect addressed operations.
MOVLW 0x10 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;clear INDF
;register
INCF FSR,F ;inc pointer
BTFSC FSR,4 ;all done?
GOTO NEXT ;NO, clear next
CONTINUE : ;YES, continue
:
Location Select
Location Select
Bank Select
Indirect Addressing
Direct Addressing
Data
Memory
0Fh
10h
Bank 0 Bank 1 Bank 2 Bank 3
0
4
5
6
(FSR)
010
000 001 011
00h
1Fh
(opcode)
04
67
(BSR)
Addresses map back to
addresses in Bank 0/1
321
321
57
100 101 110 111
Bank 4 Bank 5 Bank 6 Bank 7
2012 Microchip Technology Inc. Preliminary DS41634A-page 23
PIC12F529T48A
5.0 FLASH DATA MEMORY
CONTROL
The Flash data memory is readable and writable during
normal operation (full VDD range). This memory is not
directly mapped in the register file space. Instead, it is
indirectly addressed through the Special Function
Registers (SFRs).
5.1 Reading Flash Data Memory
To read a Flash data memory location the user must:
• Write the EEADR register
• Set the RD bit of the EECON register
The value written to the EEADR register determines
which Flash data memory location is read. Setting the
RD bit of the EECON register initiates the read. Data
from the Flash data memory read is available in the
EEDATA register immediately. The EEDATA register
will hold this value until another read is initiated or it is
modified by a write operation. Program execution is
suspended while the read cycle is in progress. Execu-
tion will continue with the instruction following the one
that sets the WR bit. See Example 5-1 for sample code.
EXAMPLE 5-1: READING FROM FLASH
DATA MEMORY
5.2 Wr it ing and Erasing Flash Data
Memory
Flash data memory is erased one row at a time and
written one byte at a time. The 64-byte array is made
up of eight rows. A row contains eight sequential bytes.
Row boundaries exist every eight bytes.
Generally, the procedure to write a byte of data to Flash
data memory is:
1. Identify the row containing the address where
the byte will be written.
2. If there is other information in that row that must
be saved, copy those bytes from Flash data
memory to RAM.
3. Perform a row erase of the row of interest.
4. Write the new byte of data and any saved bytes
back to the appropriate addresses in Flash data
memory.
To prevent accidental corruption of the Flash data
memory, an unlock sequence is required to initiate a
write or erase cycle. This sequence requires that the bit
set instructions used to configure the EECON register
happen exactly as shown in Example 5-2 and
Example 5-3, depending on the operation requested.
5.2.1 ERASING FLASH DATA MEMORY
A row must be manually erased before writing new
data. The following sequence must be performed for a
single row erase.
1. Load EEADR with an address in the row to be
erased.
2. Set the FREE bit to enable the erase.
3. Set the WREN bit to enable write access to the
array.
4. Set the WR bit to initiate the erase cycle.
If the WREN bit is not set in the instruction cycle after
the FREE bit is set, the FREE bit will be cleared in
hardware.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Example 5-2.
Program execution is suspended while the erase cycle
is in progress. Execution will continue with the instruc-
tion following the one that sets the WR bit.
EXAMPLE 5-2: ERASIN G A FLASH DATA
MEMORY ROW
Note: Only a BSF command will work to enable
the Flash data memory read documented in
Example 5-1. No other sequence of
commands will work, no exceptions.
BANKSEL EEADR ;
MOVF DATA_EE_ADDR, W ;
MOVWF EEADR ;Data Memory
;Address to read
BANKSEL EECON1 ;
BSF EECON, RD ;EE Read
MOVF EEDATA, W ;W = EEDATA
Note 1: The FREE bit may be set by any com-
mand normally used by the core. How-
ever, the WREN and WR bits can only be
set using a series of BSF commands, as
documented in Example 5-1. No other
sequence of commands will work, no
exceptions.
2: Bits <5:3> of the EEADR register indicate
which row is to be erased.
BANKSEL EEADR
MOVLW EE_ADR_ERASE ; LOAD ADDRESS OF ROW TO
; ERASE
MOVWF EEADR ;
BSF EECON,FREE ; SELECT ERASE
BSF EECON,WREN ; ENABLE WRITES
BSF EECON,WR ; INITITATE ERASE
PIC12F529T48A
DS41634A-page 24 Preliminary 2012 Microchip Technology Inc.
5.2.2 WRITING TO FLASH DATA
MEMORY
Once a cell is erased, new data can be written.
Program execution is suspended during the write cycle.
The following sequence must be performed for a single
byte write.
1. Load EEADR with the address.
2. Load EEDATA with the data to write.
3. Set the WREN bit to enable write access to the
array.
4. Set the WR bit to initiate the erase cycle.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Example 5-3.
EXAMPLE 5-3: WRITING A FLASH DATA
MEMORY ROW
5.3 Write Verify
Depending on the application, good programming
practice may dictate that data written to the Flash data
memory be verified. Example 5-4 is an example of a
write verify.
EXAMPLE 5-4: WRITE VERIFY OF DATA
EEPROM
5.4 Code Protection
Code protection does not prevent the CPU from
performing read or write operations on the Flash data
memory. Refer to the code protection chapter for more
information.
Note 1: Only a series of BSF commands will work
to enable the memory write sequence
documented in Example 5-2. No other
sequence of commands will work, no
exceptions.
2: For reads, erases and writes to the Flash
data memory, there is no need to insert a
NOP into the user code as is done on
mid-range devices. The instruction imme-
diately following the “BSF EECON,
WR/RD” will be fetched and executed
properly.
BANKSEL EEADR
MOVLW EE_ADR_WRITE ; LOAD ADDRESS
MOVWF EEADR ;
MOVLW EE_DATA_TO_WRITE ; LOAD DATA
MOVWF EEDATA ; INTO EEDATA REGISTER
BSF EECON,WREN ; ENABLE WRITES
BSF EECON,WR ; INITITATE ERASE
MOVF EEDATA, W ;EEDATA has not changed
;from previous write
BSF EECON, RD ;Read the value written
XORWF EEDATA, W ;
BTFSS STATUS, Z ;Is data the same
GOTO WRITE_ERR ;No, handle error
;Yes, continue
2012 Microchip Technology Inc. Preliminary DS41634A-page 25
PIC12F529T48A
6.0 I/O PORT
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
6.1 GPIO
GPIO is an 8-bit I/O register. Only the low-order 6 bits
are used (GP<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s. Please note that GP3 is an input-only
pin. The Configuration Word can set several I/O’s to
alternate functions. When acting as alternate functions,
the pins will read as ‘0’ during a port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also for wake-up on change. The wake-up on
change and weak pull-up functions are not pin select-
able. If GP3/MCLR is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not enabled.
6.2 TRIS Registers
The Output Driver Control registers are loaded with
the contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRISGPIO register bit puts the
corresponding output driver in a high-impedance
(Input) mode. A ‘0’ puts the contents of the output data
latch on the selected pins, enabling the output buffer.
The TRISGPIO register is “write-only”. Bits <5:0> are
set (output drivers disabled) upon Reset.
TABLE 6-1: WEAK PULL-UP ENABLED
PINS
Note: If the T0CS bit is set to ‘1’, it will override
the TRISGPIO function on the T0CKI pin.
Pin WPU WU
GP0 Y Y
GP1 Y Y
GP2 N N
GP3 Y(1) Y
GP4 N N
GP5 N N
Note1: When MCLRE = 1, the weak pull-up on
GP3/MCLR is always enabled.
2: WPU = Weak pull-up; WU = Wake-up.
PIC12F529T48A
DS41634A-page 26 Preliminary 2012 Microchip Technology Inc.
REGISTER 6-1: GPIO: GPIO REGISTER
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— GP5 GP4 GP3 GP2 GP1 GP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 GP<5:0>: GPIO I/O Pin bits
1 = GPIO pin is >VIH min.
0 = GPIO pin is <VIL max.
REGISTER 6-2: TRISGPIO: TRI-STATE GPIO REGISTER
U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1
—— TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TRISGPIO<5:0>: GPIO Tri-State Control bits
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output
2012 Microchip Technology Inc. Preliminary DS41634A-page 27
PIC12F529T48A
6.3 I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 6-1. All port pins, except GP3 which is input
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRISGPIO must be cleared (= 0). For use
as an input, the corresponding TRISGPIO bit must be
set. Any I/O pin (except GP3) can be programmed
individually as input or output.
FIGURE 6-1: PIC12F529T 48 A EQUI VALE NT CIRCUIT FOR I/O PINS – GP0/GP1
VDD VDD
I/O
Pin
VSS
Pin Change
QD
Wake-up
on change
Latch
Q
D
Q
Q
D
CK Q
Data Latch
TRIS Latch
RD Port
TRIS ‘F’
WREG
WR
Data
GPPU
CK
CK
GP0/ICSPDAT GP1/ICSPCLK
• General purpose I/O • General purpose I/O
• In-Circuit Serial Programming™ data • In-circuit Serial Programming™ clock
• Wake-up on input change trigger • Wake-up on input change trigger
PIC12F529T48A
DS41634A-page 28 Preliminary 2012 Microchip Technology Inc.
FIGURE 6-2: GP2 / TOCK1
VDD
I/O
Pin
VSS
Q
D
Q
Q
D
CK Q
Data Latch
TRIS Latch
RD Port
TRIS ‘F’
WREG
WR
Data
CK
To Tim e r 0
TOCS
• General Purpose I/O
• A Clock Input for Timer0
2012 Microchip Technology Inc. Preliminary DS41634A-page 29
PIC12F529T48A
FIGURE 6-3: GP4 / OSC2
VDD
I/O
Pin
VSS
Q
D
Q
Q
D
CK Q
Data Latch
TRIS Latch
RD
PORT
TRIS ‘F’
WREG
WR
PORT
DATA
BUS
CK
INTOSC
RC
From OSC1 Oscillator Circuit
• General Purpose I/O
• A crystal resonator connection
PIC12F529T48A
DS41634A-page 30 Preliminary 2012 Microchip Technology Inc.
FIGURE 6-4: GP5 / OSC1/ CLKIN
VDD
I/O
Pin
VSS
Q
D
Q
Q
D
CK Q
Data Latch
TRIS Latch
RD
PORT
TRIS ‘F’
WREG
WR
PORT
DATA
BUS
CK
From OSC2 Oscillator Circuit
• General Purpose I/O
• A crystal resonator connection
• A clock input
2012 Microchip Technology Inc. Preliminary DS41634A-page 31
PIC12F529T48A
FIGURE 6-5: GP3 (WITH WEAK PULL-
UP AND WAKE-UP ON
CHANGE)
TABLE 6-2: SUMMARY OF PORT REGISTERS
Data Bus
RD Port
Note 1: GP3/MCLR pin has a protection diode to VSS
only.
GPPU
D
CK
Q
Pin Change
MCLRE
Reset
Input Pin(1)
Weak
VSS
Wake-up
on change
latch
Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0 Register
on Page
GPIO —— GP5 GP4 GP3 GP2 GP1 GP0 26
TRISGPIO —— TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 26
STATUS GPWUF PA1 PA0 TO PD ZDCC18
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 19
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, Shaded cells = unimplemented, read as ‘0’,
q = depends on the condition
PIC12F529T48A
DS41634A-page 32 Preliminary 2012 Microchip Technology Inc.
6.4 I/O Programming Considerations
6.4.1 BIDIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit 5 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit 5 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bidirectional
I/O pin (say bit 0) and it is defined as an input at this
time, the input signal present on the pin itself would be
read into the CPU and rewritten to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
Example 6-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The resulting high output currents may damage
the chip.
EXAMPLE 6-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
6.4.2 SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 6-6).
Therefore, care must be exercised if a write, followed by
a read operation, is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
FIGURE 6-6: SUCCESSIVE I/O OPERATION
;Initial GPIO Settings
;GPIO<5:3> Inputs
;GPIO<2:0> Outputs
;
; GPIO latch GPIO pins
; ---------- ----------
BCF GPIO, 5 ;--01 -ppp --11 pppp
BCF GPIO, 4 ;--10 -ppp --11 pppp
MOVLW 007h;
TRIS GPIO ;--10 -ppp --11 pppp
;
Note 1: The user may have expected the pin values to
be ‘--00 pppp’. The 2nd BCF caused GP5 to
be latched as the pin value (High).
PC PC + 1 PC + 2 PC + 3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
GP<5:0>
MOVWF GPIO NOP
Port pin
sampled here
NOPMOVF GPIO, W
Instruction
Executed MOVWF GPIO
(Write to GPIO) NOPMOVF PORTB,W
This example shows a write to GPIO followed
by a read from GPIO.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
(Read PORTB)
Port pin
written here
2012 Microchip Technology Inc. Preliminary DS41634A-page 33
PIC12F529T48A
7.0 TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two cycles (Figure 7-2 and Figure 7-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge. Restric-
tions on the external clock input are discussed in detail
in Section7.1 “Using Timer0 with an External
Clock”.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 7.2 “Prescaler” details
the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
The Timer0 contained in the CPU core follows the
standard baseline definition.
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer.
T0CKI
T0SE(1)
0
1
1
0
Pin
T0CS(1)
FOSC/4
Programmable
Prescaler(2)
Sync with
Internal
Clocks
TMR0 Reg
PSout
(2-cycle delay)
PSout
Data Bus
8
PSA(1)
PS2, PS1, PS0(1)
3
Sync
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
PIC12F529T48A
DS41634A-page 34 Preliminary 2012 Microchip Technology Inc.
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter 33*
N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 19
N/A TRISGPIO —— TRISGPIO5 TRISGPIO4 TRISGPIO3 TRISGPIO2 TRISGPIO1 TRISGPIO0 26
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, Shaded cells = unimplemented, read as ‘0’
* Page provides register information.
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 NT0 NT0 + 1
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
2012 Microchip Technology Inc. Preliminary DS41634A-page 35
PIC12F529T48A
7.1 Using Timer0 with an External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.1.1 EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 7-4).
Therefore, it is necessary for T0CKI to be high for at
least two TOSC (and a small RC delay of two Tt0H) and
low for at least two T
OSC (and a small RC delay of two
Tt0H). Refer to the electrical specification of the
desired device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI to have a period of
at least four TOSC (and a small RC delay of four Tt0H)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
7.1.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 7-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOCK
Increment Timer0 (Q4)
External Clock Input or
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
External Clock/Prescaler
Output After Sampling (3)
Prescaler Output (2)
(1)
Note 1: Delay from clock input change to Timer0 increment is three TOSC to seven TOSC. (Duration of Q = TOSC). Therefore,
the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the times at which sampling occurs.
PIC12F529T48A
DS41634A-page 36 Preliminary 2012 Microchip Technology Inc.
7.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 8.6 “Watch-
dog Timer (WDT)”). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0,
MOVWF TMR0, etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT. The prescaler is neither
readable nor writable. On a Reset, the prescaler
contains all ‘0’s.
7.2.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on-the-fly” during program
execution). To avoid an unintended device Reset, the
following instruction sequence (Example 7-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0 WDT)
To change the prescaler from the WDT to the Timer0
module, use the sequence shown in Example 7-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
EXAMPLE 7-2: CHANGING PRESCALER
(WDT TIMER0)
Note: The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and Prescaler
MOVLW b‘00xx1111’
OPTION
CLRWDT ;PS<2:0> are 000 or 001
MOVLW b‘00xx1xxx’ ;Set Postscaler to
OPTION ;desired WDT rate
CLRWDT ;Clear WDT and
;prescaler
MOVLW b‘xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
OPTION
2012 Microchip Technology Inc. Preliminary DS41634A-page 37
PIC12F529T48A
FIGURE 7-5: BLOCK DIAGRAM OF THE TIME R0/WDT PRESCALER(1)
T0CKI
T0SE
Pin
TCY (= FOSC/4)
Sync
2
Cycles
TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
MUX
Watchdog
Timer
PSA
01
0
1
WDT
Time-Out
PS<2:0>
8
PSA
WDT Enable bit
0
1
0
1
Data Bus
8
PSA
T0CS
M
U
XM
U
X
U
X
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
PIC12F529T48A
DS41634A-page 38 Preliminary 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. Preliminary DS41634A-page 39
PIC12F529T48A
8.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other processors
are special circuits that deal with the needs of real-time
applications. The PIC12F529T48A microcontroller has
a host of such features intended to maximize system
reliability, minimize cost through elimination of external
components, provide power-saving operating modes
and offer code protection. These features are:
• Oscillator Selection
• Reset:
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
The PIC12F529T48A device has a Watchdog Timer,
which can be shut off only through Configuration bit
WDTE. It runs off of its own RC oscillator for added
reliability. If using XT or LP selectable oscillator options,
there is always an 18 ms (nominal) delay provided by
the Device Reset Timer (DRT), intended to keep the
chip in Reset until the crystal oscillator is stable. If using
INTRC or EXTRC, the DRT provides a 1 ms (nominal)
delay.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up the device
from Sleep through a change-on-input-pin or through a
Watchdog Timer time-out. Several oscillator options are
also made available to allow the part to fit the
application, including an internal 4 MHz or 8 MHz
oscillator. The EXTRC oscillator option saves system
cost while the LP crystal option saves power. A set of
Configuration bits are used to select various options.
8.1 Configuration Bits
The PIC12F529T48A Configuration Words consist of
12 bits. Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type; one bit is the Watchdog
Timer enable bit, one bit is the MCLR enable bit and six
bits are for code protection (Register 8-1).
PIC12F529T48A
DS41634A-page 40 Preliminary 2012 Microchip Technology Inc.
REGISTER 8-1: CONFIG: CONFIGURATION WORD REGISTER(1)
U-1 P-1 P-1 P-1 P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
— CP3 CP2 CP1 CP0 CPDF IOSCFS MCLRE CP WDTE FOSC1 FOSC0
bit 11 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 11 Unimplemented: Read as ‘1’
bit 10-7 CP<3:0>: Enhanced Code Protect bits
1011 = Code protect disabled
0010 = Code protect enabled
All others = Memory access disabled(3)
bit 6 CPDF: Code Protection bit – Flash Data Memory
1 = Code protection off
0 = Code protection on
bit 5 IO SCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 4 MCLRE: Master Clear Enable bit
1 =GP3/MCLR pin functions as MCLR
0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD
bit 3 CP: Configuration Word Parity bit(4)
1 = Parity bit set
0 = Parity bit clear
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC<1:0>: Oscillator Selection bits
00 = LP oscillator with 18 ms DRT(2)
01 = XT oscillator with 18 ms DRT(2)
10 = INTRC with 1 ms DRT(2)
11 = EXTRC with 1 ms DRT(2)
Note 1: Refer to the “PIC12F529T48A Memory Programming Specification”, DS41619 to determine how to
program/erase the Configuration Word.
2: DRT length (18 ms or 1 ms) is a function of clock mode selection. It is the responsibility of the application
designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in
acceptable operation. Refer to Figure 12-1 for VDD rise time and stability requirements for this mode of
operation.
3: See Section 8.9 “Program Verification/Code Protection”.
4: Set or clear to create odd parity with Configuration Word excluding CP<3:0>.
2012 Microchip Technology Inc. Preliminary DS41634A-page 41
PIC12F529T48A
8.2 Oscillator Configurations
8.2.1 OSCILLATOR TYPES
The PIC12F529T48A device can be operated in up to
four different oscillator modes. The user can program
using the Configuration bits (FOSC<1:0>), to select one
of these modes:
• LP: Low-Power Crystal
• XT: Crystal/Resonator
• INTRC: Internal 4 MHz or 8 MHz Oscillator
• EXTRC: External Resistor/Capacitor
8.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT or LP modes, a crystal or ceramic resonator is
connected to the (GP5)/OSC1/(CLKIN) and
(GP4)/OSC2 pins to establish oscillation (Figure 8-1).
The PIC12F529T48A oscillator designs require the use
of a parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications. When in XT or LP modes, the device can
have an external clock source drive the
(GP5)/OSC1/CLKIN pin (Figure 8-2). When the part is
used in this fashion, the output drive levels on the OSC2
pin are very weak. This pin should be left open and
unloaded. Also when using this mode, the external clock
should observe the frequency limits for the clock mode
chosen (XT or LP).
FIGURE 8-1: CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
(XT OR LP OSC
CONFIGURATION)
FIGURE 8-2: EXTERNAL CLOCK INPUT
OPERATION (XT OR LP
OSC CONFIGURATION)
T ABLE 8-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS (1)
T ABLE 8-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR –
PIC12F529T48A(2)
Note 1: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capaci-
tor values and/or the Oscillator mode
may be required.
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF approx. value = 10 M.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3) Sleep
To internal
logic
RS(2)
PIC12F529T48A
Osc.
Type Resonator
Freq. Cap. Range
C1 Cap. Range
C2
XT 4.0 MHz 30 pF 30 pF
Note 1: Component values shown are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external compo-
nents.
Osc.
Type Resonator
Freq. Cap.Range
C1 Cap. Range
C2
LP 32 kHz(1) 15 pF 15 pF
XT 200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
Note 1: For VDD > 4.5V, C1 = C2 30 pF is
recommended.
2: Component values shown are for design
guidance only. Rs may be required to
avoid overdriving crystals with low drive
level specification. Since each crystal has
its own characteristics, the user should
consult the crystal manufacturer for
appropriate values of external compo-
nents.
Clock from
ext. system
OSC1
OSC2
Open
PIC12F529T48A
PIC12F529T48A
DS41634A-page 42 Preliminary 2012 Microchip Technology Inc.
8.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators provide
a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 8-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a
parallel oscillator requires. The 4.7 k resistor provides
the negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator designs.
FIGURE 8-3: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Figure 8-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 8-4: EX TERN AL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
8.2.4 EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC circuit option
offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, especially
for low CEXT values. The user also needs to take into
account variation due to tolerance of external R and C
components used.
Figure 8-5 shows how the R/C combination is
connected to the PIC12F529T48A device. For REXT
values below 3.0 k, the oscillator operation may
become unstable, or stop completely. For very high
REXT values (e.g., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. It is
recommended keeping REXT between 5.0 k and
100 k.
Although the oscillator will operate with no external
capacitor (CEXT = 0pF), it is recommended using
values above 20 pF for noise and stability reasons. With
no or small external capacitance, the oscillation
frequency can vary dramatically due to changes in
external capacitances, such as PCB trace capacitance
or package lead frame capacitance. See Figure 12-1
and Figure 12-2.
FIGURE 8-5: EXTERNAL RC
OSCILLATOR MODE
20 pF
+5V
20 pF
10k
4.7k
10k
74AS04
XTAL
10k
74AS04
PIC12F529T48A
CLKIN
To O th e r
Devices
330
74AS04 74AS04
CLKIN
To Other
Devices
XTAL
330
74AS04
0.1 mF
PIC12F529T48A
VDD
REXT
CEXT
VSS
OSC1
Internal
clock
PIC16F529T48A
N
2012 Microchip Technology Inc. Preliminary DS41634A-page 43
PIC12F529T48A
8.2.5 INTERNAL 4/8 MHz RC
OSCILLATOR
The internal RC oscillator provides a fixed 4/8 MHz
(nominal) system clock at VDD = 3.5V and 25°C, (see
Section 12.0 “Electrical Characteristics” for
information on variation over voltage and temperature).
In addition, a calibration instruction is programmed into
the last address of memory, which contains the
calibration value for the internal RC oscillator. This
location is always non-code-protected, regardless of the
code-protect settings. This value is programmed as a
MOVLW XX instruction where XX is the calibration value,
and is placed at the Reset vector. This will load the W
register with the calibration value upon Reset and the
PC will then roll over to the users program at address
0x000. The user then has the option of writing the value
to the OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
For the PIC12F529T48A device, only bits <7:1> of
OSCCAL are used for calibration. See Register 4-3 for
more information.
8.3 Reset
The device differentiates between various kinds of
Reset:
• Power-on Reset (POR)
•MCLR
Reset during normal operation
•MCLR Reset during Sleep
• WDT Time-out Reset during normal operation
• WDT Time-out Reset during Sleep
• Wake-up from Sleep on pin change
Some registers are not reset in any way, and they are
unknown on Power-on Reset (POR) and unchanged in
any other Reset. Most other registers are reset to
“Reset state” on Power-on Reset (POR), MCLR, WDT
or Wake-up on pin change Reset during normal
operation. They are not affected by a WDT Reset
during Sleep or MCLR Reset during Sleep, since these
Resets are viewed as resumption of normal operation.
TABLE 8-3: RESET CONDITIONS FOR REGISTERS
Note: Erasing the device will also erase the
pre-programmed internal calibration value
for the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
Note: The bit 0 of the OSCCAL register is
unimplemented and should be written as
‘0’ when modifying OSCCAL for
compatibility with future devices.
Register Address Power-on Reset MCLR Reset, WDT Time-out,
Wake-up On Pin Change
W—qqqq qqq0(1) qqqq qqq0(1)
INDF 00h xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu
PCL 02h 1111 1111 1111 1111
STATUS 03h 0001 1xxx q00q quuu(2), (3)
FSR 04h 110x xxxx 11uu uuuu
OSCCAL 05h 1111 111- uuuu uuu-
PORTB 06h --xx xxxx --uu uuuu
OPTION — 1111 1111 1111 1111
TRIS — --11 1111 --11 1111
BSR — ---- -000 ---- -000
EECON 21h ---0 x000 ---0 q000
EEDATA 25h xxxx xxxx uuuu uuuu
EEADR 26h --xx xxxx --uu uuuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory.
2: See Table 8-4 for Reset value for specific conditions.
3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
PIC12F529T48A
DS41634A-page 44 Preliminary 2012 Microchip Technology Inc.
TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS
8.3.1 MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 8-6.
FIGURE 8-6: MCLR SELECT
8.4 Power-on Reset (POR)
The PIC12F529T48A device incorporates an on-chip
Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the internal POR,
program the GP3/MCLR/VPP pin as MCLR and tie
through a resistor to VDD, or program the pin as GP3, in
which case, an internal weak pull-up resistor is
implemented using a transistor (refer to Table 12-3 for
the pull-up resistor ranges). This will eliminate external
RC components usually needed to create a Power-on
Reset. A maximum rise time for VDD is specified. See
Section 12.0 “Electrical Characteristics” for details.
When the devices start normal operation (exit the Reset
condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-7.
The Power-on Reset circuit and the Device Reset Timer
(see Section 8.5 “Device Reset Timer (DRT)”) circuit
are closely related. On power-up, the Reset latch is set
and the DRT is reset. The DRT timer begins counting
once it detects MCLR to be high. After the time-out
period, which is typically 18 ms or 1 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 8-8. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT after MCLR goes high.
In Figure 8-9, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be GP3). The VDD is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 8-10 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, VDD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-9).
For additional information, refer to Application Note
AN522, “Power-Up Consideratio ns ” (DS00522).
STATUS Addr: 03h
Power-on Reset 0-01 1xxx
MCLR Reset during normal operation 0-0u uuuu
MCLR Reset during Sleep 0-01 0uuu
WDT Reset during Sleep 0-00 0uuu
WDT Reset normal operation 0-00 uuuu
Wake-up from Sleep on pin change 1-01 0uuu
Legend: u = unchanged, x = unknown
GP3/MCLR/VPP
MCLRE Internal MCLR
GPPU
Note: When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
2012 Microchip Technology Inc. Preliminary DS41634A-page 45
PIC12F529T48A
FIGURE 8-7: SI MPLI FIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
FIGURE 8-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
SQ
RQ
VDD
GP3/MCLR/VPP
Power-up
Detect POR (Power-on Reset)
WDT Reset
CHIP Reset
MCLRE
Wake-up on pin Change Reset
Start-up Timer
(10 s, 1 ms
WDT Time-out
Pin Change
Sleep
MCLR Reset
or 18 ms)
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
PIC12F529T48A
DS41634A-page 46 Preliminary 2012 Microchip Technology Inc.
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
V1
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 VDD min.
2012 Microchip Technology Inc. Preliminary DS41634A-page 47
PIC12F529T48A
8.5 Device Reset Timer (DRT)
On the PIC12F529T48A device, the DRT runs any time
the device is powered up. DRT runs from Reset and
varies based on oscillator selection and Reset type (see
Table 8-5).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the devices in a Reset condition after MCLR has
reached a logic high (VIH MCLR) level. Programming
GP3/MCLR/VPP as MCLR and using an external RC
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/or
space restricted applications, as well as allowing the
use of the GP3/MCLR/VPP pin as a general purpose
input.
The Device Reset Time delays will vary from
chip-to-chip due to VDD, temperature and process
variation. See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.8.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 8-5: DRT (DEVICE RESET TIMER
PERIOD)
8.6 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5)/OSC1/CLKIN pin
and the internal 4 or 8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by
programming the configuration WDTE as a ‘0’ (see
Section 8.1 “Configuration Bits”). Refer to the
PIC12F529T48A Programming Specification
(DS41316) to determine how to access the
Configuration Word.
8.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writing
to the OPTION register. Thus, a time-out period of a
nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2 WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Oscillator
Configuration POR Reset Subsequent
Resets
INTOSC, EXTRC 1 ms (typical) 10 s (typical)
LP, XT 18 ms (typical) 18 ms (typical)
PIC12F529T48A
DS41634A-page 48 Preliminary 2012 Microchip Technology Inc.
FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 8-6: SUMMARY OF REGISTER ASSOCIATED WITH THE WATCHDOG TIMER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 19
Legend: Shaded boxes = Not used by Watchdog Timer.
(Figure 7-1)
Postscaler
Note 1: PSA, PS<2:0> are bits in the OPTION register.
WDT Time-out
Watchdog
Time
From Timer0 Clock Source
WDT Enable
Configuration
Bit
PSA
Postscaler
8-to-1 MUX PS<2:0>
(Figure 7-3)
To Timer0
0
1M
U
X
1
0
PSA
MUX
2012 Microchip Technology Inc. Preliminary DS41634A-page 49
PIC12F529T48A
8.7 Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF )
The TO, PD and (GPWUF) bits in the STATUS register
can be tested to determine if a Reset condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) Reset.
TABLE 8-7: TO/PD/(GPWUF) STATUS
AFTER RESET(1)
8.8 Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
8.8.1 SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
GP3/MCLR/VPP pin must be at a logic high level if
MCLR is enabled.
8.8.2 WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1. An external Reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
2. A Watchdog Timer Time-out Reset (if WDT was
enabled).
3. A change on input pin GP0, GP1 and GP3 when
wake-up on change is enabled.
These events cause a device Reset. The TO, PD and
GPWUF bits can be used to determine the cause of a
device Reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
Sleep at pins GP0, GP1 and GP3 (since the last file or
bit operation on GPIO port).
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
GPWUF TO PD Reset Caused By
000WDT wake-up from Sleep
00uWDT time-out (not from
Sleep)
010MCLR wake-up from Sleep
011Power-up
0uuMCLR not during Sleep
110Wake-up from Sleep on pin
change
Legend: u = unchanged
Note 1: The TO, PD and GPWUF bits maintain
their status (u) until a Reset occurs. A
low-pulse on the MCLR input does not
change the TO, PD and GPWUF Status
bits.
Note: A Reset generated by a WDT time-out
does not drive the MCLR pin low.
CAUTION
Right before entering Sleep, read the input pins.
When in Sleep, wake-up occurs when the values at
the pins change from the state they were in at the
last reading. If a wake-up on change occurs and the
pins are not read before re-entering Sleep, a
wake-up will occur immediately even if no pins
change while in Sleep mode.
PIC12F529T48A
DS41634A-page 50 Preliminary 2012 Microchip Technology Inc.
8.9 Program Verification/Code
Protection
Code protection is enabled or disabled by writing the
correct value to the CP<3:0> bits of the Configuration
register. These bits must be written every time the
device is erased.
If the code protection bits have not been enabled, the
on-chip program and data memory can be read out for
verification purposes.
The last location (the oscillator calibration value) can
be read, regardless of the setting of the program
memory's code protection bit. If the code protect bit
specific to the Flash data memory is programmed,
then none of the contents of this memory region can
be verified externally.
Refer to PIC12F5 29T48A/ T39A Memory Programmin g
Specification (DS41619) for more information on
programming the Configuration Word.
8.10 ID Locations
Four memory locations are designated as ID locations
where users can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during program/verify.
Use only the lower 4 bits of the ID locations. The upper
bits should be programmed as 0s.
8.11 In-Circuit Serial Programming™
The PIC12F529T48A device can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows users to manufacture boards with
unprogrammed PIC12F529T48A device and then
program the PIC12F529T48A device just before
shipping the product. This also allows the most recent
firmware, or a custom firmware, to be programmed.
The PIC12F529T48A device is placed into a
Program/Verify mode by holding the GP1 and GP0 pins
low while raising the MCLR (VPP) pin from VIL to VIHH
(see programming specification). The GP1 pin
becomes the programming clock, and the GP0 pin
becomes the programming data. Both GP1 and GP0
pins are Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. Depending on the command, 14 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
details of serial programming, please refer to the
“PIC12F529T48A/T39A Memory Programming
Specification,” (DS41619).
A typical In-Circuit Serial Programming connection is
shown in Figure 8-12.
FIGURE 8-12: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
Note: The device code protection must be dis-
abled before attempting to program Flash
memory.
External
Connector
Signals
To No r m a l
Connections
To No r m a l
Connections
PIC12F529T48A
VDD
VSS
MCLR/VPP
GP1/ICSPCLK
GP0/ICSPDAT
VDD
VSS
VPP
CLK
Data
VDD
2012 Microchip Technology Inc. Preliminary DS41634A-page 51
PIC12F529T48A
9.0 RF TRANSMITTER
The RF transmitter is a fully integrated transmitter,
capable of Frequency-Shift Keying (FSK) and On-Off
Keying (OOK) modulation of an input data stream. The
transmitter is capable of operating in Preset or
Advanced mode. The Preset mode configures the RF
transmitter in one or two fixed configurations.
9.1 Mode Selection
Two modes of operation are supported: Preset and
Advanced. Preset mode allows operation in one of two
preconfigured modes. Advanced mode allows full con-
figuration of all features of the transmitter. Mode selec-
tion is made by applying a logical ‘1’ or ‘0’ on the CTRL
pin during power-up, followed by a clock signal on the
DATA pin if Advanced mode is required.
FIGURE 9-1: MODE SELEC T I ON
9.1.1 PRESET MODE
In Preset mode, the transmitter is configured according
to Ta b l e 9 - 1 . One of the two configuration modes can
be selected by changing the logical state of the CTRL
pin at power-up. The timing of a typical transmit opera-
tion in Preset mode is shown in Figure 9-2. A rising
edge on the DATA pin activates the transmitter. DATA
must be held high for the start-up time, TWAKE, while
the transmitter transitions out of Sleep mode. Signals
on the DATA pin, after the start-up time has elapsed,
are then transmitted.
The transition back to Sleep mode is managed auto-
matically. In 868 MHz FSK mode, the transmitter
returns to Sleep mode after 2 ms of inactivity on the
DATA line. In 434 MHz OOK mode, the transmitter
returns to Sleep after 20 ms of inactivity.
TABLE 9-1: PRESET MODE
CONFIGURATIONS
FIGURE 9-2: TRANSMITTER TIMING IN
PRESET MODE
Circuit Start-up
Wait tSTART
Check
CTRL Pin
Preset
434 MHz OOK Tx
Preset
868 MHz FSK Tx
Advanced Mode
User-defined
Configuration
Clock Signal
Logic ‘1’ Logic ‘0’
CTRL Configuration
1OOK 433.92 MHz, 10 dBm
0FSK 868.3 MHz, FDEV = 20 kHz, 10 dBm
Note 1: While the logic level of the CTRL pin dur-
ing TSTART does not have any effect on
the device operation, the pin should not
be connected to VDD through an imped-
ance lower than 20 kΩ or higher than
1 MΩ.
tWAKE tOFFT
Data
RF Out
PIC12F529T48A
DS41634A-page 52 Preliminary 2012 Microchip Technology Inc.
9.1.2 ADVANCED MODE
Advanced mode allows full configuration of the trans-
mitter by writing to the Configuration register. Writing
and reading from this register is performed via a
two-wire interface formed by the CTRL and DATA pins.
Advanced mode is enabled by applying a rising signal
on the CTRL pin while driving DATA low. Upon detec-
tion of this rising edge, the data applied to the DATA pin
is accepted as register configuration information. Data
bits are clocked on subsequent rising edges of the
clock signal. The first bit of serial data selects register
read or write operation. The timing for module Configu-
ration register ‘write’ is shown in Figure 9-3. When writ-
ing, all 13 data bits must be written to the register.
Similarly, the Configuration register may be read using
the timing of Figure 9-4. When reading, all 13 bits of
configuration and all 43 bits of test data must be read.
The contents of the Configuration register are
described in Table 9-2. During the register ‘write’ or
‘read’ phases, the transmitter remains in Sleep mode.
The CTRL pin is sampled after tSTART has elapsed. The
CTRL pin should not be allowed to float.
FIGURE 9-3: CONFIGURATION REGISTER ‘WRITE’
FIGURE 9-4: CONFIGURATION REGISTER ‘READ’
CTRL
DATA R/W D11 D8 D5 D2ACC D12 D10 D9 D7 D6 D4 D3 D1 D0
000
CTRL
DATA R/W 0 0 D10 D0ACC 000D12 D11 D1 T42 T41
010
T1 T0
Legend: DATA pin is an output.
Note 1: When reading the Configuration register,
64 clock cycles on the CTRL pin must be
issued, shifting out on the DATA pin the
13 Configuration bits, plus 43 internal test
bits. Reading only the 13 Configuration
bits is not allowed.
2012 Microchip Technology Inc. Preliminary DS41634A-page 53
PIC12F529T48A
FIGURE 9-5: POWER-UP TIMING
When operating in Advanced mode, two possibilities
exist for operation of the transmitter, these are
dependent upon the state of the TX mode bit (D12 of
the register description in Table 9-2).
When set to logical ‘0’, operation is identical to that of
the Preset mode. Transmit operation will be in accor-
dance with that of Figure 9-2 with the time TOFFT corre-
sponding to that set in the Configuration register.
Note that prior to programming the default, logical ‘0’,
configuration is loaded. Note also that subsequent pro-
gramming iterations can only be performed once the
transmit cycle is finished – including the time required
for switching off the PA (T
OFFT).
With TX mode (D12) set, the transmitter is placed
directly in Transmit mode. It will remain in Transmit
mode until a second register write operation clears the
TX mode bit. Refer to Figure 9-6.
FIGURE 9-6: MANUAL CONTROL OF TRANSMITTER
VDD
CTRL
State
tSTART
Don’t Care Valid Logic Level
Sleep
Power-Up
3.7V
1.8V
Note 1: Once in Sleep mode, activity on the DATA
pin (without clocking of the CTRL line) will
trigger transmission according to the
current configuration settings. Care must
be taken to avoid inadvertent
transmissions.
tRAMPtWAKE
TWI Config TWI Config
TX OFF
TX ENABLE
D12 = 1D12 = 0
DATA
CTRL
RF OUT
DATA TRANSMISSION
PIC12F529T48A
DS41634A-page 54 Preliminary 2012 Microchip Technology Inc.
TABLE 9-2: CONFIGURATION REGISTER
Bit Name Value Setting Default Notes
CTRL = 0CTRL = 1
D12 Tx Mode 0Preset 00When set to ‘1’, the transmitter
will continuously transmit
1Forced Transmit
D(11:9) Frequency 000 418.00 MHz 100 010 RF operating center frequency
001 433.42 MHz
010 433.92 MHz
011 864.00 MHz
100 868.30 MHz
101 868.65 MHz
110 868.95 MHz
111 869.85 MHz
D8 Modulation 0FSK 01Modulation format
1OOK
D(7:5) Freq. Deviation 000 10 kHz 010 010 FSK frequency deviation (not
used in OOK mode)
001 12.5 kHz
010 20 kHz
011 25 kHz
100 40 kHz
101 50 kHz
110 80 kHz
111 100 kHz
D4 RF Power 00 dBm 11Programmed RF output power
110 dBm
D3 TX Timer 02 ms 01Transmit power-off timer, TOFFT
120 ms
D(2:0) Fine Tuning 011 fc + 6 * PLL Step 000 000 Fine tuning from programmed
center frequency
010 fc + 4 * PLL Step
001 fc + 2 * PLL Step
000 fc + 0 * PLL Step
111 fc - 2 * PLL Step
110 fc - 4 * PLL Step
101 fc - 6 * PLL Step
100 fc - 8 * PLL Step
2012 Microchip Technology Inc. Preliminary DS41634A-page 55
PIC12F529T48A
10.0 INSTRUCTION SET SUMMARY
The PIC12F529T48A instruction set is highly orthogo-
nal and is comprised of three basic categories.
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
Each PIC12F529T48A instruction is a 12-bit word
divided into an opcode, which specifies the instruction
type, and one or more operands which further specify
the operation of the instruction. The formats for each of
the categories is presented in Figure 10-1, while the
various opcode fields are summarized in Table 10-1.
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 s.
Figure 10-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
where ‘h’ signifies a hexadecimal digit.
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
f Register file address (0x00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant data or label
x Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility with
all Microchip software tools.
d Destination select;
d = 0 (store result in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label Label name
TOS Top-of-Stack
PC Program Counter
WDT Watchdog Timer counter
TO Time-out bit
PD Power-down bit
dest Destination, either the W register or the specified
register file location
[ ] Options
( ) Contents
Assigned to
< > Register bit field
In the set of
italics User defined term (font is courier)
Byte-oriented file register operations
11 6 5 4 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register ope rations
11 8 7 5 4 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Literal and control operations – GOTO instruction
11 9 8 0
OPCODE k (literal)
k = 9-bit immediate value
PIC12F529T48A
DS41634A-page 56 Preliminary 2012 Microchip Technology Inc.
TABLE 10-2: INSTRUCTION SET SUMMARY
Mnemonic,
Operands Description Cycles 12-Bit Opcode Status
Affected Notes
MSb LSb
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C, DC, Z
None
Z
1, 2, 4
2, 4
4
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
2, 4
2, 4
1, 2, 4
2, 4
2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2, 4
2, 4
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
MOVLB
OPTION
RETLW
SLEEP
TRISGPIO
XORLW
k
k
–
k
k
k
k
–
k
–
f
k
AND literal with W
Call Subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Move literal to BSR
Load OPTION register
Return, place literal in W
Go into Standby mode
Load TRISGPIO register
Exclusive OR literal to W
1
2
1
2
1
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0001
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0kkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
None
TO, PD
None
Z
1
3
Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.6 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of GPIO. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
2012 Microchip Technology Inc. Preliminary DS41634A-page 57
PIC12F529T48A
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 31
d 01
Operation: (W) + (f) (dest)
Status Affected: C, DC, Z
Description: Add the contents of the W register
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W).AND. (k) (W)
Status Affected: Z
Description: The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W) .AND. (f) (dest)
Status Affected: Z
Description: The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 31
0 b 7
Operation: 0 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 31
0 b 7
Operation: 1 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 31
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a two-cycle instruction.
PIC12F529T48A
DS41634A-page 58 Preliminary 2012 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 31
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a two-cycle instruction.
CALL Subroutine Call
Syntax: [ label ] CALL k
Operands: 0 k 255
Operation: (PC) + 1 Top-of-Stack;
k PC<7:0>;
(STATUS<6:5>) PC<10:9>;
0 PC<8>
Status Affected: None
Description: Subroutine call. First, return
address (PC + 1) is pushed onto
the stack. The eight-bit immediate
address is loaded into PC
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS<6:5>, PC<8> is cleared.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 31
Operation: 00h (f);
1 Z
Status Affected: Z
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W);
1 Z
Status Affected: Z
Description: The W register is cleared. Zero bit
(Z) is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT;
0 WDT prescaler (if assigned);
1 TO;
1 PD
Status Affected: TO, PD
Description: The CLRWDT instruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
2012 Microchip Technology Inc. Preliminary DS41634A-page 59
PIC12F529T48A
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – 1 (dest)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – 1 d; skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead making it a two-cycle
instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 511
Operation: k PC<8:0>;
STATUS<6:5> PC<10:9>
Status Affected: None
Description: GOTO is an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTO is a two-
cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) + 1 (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 31
d [0,1]
Operation: (f) + 1 (dest), skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead making it a
two-cycle instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. (k) (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
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DS41634A-page 60 Preliminary 2012 Microchip Technology Inc.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W).OR. (f) (dest)
Status Affected: Z
Description: Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file
register ‘f’. ‘d’ = 1 is useful as a
test of a file register, since status
flag Z is affected.
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0 k 7
Operation: k BSR
Status Affected: None
Description: The three-bit literal ‘k’ is loaded into
the Bank Select Register (BSR). The
“don’t cares” will be assembled at ‘0’.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The eight-bit literal ‘k’ is loaded
into the W register. The “don’t
cares” will assembled as ‘0’s.
MOVWF M ove W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 31
Operation: (W) (f)
Status Affected: None
Description: Move data from the W register to
register ‘f’.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
OPTION Load OPTION Register
Syntax: [ label ] Option
Operands: None
Operation: (W) Option
Status Affected: None
Description: The content of the W register is
loaded into the OPTION register.
2012 Microchip Technology Inc. Preliminary DS41634A-page 61
PIC12F529T48A
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affected: None
Description: The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address). This
is a two-cycle instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 31
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is stored back in reg-
ister ‘f’.
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 31
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Cregister ‘f’
Cregister ‘f’
SLEEP Enter SLEEP Mode
Syntax: [label ]SLEEP
Operands: None
Operation: 00h WDT;
0 WDT prescaler;
1 TO;
0 PD
Status Affected: TO, PD, GPWUF
Description: Time-out Status bit (TO) is set. The
Power-down Status bit (PD) is
cleared.
GPWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See Section 8.8 “Power-down
Mode (Sleep)” on Sleep for more
details.
SUBWF Subtract W from f
Syntax: [label ] SUBWF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – (W) dest)
Status Affected: C, DC, Z
Description: Subtract (two’s complement
method) the W register from regis-
ter ‘f’. If ‘d’ is ‘0’, the result is stored
in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 31
d [0,1]
Operation: (f<3:0>) (dest<7:4>);
(f<7:4>) (dest<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
PIC12F529T48A
DS41634A-page 62 Preliminary 2012 Microchip Technology Inc.
TRIS Load TRIS Register
Syntax: [ label ] TRIS f
Operands: f = 6
Operation: (W) TRIS register f
Status Affected: None
Description: TRIS register ‘f’ (f = 6 or 7) is
loaded with the contents of the W
register.
XORLW Exclusive OR literal with W
Syntax: [label ]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W) .XOR. (f) dest)
Status Affected: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2012 Microchip Technology Inc. Preliminary DS41634A-page 63
PIC12F529T48A
11.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
11.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
PIC12F529T48A
DS41634A-page 64 Preliminary 2012 Microchip Technology Inc.
11.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
11.3 HI-TECH C for Vario us Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
11.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
11.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
11.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
2012 Microchip Technology Inc. Preliminary DS41634A-page 65
PIC12F529T48A
11.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
11.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
11.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
11.10 PICkit 3 In-Circuit De bugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
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DS41634A-page 66 Preliminary 2012 Microchip Technology Inc.
11.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
11.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
11.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2012 Microchip Technology Inc. Preliminary DS41634A-page 67
PIC12F529T48A
12.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias............................................................................................................ -40°C to +85°C
Storage temperature ............................................................................................................................ -55°C to +150°C
Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V
Voltage on VDDRF with respect to VSSRF .......................................................................................................0 to +3.9V
Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) .................................................................................................................................. 700 mW
Max. current out of VSS pin ................................................................................................................................ 200 mA
Max. current into VDD pin ...................................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)20 mA
Max. output current sunk by any I/O pin .............................................................................................................. 25 mA
Max. output current sourced by any I/O pin ......................................................................................................... 25 mA
Max. output current sourced by I/O port .............................................................................................................. 75 mA
Max. output current sunk by I/O port ................................................................................................................... 75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC12F529T48A
DS41634A-page 68 Preliminary 2012 Microchip Technology Inc.
FIGURE 12-1: PI C12F52 9T 48 A VOLTAGE-FREQUENCY GRAPH, -40C TA +85C
FIGURE 12-2: MAXIMUM OSCILLATOR FREQUENCY TA BLE
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
8
INTOSC ONLY
0 200 kHz 4 MHz
Frequency (MHz)
8MHz
LP
XT
EXTRC
INTOSC
Oscillator Mode
2012 Microchip Technology Inc. Preliminary DS41634A-page 69
PIC12F529T48A
12.1 DC Characteri stics
TABLE 12-1: DC CHARACTERISTICS: PIC12F529T48A (INDUSTRIAL)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
D001 VDD Supply Voltage 2.0 3.7 V See Figure 12-1
D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
Power-on Reset
— Vss — V See Section 8.4 “Power-on
Reset (POR)” for details
D004 SVDD VDD Rise Rate to ensure
Power-on Reset
0.05* — — V/ms See Section 8.4 “Power-on
Reset (POR)” for details
D005 IDDP Supply Current During Prog/
Erase.
— 250* — A
D010 IDD Supply Current(3,4) — 175 250 AFOSC = 4 MHz, VDD = 2.0V
— 250 400 AF
OSC = 8 MHz, VDD = 2.0V
—1120AFOSC = 32 kHz, VDD = 2.0V
D020 IPD Power-down Current (5) —0.11.2AVDD = 2.0V
D022 IWDT WDT Current —1.03.0AVDD = 2.0V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design
guidance only and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail for external clock modes; all I/O pins tri-stated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep
mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.
PIC12F529T48A
DS41634A-page 70 Preliminary 2012 Microchip Technology Inc.
12.2 RF Transmitter Electrical Specifications
Symbol Description Conditions Min Typ Max Unit
Current Consumption
IDDSL Supply current in Sleep mode — — 0.5 1 µs
IDDT Supply current in Transmit
mode with appropriate exter-
nal matching
RF Power o/p = +10
dBm
—16.5—mA
RF Power o/p = 0 dBm — 9 — mA
RF and Baseband Specifications
FDA_D Frequency deviation, FSK Number of programma-
ble values
—8——
FDA Frequency deviation, FSK* — 10 — 100 kHz
BRF Bit rate, FSK Permissible Range 0.5 — 100 kbps
BRO Bit rate, OOK Permissible Range 0.5 — 10 kbps
OOK_B OOK Modulation Depth — — 50 — dB
RFOP RF output power in 50 ohms High Power Setting 7 10 — dBm
Low Power Setting** -3 0 — dBm
DRFOPV Variation in RF output power
with supply voltage
2.5V to 3.3V — — 3 dB
1.8V to 3.7V — — 7 dB
PHN Transmitter phase noise at
868.3 MHz
Offset from center fre-
quency: 100 kHz
——-76dBc/Hz
350 kHz — — -81 dBc/Hz
550 kHz — — -91 dBc/Hz
1.15 MHz — — -101 dBc/Hz
FR Number of selectable frequen-
cies
——8——
FXOSC Crystal Oscillator Frequency — 26 26 26 MHz
STEP RF Frequency Step 868 MHz — 3.174 — kHz
434 MHz — 1.587 — kHz
DFXOSC Frequency variation of the
Oscillator Circuit
No crystal contribution — — +/-25 ppm
Timing Specifications
tWAKE Time from Sleep to TX mode — — — 2 ms
tOFFT Timer from TX data activity to
Sleep
Programmable — 2 — ms
——20—ms
tRAMP PA Ramp up and down time — — 20 — µs
tSTART Time before CTRL Pin mode
selection
Time from power on to
sampling of CTRL
— 200 µs +
TS_OSC
—ms
Serial Interface Timing Specifications
fctrl CTRL Clock Frequency — — — 10 MHz
fch CTRL Clock High time — 45 — — ns
fcl CTRL Clock Low time — 45 — — ns
trise CTRL Clock Rise time — — — 5 ns
tfall CTRL Clock Fall time — — — 5 ns
tsetup DATA Setup time From DATA transition to
CTRL rising edge
45 — — ns
thold DATA Hold time From CTRL rising edge
to DATA transition
45 — — ns
2012 Microchip Technology Inc. Preliminary DS41634A-page 71
PIC12F529T48A
TABLE 12-2: DC CHARACTERISTICS: PIC12F529T48A (Industrial)
DC CHARACTERISTICS Standard Operati ng Conditions (unless otherwise specif ied)
Operating temperature -40°C TA +85°C (industrial)
Operating voltage VDD range as described in DC specification.
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
VIL Input Low Voltage
I/O ports
D030A Vss — 0.15
VDD
V Otherwise
D031 with Schmitt Trigger buffer Vss — 0.15
VDD
V
D032 MCLR, T0CKI Vss — 0.15
VDD
V
D033 OSC1 (EXTRC mode) Vss — 0.15
VDD
V(Note 1)
D033A OSC1 (XT and LP modes) Vss — 0.3 V
VIH Input High Voltage
I/O ports —
D040A 0.25 VDD
+ 0.8V
—V
DD V Otherwise
D041 with Schmitt Trigger buffer 0.85 VDD —VDD V For entire VDD range
D042 MCLR, T0CKI 0.85 VDD —VDD V
D042A OSC1 (EXTRC mode) 0.85 VDD —VDD V(Note 1)
D043 OSC1 (XT and LP modes) 1.6 — VDD V
D070 IPUR I/O PORT weak pull-up
current(5) 50 250 400 AVDD = 3.7V, VPIN = VSS
IIL Input Leakage Current(2), (3)
D060 I/O ports — — ±1 AVss VPIN VDD, Pin at high-impedance
D061 GP3/MCLR(4) —±0.7±5 AVss VPIN VDD
D063 OSC1 — — ±5 AVss VPIN VDD, XT and LP osc
configuration
Output Low Voltage
D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, –40C to +85C
Output High Voltage
D090 I/O ports(3) VDD –
0.7
—— VIOH = -3.0 mA, VDD = 4.5V, –40C to
+85C
Capacitive Loading Specs on Output Pins
D101 All I/O pins — — 50 pF
Flash Data Memory
D120 EDByte endurance 100K 1M — E/W –40C TA +85C
D121 VDRW VDD for read/write VMIN —3.7 V
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12F529T48A be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: This specification applies to GP3/MCLR configured as GP3 with internal pull-up disabled.
5: This specification applies to all weak pull-up devices, including the weak pull-up found on GP3/MCLR. The current value
listed will be the same whether or not the pin is configured as GP3 with pull-up enabled or MCLR.
PIC12F529T48A
DS41634A-page 72 Preliminary 2012 Microchip Technology Inc.
TABLE 12-3: PULL-UP RESISTOR RANGES
VDD (Volts) T emperature
(C) Min. Typ. Max. Units
GP0/GP1
2.0 –40 73K 105K 186K
25 73K 113K 187K
85 82K 123K 190K
GP3
2.0 –40 63K 81K 96K
25 77K 93K 116K
85 82K 96K 116K
2012 Microchip Technology Inc. Preliminary DS41634A-page 73
PIC12F529T48A
12.3 Timing Parameter Symbology and Load Conditions – PIC12F52 9T48A
The timing parameter symbols have been created following one of the following formats:
FIGURE 12-3: LOAD CONDITIONS – PIC12F529T48A
FIGURE 12-4: EXTERNAL CLOCK TIMING – PIC12F529T48A
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
2to mcMCLR
ck CLKOUT osc Oscillator
cy Cycle time os OSC1
drt Device Reset Timer t0 T0CKI
io I/O port wdt Watchdog Timer
Uppercase letters and their meanings:
S
FFall PPeriod
HHigh RRise
I Invalid (high-impedance) V Valid
L Low Z High-impedance
CL
VSS
pin
Legend:
CL = 50 pF for all pins except OSC2
15 pF for OSC2 in XT or LP modes
when external clock is used
to drive OSC1
OSC1
Q4 Q1 Q2 Q3 Q4 Q1
133
44
2
PIC12F529T48A
DS41634A-page 74 Preliminary 2012 Microchip Technology Inc.
12.4 AC Characteri stics
TABLE 12-4: EXTERNAL CLOCK TIMING REQUIREMENTS
TABLE 12-5: CALIBRATED INTERNAL RC FREQUENCIES
AC CHARACTERISTICS
Standard Operating Conditions (unle ss otherw is e speci fied)
Operating Temperature -40C T
A +85C (industrial),
Operating Voltage VDD range is described in Section 12.0 “Electri-
cal Characteristics”.
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
1A FOSC External CLKIN Frequency(2) DC — 4 MHz XT Oscillator mode
DC — 200 kHz LP Oscillator mode
Oscillator Frequency(2) DC — 4 MHz EXTRC Oscillator mode
0.1 — 4 MHz XT Oscillator mode
DC — 200 kHz LP Oscillator mode
1T
OSC External CLKIN Period(2) 250 — — ns XT Oscillator mode
5— —s LP Oscillator mode
Oscillator Period(2) 250 — — ns EXTRC Oscillator mode
250 — 10,000 ns XT Oscillator mode
5— —s LP Oscillator mode
2T
CY Instruction Cycle Time 200 4/FOSC DC ns
3 TosL,
To s H
Clock in (OSC1) Low or High
Time
50* — — ns XT Oscillator
2* — — s LP Oscillator
4TosR,
To s F
Clock in (OSC1) Rise or Fall
Time
— — 25* ns XT Oscillator
— — 50* ns LP Oscillator
* These parameters are characterized but not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. When an external clock
input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial),
Operating Voltage VDD range is described in Sect ion 12.0 “Elec trica l
Characteristics”.
Param
No. Sym. Characteristic Freq.
Tolerance Min. Typ† Max. Units Conditions
F10 FOSC Internal Calibrated
INTOSC Frequency(1) 1% 7.92 8.00 8.08 MHz 3.5V, 25C
2% 7.84 8.00 8.16 MHz 2.5V VDD 3.7V
0C TA +85C
5% 7.60 8.00 8.40 MHz 2.0V VDD 3.7V
-40C T
A +85C (Ind.)
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 3.7V, 25C unless otherwise stated. These parameters are for
design guidance only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
2012 Microchip Technology Inc. Preliminary DS41634A-page 75
PIC12F529T48A
FIGURE 12-5: I/O TIMING
TABLE 12-6: TIMING REQUIREMENTS
OSC1
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
17
20, 21
18
Old Value New Value
19
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
Operating Voltage VDD range is described in Section 12.0 “Electric al Char acte ristic s” .
Param
No. Sym. Characteristic Min. Typ(1) Max. Units
17 TOSH2IOVOSC1 (Q1 cycle) to Port Out Valid(2), (3) — — 100* ns
18 T
OSH2IOIOSC1 (Q2 cycle) to Port Input Invalid (I/O in hold
time)(2) 50 — — ns
19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 20 — — ns
20 TIOR Port Output Rise Time(3) — 10 50** ns
21 TIOF Port Output Fall Time(3) — 10 50** ns
TBD = To be determined.
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1: Data in the Typical (“Typ”) column is at 3.7V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 12-3 for loading conditions.
PIC12F529T48A
DS41634A-page 76 Preliminary 2012 Microchip Technology Inc.
FIGURE 12-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
TABLE 12-7: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F529T48A
TABLE 12-8: DRT (DEVICE RESET TIMER PERIOD)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
Operating Voltage VDD range is described in Table 12-2.
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
30 TMCLMCLR Pulse Width (low) 2000* — — ns VDD = 3.0V
31 TWDT Watchdog Timer Time-out Period
(no prescaler)
9* 20* 35* ms VDD = 3.0V (Industrial)
32 TDRT Device Reset Timer Period
Standard 9* 20* 35* ms VDD = 3.0V (Industrial)
Short 0.5* 1.125* 2* ms VDD = 3.0V (Industrial)
34 TIOZ I/O High-impedance from MCLR
low
— — 2000* ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 3.7V, 25C unless otherwise stated. These parameters are for
design guidance only and are not tested.
Oscillator Configuration POR Reset Subsequent Resets
IntRC and ExtRC 1 ms (typical) 10 s (typical)
XT and LP 18 ms (typical) 18 ms (typical)
VDD
MCLR
Internal
POR
DRT
Time-out(2)
Internal
Reset
Watchdog
Timer
Reset
32
31
34
I/O pin(1)
32 32
34
30
Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT Reset only in XT and LP.
2012 Microchip Technology Inc. Preliminary DS41634A-page 77
PIC12F529T48A
FIGURE 12-7: TIMER0 CLOCK TIMINGS
TABLE 12-9: TIMER0 CLOCK REQUIREMENTS
TABLE 12-10: FLASH DATA MEMORY WRITE/ERASE REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
Operating Voltage VDD range is described in Table 12-2.
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
40 Tt0H T0CKI High Pulse
Width
No Prescaler 0.5 T
CY + 20* — — ns
With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse
Width
No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
42 Tt0P T0CKI Period 20 or T
CY + 40* N — — ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 3.7V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
AC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
Operating Voltage VDD range is described in Table 12-2.
Param
No. Sym. Characteristic Min. Typ(1) Max. Units Conditions
43 TDW Flash Data Memory
Write Cycle Time
23.55ms
44 TDE Flash Data Memory
Erase Cycle Time
234ms
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 3.7V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
T0CKI
40 41
42
PIC12F529T48A
DS41634A-page 78 Preliminary 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. Preliminary DS41634A-page 79
PIC12F529T48A
13.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
“Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean + 3) or
(mean - 3) respectively, where is a standard deviation, over each temperature range.
FIGURE 13-1: TYPICAL IDD vs. FOSC OVER VDD (XT, EXTRC mode)
FIGURE 13-2: MAXIMUM IDD vs. FOSC OVER VDD (XT, EXTRC mode)
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FOSC (MHz)
0
100
200
300
400
500
600
700
800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
024
31 5
2V
IDD (A)
FOSC (MHz)
0
100
200
300
400
500
600
700
800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
024
31 5
2V
IDD (A)
PIC12F529T48A
DS41634A-page 80 Preliminary 2012 Microchip Technology Inc.
FIGURE 13-3: IDD vs. VDD OVER FOSC (LP MODE)
40
60
80
100
VDD (V)
IDD (A)
24
31 5
120
Typical: Statistical Mean @25°C
32 kHz Maximum Industrial
32 kHz Typical
20
0
6
Industrial: Mean (Worst-Case Temp) + 3σ
(-40°C to 85°C)
2012 Microchip Technology Inc. Preliminary DS41634A-page 81
PIC12F529T48A
FIGURE 13-4: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 13-5: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
0.0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
Max. 85°C
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
PIC12F529T48A
DS41634A-page 82 Preliminary 2012 Microchip Technology Inc.
FIGURE 13-6: TYPICAL WDT IPD vs. VDD
FIGURE 13-7: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
0
1
2
3
4
5
6
7
8
9
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
Max. 85°C
0.0
5.0
10.0
15.0
20.0
25.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IPD (A)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
2012 Microchip Technology Inc. Preliminary DS41634A-page 83
PIC12F529T48A
FIGURE 13-8: WD T TIME-OUT v s. VDD OVER TEMPERATURE (NO PRESCALER)
FIGURE 13-9: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
0
5
10
15
20
25
30
35
40
45
50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Time (ms)
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
Max. 85°C
Typical. 25°C
Min. -40°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
IOL (mA)
VOL (V)
Max. 85°C
Typical 25°C
Min. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
PIC12F529T48A
DS41634A-page 84 Preliminary 2012 Microchip Technology Inc.
FIGURE 13-10 : VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
FIGURE 13-11: TTL INPUT THRESHOLD VIN vs. VDD
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-4.0-3.5-3.0-2.5-2.0-1.5-1.0-0.50.0
IOH (mA)
VOH (V)
Typ. 25°C
Max. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
0.5
0.7
0.9
1.1
1.3
1.5
1.7
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
Typ. 25°C
Max. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
2012 Microchip Technology Inc. Preliminary DS41634A-page 85
PIC12F529T48A
FIGURE 13-12: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
FIGURE 13-13: DEVICE RESET TIMER (XT AND LP) vs. VDD
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VIN (V)
VIH Max. 125°C
VIH Min. -40°C
VIL Max. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0
5
10
15
20
25
30
35
40
45
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
DRT (ms)
Min. -40°C
Typical 25°C
Max. 85°C
PIC12F529T48A
DS41634A-page 86 Preliminary 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. Preliminary DS41634A-page 87
PIC12F529T48A
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
14-Lead TSSOP (4.4 mm) Example
YYWW
NNN
XXXXXXXX
529T48A
1010
017
*Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
PIC12F529T48A
DS41634A-page 88 Preliminary 2012 Microchip Technology Inc.
14.2 Package Details
The following sections give the technical details of the packages.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012 Microchip Technology Inc. Preliminary DS41634A-page 89
PIC12F529T48A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC12F529T48A
DS41634A-page 90 Preliminary 2012 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012 Microchip Technology Inc. Preliminary DS41634A-page 91
PIC12F529T48A
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (04/2012)
Initial release of this data sheet.
PIC12F529T48A
DS41634A-page 92 Preliminary 2012 Microchip Technology Inc.
NOTES:
2012 Microchip Technology Inc. Preliminary DS41634A-page 93
PIC12F529T48A
INDEX
A
ALU ..................................................................................... 11
Assembler
MPASM Assembler..................................................... 64
B
Block Diagram
On-Chip Reset Circuit................................................. 45
Timer0......................................................................... 33
TMR0/WDT Prescaler................................................. 37
Watchdog Timer.......................................................... 48
C
C Compilers
MPLAB C18 ................................................................ 64
Carry ................................................................................... 11
Clocking Scheme ................................................................ 14
Code Protection ............................................................ 39, 50
CONFIG1 Register.............................................................. 40
Configuration Bits................................................................ 39
Customer Change Notification Service ............................... 95
Customer Notification Service............................................. 95
Customer Support ............................................................... 95
D
DC and AC Characteristics ................................................. 79
Graphs and Tables ..................................................... 79
Development Support ......................................................... 63
Digit Carry ........................................................................... 11
E
Errata .................................................................................... 5
F
FSR..................................................................................... 22
FSR Register ...................................................................... 22
Fuses. See Configuration Bits
G
GPIO ................................................................................... 25
I
I/O Interfacing ..................................................................... 27
I/O Port................................................................................ 25
I/O Ports.............................................................................. 25
I/O Programming Considerations........................................ 32
ID Locations .................................................................. 39, 50
INDF.................................................................................... 22
INDF Register ..................................................................... 22
Indirect Data Addressing..................................................... 22
Instruction Cycle ................................................................. 14
Instruction Flow/Pipelining .................................................. 14
Instruction Set
MOVLB ....................................................................... 60
Instruction Set Summary..................................................... 56
Internet Address.................................................................. 95
L
Loading of PC ..................................................................... 21
M
Memory Map
PIC12F529T48A ......................................................... 15
Memory Organization.......................................................... 15
Data EEPROM Memory ............................................. 23
Program Memory (PIC12F529T48A).......................... 15
Microchip Internet Web Site................................................ 95
MOVLB ............................................................................... 60
MPLAB ASM30 Assembler, Linker, Librarian ..................... 64
MPLAB Integrated Development Environment Software.... 63
MPLAB PM3 Device Programmer ...................................... 66
MPLAB REAL ICE In-Circuit Emulator System .................. 65
MPLINK Object Linker/MPLIB Object Librarian .................. 64
O
OPTION Register................................................................ 19
OSC selection..................................................................... 39
OSCCAL Register............................................................... 20
Oscillator Configurations..................................................... 41
Oscillator Types
HS............................................................................... 41
LP ............................................................................... 41
RC .............................................................................. 41
XT ............................................................................... 41
P
Packaging
PDIP Details ............................................................... 88
PIC12F529T48A Device Varieties........................................ 9
POR
Device Reset Timer (DRT) ................................... 39, 47
PD............................................................................... 49
TO............................................................................... 49
Power-down Mode.............................................................. 49
Prescaler ............................................................................ 36
Program Counter ................................................................ 21
Q
Q cycles.............................................................................. 14
R
RC Oscillator....................................................................... 42
Reader Response............................................................... 96
Read-Modify-Write.............................................................. 32
Registers
CONFIG1 (Configuration Word Register 1)................ 40
Special Function ......................................................... 17
Reset .................................................................................. 39
Revision History.................................................................. 91
RF Transmitter.................................................................... 51
S
Sleep ............................................................................ 39, 49
Software Simulator (MPLAB SIM) ...................................... 65
Special Features of the CPU .............................................. 39
Special Function Registers................................................. 17
Stack................................................................................... 21
STATUS Register ......................................................... 11, 18
T
Timer0
Timer0 (TMR0) Module .............................................. 33
TMR0 with External Clock .......................................... 35
Timing Diagrams and Specifications .................................. 73
Timing Parameter Symbology and Load Conditions .......... 73
TRIS Registers ................................................................... 25
PIC12F529T48A
DS41634A-page 94 Preliminary 2012 Microchip Technology Inc.
W
Wake-up from Sleep ........................................................... 49
Watchdog Timer (WDT) ................................................ 39, 47
Period.......................................................................... 47
Programming Considerations ..................................... 47
WWW Address.................................................................... 95
WWW, On-Line Support........................................................ 5
Z
Zero bit................................................................................11
2012 Microchip Technology Inc. Preliminary DS41634A-page 95
PIC12F529T48A
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
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Users of Microchip products can receive assistance
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Customers should contact their distributor,
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customers. A listing of sales offices and locations is
included in the back of this document.
Technic al suppo rt is avail able throug h the we b site
at: http://microchip.com/support
PIC12F529T48A
DS41634A-page 96 Preliminary 2012 Microchip Technology Inc.
READER RESP ONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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DS41634APIC12F529T48A
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2012 Microchip Technology Inc. Preliminary DS41634A-page 97
PIC12F529T48A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC12F529T48A
Tape and Reel
Option: Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range: I= -40C to+85C (Industrial)
Package: ST = 14-pin TSSOP
Pattern: Special Requirements
Examples:
a) PIC12F529T48A-I/P = Industrial temp.,
TSSOP package (Pb-free)
[X](1)
Tape and Reel
Option
Note: Tape and Reel available for only the following packages: TSSOP.
DS41634A-page 98 Preliminary 2012 Microchip Technology Inc.
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11/29/11
