1
LTC4221
4221fa
Dual Hot Swap Controller/
Power Sequencer with Dual Speed,
Dual Level Fault Protection
■
Allows Safe Board Insertion and Removal from a
Live Backplane
■
Configurable Power Supply Sequencing
■
Soft-Start with Current Foldback Limits Inrush
Current
■
No External Gate Capacitor Required
■
Adjustable Dual Level Circuit Breaker Protection
■
Controls Supply Voltages from 1V to 13.5V
■
Independent N-Channel MOSFET High Side Drivers
■
FB
Pin Monitors V
OUT
for Overvoltage Protection
■
Latch Off or Automatic Retry on Current Fault
■
FAULT and PWRGD Outputs
■
Narrow 16-Pin SSOP Package
■
Electronic Circuit Breaker
■
Power Supply Sequencing
■
Live Board Insertion and Removal
■
Industrial High Side Switch/Circuit Breaker
The LTC
®
4221 is a 2-channel Hot Swap
TM
controller that
allows a board to be safely inserted and removed from a
live backplane. Using two independent high side gate
drivers to control two external N-channel pass transistors,
the output voltages can be ramped up with current foldback
to limit the inrush current during the start-up period. No
external compensation capacitors are required at the
GATE pins. The two channels can be configured to ramp up
and down separately or simultaneously for supply volt-
ages ranging from 2.7V to 13.5V and 1V to 13.5V for
channels 1 and 2 respectively.
Each channel has two current limit comparators that
provide dual level and dual speed overcurrent circuit
breaker protection after the start-up period. If any current
sense voltage exceeds 100mV for 1μs or 25mV for the
timeout delay (set by the C
FILTER
at the FILTER pin), then
the FAULT latch is set and both GATE pins are pulled low.
The FB pins monitor the respective channel output volt-
ages and provide the inputs for the PWRGD comparators
as well as overvoltage protection.
Hot Swap is a trademark of Linear Technology Corporation.
2-Channel Hot Swap Controller
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
U
ON2
FAULT
GND
LTC4221
FB2
PWRGD2
PWRGD1
PWRGD2
V
OUT1
3.3V/5A
V
OUT2
2.5V/5A
PWRGD1
FB1
LONG
LONG
SHORT
GND
FAULT LONG
*SMAJ10 (OPTIONAL)
SHORT
TIMER FILTER
ON1
V
CC1
SENSE1 GATE1 V
CC2
SENSE2 GATE2
SHORT
VCC1
3.3V
VCC2
2.5V
BACKPLANE
CONNECTOR
(FEMALE)
PCB EDGE
CONNECTOR
(MALE)
10Ω
21k
13.3k
10k
10k
10Ω
14.3k
IRF7413
5.11k 10k 10k
20k
5.11k
4221 TA01
100nF **
1nF
470nF
100nF
IRF7413
0.004Ω
0.004Ω
2
LTC4221
4221fa
(Note 1)
Supply Voltage (V
CC
n
) ............................................ 17V
SENSE
n
Pins ............................ – 0.3V to (V
CC
n
+ 0.3V)
FB, ON Pins .............................. –0.3V to (V
CC1
+ 0.3V)
TIMER Pin .................................................. –0.3V to 2V
GATE Pins (Note 3)................................... –0.3V to 21V
PWRGD, FAULT, FILTER Pins................... –0.3V to 17V
Operating Temperature Range
LTC4221C ............................................... 0°C to 70°C
LTC4221I............................................ – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°CT
JMAX
= 125°C, θ
JA
= 130°C/W
ABSOLUTE MAXIMUM RATINGS
W
WW
U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC1
Supply Voltage Channel 1 ●2.7 13.5 V
V
CC2
Supply Voltage Channel 2 V
CC2
≤ V
CC1
●1 13.5 V
I
CC1
V
CC1
Supply Current ON1, ON2 = 2V ●2.2 3 mA
I
CC2
V
CC2
Supply Current ON1, ON2 = 2V ●0.05 0.15 mA
V
CC1(UVL)
Undervoltage Lockout for Channel 1 V
CC1
Rising ●2.1 2.5 2.675 V
ΔV
CC1(HYST)
Undervoltage Lockout Hysteresis 110 mV
V
CC2(UVL)
Undervoltage Lockout for Channel 2 V
CC2
Rising ●0.65 0.8 0.975 V
ΔV
CC2(HYST)
Undervoltage Lockout Hysteresis 25 mV
I
SENSE1(IN)
SENSE1 Pin Input Current 0V ≤ V
SENSE1
≤ V
CC1
●±0.03 ±5μA
I
SENSE2(IN)
SENSE2 Pin Input Current V
SENSE2
= V
CC2
●±0.2 ±5μA
V
SENSE2
= 0V 1000 μA
V
SENSE(FC)
SENSE
n
Threshold Voltage Channel
n
Fast Comparator Threshold ●85 100 115 mV
V
SENSE(SC)
SENSE
n
Threshold Voltage Channel
n
Slow Comparator Threshold 22.5 25 27.5 mV
●20.5 25 29.5 mV
V
SENSE(ACL)
SENSE
n
Voltage at Active V
FB
n
= 0 4 9 16 mV
Current Limit V
FB
n
= 0.65V 17.5 25 32.5 mV
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
ON1
VCC1
SENSE1
GATE1
FB1
PWRGD1
FAULT
FILTER
ON2
VCC2
SENSE2
GATE2
FB2
PWRGD2
GND
TIMER
ELECTRICAL CHARACTERISTICS
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4221CGN#PBF LTC4221CGN#TRPBF 4221 16-Lead Plastic SSOP 0°C to 70°C
LTC4221IGN#PBF LTC4221IGN#TRPBF 4221I 16-Lead Plastic SSOP –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4221CGN LTC4221CGN#TR 4221 16-Lead Plastic SSOP 0°C to 70°C
LTC4221IGN LTC4221IGN#TR 4221I 16-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ORDER I FOR ATIO
UUW
PI CO FIGURATIO
UUU
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3
LTC4221
4221fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
GATE(UP)
GATE
n
Output Current V
ON1
= V
ON2
= 2V, V
GATE
n
= 0V ●–7 –9.5 –12 μA
I
GATE(DN)
GATE
n
Output Current V
ON1
= V
ON2
= 0.6V, V
GATE
n
= 3.3V ●75 100 125 μA
I
GATE(FSTDN)
GATE
n
Output Current UVLO with V
GATE
n
= 3.3V or FAULT 16 mA
Latched with V
GATE
n
= 3.3V
ΔV
GATE
External N-Channel Gate Drive V
GATE
n
– V
CC1
for V
CC1
= 2.7V, V
CC2
= 1V ●4.5 13 V
V
GATE
n
– V
CC1
for V
CC1
= 3.3V, V
CC2
= 2.5V ●516V
V
GATE
n
– V
CC1
for V
CC1
= 5V, V
CC2
= 3.3V ●816V
V
GATE
n
– V
CC1
for V
CC1
= 12V, V
CC2
= 12V ●718V
V
GATE(OV)
GATE
n
Overvoltage Lockout Threshold ●0.4 0.5 V
I
ON(IN)
ON
n
Pin Input Current 0V ≤ V
ON
n
≤ V
CC1
●±0.01 ±1μA
V
ON(RESET)
ON1 Reset Threshold V
ON1
Falling ●0.375 0.4 0.425 V
ΔV
ON(RESETHYST)
ON1 Reset Threshold Hysteresis 25 mV
V
ON(OFF)
ON
n
Off Threshold High to Low, GATE
n
Turns Off by 100μA●0.796 0.821 0.846 V
Pull-Down
ΔV
ON(OFFHYST)
ON
n
Off Threshold Hysteresis 30 mV
I
FB(IN)
FB
n
Input Current 0V ≤ V
FB
n
≤ V
CC
n
●±0.01 ±1μA
V
FB(UV)
FB
n
Undervoltage Threshold FB
n
Falling ●0.605 0.617 0.629 V
ΔV
FB(UVHYST)
FB
n
Undervoltage Threshold Hysteresis 3 mV
ΔV
FB(LREG)
FB
n
Threshold Line Regulation 2.7V ≤ V
CC1
≤ 13.5V 2 mV
V
FB(OV)
FB
n
Overvoltage Threshold FB
n
Rising ●0.805 0.822 0.838 V
I
FILTER(UP)
FILTER Pull-Up Current During Current Fault Condition ●–80 –105 –132 μA
I
FILTER(DN)
FILTER Pull-Down Current During Normal Cycle ●1.15 1.8 2.45 μA
V
FILTER(TH)
FILTER Threshold Latched Off Threshold, FILTER Rising ●1.18 1.24 1.30 V
ΔV
FILTER(HYST)
FILTER Threshold Hysteresis 105 mV
I
TMR(UP1)
TIMER Pull-Up Current 1 Initial Timing Cycle ●–1.2 –1.9 –2.6 μA
I
TMR(UP2)
TIMER Pull-Up Current 2 Start-Up Cycle ●–15 –20 –25 μA
I
TMR(FSTDN)
TIMER Pull-Down Current V
TIMER
= 1.5V, End of Initial Timing Cycle 9 mA
V
TMR(H)
TIMER High Threshold TIMER Rising ●1.172 1.234 1.27 V
V
TMR(L)
TIMER Low Threshold TIMER Falling ●0.1 0.4 0.5 V
I
FAULT(UP)
FAULT Pull-Up Current ●–2.5 –3.8 –5 μA
V
FAULT(TH)
FAULT Threshold FAULT Falling ●0.791 0.816 0.841 V
ΔV
FAULT(HYST)
FAULT Hysteresis 35 mV
V
FAULT(OL)
FAULT Output Low Voltage I
FAULT
= 1.6mA, V
CC1
= 5V ●0.14 0.4 V
I
PWRGD(LK)
PWRGD
n
Leakage Current V
PWRGD
n
= V
CC1
, V
FB
n
= 0.7V, Normal Cycle ●±0.01 ±10 μA
V
PWRGD(OL)
PWRGD
n
Output Low Voltage I
PWRGD
n
= 1.6mA, V
CC1
= 5V, V
FB
n
= 0V, ●0.14 0.4 V
Normal Cycle
t
P(FC-GATE)
Fast Comparator Trip to GATE
n
V
SENSE
n
= V
CC
n
to (V
CC
n
– 200mV) Step ●1 1.5 μs
Discharging
t
P(SC-FAULT)
Slow Comparator Trip to FILTER V
SENSE
n
= V
CC
n
to (V
CC
n
– 50mV) Step. ●15 35 μs
High and FAULT Latched FILTER Open
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
4
LTC4221
4221fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
I
CC1
vs Temperature
TEMPERATURE (°C)
–50
I
CC1
(mA)
4
5
6
25 75
4221 G01
3
2
–25 0 50 100 125
1
0
V
CC2
= 1V
V
CC1
= 13.5V
V
CC1
= 12V
V
CC1
= 5V
V
CC1
= 2.7V
TEMPERATURE (°C)
–50
I
CC2
(mA)
0.175
25
4221 G02
0.100
0.050
–25 0 50
0.025
0
0.200
0.150
0.125
0.075
75 100 125
V
CC1
= 13.5V
V
CC2
= 13.5V
V
CC2
= 12V
V
CC2
= 5V
V
CC2
= 3.3V
V
CC2
= 1V
TEMPERATURE (°C)
–50
V
CC1(UVL)
(V)
2.50
25
4221 G03
2.44
2.40
–25 0 50
2.38
2.36
2.52
2.48
2.46
2.42
75 100 125
TIMER = 0.3V
RISING
FALLING
I
CC2
vs Temperature V
CC1(UVL)
vs Temperature
V
CC2(UVL)
vs Temperature |ISENSE2(IN)| vs VSENSE2 V
SENSE(FC)
vs VCC1
TEMPERATURE (°C)
–50
0.770
V
CC2(UVL)
(V)
0.775
0.785
0.790
0.795
50
0.815
4221 G04
0.780
0
–25 75 100
25 125
0.800
0.805
0.810
TIMER = 0.3V
RISING
FALLING
V
SENSE2
(V)
0
|I
SENSE2(IN)
| (μA)
1000
6
4221 G05
1
0.01
24 8
0.001
0.0001
10000
100
10
0.1
10 12
V
CC1
= 2.7V, V
CC2
= 1V
V
CC1
= 5V, V
CC2
= 3.3V
V
CC1
= 13.5V, V
CC2
= 13.5V
V
CC1
(V)
0
V
SENSE(FC)
(mV)
101.0
101.5
102.0
610 16
4221 G06
100.5
100.0
99.5
24 812 14
V
CC2
= V
CC1
T
A
= 25°C
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All current into device pins are positive. All voltages are referenced
to ground unless otherwise specified.
Note 3: An internal zener on each GATE pin clamps the charge pump
voltage to a typical maximum operating voltage of 26V. External overdrive
of either GATE pin beyond its internal zener voltage may damage the
device.
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 3.3V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
P(FAULT-GATE)
FAULT Low to GATE
n
Discharging V
FAULT
= 3.3V to 0V ●15 35 μs
t
P(OV-GATE)
FB
n
OV Comparator Trip to GATE
n
V
FB
n
= 0V to 1V ●18 35 μs
Discharging
t
P(FILTER-GATE)
Filter Comparator Trip to GATE
n
V
FILTER
= 0V to 1.5V ●15 35 μs
Discharging
t
RESET
Circuit Breaker Reset Delay Time V
ON1
< 0.4V to FAULT High ●15 30 μs
t
P(ON-GATE)
Turn Off Propagation Delay V
ON
n
≤ 0.821V to GATE
n
Discharging ●15 35 μs
5
LTC4221
4221fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VSENSE(ACL) vs VFB I
GATE(UP)
vs Temperature I
GATE(DN)
vs Temperature
I
GATE(FSTDN)
vs Temperature ΔVGATE
n
(VGATE
n
– VCC1) vs VCC1
V
FB
(V)
0
V
SENSE(ACL)
(mV)
20
25
30
0.3 0.5
4221 G10
15
10
0.1 0.2 0.4 0.6 0.7
5
0
V
CC1
= 5V
V
CC2
= 3.3V
T
A
= 25°C
TEMPERATURE (°C)
–50
I
GATE(UP)
(μA)
–8
–7
–6
25 75
4221 G11
–9
–10
–25 0 50 100 125
–11
–12
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
GATE
= 0V
TEMPERATURE (°C)
–50
101
102
104
25 75
4221 G12
100
99
–25 0 50 100 125
98
97
103
I
GATE(DN)
(μA)
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
GATE
= 3.3V
TEMPERATURE (°C)
–50
I
GATE(FSTDN)
(mA)
40
50
60
25 75
4221 G13
30
20
–25 0 50 100 125
10
0
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
GATE
= 3.3V
V
CC1
(V)
0
6
V
GATE
n
(V)
7
9
10
11
8
15
4221 G14
8
4
210 12
614
12
13
14
V
CC2
= V
CC1
– 1.5V
T
A
= 25°C
ΔV
GATE1
ΔV
GATE2
ΔVGATE1 (VGATE1 – VCC1)
vs Temperature
TEMPERATURE (°C)
–50
12
14
18
25 75
4221 G15
10
8
–25 0 50 100 125
6
4
16
ΔV
GATE1
(V)
V
CC1
= 2.7V, V
CC2
= 1V
V
CC1
= 5V, V
CC2
= 3.3V
V
CC1
= 13.5V, V
CC2
= 13.5V
V
SENSE(FC)
vs Temperature VSENSE(SC) vs VCC1 V
SENSE(SC)
vs Temperature
TEMPERATURE (°C)
–50
V
SENSE(FC)
(mV)
101.0
101.5
102.0
25 75
4221 G07
100.5
100.0
–25 0 50 100 125
99.5
99.0
V
CC1
= 5V
V
CC2
= 3.3V
V
CC1
(V)
0
V
SENSE(SC)
(mV)
25.0
25.2
25.4
12
4221 G08
24.8
24.6
48
214
610 16
24.4
24.2
25.6 V
CC2
= V
CC1
T
A
= 25°C
TEMPERATURE (°C)
–50
V
SENSE(SC)
(mV)
25.8
25
4221 G09
25.2
24.8
–25 0 50
24.6
24.4
26.0
25.6
25.4
25.0
75 100 125
V
CC1
= 5V
V
CC2
= 3.3V
6
LTC4221
4221fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VON(RESET) vs Temperature V
ON(OFF)
vs VCC1 V
ON(OFF)
vs Temperature
TEMPERATURE (°C)
–50
0.395
V
ON(RESET)
(V)
0.405
0.410
0.415
50
0.440
4221 G19
0.400
0
–25 75 100
25 125
0.425
0.420
0.430
0.435
V
CC1
= 5V
V
CC2
= 3.3V
RISING
FALLING
V
CC1
(V)
0
V
ON(OFF)
(V)
0.840
0.845
0.850
16
4221 G20
0.835
0.830
0.815 4812
2610 14
0.825
0.820
0.860
0.855
V
CC2
= 1V
T
A
= 25°C
RISING
FALLING
TEMPERATURE (°C)
–50
V
ON(OFF)
(V)
0.85
0.86
0.87
25 75
4221 G21
0.84
0.83
–25 0 50 100 125
0.82
0.81
V
CC1
= 5V
V
CC2
= 3.3V
RISING
FALLING
VFB(UV) vs VCC1 V
FB(UV)
vs Temperature V
FB(OV)
vs VCC1
V
CC1
(V)
0
V
FB(UV)
(V)
0.618
0.620
16
4221 G22
0.616
0.614 4812
2610 14
0.622
0.617
0.619
0.615
0.621
V
CC2
= 1V
T
A
= 25°C
RISING
FALLING
TEMPERATURE (°C)
–50
VFB(UV) (V)
0.623
0.622
0.621
0.620
0.619
0.618
0.617
0.616
0.615
0.614
0.613 050 75
4221 G23
–25 25 100 125
VCC1 = 5V
VCC2 = 3.3V
RISING
FALLING
V
CC1
(V)
0
V
FB(OV)
(V)
0.8210
0.8215
0.8220
12
4221 G24
0.8205
0.8200
48
214
610 16
0.8195
0.8190
0.8225 V
CC2
= 1V
T
A
= 25°C
VGATE(OV) vs Temperature V
ON(RESET)
vs VCC1
ΔVGATE2 (VGATE2 – VCC1)
vs Temperature
TEMPERATURE (°C)
–50
ΔV
GATE2
(V)
12
14
16
25 75
4221 G16
10
8
–25 0 50 100 125
6
4
V
CC1
= 2.7V, V
CC2
= 1V
V
CC1
= 5V, V
CC2
= 3.3V
V
CC1
= 13.5V, V
CC2
= 13.5V
TEMPERATURE (°C)
–50
0.375
V
GATE(OV)
(V)
0.385
0.390
0.395
50
0.420
4221 G17
0.380
0
–25 75 100
25 125
0.405
0.400
0.410
0.415
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
TIMER = 0.5V
V
CC1
(V)
0
V
ON(RESET)
(V)
0.415
0.420
0.425
12
4221 G18
0.410
0.405
48
214
610 16
0.400
0.395
0.430 V
CC2
= 1V, T
A
= 25°C
FALLING
RISING
7
LTC4221
4221fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VFILTER(TH) vs Temperature I
TMR(UP1)
vs Temperature
TEMPERATURE (°C)
–50
V
FILTER(TH)
(V)
1.246
1.244
1.242
1.240
1.238
1.236
1.234
1.232
1.230
1.228
1.226
1.224 050 75
4221 G28
–25 25 100 125
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
GATE1
= 0.2V
TEMPERATURE (°C)
–50
I
TMR(UP1)
(μA)
–1.8
–1.7
–1.6
25 75
4221 G29
–1.9
–2.0
–25 0 50 100 125
–2.1
–2.2
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
TMR
= 0.25V
I
TMR(UP2)
vs Temperature
TEMPERATURE (°C)
–50
I
TMR(UP2)
(μA)
–17.0
–17.5
–18.0
–18.5
–19.0
–19.5
–20.0
–20.5
–21.0
–21.5
–22.0 050 75
4221 G30
–25 25 100 125
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
TMR
= 0.25V
ITMR(FSTDN) vs Temperature V
TMR(H)
vs Temperature
TEMPERATURE (°C)
–50 –25
0
I
TMR(FSTDN)
(mA)
10
25
050 75
4221 G31
5
20
15
25 100 125
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
TMR
= 1.5V
TEMPERATURE (°C)
–50
V
TMR(H)
(V)
1.240
1.238
1.236
1.234
1.232
1.230
1.228
1.226
1.224
1.222
1.220 050 75
4221 G32
–25 25 100 125
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
TMR(L)
vs Temperature
TEMPERATURE (°C)
–50
V
TMR(L)
(V)
0.403
25
4221 G33
0.400
0.398
–25 0 50
0.397
0.396
0.404
0.402
0.401
0.399
75 100 125
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
VFB(OV) vs Temperature I
FILTER(UP)
vs Temperature
TEMPERATURE (°C)
–50
VFB(OV) (V)
0.825
0.824
0.823
0.822
0.821
0.820
0.819
0.818
0.817
0.816
0.815 050 75
4221 G25
–25 25 100 125
VCC1 = 5V
VCC2 = 3.3V
TEMPERATURE (°C)
–50
I
FILTER(UP)
(μA)
–98
–93
–88
25 75
4221 G26
–103
–108
–25 0 50 100 125
–113
–118
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
FILTER
= 1V
I
FILTER(DN)
vs Temperature
TEMPERATURE (°C)
–50
1.85
1.90
2.00
25 75
4221 G27
1.80
1.75
–25 0 50 100 125
1.70
1.65
1.95
I
FILTER(DN)
(μA)
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
FILTER
= 1V
8
LTC4221
4221fa
UU
U
PI FU CTIO S
ON1
(Pin 1): System/Channel 1 On Input. Both GATE pins
are pulled low by internal 100μA pull-downs and the
FAULT latch is reset when V
ON1
< 0.4V. When 0.425V <
V
ON1
< 0.821V, the FAULT latch is released from reset.
When V
ON1
> 0.851V, GATE1 ramps up after an initial
timing cycle.
V
CC1
(Pin 2): Channel 1 Positive Supply Input. It powers
all the internal circuitry. V
CC1
can range from 2.7V to 13.5V
for normal operation but it must be ≥V
CC2
. An undervolt-
age lockout circuit disables both channels whenever the
voltage at V
CC1
is less than 2.5V.
SENSE1 (Pin 3): Channel 1 Current Sense Input. A sense
resistor R
SENSE1
is placed in the supply path between V
CC1
and SENSE1 to sense channel 1 load current. If V
RSENSE1
exceeds 100mV for more than 1μs or 25mV for an adjust-
able time (set by the C
FILTER
), the FAULT latch is set and
fast pull-down circuits are triggered to discharge both
GATEs
low. During the start-up cycle, GATE1
ramp-up is
controlled to servo V
RSENSE1
≤ V
SENSE(ACL)
. V
SENSE(ACL)
increases from 9mV to 25mV as V
FB1
ramps from 0V to
0.5V. To disable the current limit and circuit breaker
function for channel 1, tie SENSE1 to V
CC1
.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VPWRGD(OL)/VFAULT(OL)
vs Temperature tp
(SC-FAULT)
vs Temperature
TEMPERATURE (°C)
–50
VOL (V)
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0050 75
4221 G37
–25 25 100 125
VCC1 = 2.7V
VCC1 = 5V
VCC1 = 13.5V
VCC2 = 1V, IPWRGD/IFAULT = 1.6mA
tp
(FC-GATE)
vs Temperature
TEMPERATURE (°C)
–50
tp
(SC-FAULT)
(μS)
16
17
18
25 75
4221 G38
15
14
–25 0 50 100 125
13
12
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
TIMER = 0.5V
TEMPERATURE (°C)
–50
tp
(FC-GATE)
(μS)
1.4
1.6
1.8
25 75
4221 G39
1.2
1.0
–25 0 50 100 125
0.8
0.6
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
TIMER = 0.5V
IFAULT(UP) vs Temperature V
FAULT(TH)
vs VCC1 V
FAULT(TH)
vs Temperature
TEMPERATURE (°C)
–50
–3.7
–3.5
–3.1
25 75
4221 G34
–3.9
–4.1
–25 0 50 100 125
–4.3
–4.5
–3.3
I
FAULT(UP)
(μA)
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V
V
FAULT
= 1.5V
VCC1 (V)
0
0.810
VFAULT(TH) (V)
0.815
0.825
0.830
0.835
0.860
0.845
4810
4221 G35
0.820
0.850
0.855
0.840
26 12 14 16
VCC2 = 1V
TA = 25°C
RISING
FALLING
TEMPERATURE (°C)
–50
0.84
0.85
0.87
25 75
4221 G36
0.83
0.82
–25 0 50 100 125
0.81
0.80
0.86
V
FAULT(TH)
(V)
V
CC1
= 5V
V
CC2
= 3.3V RISING
FALLING
9
LTC4221
4221fa
UU
U
PI FU CTIO S
GATE1 (Pin 4): Channel 1 Gate Drive. This pin is the high
side gate drive of an external N-channel MOSFET. When
V
ON1
< 0.821V, GATE1 is held low by a 100μA current
source. When V
ON1
> 0.851V, an initial timing cycle is
followed by a start-up cycle when an internal charge pump
provides a 9.5μA pull-up to ramp up GATE1 with inrush
current limiting. UVLO, overvoltage, overcurrent and ex-
ternally generated faults override the ON1 pin and pull
GATE1 low.
FB1
(Pin 5): V
OUT1
Feedback Input. FB1
monitors the
channel 1 output voltage with an external resistive divider.
When V
FB1
< 0.617V, the PWRGD1
pin is pulled low. When
V
FB1
> 0.822V, overvoltage is detected, the FAULT latch is
set and both GATEs are pulled low. The FB1
pin is also used
to control the channel 1 current limit during its start-up
cycle.
PWRGD1 (Pin 6): Channel 1 Power Good Output. PWRGD1
is pulled low when V
FB1
< 0.617V, during the initial timing
cycle or when the chip is in UVLO. An external pull-up is
required to generate a logic high at the open-drain PWRGD1
pin.
FAULT (Pin 7): Fault Status Input/Output. FAULT is a
bidirectional pin. As an input, pulsing V
FAULT
< 0.816V will
set the FAULT latch and bring the LTC4221 into the fault
state. As an output, FAULT is pulled high by an internal
3.8μA pull-up under normal operating conditions. When
an overcurrent fault is detected by a SENSE pin or a
overvoltage fault detected by an FB pin, the FAULT latch is
set and the LTC4221 goes into the fault state. The FAULT
latch is reset by a UVLO or the ON1 pin being driven below
0.4V.
FILTER (Pin 8): Overcurrent Fault Timing Filter. The
FILTER pin requires an external capacitor to ground to
adjust the response time of the two slow comparators. The
FILTER pin can be left unconnected for a default slow
comparator response time of 15μs.
TIMER (Pin 9): Analog System Timer. The TIMER pin
requires an external capacitor to ground to generate
timing delay cycles during start-up. The LTC4221’s initial
and start-up timing cycles are controlled by C
TIMER
and the
internal current sources connected to the TIMER pin.
GND (Pin 10): Ground. Connect to a ground plane for
optimum performance.
PWRGD2 (Pin 11): Channel 2 Power Good Output. Similar
functionality as PWRGD1. Controlled by FB2.
FB2 (Pin 12): V
OUT2
Feedback Input. Similar functionality
as FB1. Monitors channel 2 output voltage, controls
PWRGD2 output and channel 2 start-up current limit.
GATE2 (Pin 13): Channel 2 Gate Drive. Similar functional-
ity as GATE1. Controls the gate drive of the channel 2
external N-channel MOSFET. ON2 controls GATE2 in the
same manner as ON1 controls GATE1. V
ON1
< 0.4V over-
rides conditions at ON2 and GATE2 is held low by a 100μA
current source. UVLO, overvoltage, overcurrent and exter-
nally generated faults override conditions at ON1 and ON2,
and pull GATE2 low.
SENSE2 (Pin 14): Channel 2 Current Sense Input. Similar
functionality as SENSE1. Monitors channel 2 load current
through R
SENSE2
placed in the supply path between V
CC2
and SENSE2. To disable the current limit and circuit
breaker function for channel 2, tie SENSE2 to V
CC2
.
V
CC2
(Pin 15): Channel 2 Positive Supply Input. V
CC2
can
range from 1V to 13.5V for normal operation but it must
be ≤V
CC1
. An undervoltage lockout circuit disables both
channels whenever the voltage at V
CC2
is less than 0.8V.
ON2 (Pin 16): Channel 2 On Input. GATE2 is pulled to
ground by a 100μA current source when V
ON2
< 0.821V.
When V
ON2
> 0.851V, GATE2 ramps up after an initial
timing cycle.
10
LTC4221
4221fa
BLOCK DIAGRA
W
26V
9.5μA
100μA
CPO2
V
CC2
CUR_LIMIT2
FPD2
+
–
CHARGE
PUMP 1
CHARGE
PUMP 2
UVLO
OSCILLATOR
V
CC1
V
CC1
V
CC2
CPO1
CPO2
0.821V
ON1
COMPARATOR
SYSTEM
CONTROL
LOGIC
0.4V
V
CC1
1
ON1
+
–
ON2
COMPARATOR
FILTER
COMPARATOR
TMRHI
COMPARATOR
FAULT
COMPARATOR
0.821V
FTRHI
TMRHI
TIMER
1.234V
FAULT_LO
105μA
1.8μA
+
–
+
–
1.24V
0.816V
+
–
0.617V
+
–
OV1
COMPARATOR
FB1
COMPARATOR
0.822V
+
–
16 9
ON2
8
FILTER
V
CC1
3.8μA
V
CC1
V
CC1
FAULT 7GND
10
GATE1
26V
PWRGD1
CHANNEL ONE
20μA1.9μA
V
CC1
V
CC1
9.5μA12V
12V
100μA
CPO1
V
CC1
CUR_LIMIT1
FPD1
TMRLO
COMPARATOR
TMRLO 0.4V
+
–
+
–
SLOW
COMPARATOR 1
CHANNEL 1
CONTROL
LOGIC
SLOWHI1
9mV TO 25mV
FASTHI1
2
V
CC1
+
–
FAST
COMPARATOR 1
GATELO1
COMPARATOR
GATELO1 0.4V
+
–
SENSE1
+
–
V
CC1
100mV
+
–
3
FB1 5
6
4
0.617V
+
–
OV2
COMPARATOR
FB2
COMPARATOR
0.822V
+
–
V
CC2
GATE2
PWRGD2
4221 BD
CHANNEL TWO
+
–
SLOW
COMPARATOR 2
CHANNEL 2
CONTROL
LOGIC
SLOWHI2
9mV TO 25mV
FASTHI2
15
V
CC2
+
–
FAST
COMPARATOR 2
GATELO2
COMPARATOR
GATELO2 0.4V
+
–
SENSE2
+
–
V
CC2
100mV
+
–
14
FB2 12
11
13
11
LTC4221
4221fa
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current may damage the connector pins and glitch the
power bus, causing other boards in the system to reset.
The LTC4221 is designed to turn on and off a circuit
board’s supply voltages in a controlled manner, allowing
insertion or removal without glitches or connector dam-
age. The LTC4221 can reside on the backplane or on the
removable circuit board for hot insertion applications. It
controls the path between the backplane power bus and
the daughter board load with an external MOSFET switch.
Both inrush control and short-circuit protection are pro-
vided by the external MOSFET. Each LTC4221 controls
two channels, each with its individual MOSFET for sup-
plies from 1V to 13.5V.
Overview
The timing diagram in Figure 1 shows some typical wave-
forms of the LTC4221. The V
CC
and GND pins receive
power through the longest connector pins and are the first
to connect when the board is inserted. During the under-
voltage lockout (UVLO) state before time point 1, both
GATE pins are held low by internal N-channel MOSFET
pull-downs, turning the external MOSFETs off. Once both
V
CC
pins are valid at time point 1, the LTC4221 enters into
a reset state as ON1 is below its reset threshold. At time
point 2, ON1 clears its reset threshold and the device goes
from the reset state to an off state. When either ON1 or
ON2 clears its off threshold, both GATE pins are < 0.4V and
TIMER < 0.4V (time points 3 and 4), the TIMER pin sources
1.9μA and an initial timing cycle starts. Any transition of
ON1 and ON2 through their off thresholds will reset the
initial timing cycle. At time point 5, TIMER reaches its high
threshold and is pulled down by an internal N-channel
MOSFET to its low threshold at time point 6. The LTC4221
then checks that FILTER pin voltage is low and FAULT pin
voltage is high. If both conditions are met, the electronic
circuit breaker is armed. The channel 1 start-up timing
cycle starts at time point 6 since ON1 has cleared its off
threshold and ON2 has not.
OPERATIO
U
During the start-up cycle, TIMER sources 20μA and GATE1
sources 9.5μA. As GATE1 ramps up, MOSFET1 starts to
turn on and current flows through to charge up the load
capacitance. As V
OUT1
and FB1 ramp up, the load current
is monitored through the external SENSE1 resistor. Be-
tween time points 7 and 8, the GATE1 9.5μA pull-up is
controlled to servo the voltage across R
SENSE1
to be less
than the SENSE1 active current limit voltage, which has a
component controlled by the FB1 voltage (see Applica-
tions Information: Start-Up Cycle with Current Limit). In
this way, inrush current is limited and MOSFET1 does not
overheat during the start-up cycle. When FB1 clears its
undervoltage threshold, PWRGD1 asserts high. At time
point 9, TIMER reaches its high threshold and is pulled
down by an internal N-channel MOSFET to its low thresh-
old at time point 10. Channel 1’s slow comparator is armed
at time point 9 and enters a fault monitor mode, bringing
the channel 1 start-up cycle to an end.
At time point 10, ON2 voltage is monitored and since ON2
has cleared its off threshold, the start-up timing cycle
repeats for channel 2. The inrush current is low and GATE2
ramps up without need for current limiting. Channel 2’s
slow comparator is armed at time point 11 and enters a
fault monitor mode, ending the channel 2 start-up cycle.
Overcurrent faults translate to an increase in either V
RSENSE
.
At time point 13, V
RSENSE1
> 25mV (slow comparator
threshold). The 1.8μA pull-down on the FILTER changes to
a 105μA pull-up. When the FILTER pin hits its threshold at
time point 14, it triggers a fault state when FAULT is
latched low and both GATE pins are pulled low by internal
N-channel MOSFETs, turning off the external MOSFETs.
As each channel output discharges, its FB pin goes below
the undervoltage threshold and the PWRGD pin deasserts.
Higher overcurrents when either V
RSENSE
> 100mV (fast
comparator threshold) for more than 1μs will trigger the
same condition. This fault state can only be cleared by a
UVLO at either V
CC
pin or a hard reset at the ON1 pin, as
at time point 15, when ON1 is pulled below its reset
threshold. The LTC4221 then reverts back to its reset state
as between time points 1 and 2.
12
LTC4221
4221fa
OPERATIO
U
V
CC
n
TIMER
FAULT
FILTER
ON1
V
ON(OFF)
+ ΔV
ON(OFFHYST)
V
ON(RESET)
+ ΔV
ON(RESETHYST)
V
ON(OFF)
V
GATE(OV)
V
ON(OFF)
+ ΔV
ON(OFFHYST)
ON2
GATE1
GATE2
SENSE1
SENSE2
V
OUT1
V
OUT2
PWRGD1
PWRGD2
UVLO OFF INITIAL TIMING
RESET
100μA
100μA
V
CC
n
(UVL)
1
V
CC
n
CLEARS V
CC
n
(UVL)
ELECTRONIC CIRCUIT BREAKER ARMED, CHECK FILTER < V
FILTER(TH)
,
FAULT > V
FAULT(TH)
+ ΔV
FAULT(HYST)
ON1 > V
ON(RESET)
+ ΔV
ON(RESETHYST)
CHANNEL 1 SLOW COMPARATOR ARMED
ON2 > V
ON(OFF)
, + ΔV
ON(OFFHYST)
,
CHECK GATE < V
GATE(OV)
,
TIMER < 0.4V
ON1 > V
ON(OFF)
+ ΔV
ON(OFFHYST)
,
CHECK GATE < V
GATE(OV)
,
TIMER < 0.4V
2
CHANNEL 2 SLOW COMPARATOR ARMED
3 4 5 6 7 8 9 10 11 12 13 14 15
1.9μA
V
TMR(H)
V
TMR(L)
20μA20μA
1.8μA
V
FILTER(TH)
105μA
V
ON1(RESET)
V
GATE(OV)
9.5μA
9.5μA
25mV
9mV
9mV
V
SENSE(FC)
V
SENSE(SC)
FB1 > V
FB(UV)
+ ΔV
FB(HYST)
FB1 < V
FB(UV)
FB2 < V
FB(UV)
FB2 > V
FB(UV)
+ ΔV
FB(HYST)
CHANNEL 1
START-UP
CHANNEL 2
START-UP
NORMAL FAULT RESET
4221 F01
Figure 1. LTC4221 Operation
13
LTC4221
4221fa
APPLICATIO S I FOR ATIO
WUUU
Undervoltage Lockout
An internal undervoltage lockout (UVLO) occurs if either
V
CC
supply is too low for normal operation. The LTC4221
is kept in lockout mode in which the internal charge pumps
are off, the GATE pins, TIMER are held low by internal
N-channel MOSFET pull-downs and the FAULT latch reset,
cutting off both channels. V
CC1
has a low-to-high UVLO
threshold of 2.5V with 110mV hysteresis. V
CC2
has a low-
to-high UVLO threshold of 0.8V with 25mV hysteresis.
Both UVLOs have glitch filters that filter out dips that are
less than 30μs, allowing for bus supply transients. An
additional requirement for normal operation is V
CC1
≥
V
CC2
.
ON Pin Functions
The ON1 pin serves as a global reset for the LTC4221. It
has an internal reset comparator with a high-to-low thresh-
old of 0.4V, a 25mV hysteresis and a high-to-low glitch
filter of 15μs. Pulling ON1 below this threshold will put the
LTC4221 into a reset state in which the TIMER is pulled low
by an internal N-channel MOSFET pull-down, the GATE
pins are pulled low by separate internal 100μA pull-downs
and the FAULT latch resets. A low-to-high transition on the
ON1 pin past the reset threshold releases the reset on the
FAULT latch and both channels go into an off state.
In addition to its global reset function, ON1 also serves as
an on/off switch for channel 1. ON2 performs the same
role for channel 2. Both pins have an off comparator with
a high-to-low threshold of 0.821V and 30mV hysteresis.
With these, ON1 and ON2 can be used to force a simulta-
neous or sequential power-up/power-down of the two
channels. A simultaneous power-up and power-down is
shown in Figure 2b. Both V
CC
pins clear their respective
UVLO at time point 1 and both channels enter reset state.
When ON1 clears its reset threshold, either ON1 or ON2
clears its off threshold, both GATEs
< 0.4V and TIMER <
0.4V (time point 2), an initial timing cycle starts. At time
point 4, the initial timing cycle completes and the LTC4221
checks that FILTER is low and FAULT is high. If both
conditions are met, it then monitors the voltage of ON1 and
ON2. As long as its ON pin has cleared its off threshold,
each channel powers up regardless of the state of the other
channel. Similarly, if its ON pin goes below its off thresh-
old, each channel pulls its GATE pin down with an internal
100μA pull-down and turns off its external MOSFET re-
gardless of the state of the other channel. As the circuit in
Figure 2a has its two ON pins shorted together, a simulta-
neous power-up is programmed at time points 4 to 5 and
a simultaneous power down is programmed between time
points 7 and 8. The timing waveforms in Figure 3 show a
+
V
CC1
ON1
SENSE1ON2
R
F2
15k
LTC4221*
GATE1
FB1
4221 F02a
4221 F02b
1
16
10
9C
TIMER
1μF
GND
TIMER
(2a) Circuit (2b) Timing Waveforms
R
F1
56k
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
Q1
IRF7413
R
SENSE1
0.004Ω
C
LOAD1
Z1
Z1 = SMAJ10
* ADDITIONAL DETAILS
OMITTED FOR CLARITY
R
X1
10Ω
C
X1
100nF
R1
10k
R2
10k
LONG
V
CC1
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
LONG
V
CC2
DISCHARGE
BY LOAD
1
V
CC
n
V
OUT
n
ON
n
GATE
n
UVLO INITIAL
TIMING
CHANNEL
START-UP
RESET STATE
TIMER
0.851V
1.234V
0.821V
9.5μA100μA
V
TH
20μA
234 56 78
NORMAL RESET
V
CC
n
(UVL)
1.9μA
Figure 2. Simultaneous Power On/Off
14
LTC4221
4221fa
sequential power up from time points 4 to 8 and a
sequential power-down programmed from time points 9
to 11. To achieve this the circuit requires the functionality
of the PWRGD1 pin and will be featured in the next section.
The circuit in Figure 2a sits on a daughter board with
staggered pins on its edge connectors. Supply voltage and
ground connections are wired to long-edge connector
pins while both ON pins are connected to a short-edge
connector pin through a resistive divider. Until the con-
nectors are fully mated, ON1 is pulled low and holds both
channels in the reset state. When the connectors have
properly seated, the ON pins are pulled above 0.851V and
an initial timing cycle starts. This cycle is restarted by any
transitions on the ON pins across their off thresholds and
adds a further delay for the plug-in transients to die off
before allowing a start-up cycle. The Typical Application
circuit on the first page of this data sheet shows similar
considerations in the design of its PCB edge connectors,
and the resistive dividers connected to ON1 and ON2 act
as an external UVLO to override the internal one. An RC
filter can be added at the ON1 pin to increase the delay time
at card insertion to allow bus supply transients to stabilize.
FB and PWRGD Pin Functions
Each FB pin is used to detect undervoltage and overvoltage
in its channel output voltage (V
OUT
) through a resistive
divider. Each FB pin has an undervoltage comparator with
a high-to-low threshold of 0.617V and 3mV hysteresis.
The output of this comparator controls the channel’s
open-drain PWRGD output. During UVLO, both PWRGD
pins are pulled low by internal N-channel MOSFET pull-
downs. As both channels come out of UVLO, control of
PWRGD1 is passed to FB1and control of PWRGD2 to FB2.
Each PWRGD pin can be connected to a pull-up resistor to
0.821V
100μA
V
CC
n
12 34 5 67 8 91011
ON1
TIMER
GATE1
V
OUT1
PWRGD1
ON2
GATE2
UVLO INITIAL
TIMING
RESET
V
OUT2
V
CC
n
(UVL)
0.851V 0.821V
0.4V
1.234V 20μA
100μA
DISCHARGE
BY LOAD
DISCHARGE
BY LOAD
4221 F03
20μA
9.5μA
9.5μA
V
TH
0.851V
V
TH
V
FB1
= 0.620V V
FB1
= 0.617V
CHANNEL 1
START-UP
CHANNEL 2
START-UP CHANNEL 1 OFF
CHANNEL 2 NORMAL
NORMAL OFF
1.9μA
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Sequential Power On/Off Timing Waveforms
15
LTC4221
4221fa
generate a logic high output to indicate that V
OUT
is valid.
An internal high-to-low glitch filter helps to prevent nega-
tive voltage transients on each FB pin from deasserting its
PWRGD. The relationship between glitch filter time and an
FB pin transient voltage is shown in Figure 4. Using the
functionality of the PWRGD1 pin, the LTC4221 can be
configured to do sequential power-up and power-down as
shown by the circuit in Figure 5. Referring back to Figure 3,
ON2 is held low until V
OUT1
ramps high enough for FB1 to
exceed its undervoltage threshold at time point 5 when
PWRGD1 ramps up, pulling ON2 high. At time point 7, the
control logic sees ON2 exceeding its off threshold and so
commences a start-up cycle for channel 2. Similarly, when
ON1 is forced low by Q2 at time point 9, GATE1 is pulled
low by its 100μA pull-down while ON2 is held high by the
R4 pull-up on PWRGD1. Its is only when channel 1 is
powered off and V
OUT1
discharges below its undervoltage
threshold at time point 10 that PWRGD1’s internal
N-channel MOSFET pull-down is triggered and ON2 goes
low. At time point 11, ON2 trips its off threshold and
GATE2 pulls low with a 100μA pull-down, powering off
channel 2.
For V
OUT
overvoltage detection, each FB pin has an over-
voltage comparator with a low-to-high threshold of 0.822V
and a low-to-high glitch filter of 18μs. This threshold is
designed to be 33% higher than the undervoltage thresh-
old. If either FB pin trips this threshold, the fault latch is set,
all GATE pins are pulled low with internal NFET pull-downs
and the LTC4221 goes into a fault state.
In the third function, each FB pin is used to control its
channel’s current limit during its start-up cycle. This will
be featured in the Start-Up Cycle with Current Limit
section.
GATE Pin Functions
Each GATE pin controls the gate of its channel’s external
N-channel MOSFET. Individual internal charge pumps
powered by V
CC1
guarantee a gate drive of minimum 4.5V
and maximum 18V (internally clamped) for GATE1 and
GATE2. During UVLO, the internal charge pumps are off
and both GATE pins are pulled low by internal N-channel
MOSFET pull-downs. Outside UVLO, when ON1 is below
its off threshold, the charge pumps are on and GATE1 is
held low by an internal 100μA current pull-down. Once
APPLICATIO S I FOR ATIO
WUUU
+
VCC1
ON1
SENSE1ON2
PWRGD1
RF2
15k
LTC4221*
GATE1
FB1
4221 F05
1
16
6
10
9CTIMER
1μF
GND
TIMER
RF1
56k
VOUT1
3.3V
5A
VOUT2
2.5V
5A
Q1
IRF7413
RSENSE1
0.004Ω
CLOAD1
Z1
Q2: 2N7002LT1
Z1: SMAJ10
* ADDITIONAL DETAILS
OMITTED FOR CLARITY
RX1
10Ω
CX1
100nF
R4
10k
R2
2k
Q2 R1
10k
R6
10k
R5 10Ω
R3 10k
LONG
VCC1
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
LONG
VCC2
ON/OFF
Figure 5. Using PWRGD1 to Configure Sequential Power-Up/Power-Down
FEEDBACK TRANSIENT (mV)
GLITCH FILTER TIME (μs)
40
60
80
20
50
70
30
10
00 20 40 60 80 100 120 140 160 180 200
4221 F04
TA = 25°C
Figure 4. FB Comparator Glitch Filter
Time vs Feedback Transient Voltage
16
LTC4221
4221fa
ON1 clears its off threshold and the initial timing cycle is
complete, the GATE1 pin is pulled up by a 9.5μA current
source connected to the charge pump output during the
channel start-up cycle. GATE1 can be servoed by adjusting
the ramp up current to <9.5μA to control the inrush
current to the load during start-up. ON2 controls GATE2 in
a similar manner but is overwritten by ON1’s global reset
function. During an overcurrent fault condition that sets
the fault latch, both GATE pins are pulled down by their
respective internal N-channel MOSFET pull-downs.
During hot insertion of the PCB, an abrupt application of
supply voltage charges the external MOSFET drain/gate
capacitance. This can cause an unwanted gate voltage
spike. An internal proprietary circuit holds both GATE pins
low before the internal circuitry wakes up. This reduces the
MOSFET current surges substantially at insertion.
Electronic Circuit Breaker
The LTC4221 features an electronic circuit breaker func-
tion that protects against supply overvoltage, externally
generated fault conditions and shorts or excessive load
current conditions on any of the supplies. If the circuit
breaker trips, both GATE pins are immediately pulled to
ground, the external N-channel MOSFETs are quickly
turned OFF and FAULT is latched low.
During the normal cycle, a supply overvoltage on channel
n
propagates via the V
OUT
n
resistive dividers to the FB
n
pin.
A supply overvoltage high enough to pull either FB pin
above 0.822V for more than 18μs will trip the circuit
breaker.
The circuit breaker can also be made to trip by externally
forcing the bidirectional FAULT pin below 0.816V. The
FAULT pin has 35mV of hysteresis. An internal glitch filter
of 15μs filters out noise on the FAULT pin.
The slow comparator of channel
n
trips the circuit breaker
if V
RSENSE
n
= (V
CC
n
– V
SENSE
n
) is greater than its 25mV
threshold for more than 15μs. There may be applications
where this inherent response time is not long enough, for
example, because of excessive supply voltage noise. To
adjust the response time of the slow comparator, a capaci-
tor can be connected from the FILTER pin to GND. If this
pin is left unused, each slow comparator’s delay defaults
to 15μs. During normal operation, the FILTER output pin
is held low by an internal 1.8μA pull-down current source.
During an overcurrent condition on either channel as
shown in Figure 6, the 1.8μA pull-down on the FILTER pin
becomes an internal 105μA pull-up and C
FILTER
charges
up. Once the FILTER pin voltage ramps past its low-to-
high threshold of 1.24V at time point 2, the electronic
circuit breaker trips and the LTC4221 shuts down. The
FILTER pin’s internal 1.8μA pull-down discharges C
FILTER
and holds FILTER low. Each slow comparator’s response
time from an overcurrent fault condition is:
tVC
As
FILTER FILTER
=μ+μ
124
105 15
.•
(1)
Intermittent overloads may exceed the current limit as in
Figure 7, but if the duration is sufficiently short, the FILTER
pin may not reach the V
FILTER(TH)
threshold and the
LTC4221 will not shut down. To handle this situation, the
FILTER discharges with 1.8μA whenever both V
RSENSE
are
below 25mV. Any intermittent overload with an aggregate
APPLICATIO S I FOR ATIO
WUUU
Figure 7. Multiple Intermittent Overcurrent Condition
A1 B1 A2 B2 A3 B3
~25mV/RSENSE1
~25mV/RSENSE2
CIRCUIT BREAKER
TRIPS
1.8μA
1.8μA
4221 F07
1.8μA
105μA
105μA
105μA
ILOAD1
ILOAD2
VFILTER
VGATE
1.24V
1.8μA
SLOW
COMPARATOR
TRIP
SLOW
COMPARATOR
TRIP
SLOW
COMPARATOR
TRIP
Figure 6. A Continuous Fault Timing
1.24V
12
NORMAL SLOW
COMPARATOR
TRIP
VFILTER
CIRCUIT BREAKER TRIPS.
GATE1, GATE2 AND
FAULT PULL LOW
1.8μA
1.8μA
4221 F06
1.8μA105μA
17
LTC4221
4221fa
duty cycle of more than 1.8% will eventually trip the circuit
breaker. Figure 8 shows the circuit breaker response time
in seconds normalized to 1μF. The asymmetric charging and
discharging of FILTER is a fair gauge of MOSFET heating.
t
CF
V
AD A
FILTER
μ
()
=μ
()
μ
124
105 1 8
.
•–.
(2)
The fast comparators trip the circuit breaker to protect
against fast load overcurrents if V
RSENSE
is greater than
V
SENSE(FC)
(100mV) for 1μs. The response time of each fast
comparator is fixed at 1μs nominal. The timing diagram in
Figure 9 illustrates the operation of the LTC4221 when the
load current conditions cause V
RSENSE
of channel 1 to ex-
ceed 100mV for more than 1μs between time points 7 and
8. Figure 9 also illustrates when the LTC4221’s electronic
circuit breaker is armed. After the initial timing cycle, it is
armed at time point 3. Arming the circuit breaker at time
point 3 ensures that the system is protected against an over-
current condition during the channel start-up cycle. At time
point 4, the slow comparators are armed when the internal
control loop is disengaged.
Autoretry After a Fault
Once the LTC4221 circuit breaker is tripped, FAULT is
latched low and both GATE pins are pulled to ground. To
clear the internal FAULT latch and to restart the LTC4221,
its ON1 pin must be pulsed below its reset threshold
(V
ON(RESET)
= 0.4V) for at least 15μs.
APPLICATIO S I FOR ATIO
WUUU
TIMER
FAULT
FILTER
ON
n
0.851V
GATE
n
SENSE
n
V
OUT
n
RESET INITIAL TIMING
21
1.9μA
V
TMR(L)
V
TMR(H)
ELECTRONIC CIRCUIT BREAKER
ARMED
SLOW COMPARATORS
ARMED
3
20μA20μA
1.8μA
0.4V
105μA
9.5μA
V
FILTER(TH)
V
SENSE(FC)
V
SENSE(SC)
45 6 7 8 9
RESET
4221 F09
CHANNEL
START-UP
NORMAL FAULT
Figure 9. Fast Comparator Trip Timing Waveforms
Figure 8. Circuit Breaker Filter Response
for Intermittent Overload
OVERLOAD DUTY CYCLE, D (%)
NORMALIZED RESPONSE TIME (s/μF)
1
0.01
0.1
0 102030405060708090100
4221 F08
t
CFILTER (μF)
1.24V
105 • D – 1.8
=
18
LTC4221
4221fa
The LTC4221 can also be configured to automatically retry
after a fault condition. As shown in Figure 10, the FAULT
(which has an internal 3.8μA pull-up current source) and
both ON pins are connected together. The timing diagram
in Figure 11 illustrates a simultaneous start-up sequence
where the LTC4221 is powered up into a load overcurrent
condition on channel 1. After the slow comparators are
armed at the end of the start-up cycle at time point 4, slow
comparator 1 immediately trips and FILTER ramps up.
FILTER ramps past its high threshold at time point 6 and
trips the circuit breaker. FAULT and both ON pins are
pulled low by an internal N-channel MOSFET and over-
shoots below the 0.4V reset threshold of the ON1 pin.
Once ON1 < 0.4V for more than 15μs, the internal fault
APPLICATIO S I FOR ATIO
WUUU
+
VCC1
ON1
SENSE1ON2
FAULT
RF2
15k
LTC4221*
GATE1
FB1
4221 F10
1
16
7
10
9C
TIMER
1μF
GND
TIMER
R
F1
56k
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
Q1
IRF7413
R
SENSE1
0.004Ω
C
LOAD1
8
C
FILTER
1nF
FILTER
Z1
Q2: 2N7002LT1
Z1: SMAJ10
* ADDITIONAL DETAILS
OMITTED FOR CLARITY
R
X1
10Ω
C
X1
100nF
C
ON1
0.47μF
R1
1M
LONG
V
CC1
LONG
PCB EDGE
CONNECTOR
(MALE)
SHORT
BACKPLANE
CONNECTOR
(FEMALE)
LONG
V
CC2
FAULT
Figure 10. Using FAULT to Configure Autoretry
213456789
20μA
ELECTRONIC CIRCUIT BREAKER
ARMED
20μA2μA
1.8μA
0.4V 0.4V 0.851V
VFILTER(TH)
VSENSE(FC)
VSENSE(SC)
9.5μA
105μA
1.9μA
VTMR(L)
VTMR(H)
0.851V
TIMER
ON
n
, FAULT
FILTER
GATE1
SENSE1
VOUT1
RESET CHANNEL
START-UP
FILTER
RAMP
RESET
tON tINITIAL
OFF INITIAL
TIMING
4221 F11
INITIAL TIMING
tINITIAL tSTARTUP tFILTER
SLOW COMPARATORS
ARMED
Figure 11. Autoretry Timing Waveforms
19
LTC4221
4221fa
latch is cleared and the FAULT pin sources a 3.8μA pull-up
current to charge up C
ON1
. The typical delay t
ON
is :
tVV
C
A
ON ON
=
()
μ
0 851 0 4 38
1
.–.•
.
(3)
As shown in the timing diagram of Figure 11, the autoretry
circuitry will attempt to restart the LTC4221 with a duty
cycle:
Duty Cycle = tSTARTUP +
()
++ +
t
tt t t
FILTER
ON INITIAL STARTUP FILTER
•%100
(4)
t
FILTER
is defined in Equation 1 and t
ON
is defined in Equa-
tion 3. t
INITIAL
, the initial timing cycle delay, is given in
Equation 9 located in the Initial Timing Cycle section.
t
STARTUP
, the start-up cycle delay, is given in Equation 10
and found in the Start-Up Cycle Without Current Limit
section. Using the capacitor values as shown in Figure 10,
the Autoretry Duty cycle works out to be approximately 6%.
Sense Resistor Consideration
The fault current level at which the LTC4221’s internal
electronic circuit breaker trips is determined by sense
resistors connected between each channel’s V
CC
and
SENSE pins. For both channels, the slow comparator trip
current and the fast comparator trip current are given by
equations (5) and (6) respectively.
IV
R
mV
R
TRIP SC SENSE SC
SENSE SENSE
() ()
==
25
(5)
IV
R
mV
R
TRIP FC SENSE FC
SENSE SENSE
() ()
==
100
(6)
The power rating of the sense resistor should be rated at
the fault current level. Table 1 in the Appendix lists some
common sense resistors.
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and each channel’s
V
CC
and SENSE pins are strongly recommended. The
drawing in Figure 12 illustrates the connections between
the LTC4221 and the sense resistor. PCB layout should be
balanced and symmetrical to minimize wiring errors. In
addition, the PCB layout for the sense resistor should
include good thermal management techniques for optimal
sense resistor power dissipation.
Calculating Current Limit
For a selected R
SENSE
, the load current must not exceed
I
TRIP(SC)
. The minimum I
TRIP(SC)
is given by Equation 7:
IV
R
mV
R
TRIP SCMIN SENSE SCMIN
SENSE MAX SENSE MAX
() ()
() ()
.
==
20 5
(7)
where
RR
R
SENSE MAX SENSE TOL
() •=+
⎛
⎝
⎜⎞
⎠
⎟
1100
The maximum I
TRIP(SC)
is given by Equation 8:
IV
R
mV
R
TRIP SCMAX SENSE SCMAX
SENSE MIN SENSE MIN
() ()
() ()
.
==
29 5
(8)
where
RR
R
SENSE MIN SENSE TOL
() •–=⎛
⎝
⎜⎞
⎠
⎟
1100
If a 7mΩ sense resistor with ±1% tolerance is used for
current limiting, the nominal slow comparator trip current
is 3.57A. From Equations 7 and 8, I
TRIP(SCMIN)
= 2.9A and
I
TRIP(SCMAX)
= 4.26A. For proper operation, the minimum
I
TRIP(SC)
must exceed the circuit maximum operating load
current. For reliability purposes, the operation at the
maximum trip current must be evaluated carefully. If
necessary, two resistors with the same R
TOL
can be
connected in parallel to yield a nominal R
SENSE
value that
fits the circuit requirements.
APPLICATIO S I FOR ATIO
WUUU
SENSE RESISTOR
TO
VCC
n
TO
SENSE
n
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMP
ON 1oz COPPER
W
4221 F12
Figure 12. PCB Connections to the Sense Resistor
20
LTC4221
4221fa
Timer Function
The TIMER pin controls the initial cycle and the channel
start-up cycles with an external capacitor, C
TIMER
. There
are two comparator thresholds: V
TMR(H)
(1.234V) and
V
TMR(L)
(0.4V). In addition, the pin has a 1.9μA pull-up
current, a 20μA pull-up current and a N-channel MOSFET
pull-down.
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supplies at time
point 1 of Figure 13. The LTC4221 is in reset mode as the
ON1 pin is low. Both GATE pins and the TIMER pin are
pulled low. At time point 2, the short pin makes contact and
both ON pins are pulled high. At this instant, a start-up
check requires that both supply voltages be above UVLO,
at least one ON pin be above 0.851V, both GATE pins
< 0.4V and TIMER < 0.4V. When these four conditions are
fulfilled, the initial cycle begins and the TIMER pin is pulled
high with 1.9μA. At time point 3, the TIMER reaches
V
TMR(H)
and is pulled down below V
TMR(L)
by the N-
channel MOSFET pull-down, ending the initial cycle at time
point 4. The initial cycle delay is:
tV
C
A
INITIAL TIMER
=μ
1 234 19
.•
.
(9)
At time point 4, the LTC4221 checks whether the FILTER
pin is <1.24V and FAULT is > 0.851V. If both conditions are
met, a channel start-up cycle commences.
Start-Up Cycle Without Current Limit
During a channel start-up cycle, the TIMER pin ramps up
with a 20μA internal pull-up so the start-up cycle delay is:
tVV
C
A
STARTUP TIMER
=
()
μ
1 234 0 4 20
.–.•
(10)
At the beginning of the start-up timing cycle (time point 4),
the LTC4221’s electronic circuit breaker is armed and each
channel has an internal 9.5μA current source working with
an internal charge pump to provide the gate drive to its
external pass transistor. At time point 5, GATE1 reaches
the external pass transistor threshold and V
OUT1
starts to
follow the GATE1 ramp-up. If the inrush current is below
current limit, GATE1 ramps at a constant rate of:
Δ
Δ=
V
T
I
C
GATE GATE
GATE
(11)
where C
GATE
is the total capacitance at the GATE1 pin. The
inrush current through R
SENSE1
can be divided into two
components; I
CLOAD
due to the total load capacitance
C
LOAD
and I
LOAD
due to the noncapacitive load elements.
The load bypass capacitance typically dominates C
LOAD
.
For a successful channel start-up without current limit,
I
INRUSH
< active current limit. Due to the voltage follower
configuration, the V
OUT1
ramp rate approximately tracks
V
GATE1
. The inrush current during a start-up cycle without
current limit is :
IC
V
TI
IC
V
TI
IC
I
CI
INRUSH LOAD OUT LOAD
INRUSH LOAD GATE LOAD
INRUSH LOAD GATE
GATE LOAD
=Δ
Δ
⎛
⎝
⎜⎞
⎠
⎟+
=Δ
Δ
⎛
⎝
⎜⎞
⎠
⎟+
=⎛
⎝
⎜⎞
⎠
⎟+
•
•
•
(12)
At time point 6, V
OUT1
is approximately V
CC1
but GATE1
ramp-up continues until it reaches a maximum voltage.
This maximum voltage is determined either by the charge
pump or the internal clamp.
APPLICATIO S I FOR ATIO
WUUU
1.234V
VCC
n
VOUT1
ON
n
TIMER
GATE1
RESET
STATE
INITIAL
TIMING
CHANNEL 1
START-UP
NORMAL
20μA
9.5μA
0.4V
VTH
DISCHARGE
BY LOAD
4221 F13
0.851V
0.4V
12 345 6 7
1.9μA
Figure 13. Channel 1 Start-Up Without Current Limit
21
LTC4221
4221fa
0.4V
V
TH
1.234V
1.9μA20μA
<9.5μA
9.5μA9.5μA
DISCHARGE
BY LOAD
4221 F14
0.851V
0.4V
1.234V
12
V
CC
n
V
ON
n
V
TIMER
V
GATE2
V
OUT2
I
RSENSE2
3456 78 9 A
REGULATED AT 25mV/R
SENSE
REGULATED AT
V
SENSE(ACL)
(t)/R
SENSE
RESET
STATE
INITIAL
TIMING
CHANNEL 2
START-UP
NORMAL
CYCLE
Start-Up Cycle With Current Limit
During a channel start-up cycle, if the inrush current as
according to Equation (12) is large enough to cause a
voltage drop greater than the active current limit threshold
(V
SENSE(ACL)
) across the sense resistor, an internal servo
loop controls the operation of the 9.5μA current source at
the GATE pin to regulate the load current to:
IV
R
INRUSH SENSE ACL
SENSE
=()
(13)
The active current limit threshold for channel
n
has a
component controlled by the voltage at the FB
n
pin. When
FB
n
= 0V, V
SENSE(ACL)
= 9mV. As V
OUT
n
and FB
n
ramp up,
V
SENSE(ACL)
increases linearly until FB
n
reaches 0.5V,
where V
SENSE(ACL)
saturates at 25mV. In this fashion, the
inrush current is controlled by this “foldback” limiting that
tends to keep the power dissipation in the external MOSFET
constant during the start-up cycle.
The timing diagram in Figure 14 illustrates the operation of
the LTC4221 in a channel start-up cycle with limited inrush
current as described by Equation 13. Between time points
5 and 6, the GATE2 pin ramps up with I
GATE
= 9.5μA. At
time point 6, the inrush current increases enough to trip
V
SENSE(ACL)
(t) and an internal servo loop engages, limiting
the inrush current to the level as in Equation 13 by
decreasing I
GATE
(<9.5μA). As a result, the ramp rate of
both V
GATE2
and V
OUT2
decreases and V
SENSE2
increases
linearly until it saturates at 25mV at time point 7. At time
point 8, the external MOSFET enters triode operation.
I
INRUSH
drops as the ramp rate of V
OUT2
falls below that of
V
GATE2
so I
GATE
reverts back to 9.5μA. At time point 9, the
internal servo loop to control I
INRUSH
is disengaged and
channel 2 slow comparator is armed, ending the channel 2
start-up cycle. So if C
LOAD2
is not fully charged up at this
point, I
INRUSH
will be subject to the slow comparator
threshold and actions as outlined in the Electronic Circuit
Breaker section. For a successful channel start-up, the
current limited part of the V
OUT
ramp-up (time points 6 and
8 of Figure 14) must not exceed the sum of start-up cycle
delay as given by Equation 10 and the slow comparator
response time as given by Equation 1. An example of an
unsuccessful start-up is Figure 11 which shows a channel
powering up into an overcurrrent at the load.
The fast comparators of both channels are armed at the
end of the initial timing cycle at time point 4 of Figure 14.
If a short circuit during the start-up cycle overrides the
servo loop and causes V
RSENSE
of either channel to exceed
100mV for more than 1μs, the electronic circuit breaker
trips and the LTC4221 enters the fault state.
Frequency Compensation at Start-Up Cycle
If a channel’s external gate input capacitance (C
ISS
) is
greater than 600pF, no external gate capacitor is required
at GATE to stabilize the internal current-limiting loop dur-
ing start-up with current limit. The servo loop that controls
the external MOSFET during current limiting has a unity-
gain frequency of about 105kHz and phase margin of 80°
for external MOSFET gate input capacitances to 2.5nF.
Power MOSFET
Power MOSFETs can be classified by R
DS(ON)
at V
GS
gate
drive ratings of 10V, 4.5V, 2.5V and 1.8V. Those rated for
R
DS(ON)
at 10V V
GS
usually have a higher V
GS
absolute
maximum rating than those at 4.5V and 2.5V. At low
APPLICATIO S I FOR ATIO
WUUU
Figure 14. Channel 2 Start-Up with Current Limit
22
LTC4221
4221fa
supply voltages, the LTC4221 can drive any MOSFET rated
with 4.5V or 2.5V gate drive. For higher supply voltages up
to 13.5V, the LTC4221 can drive any MOSFET rated with
a 10V or 4.5V gate drive. The selected MOSFET should
fulfill two V
GS
criteria:
1. Positive V
GS
absolute maximum rating > LTC4221’s
maximum ΔV
GATE
.
2. Negative V
GS
absolute maximum rating > supply volt-
age. The gate of the MOSFET can discharge faster than
V
OUT
when shutting down the MOSFET with a large
C
LOAD
.
If one of the conditions cannot be met, an external zener
clamp shown on Figure 15 can be used. The clamp
network is connected from each channel’s GATE to the
V
OUT
pins. V
GS
is clamped in both directions and R
G
limits
the current flow into the GATE
n
pin’s internal zener clamp
during transient events.
A MOSFET with a V
GS
absolute maximum rating of ±20V
meets the two criteria for all the LTC4221 application ranges
from 1V to 13.5V. Typically most 10V gate rated MOSFETs
have V
GS
absolute maximum ratings of ±20V or greater, so
no external V
GS
zener clamp is needed. There are 4.5V gate
rated MOSFETs with V
GS
absolute maximum ratings of
±20V. In addition to the MOSFET gate drive rating and V
GS
absolute maximum rating, other criteria such as V
BDSS
,
I
D(MAX)
, R
DS(ON)
, P
D
, θ
JA
, T
J(MAX)
and maximum safe
operating area (SOA) should also be carefully reviewed.
V
BDSS
should exceed the maximum supply voltage inclu-
sive of spikes and ringing. I
D(MAX)
must exceed the maxi-
mum short-circuit current in the channel during a fault
condition. R
DS(ON)
determines the MOSFET V
DS
which to-
gether with V
RSENSE
yields an error in the V
OUT
voltage. For
example, at 1V V
CC2
, V
DS
+ V
RSENSE2
= 50mV gives a 5%
V
OUT2
error. At higher V
CC
voltages the V
DS
requirement can
be relaxed in which case the MOSFET’s thermal require-
ments (P
D
, T
J(MAX)
, SOA) may limit the value of R
DS(ON)
.
The power dissipated in the MOSFET is (I
LOAD
)
2
• R
DS(ON)
and this should be less than the maximum power dissipa-
tion, P
D
, allowed in that package. Given power dissipation,
the MOSFET junction temperature, T
J
can be computed
from the operating temperature (T
A
) and the MOSFET
package thermal resistance (θ
JA
). The operating T
J
should
be less than the T
J(MAX)
specification. The V
DS
• I
LOAD
figure must also be well within the manufacturer’s recom-
mended safe operating area (SOA) with sufficient margin.
These three thermal parameters must not be exceeded for
all conditions in a channel including normal mode opera-
tion, start-up with or without current limit, fault and
autoretry after a fault. To ensure a reliable design, fault
tests should be evaluated in the laboratory.
V
CC
Transient Protection
Good engineering practice calls for bypassing the supply
rail of any analog circuit. Bypass capacitors are often
placed at the supply connection of every active device, in
addition to one or more large value bulk bypass capacitors
per supply rail. If power is connected abruptly, the large
bypass capacitors slow the rate of rise of the supply
voltage and heavily damp any parasitic resonance of lead
or PC track inductance working against the supply bypass
capacitors.
The opposite is true for LTC4221 Hot Swap circuits
mounted on plug-in cards since controlling the surge
current to bypass capacitors at plug-in is the primary
motivation for the Hot Swap controller. In most cases,
there is no supply bypass capacitor present on the pow-
ered supply voltage side of the MOSFET switch. Although
wire harness, backplane and PCB trace inductances are
usually small, these can create large spikes when large
currents are suddenly drawn, cut off or limited. Abrupt
intervention can prevent subsequent damage caused by a
catastrophic fault but it does cause a large supply tran-
sient. These ringing transients appear as a fast edge on
APPLICATIO S I FOR ATIO
WUUU
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
R
SENSE
GATE
4221 F15
Q1
RG
200Ω
D1* D2*
VCC VOUT
Figure 15. Gate Protection Zener Clamp
23
LTC4221
4221fa
the input supply line, exhibiting a peak overshoot to 2.5
times the steady-state value. This peak is followed by a
damped sinusoidal response whose duration and period
are dependent on the resonant circuit parameters. This
can cause detrimental damage to board components
unless measures are taken.
The energy stored in the lead/trace inductance is easily
controlled with snubbers and/or transient voltage sup-
pressors. Even when ferrite beads are used for electro-
magnetic interference (EMI) control, the low saturating
current of ferrite will not pose a major problem if the
transient voltage suppressors with adequate ratings are
used. The transient associated with a GATE turn off can be
controlled with a snubber and/or transient voltage sup-
pressor. Snubbers such as RC networks are effective
especially at low voltage supplies. The choice of RC is
usually determined experimentally. The value of the snub-
ber capacitor is usually chosen between 10 to 100 times
the MOSFET C
OSS
. The value of the snubber resistor is
typically between 3Ω to 100Ω. When the supply exceeds
7V or EMI beads exist in the wire harness, a transient
voltage suppressor and snubber are recommended to clip
off large spikes and reduce the ringing. For supply volt-
ages of 6V or below, a snubber network should be suffi-
cient to protect against transient voltages. These protection
networks should be mounted very close to each of
LTC4221’s two supply voltages using short lead lengths to
minimize lead inductance. This is shown schematically in
the Typical Application on the front page of this data sheet.
In many cases, a simple short-circuit test can be per-
formed to determine the need of the transient voltage
suppressor. Additional overvoltage protection is provided
by the FB
n
pins.
APPLICATIO S I FOR ATIO
WUUU
PCB Layout Considerations
A recommended layout for the SENSE resistors, the
power MOSFETs, VCC transient protection devices and
GATE drive components around the LTC4221 is shown in
Figure 16. For proper operation of the LTC4221’s elec-
tronic circuit breaker, a 4-wire Kelvin connection to each
SENSE resistor is used. Also, PCB layout for the external
N-channel MOSFETs emphasizes optimal thermal man-
agement of MOSFET power dissipation to keep θJA as low
as possible. The VCC transient protection devices are
positioned close to the supply pins to reduce lead induc-
tance and thus overshoot voltage.
In Hot Swap applications where load currents can reach
10A or more, PCB track width must be appropriately sized
to keep track resistance and temperature rise to a mini-
mum. Consult Appendix A of LTC Application Note 69 for
details on sizing and calculating trace resistances as a
function of copper thickness.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1oz copper foil plating, a good starting
point is 1A of DC current per via, making sure the via is
properly dimensioned so that solder completely fills any
void. For other plating thicknesses, check with your PCB
fabrication facility.
24
LTC4221
4221fa
APPLICATIO S I FOR ATIO
WUUU
Figure 16. Recommended Layout for LTC4221 RSENSE, Power MOSFETs and Feedback Networks
G
W
•
•
•
•
•
•
•
•
•
•
POWER MOSFET
SO-8
POWER MOSFET
SO-8
NOTE: DRAWING IS NOT TO SCALE
*ADDITIONAL DETAILS OMITTED FOR CLARITY
R
SENSE2
R
SENSE1
TRACK WIDTH W
CURRENT FLOW
TO LOAD
CHANNEL 2
OUTPUT
S
S
S
R
F3
R
F4
VIAS
BOTTOM LAYER
AND GND TRACE
VIAS
GND
TO
LOAD
D
D
D
D
LTC4221*
G
S
S
S
D
D
D
D
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
ON1
V
CC1
SENSE1
GATE1
FB1
PWRGD1
FAULT
FILTER
ON2
V
CC2
SENSE2
GATE2
FB2
PWRGD2
GND
TIMER
R
F2
R
F1
4221 F16
R4
R3
R1C
X1
R2
Z1
R
X1
R
X2
Z2
C
X2
W
CHANNEL 2
INPUT
CHANNEL 1
OUTPUT
CHANNEL 1
INPUT
GND
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
W
C
TIMER
C
FILTER
APPE DIX
U
Table 1 lists some current sense resistors that can be used
with the circuit breaker. Table 2 lists some power MOSFETs
that are available. Table 3 lists the web sites of several
manufacturers. Since this information is subject to change,
please verify the part numbers with the manufacturer.
Table 1. Sense Resistor Selection Guide
CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER
1A LRF120601R020F 0.02
Ω
0.5W 1% Resistor
IRC-TT
2.5A WSL25127L000F 0.007
Ω
1W 1% Resistor
Vishay-Dale
3.3A WSL25126L000F 0.006
Ω
1W 1% Resistor
Vishay-Dale
5A WSL25124L000F 0.004
Ω
1W 1% Resistor
Vishay-Dale
10A WSL25122L000F 0.002
Ω
1W 1% Resistor
Vishay-Dale
2A LRF120601R010F 0.01
Ω
0.5W 1% Resistor
IRC-TT
25
LTC4221
4221fa
TYPICAL APPLICATIO S
U
Simultaneous Turn-On with Autoretry Function—Individual Current Limits
ON2
FAULT
GND
LTC4221
Z1 Z2
1
16
7
10
9
8
FB2
PWRGD2
PWRGD1
PWRGD2
VOUT1
5V
5A
VOUT2
3.3V
2.5A
PWRGD1
FB1
LONG
LONG
GND LONG
Z1, Z2: SMAJ10
TIMER
FILTER
234151413
12
11
6
5
ON1
VCC1 SENSE1 GATE1 VCC2 SENSE2 GATE2
V
CC1
5V
V
CC2
3.3V
BACKPLANE
CONNECTOR
(FEMALE)
PCB EDGE
CONNECTOR
(MALE)
R
X1
10Ω
R
X2
10Ω
R3
15k
R2
21k
R1
3.16k
R
F3
20k
Q2
IRF7413
R
F4
5.11k
R
PG2
10k
R
PG1
10k
R
F1
32.4k
R
F2
5.11k
4221 TA02
C
X1
100nF
C
FILTER
1nF
C
TIMER
470nF
C
X2
100nF
Q1
IRF7413
R
SENSE1
0.004Ω
R
SENSE2
0.007Ω
APPE DIX
U
Table 2. N-Channel Selection Guide
CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER
0 to 2 MMDF3N02HD Dual N-Channel SO-8 ON Semiconductor
R
DS(ON)
= 0.1Ω, C
ISS
= 455pF
2 to 5 MMSF5N02HD Single N-Channel SO-8 ON Semiconductor
R
DS(ON)
= 0.025Ω, C
ISS
= 1130pF
5 to 10 MTB50N06V Single N-Channel DD Pak ON Semiconductor
R
DS(ON)
= 0.028Ω, C
ISS
= 1570pF
10 to 20 MTB75N05HD Single N-Channel DD Pak ON Semiconductor
R
DS(ON)
= 0.0095Ω, C
ISS
= 2600pF
Table 3. Manufacturers’ Web Sites
MANUFACTURER WEB SITE
TEMIC Semiconductor www.temic.com
International Rectifier www.irf.com
ON Semiconductor www.onsemi.com
Harris Semiconductor www.semi.harris.com
IRC-TT www.irctt.com
Vishay-Dale www.vishay.com
Vishay-Siliconix www.vishay.com
Diodes, Inc. www.diodes.com
26
LTC4221
4221fa
TYPICAL APPLICATIO S
U
Sequenced Turn-On
ON2
FAULT
GND
LTC4221
Z1 Z2
1
16
7
10
9
8
FB2
PWRGD2
PWRGD1
PWRGD2
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
FB1
LONG
LONG
GND LONG
Z1, Z2: SMAJ10
TIMER
FILTER
234151413
12
11
6
5
ON1
V
CC1
SENSE1 GATE1 V
CC2
SENSE2 GATE2
V
CC1
3.3V
V
CC2
2.5V
BACKPLANE
CONNECTOR
(FEMALE)
PCB EDGE
CONNECTOR
(MALE)
R
X1
10Ω
R
X2
10Ω
R3
14.3k
R4
10k
R2
21k
R1
10k
R
F3
14.3k
Q2
IRF7413
R
F4
5.11k
R
PG2
10k
R
F1
20k
R
F2
5.11k
4221 TA04
C
X1
100nF
C
FILTER
1nF
C
TIMER
470nF
C
X2
100nF
Q1
IRF7413
R
SENSE1
0.004Ω
R
SENSE2
0.004Ω
Simultaneous Turn-On with Autoretry Function—Linked Current Limits
ON2
FAULT
GND
LTC4221
Z1 Z2
1
16
7
10
9
8
FB2
PWRGD2
PWRGD1
PWRGD2
V
OUT1
3.3V
5A
V
OUT2
2.5V
5A
PWRGD1
FB1
LONG
LONG
GND LONG
Z1, Z2: SMAJ10
TIMER
FILTER
234151413
12
11
6
5
ON1
V
CC1
SENSE1 GATE1 V
CC2
SENSE2 GATE2
VCC1
3.3V
VCC2
2.5V
BACKPLANE
CONNECTOR
(FEMALE)
PCB EDGE
CONNECTOR
(MALE)
RX1
10Ω
RX2
10Ω
R3
12.4k
R2
16.5k
R1
4.22k
RF3
14.3k
Q2
IRF7413
RF4
5.11k
RPG2
10k
RPG1
10k
RF1
20k
RF2
5.11k
4221 TA03
CX1
100nF
CFILTER
1nF
CTIMER
470nF
CX2
100nF
Q1
IRF7413
RSENSE1
0.004Ω
RSENSE2
0.004Ω
27
LTC4221
4221fa
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
Sequenced Up/Down, Channel 1 Up First, Down Last
ON2
FAULT
GND
LTC4221
Z1 Z2
D1
1
16
7
10
9
8
FB2
PWRGD2
PWRGD1
VOUT1
3.3V
5A
VOUT2
2.5V
5A
FB1
LONG
LONG
SHORT
GND
FAULT
LONG
SHORT
D1: 1N4148
Z1, Z2: SMAJ10
TIMER
FILTER
234151413
12
11
6
5
ON1
VCC1 SENSE1 GATE1 VCC2 SENSE2 GATE2
VCC1
3.3V
VCC2
2.5V
ON
0V TO 3.3V
OR
3.3V TO 0V
BACKPLANE
CONNECTOR
(FEMALE)
PCB EDGE
CONNECTOR
(MALE)
RX1
10Ω
RX2
10Ω
R5
13k
R3
8.06k
R2
6.98k
R4
10k
R1
17.8k
RF3
14.3k
Q2
IRF7413
RF4
5.11k
RF1
20k
RF2
5.11k
4221 TA05
CX1
100nF
CFILTER
1nF
CTIMER
470nF
CX2
100nF
Q1
IRF7413
RSENSE1
0.004Ω
RSENSE2
0.004Ω
TYPICAL APPLICATIO S
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
28
LTC4221
4221fa
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0707 REV A • PRINTED IN THE USA
PART NUMBER DESCRIPTION COMMENTS
LTC1421 2-Channel, Hot Swap Controller 24-Pin, Operates from 3V to 12V and Supports –12V
LTC1422 Single Channel, Hot Swap Controller in SO-8 Operates from 2.7V to 12V, System Reset Output
LTC1642 Fault Protected, Hot Swap Controller Operates up to 16.5V, Overvoltage Protection to 33V
LTC1643AL/LTC1643AH PCI Hot Swap Controllers 3.3V, 5V and ±12V Supplies
LTC1645 Dual Channel Hot Swap Controller Operates from 1.2V to 12V, Power Sequencing
LTC1647 Dual Channel, Hot Swap Controller Operates from 2.7V to 16.5V
LTC4210 Single Channel, Hot Swap Controller in SOT-23 Operates from 2.7V to 16.5V, Multifunction Current Control
LTC4211 Single Channel, Hot Swap Controller in MSOP 2.5V to 16.5V, Multifunction Current Control
LTC4230 Triple Channel, Hot Swap Controller 1.7V to 16.5V, Multifunction Current Control
LTC4251 –48V Hot Swap Controller in S0T-23 –48V Hot Swap Controller, Active Current Limiting
LTC4252 –48V Hot Swap Controller in MSOP Active Current Limiting With Drain Acceleration
LTC4253 –48V Hot Swap Controller and Sequencer Active Current Limiting With Drain Acceleration and Three
Sequenced Power Good Outputs
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
TYPICAL APPLICATIO
U
Sequenced Up/Down, Channel 2 Up First, Down Last
ON2
FAULT
GND
LTC4221
Z1 Z2
D1
FB2
PWRGD2
PWRGD1
VOUT1
3.3V
5A
VOUT2
2.5V
5A
FB1
LONG
LONG
SHORT
GND
FAULT
LONG
SHORT
D1: 1N4148
Z1, Z2: SMAJ10
TIMER
FILTER
ON1
VCC1 SENSE1 GATE1 VCC2 SENSE2 GATE2
VCC1
3.3V
VCC2
2.5V
ON
0V TO 3.3V
OR
3.3V TO 0V
BACKPLANE
CONNECTOR
(FEMALE)
PCB EDGE
CONNECTOR
(MALE)
RX1
10Ω
RX2
10Ω
R6
10k
R3
12.1k
R2
20.5k
R4
23.2k
R1
23.7k
R5
9.53k
RF3
14.3k
Q2
IRF7413
RF4
5.11k
RF1
20k
RF2
5.11k
4221 TA06
CX1
100nF
CFILTER
1nF
CTIMER
470nF
CX2
100nF
Q1
IRF7413
RSENSE1
0.004Ω
RSENSE2
0.004Ω
