PCA9410UKZ - NXP SEMICONDUCTORS

1. General description

The PCA9410 and PCA9410A are highly efficien t 3.0 MHz, 500 mA, step-up DC-to-DC

converters. They convert input voltages from 2.5 V to 5.25 V to a fixed output voltage of

5.0 V.

These devices are optim ized for battery-powe red applications. High efficiency of up to

94 % enables an extended battery life in all portable designs. Step-up operation at a

switching frequency of 3 MHz allows using 1 H inductor or smaller.

2. Features and benefits

Efficiency up to 94 %

 3 % output voltage accuracy at nominal and static conditions

 3 % output voltage accuracy over full current, voltage and temperature range

VINVO, (Pass-Through Mode Operation)

Load disconnect

Current-mode controller

Soft start function for limiting inrush current with true load disconnect

Overcurren t an d over-temp er at ur e pr otection

The PCA9410 totally disconnects input to output when disabled

The PCA9410A connects input to output when disabled

Wafer-Level Chip-Size Package (WLCSP) with 0.4 mm pitch; allows for the use of a

smaller antenna, or for greater signal strength

3. Applications

Smartphones

NFC terminals

4. Ordering information

PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Rev. 1 — 5 August 2016 Product data sheet

WLCSP9

Table 1. Ordering information

Type number Topside

mark Package

Name Description Version

PCA9410UK P10 WLCSP9 wafer-level chip-size package; 9 bumps; body 1.24  1.24 

0.525 mm -

PCA9410AUK 10A WLCSP9 wafer-level chip-size package; 9 bumps; body 1.24  1.24 

0.525 mm -

Product data sheet Rev. 1 — 5 August 2016 2 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

4.1 Ordering options

5. Block diagram

Table 2. Ordering options

Type number Orderable part

number Package Packing method Minimum

order quantity Temperature

PCA9410UK PCA9410UKZ WLCSP9 REEL 7" Q1/T1

*SPECIAL MARK

CHIPS DP

3000 Tamb = 40 C to +85 C

PCA9410AUK PCA9410AUKZ WLCSP9 REEL 7" Q1/T1

*SPECIAL MARK

CHIPS DP

3000 Tamb = 40 C to +85 C

Fig 1. Block diagram

BANDGAP

REFERENCE

BIAS

SUPPLY

UNDERVOLTAGE

LOCKOUT

TEMPERATURE

WATCHDOG

CONTROL

LOGIC

PULSE

GENERATOR GATE

DRIVER

SOFTSTART

OVERCURRENT

PROTECTION

aaa-013240

Product data sheet Rev. 1 — 5 August 2016 3 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configu ration WLCSP9 package Fig 3. Ball mapping for WLCSP9

321

ball A1

index area

Transparent top view

aaa-013280

PCA9410/9410A

VOUT VIN

PGND AGND

PGND

21 3

Transparent top view

aaa-013281

PCA9410/9410A

VOUT

SW SW

Table 3. Pin description

Symbol Pin Description

VOUT A1, A2 Output voltage. This pin is the output voltage terminal; connect

directly to COUT.

VIN A3 Input voltage. Connect to Li-Ion battery input power source.

SW B1, B2 Switching node. Connect to inductor.

EN B3 Enable. Used to enable/disable the device; HIGH = enabled.

Non-A version: EN low = total disconnect

A version: EN low = forced pass through

PGND C1, C2 Power ground. This is the power return for the IC. COUT capacitor

should be returned with the shortest path possible to these pins.

AGND C3 Analog ground. This is the signal ground reference fo r the IC. All

voltage levels are measured with respect to this pin; connect to

PGND at a single point. The AGND pin should be flooded over by

the ground plane that is connecti ng the PGND pins to both the

input caps and the output caps.

Product data sheet Rev. 1 — 5 August 2016 4 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

7. Functional description

The step-up converter (Figure 4) generates a regulated constant output voltage.

7.1 Enable (EN) pin

EN pin enables the boost conver ter when HIGH. However the effect of the EN when LOW

has two methods of operation, depending on which device is used.

PCA9410 device: the EN pin when LOW causes the part to go into a total disconnect

mode from input to output.

PCA9410A device: EN pin when LOW forces the part into Pass Through mode where th e

output voltage is the same as the input voltage. This device emulates a conventional

boost converter (without the voltage drop of the internal diode).

When the EN pin is pulled HIGH it should be held HIGH for at least 500 s for the device

to properly initialize. This is for getting the forced Pass Through mode set up properly.

Shorter pulses may cause unpredictable behavior.

7.1.1 Pass-Through (PT) mode

With both devices, the device automatically transitions from Boost Mod e to Pass-T hrough

Mode if VIN goes above the VOUT target. In Pass-Through Mode, the de vice provides a

very low impedance path from VIN to VOUT. Ent ry to the Pass-Through Mode is triggered

Fig 4. Typical DC-to-DC application

SW SW

VIN VIN

ENEnable

AGND

VOUT

aaa-013259

PGND PGND

i(ext)

VOUTVOUT

Table 4. Operating modes

Mode Description Invoked when

LIN linear start-up VIN > VOUT

SS boost soft-start VIN < VOUT < VOUT(TARGET)

BST boost operating mode VOUT = VOUT(TARGET)

PT pass-through mode VIN > VOUT(TARGET) or in the advanced

part when EN is pulled LOW

Product data sheet Rev. 1 — 5 August 2016 5 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

by condition where VIN > VOUT target. Pass-Through Mode exit is trigge red when VOUT

going down reach es the target VOUT voltage. During Automatic Pass-Through Mode, the

PMOS overcurrent protection remains enabled.

In the PCA9410A, user can force the device in Forced Pass-Through Mode through the

EN pin. If the EN pin is pulled HIGH, the device starts operating in Boost Mode. Once the

EN pin is pulled LOW, the device is forced into Pass-Through Mode. To disable the

device, the input supply voltage must be removed. The device cannot start-up in Forced

Pass-Through Mode. During st art-up, keep the EN pulle d HIGH for 500 s, before pulling

it LOW and putting the device into Forced Pass-Through Mode. The EN pin has an

internal pull-down resistor (see Figure 5 for the sequence).

7.2 Inrush current limiter (soft start)

The PCA9410 and PCA9410A have an integrated pre-charge circuit that prevents large

inrush current s when input voltage is applied. This inrush is accompanied with a current

limit that shuts down the device, and runs a delay timer then attempts a restart.

Once the output volt age reach es the input vo lt age the so ft sta rt function is enabled to limit

the maximum current in boost time and to reduce an input voltage dip. Therefore the

system has a turn-on pr oced ur e which starts up step-by-step and limits the inrush current

via a duty cycle control up to the maximum current capability.

7.3 Thermal protection

The PCA9410 and PCA9410A have an integrated thermal protection. The protection

circuit senses the internal temperature of the chip and switches off the integrated PMOS

power switch transistor when temperature reaches 150 C. After th e temperature returns

to a safe value 20 C below the shutdown temperature, th e system restarts in the

pre-charg e ph ase.

Table 5. Enable

EN logic level Description Non-A Description A

LOW Power-down isolated output Forced pass-through

HIGH Boost mode Boost mode

Fig 5. Forced pass-through

Enable

OUT

Boost

Forced Pass through

Boost

Disconnect

aaa-019181

Product data sheet Rev. 1 — 5 August 2016 6 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

7.4 Overcurrent protection

Overcurrent protection circuit senses the current through the integrated PMOS. If the

diagnostic circuit detect s an overcurre nt, the system switches of f the PMOS and NMOS to

break the current flow, and a 20 ms timeout is started. Once the 20 ms timeout expires,

the part restarts in the pre-charge phase .

Product data sheet Rev. 1 — 5 August 2016 7 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

8. Limiting values

[1] Internally limited

9. Recommended operating conditions

[1] This is the capacitance at 5 V bias. Check application section for more details.

Table 6. L imiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VIN voltage on pin IN 0.5 +6.0 V

Viinput voltage on pin EN 0.3 VIN + 0.3 V, up to

+6.0 V V

VOoutput voltage on pins SW, OUT 0.5 +6.0 V

Ptot total power dissipation [1]

Tstg storage temperature 65 +150 C

Tjjunction temperature 40 +125 C

Tamb ambient temperature 40 +85 C

VESD electrostatic discharge voltage human body model

(JESD22-001)

2+2 kV

Table 7. Ope rating conditions

Symbol Parameter Conditions Min Typ Max Unit

VIN voltage on pin IN 2.5 -5.25 V

Viinput voltage on pin EN 0.3 - VIN V

C1external input capacitance VIN = 4.8 V [1] 2.0 4.2 -F

C2external output capacitance VO = 5 V [1] 3.0 4.2 10 F

Li(ext) external input inductance [1] 0.47 12.2 H

Product data sheet Rev. 1 — 5 August 2016 8 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

10. Static characteristics

Table 8. Static characteristics

At recommended input voltages and Tamb =





C to +85



C; voltages are referenced to GND (ground = 0 V); unless

otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Input voltage and input current

VIN input voltage 2.5 3.6 5.25 V

IQsupply current EN = 0 V -3.0 10.0 A

EN = 1.8 V, VIN = 2.5 V -36 -mA

EN = 1.8 V, VIN = 4.8 V -11 -mA

EN = 1.8 V, VIN = 5.25 V -3.57 -mA

Output voltage and output current

VOUT output voltage IO  15 mA 4.85 (3 %) 5.0 5.15 (+3 %) V

IOUT(lim) output current limit EN = HIGH 0.5 - - A

fo(boost) boost output frequency 2.91 33.09 MHz

Vth(r)(UVLO) rising threshold voltage

on VIN UVLO 1.9 2.1 2.3 V

Vth(f)(UVLOhyst) falling UVLO hysteresis 70 -120 mV

Vo(noise_p-p_coh) Vo coherent

peak-to-peak noise 100 kHz to 1.5 MHz, VIN < 4.8 V 2 mV

12 MHz to 15 MHz, VIN < 4.8 V 2 mV

Vo(noise_rms) Vo rms noise (incoherent

noise) 100 kHz to 1.5 MHz, VIN < 4.8 V 660 µV rms

12 MHz to 15 MHz, VIN < 4.8 V 660 µV rms

Control input and timing

VIH HIGH-level input voltage pins EN 1.16 - - V

VIL LOW-level input voltage pins EN - - 0.4 V

tstartup start-up time -500 600 S

Over-temperature protection

Tsd shut d o w n temperature -150 -C

Tsd(hys) hysteresis of shutdown

temperature -20 -C

Switches

RDSon drain-source on-state

resistance N-channel FET -70 - m

P-channel FET -80 - m

ILleakage current VIN = 3.6 V; EN = LOW 00.051 10 A

Rpd(en_low) enable pull down EN = LOW 450 640 800 k

I(ena-pulldown) enable pull down current EN = HIGH, VIN  2.5 V -100 -nA

Product data sheet Rev. 1 — 5 August 2016 9 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Fig 6. Output regula ti on v s Ilo a d an d V IN

Fig 7. Output ripple vs Iload and VIN

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Product data sheet Rev. 1 — 5 August 2016 10 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Fig 8. Output regulation v s Ilo a d an d temp (VIN = 3.6 V)

Fig 9. Frequen cy vs load current and VIN

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Product data sheet Rev. 1 — 5 August 2016 11 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Fig 10. Efficiency vs Iload and VIN

Fig 11. Efficiency vs Iload and temp (VIN = 3.6 V)

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Product data sheet Rev. 1 — 5 August 2016 12 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Fig 12. Line step response

Fig 13. Pass through

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Product data sheet Rev. 1 — 5 August 2016 13 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Fig 14. L oa d step

Fig 15. Typical load current capability vs VIN and temp

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Product data sheet Rev. 1 — 5 August 2016 14 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

11. Application information

11.1 Overcurrent protection

Conventiona l Boo st co nve rtor s ha ve no ou tp ut current limit protection. Additionally they

have a phantom power path made up of the inductor and output diode connecting the

input directly to the output; this causes an inrush of current when power is applied. The

PCA9410 has extra provisions to prevent the inrush current and output current limit

problems.

To implement these protections this device has a start-up state machine. This machine

includes a two-stage pre-char ge of the output circuitry:

•Stage 1, Inrush control: a 1 A current source is turned on providing a path from input

to output while a voltage comp arator and a timer1 are active. If the output voltage

doesn't reach VIN - 200 mV within 1 ms, the device goes into the fault state. If the

output voltage reaches 200 mV below the input voltage first the state machine

advances to the boost mode soft start state .

•Stage 2, Boost Soft-Start: Starting from VOUT = VIN, the output will ramp up to VOUT

target. The PMOS current limit will be enabled during this stage.

The curren t levels are impleme nted through th e synchronous rectifier transistor pr operties

and drive states.

11.2 Thermal shutdown

A thermal shutdown state shuts out all other states out until the device has cooled to the

(HiTemp  Thysteresis) turn back on temperature, and then it enters the fault state.

11.3 Fault recovery

When a fault occurs, the device has a faul t state that disables the output for 20 ms. After

the 20 ms timeout, the device will attempt a restart starting from the inrush state.

11.4 Enable delay

Once the device has been running and gets disabled, it cannot be re-enabled until the

output volta ge discharges down to the input voltage. Th e device has an internal pull-down

to accomplish this, however in the absence of any external load this will take 3 ms. Any

external load will shorten the time it takes to get re-enabled.

11.5 Connection diagram

The DC-to-DC converter requires an external inductor and two decoup ling capacitors.

Product data sheet Rev. 1 — 5 August 2016 15 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

11.6 Recommended inductors

In order to ensure proper operation of the step-up DC-to-DC converter an inductor with a

suff icient inductance a n d su f f i c i e n t s a t u r a t i o n c u r r e n t v a l u e needs to be used. Re co mm en de d

inductance is 1 H. Using this recommended 0603 i nductor puts a 300 mA current limit on the

circuit; this inductor has a 800 mA saturation current. For more output cur rent a larger, hi gher

saturation current inductor will be required according to Figure 17. The saturation current of the

inductor has to be properly chosen for the input voltage and load current range. The lower the

input voltage th e higher the input current for a given load current . Once the saturation cur rent of

the inductor is reached, the ferromagnetic core of the inductor will show a rapid nonlinear

behavior and the output current capability of the circuit will drop significantly.

Fig 16. Simple DC-to-DC application diag ram

SW SW

VIN VIN

ENEnable

AGND

VOUT

aaa-013259

PGND PGND

i(ext)

VOUTVOUT

Table 9. Recommended inductors

Inductor Manufacturer Product Parameter Package size

LAbracon ASMPH-0603-1R0M-T 1 H0603

Product data sheet Rev. 1 — 5 August 2016 16 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

11.7 Input capacitor

To eliminate unwanted voltage transient s at the input, place an input decoupling cap acitor

of at least 2.2 F as close as possible to the input pin. Due to the voltage dependence of

the capacitor, care should be taken that the effective capacitance of 2 F is available at

input voltages up to 5.25 V. To ensure best performance, it is recommended to use a

capacitor with a low Equivalent Series Resistance (ESR). When using a capacitor with

X5R or X7R dielectric keep in mind that the capacitance drops significantly with voltage,

thus a 22 F cap will actually only have 4.2 F at 5 V as show n in Table 10.

Fig 17. Inductor peak current vs Iload an d VIN

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Table 10. Recommended input capacitors

Manufacturer Product Parameter Package size

Samsung CL05A106MQ5NUNC 10 f 6.3 V, 

2.5 F at 5 V 0402

TDK C1608X5R0J226M080AC 22 f at 6.3 V,

4.2 F at 5 V 0603

Product data sheet Rev. 1 — 5 August 2016 17 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

11.8 Output capacitor

Because of the narrow voltage-dependent capacitance spread, high temperature stability

and low ESR at high frequencies, it is recommended to use the dielectric X7R or X5R.

The rated capacitance of the output capacitor will be much greater than the actual

capacit ance at the 5 V output voltage. The device requires at least 3 F of output

capacit ance at it s rated output volt age for su ppression of ringing, overshoot, as well as for

loop stability. We recommend a 22 F 6.3 V capacitor that is actually a 4.2 F capacitor

when biased at 5 V.

When the space on th e application board allows, it is recommended to use two capacitors

instead of a single large va lue. The reason is that the equivalent series inductance

reduces to half when using two capacitors with the same value and this helps the

capacitors to work more efficiently against high frequency noise where it can be re duced

by a factor of 2. The minimum capacitance needed can either be obtained with a single

22 F capacitor or two 10 F capacitors when the space allows and low er nois e is

targe ted; keep in m ind that the bu lk cap a cit ance a t the ou tput volt ag e needs to b e gre ater

than 3.0 F for control loop stability, and two large capacitors will have superior

performance when compared with two smaller capacitors. The boost factor, output

current, switching fr equency an d the desir ed peak to peak ripple limit define the minimu m

capacitance needed.

The duty cycle (D) needed with 90 % efficiency at a worst case of 2.5 V VIN.

(1)

For the minimum input voltage 2.5 V and 5 V output voltage D = 0.55

Using the simplified correlation between the current (IOUT(max)), ripple (Vripple), duty cycle

(D) and switching frequency (fsw) the minimum Cout capacitance can be calculated as

follows:

(2)

With a sample set of values: Iout = 300 mA, D = 0.55, fsw = 3 MHz, Vripple = 20 mV

COUT(min) = 2.75 F (This is not the nominal value at 0 V bias, it is the derated value at 5 V

bias).

This value presumes that the ESR and ESL of the capacitor is negligible and the path

output-capacitor-ground is as short as possible. Compensating for the listed factors, the

minimum outp ut capacitance is specified at 3.0 f at 5 V. How much the capacitance

degrades at high bias voltage is supplier dependent and especially when 0402 size

capacitors are chosen the voltage dependence should be taken into consideration.

Table 11. Recommended output capacitors

Cap Manufacturer Product Parameter Package size

C2TDK C1608X5R0J226M080AC 22 F 6.3 V, 

4.2 F at 5 V 0603

Eff VIN



VOUT

----------------------

–=

COUT min IOUT max

fsw Vripple



-----------------------------

=

Product data sheet Rev. 1 — 5 August 2016 18 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

11.9 Layout of the PCB

The most critical layout constraint of this circuit is that the output Cap C2 be placed as

close to the IC as possible. Use short wide traces to connect this capacitor to the IC. See

below for an example of the layout detailing the IC and the output capacitor. The

connection from switch pin to the inductor should have minimum capacitance to GND.

Fig 18. Layout of PCB

aaa-016344

Product data sheet Rev. 1 — 5 August 2016 19 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

12. Package outline

Fig 19. Package outline WLCSP9

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Product data sheet Rev. 1 — 5 August 2016 20 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Fig 20. WLCSP9 Under Ball Metal (UBM) structure

aaa-019496

UBM: 240 µm ± 4 µm

PI opening: 160 µm

Passivation opening: 190 µm

Al pad: 220 µm

PI: 10 µm

1K Ti: 1K ± 0.2K

2 K Cu: 2K ± 0.2K

8.3 µm Cu:

All: 8.6 µm ± 1.7 µm

UBM:

Solder ball: SAC105N

BD: 260 µm ± 30 µm

BH: 200 µm ± 30 µm

Product data sheet Rev. 1 — 5 August 2016 21 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

13. Soldering of WLCSP packages

13.1 Introduction to soldering WLCSP packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note

AN10439 “W afer Level Chip Scale Package” and in application note AN10365 “Surface

mount reflow soldering description”.

Wave soldering is not suitable for this package.

All NXP WLCSP packages are lead-free.

13.2 Board mounting

Board mounting of a WLCSP requires several steps:

1. Solder paste printing on the PCB

2. Component placement with a pick and place machine

3. The reflow soldering itself

13.3 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 21) than a SnPb process, thus

reducing the process window

•Solder paste printing issues, such as smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature), and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characterist ic) while be ing low en oug h th at th e packages an d/or boards are no t

damaged. The pea k temperature of the package depends on package thickness and

volume and is classified in accordance with Table 12.

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures dur ing reflow

soldering, see Figure 21.

Table 12. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2 000 > 2 000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 1 — 5 August 2016 22 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

For further information on temperature profiles, re fer to application note AN10365

“Surface mount reflow soldering description”.

13.3.1 Stand off

The stand off between the substrate and the chip is determined by:

•The amount of printed solder on the substrate

•The size of the solder land on the substrate

•The bump height on the chip

The higher the stand off, the better the stresses are released due to TEC (Thermal

Expansion Coefficient) differences between substrate and chip.

13.3.2 Quality of solder joint

A flip-chip joint is considered to be a good joint when the entire solder land has been

wetted by the solder from the bump. The surface of the joint should be smooth and the

shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps

after reflow can occur during the reflow process in bumps with high ratio of bump diameter

to bump height, i.e. low bumps with large diameter. No failures have been found to be

related to these voids. Solder joint inspection after reflow can be done with X-ray to

monitor defects such as bridging, open circuits and voids.

13.3.3 Rework

In general, rework is not recommended. By rework we mean the process of removing the

chip from the substrate and replacing it with a new chip. If a chip is removed from the

substrate, most solder balls of the chip will be damaged. In that case it is recommended

not to re-use the chip again.

MSL: Moisture Sensitivity Level

Fig 21. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 1 — 5 August 2016 23 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Device removal can be done when the substrate is heated until it is certain that all solder

joints are molten. The chip can then be carefully removed fro m the substrate without

damaging the tracks and solder lands on the substrate. Removing the device must be

done using plastic tweezers, because metal tweezers can damage the silicon. The

surface of the substrate should be carefully cleaned and all solder and flux residues

and/or underfill removed. When a new chip is placed on the substrate, use the flux

process instead of solder on the sold er lands. Apply flux on the bumps at th e chip side a s

well as on the solder pads on the substrate. Place and align the new chip while viewing

with a microscope. To reflow the solder, use the solder profile shown in application note

AN10365 “Surface mount reflow soldering description”.

13.3.4 Cleaning

Cleaning can be done after reflow soldering.

14. References

[1] IEC60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[2] IEC61340-3-1 — Method for simulation of electrostatic ef fects - Human body model

(HBM) electrostatic discharge test waveforms

[3] JESD22-A115C — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[4] NX2-00001 — NXP Semiconductors Quality and Reliability Specification

[5] AN10365 — NXP Semiconductors application note “Surface mount reflow soldering

description”

Product data sheet Rev. 1 — 5 August 2016 24 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

15. Revision history

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9410 v.1.1 20160805 Product data sheet -PCA9410 v.1

Modifications: •Deleted Figure 12 Sta r tup

PCA9410 v.1 20151008 Product data sheet - -

Product data sheet Rev. 1 — 5 August 2016 25 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors product s are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environment al

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semicondu ctors products , and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whet her the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specif ication.

Product [short] dat a sheet Production This document cont ains the product specification.

Product data sheet Rev. 1 — 5 August 2016 26 of 27

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9410/9410A

3.0 MHz, 500 mA, DC-to-DC boost converter

For more information, please visit: http://www.nxp.com 

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 5 August 2016

Document identifier: PCA9410

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

7.1 Enable (EN) pin . . . . . . . . . . . . . . . . . . . . . . . . 4

7.1.1 Pass-Through (PT) mode. . . . . . . . . . . . . . . . . 4

7.2 Inrush current limiter (soft start) . . . . . . . . . . . . 5

7.3 Thermal protection . . . . . . . . . . . . . . . . . . . . . . 5

7.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . 6

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7

9 Recommended operating conditions. . . . . . . . 7

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8

11 Application information. . . . . . . . . . . . . . . . . . 14

11.1 Overcurrent protection . . . . . . . . . . . . . . . . . . 14

11.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . 14

11.3 Fault recovery. . . . . . . . . . . . . . . . . . . . . . . . . 14

11.4 Enable delay. . . . . . . . . . . . . . . . . . . . . . . . . . 14

11.5 Connection diagram . . . . . . . . . . . . . . . . . . . . 14

11.6 Recommended inductors . . . . . . . . . . . . . . . . 15

11.7 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . 16

11.8 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . 17

11.9 Layout of the PCB . . . . . . . . . . . . . . . . . . . . . 18

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

13 Soldering of WLCSP packages. . . . . . . . . . . . 21

13.1 Introduction to soldering WLCSP packages. . 21

13.2 Board mounting . . . . . . . . . . . . . . . . . . . . . . . 21

13.3 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 21

13.3.1 Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

13.3.2 Quality of solder joint . . . . . . . . . . . . . . . . . . . 22

13.3.3 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

13.3.4 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

14 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

17 Contact information. . . . . . . . . . . . . . . . . . . . . 26

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27