PS4013B-0600
2365 NE Ho p kin s Co urt
Pullman, WA 99163-5601
tel: 509.334.1000
fax: 509.334.9000
e-mail: sales@aha . com
www.aha.com
advancedhardwarearchitectures
Product Specification
AHA4013B
12.5 MBytes/sec Reed-Solomon
Error Correction Device
Advanced Hardware Architectures, Inc.
PS4013B-0600 i
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2.1 Definition of Correction Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.2 Correcting Capability and Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.5 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.5.1 Shortened Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.6 Reset and Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.6.1 Initialization Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.7 Encode, Decode or Pass-Through Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.8 Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.9 Data Rates and Latencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.9.1 Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.9.2 Continuous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.10 Reed-Solomon (ECC) Module and Error Rate Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.11 Determining Decoder Performance Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.12 Erasures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.0 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.4 Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4
4.0 Signal Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1 Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6
4.2 Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3 Power & Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.5 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.0 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Advanced Hardware Arc h itectur es, Inc.
ii PS4013B-0600
Figures
Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 2: Typical Applications Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3: Data Input and Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4: Burst and Continuous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5: Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes . . . . . . . . . . . . . . . . .11
Figure 6: CLK Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7: Initialization and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 8: Data Input - Buffer Always Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4
Figure 9: Data Input - Buffer Not Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 10: Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11: CRTN Timing - Reverse Order Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Advanced Hardware Architectures, Inc.
PS4013B-0600 iii
Tables
Table 1: Initialization Register Settings for Encode, Decode and Pass-Through Operations . . . . . . . . . . . . . . . . . .7
Table 2: Burst Operation Using 50 MHz Clock and 1 Clock/Byte, Forward Order Output. . . . . . . . . . . . . . . . . . . . .9
Table 3: Continuous Operation Using 50 MHz Clock and Specified Clocks/Byte, Forward OutputOrder. . . . . . . .10
Table 4: Continuous Operation for IESS-308 Codes Using 50 MHz Clock and Specified Clocks/Byte,
Forward Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PS4013B-0600 Page 1 of 24
Advanced Hardware Architectures, Inc.
1.0 INTRODUCTION
The AHA4013B is a single chip integrated
circuit that implements a high speed Reed-Solomon
Forward Error Correction algorithm. The
AHA4013B is a member of the AHA PerFEC
family of high speed forward error correction (FEC)
devices conforming to the Intelsat IESS-308
specification.
The device supports several programmable
parameters, including, block size, error threshold,
number of check bytes, order of output and mode of
operati ons. Shortened blocks are su pported without
requirement of zero padding typically required in
Reed-Solomon decoders. The data input port is used
to initialize the programmable parameters and the
two on-chip buffers are used to input and output
data. Discontinuities in data f low may be controlled
by dedicated control pins.
High operating frequency , input and output data
rate flexibility, low processing latency and various
programmable parameters make this device ideal
for many applications including: DTV, DBS,
ADSL, Satellite Communications, ISDN, High
Performance Modems and networks.
This specificat ion provi des full elect ri cal and
mechanical informatio n to h elp a syst em engineer
develop a system using AHA4013B. This document
contains descriptions on correction terms, pinout,
functi ons and featu res , DC an d AC ch ar act er is tics,
package and mechanical specifications, ordering
information and Related Technical Publications.
Software simulation of the RS code as implemented
in the dev ic e i s also ava il abl e. Please co nta ct AHA
or its authorized sales repr esentative s worldwide or
visit our web s ite a t http:/ /www.aha.com for co pies
of Related Technical Publications and software
simulation.
1.1 FEATURES
HIGH PERFORMANCE
• Polynomial complies to Intelsat IESS-308;
RTCA DO-217 Appendix F, Revision D and
proposed ITU-TS SG-18 (Formerly CCITT SG-
18) standards
• 50 MBytes/ se c burs t transfe r ra te with a 50 MHz
clock for all block lengths
• Sustained data transfer rate of 12.5 MBytes/sec
for block lengths from 54 bytes through 255
bytes using a 50 MHz clock
• Processing latency time less than 12.2 µsec in
continuous operation for block lengths of 100
bytes
FLEXIBILITY
• Programmabl e to c orrec t fro m 1 to 10 error by tes
or 20 erasure bytes per block
• Block lengths programmable from 3 to 255 bytes
• Encode, decode or pass -t hr ough capabili ty in-
line with data flow
• Outputs corrected data or correction vectors in
forward or reverse order
• Continuous or burst data transfer
• Programmable error threshold to help determine
channel performanc e
SYSTEM INTERFACE
• Byte wide synchronous I/O ports with internal
buffering on both ports
• Dedicated control pins permit discontinuities in
system data flow
OTHERS
• 44 pin PLC C; 50 mil lead pitch
• Pin compatible with lower performance
AHA4011/12
• Plug compa tible with AHA4011 /12 ex cep t for an
initialization register setting
• Software emulation of the algorithm available
1.2 CONVENTIONS, NOTATIONS AND
DEFINITIONS
– Certain signals are logically true at a voltage
defined as “low” in the data sheet. All such signals
have an “N” appended to the end of the signal
name. For example, RSTN and DSON.
– “Signal assertion” means the output signal is
logically true.
– Hex values are defined with a prefix of “0x” , such
as “0x10”.
– A range of signal names is denoted by a set of
colons between the numbers. Most significant bit
is always shown first, followed by least significant
bit. F or ex ampl e, DI[7:0] repre sents Data Input
Bus 7 through 0.
– A product of two variables is expressed with an
“×”, for example, N × Ci represents Codeword
Length multiplied by Input clocks/byte.
– Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
Page 2 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
1.2.1 DEFINITION OF CORRECTION TERMS
* For every 2 check bytes, the AHA4013B can correct either 2 erasures or 1 error.
** An erasure is detected by a parity detector or a signal dropout detector. The presence of an erasure is indicated
by asserting the ERASE signal when the erased byte is clocked into the AHA4013B.
2.0 FUNCTIONAL DESCRIPTION
This section describes an archi tectural
overview of the chip and its many functions,
features and operations. The block diagram for the
chip shows the Reed-Solomon ECC module, the
Input and Output Buffers, and their associated
control. All input and output data are clocked on the
rising edge of CLK.
2.1 FUNCTIONAL OVERVIEW
The AHA4013B Reed-So lomon co dec ( code r/
decoder) is a member of the AHA PerFEC™ family
of high speed forward error correction (FEC) devices.
This single chip, three-layer metal, CMOS device can
operate i n enc ode, decode or pas s-t hro ugh modes .
The ECC core implements a full error
correcting Reed-Solomon decoder. This code is
capable of cor rect ing up t o 10 (t =10) byt e-err ors or
20 (t=10) erasures in a RS block.
The ECC core has three phases of operation:
Data In, Calculation and Data Out. Data to be
processed is first input into a single ported Input
Buffer using a control signal DSIN . ECC core
arbitr at es f o r the inpu t da ta out of th e Input Buffer.
ECC core has access to the Input Buffer on clock
edges where DSIN is not asserted.
Each block is processed within the ECC core
and calculations are made. The entire block is
processed through the ECC core, and transferred
into the Output Buf fer. The device asserts RDYON
signal and holds active until the Output Buffer is
completely emptied.
The ECC c ore lo ads th e Out put B uffer in
reverse order for either operation. Data may be
strobed out of the device in forward or reverse order .
If forward order is desired, output data cannot be
strobed out of the device until the entire block has
been loaded into the Output Buffer.
TERM NAME
(other references) DEFINITION RANGE
(number of bytes)
KMessage Length (user
data or message bytes)
Number of user data symbols in one message block.
Size of a symbo l in AHA4013B i s 8- bit s. Mes sag e
length is K = N − R. The first message byte is
referred to as XK−1; the last message byte is X0.
1 through 253
(1, 2, 3, 4... 253)
RCheck Symbols
(parity or redundancy)
Symbols appended to the user data to detect and
correct errors. The number of check symbols
requir ed in a sys tem is R ≥ E + 2e.* The f irst check
symbol is referred to as YR−1; the last check symbol
is Y0.
2 through 20 in
increments of 1
(2, 3, 4... 20)
NCodeword Length
(block length) Sum of message and check symbols. N = K + R. 3 through 255
(3, 4, 5, 6... 255)
t Error Corrections Maximum number of error corrections performed
by the de vice . The value is t = Integer . 1 through 10
(1, 2, 3... 10)
P Error Threshold
The threshold limit to determine uncorrectability of
a Codeword and the number of check bytes
allocated for correction-only purposes (not for
detection).
2 through 20
(2, 3, 4... 20)
e Number of Errors An error is defined as an erroneous byte whose
correct value and position within the message block
are both unknown. 0 through N
E Number of Erasures An erasure is defined as an error whose position is
known within the message block.** 0 through N
G Burden of Correction A measure of the burden of corr ection being placed
on the capabilities of the device f or tha t message
block. The value G = 2e + E. 0 through R
NK–
2
--------------
PS4013B-0600 Page 3 of 24
Advanced Hardware Architectures, Inc.
The use of internal buffers is restricted per the
rules defined in Section 2.9 Data Rates and
Latencies.
Maximum delay required for each block of a
given length to pass through the device is f ixed, and
does not vary with the location or the number of
errors received. This delay (or latency), expressed
in the number o f clocks is discussed in a later
section.
2.2 CORRECTING CAPABILITY AND
POLYNOMIALS
Compared with other codes, RS codes require
relatively few “overhead” check bytes to be added
to the data str eam t o ac hieve a high degree of er ro r
detection and correction. Since the AHA4013B
deals with bytes (or symbols) rather than with
individual bits, when a byte is in error it does not
matter how many bits within the byte are corrupted;
it is counted as one error.
The Reed-Solomon code is defined over the
finite field GF(28). The field defining primitive
polynomial is:
P(x) = x8 + x7 + x2 + x + 1
and the generator polynomial, dependent on the
variable R, is given by:
where R ∈ {2, 3, 4, 5,... 20} for the AHA4013B. This
polynomial is specified in in ternational sta ndards,
Intelsat IESS 308; R TCA DO-217 Appendix F (Rev
D) and the proposed CCITT SG-18.
For every 2 check bytes, the decoder corrects
either 2 erasures or 1 error. An erasure can be
determined with a parity detector or a signal dropout
detector external to the chip. An erasure is indicated
by the ERASE signal when the erased byte is
clocked in the device.
Correcting “erasures” takes only half as much
of the correction capability of the RS code as it takes
to correct “errors”, since the position information is
already known for “erasures”. The correction ability
of the code is bounded as:
R ≥ # erasures + 2(# errors)
Valid block length (N) is defined by the
relationship:
R + 1 ≤ N ≤ 255
where R ranges from 2 to 20.
A complete codeword can th erefore range from
a minimum of 3 bytes to a maximum of 255 bytes.
For further dis cussi on on error rate
performance, refer to Section 2.10 Reed-Solomon
(ECC) Module and Error Rate Performance.
Figure 1: Block Diagram
Figure 2: Typ ical Applications Diagram
Gx() xαi
–()
i 120=
119 R+
∏
=
DI
INPUT BUFFER
ECC CORE
CONTROL
DO
367x9
OUTPUT BUFFE R
256x9
REGISTER
RDYON
RSTN
DSIN
DSON
GND
VDD
CRTN
RDYIN CLK
RDYIN
REGISTER
ERASE DI[7:0] CLK
RSTN
DSIN
DSON
RDYON CRTN DO[7:0] ERR
VDD
GND
DATA SOURCE AHA4013B
ECC COPROCESSOR CHANNEL
1 TO x BITS WIDE AHA4013B
ECC COPROCESSOR DATA SINK
SYSTEM
CONTROLLER SYSTEM
CONTROLLER
A8 8 8 8
B C
ENCODER COMMUNICATIONS DECODER
BLOCK FORMAT AT:
KDATA PLUS R “DUMMY” BYTES
KDATA PLUS R CHECK BYTES
KDATA BYTES
A
B
C
Page 4 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
2.3 SIGNAL DESCRIPTIONS
Input Pins
DI[7:0] Data Input Bus. The input byte and ERASE
are latched on the rising edge of the clock
when both DSI N and RDYIN are active. I f
either DSIN or RDYIN are inactive, the DI
and ERASE are ignored.
DSIN Data Input Strobe . Enables data from DI to
be loaded into the chip. When RDYIN is
active, DSIN being active on the rising
edge of the clock loads the input data in the
device. DSI N must be activ e f or one c lock
edge only per each input byte. DSIN is
ignored if RDYIN is inactive. Signal is
active low.
DSON Data Output Strobe. This input strobe
acknowledges to the chip that data
availa ble on the Ou tput Bus, DO, has been
received by the system. The device uses
this strobe to increment its internal address
counter to the next data location. DSON
must be act ive for one clo ck edge on ly per
each output byte. DSON is ignored if
RDYON is inactive. Active low.
E RASE Eras ure input fla g fo r symbol c urr ent l y on
DI. Signal i s a cti ve hi gh. ERASE sig nal i s
used for marking all check Bytes as
erasures (dummy check Bytes) during
encode operation. It is also used to mark
input symbols that contain errors during
decoding. If not used, connect this signal to
ground.
RSTN Reset. Input pin. When RSTN is active and
DSIN and DSON are inactive, the device
forces all internal control circuitry into a
know n state and init ializes all data path
elements. RSTN is active during
Initializ ation Phase. In this phase, internal
regist er s ar e pr ogr ammed by using DI a nd
DSIN. Signal is active low.
CLK Clock. System clock input. Refer to
Section 4.4 AC Electrical Characteristics
for clock requirements.
Output Pins
RDY IN R ea dy In put. Indica te s the chip’s ability to
accept da ta input on DI. I f ac ti ve, DSI N is
allowed to enable the loading of input data
on DI. When inactive, DSIN is ignored.
Signal is active low.
DO[7:0] Data Output. The output byte is available
on th is bus . The val ue of the ou tpu t byte is
undefine d if RDYON is inac tive. Requires
an acknowledge strobe, DSON, at a rising
edge of th e clock to increment internal
address counter and output the next
location in the buffer. DO bu s is always
driven and is not tristated by the device.
RD YONReady Output. This output pin indicates the
chip’s ability to generate output data. If
active, DSON is allowed to increment the
internal addres s count er for the next data
byte. When inact ive DSON i s i gno red and
DO is undefined. Signal is active low.
CRTN Correctable. The output pin when active
indicates the block did no t exceed the error
threshold programmed by P. Error
threshold must be programmed with the
same value as the number of check symbols
R if erasures are not used. This signal is
valid when the first m essage byte, XK−1, of
the block is available out of the chip.
During a ll other times the si gnal is
undefined. Signal is valid for at least one
clock. Active low.
ERR Error. Output pin indicates the current
value on DO[7:0] is a corrected byte.
Active high.
2.4 PINOUT
6
5
4
3
2
1
44
43
42
41
40
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DISN
CLK
GND
39
29
30
31
32
33
34
35
36
37
38 VDD
GND
GND
RDYON
RDYIN
DSON
ERASE
RSTN
VDD
GND
VDD
7
17
16
15
14
13
12
11
10
9
8
VDD
GND
GND
VDD
*NC
*NC
VDD
GND
GND
VDD
GND
18
19
20
21
22
23
24
25
26
27
28
DO0
DO1
DO2
DO3
DO4
DO5
DO6
VDD
DO7
ERR
CRTN
INPUT
OUTPUT
*NC = No con ne c t, res erv e d for fu ture co ns i de rati o ns .
AHA4013B-050 PJ C
PS4013B-0600 Page 5 of 24
Advanced Hardware Architectures, Inc.
2.5 DATA FLOW
The device is first initialized for various
programmable parameters including: Erasure
Multiplie r, Error Threshold, N umber of Check
bytes, Number of Message bytes per block, Block
Length and a Cont rol byte. Fol lo wing t his six -by te
initialization, the de vice m ay be used to en code,
decode or pass-through multiple blocks of data. The
device requires reinitialization when the parameters
are changed or a reset is required.
The device processes data as “blocks”
containing Message and Check Bytes. Order of
input bytes must be first message byte XK−1 through
last mess age byte X0, followed by first check byte
YR−1 through last check byte Y0. The device
processes the block in this manner:
- a block is clocked into the I nput Buffer ;
- transferred into the ECC module;
- passed to the Outp ut Buffer in th e reverse order
from what was received at the Input Port; and
- clocked out through the Output Port via the
Output Buffer. Consecutive blocks may be
input into the Input Buffer while the Output
Buffer is being emptied.
Data is available through the Output Port in
forward or reve rs e order. Forward order clocks out
the block the same as input and reverse order clocks
the check byte Y0 through check bytes YR−1
followed by message byte X0 through message byte
XK−1.
2.5. 1 SHORTENED BLOCKS
This device allows for shortened RS blocks,
thus not requiring zero padding when decoding.
During encoding, conversely, zero padding is not
performed. When the device is programmed to
decode a block of less than 255 Bytes, only the
message bytes followed by check bytes are sent.
Prepending with zero value bytes to fill out the
block to 255 Bytes is not required.
Figure 3: Data Input and Output Order
2.6 RESET AND INITIALIZATION
SEQUENCE
Reset and initialization first requires pulling the
RST N low signal for a t least two clocks while the
DSIN and DSON signals are held inactive, i. e., high
Following this sequence, the six internal
registers, referred to as “Initialization Registers” are
strobed by DSIN. These bytes are loaded in order of
1 through 6.
The R STN m ust be activ e low for at least two
clocks before the first initialization byte is strobed
in and rema in ac ti ve for at least one clock afte r the
final byte. RSTN must be high for at least two
clocks before the firs t message byte can be st robe d
into the device. For a detailed timi ng diagram, see
Figure 7: Initialization and Reset Timing.
The ch ip m ust b e reset and init ia lized a ny t ime
a reset is nece ssary.
Caveat: All six regi sters must be initia lized
correctly for proper operation of the chip. The
device has no provisions for reading back
Initi alizati on Register settings. Thi s sequence mu st
be used if the device needs to be reset or any one
register needs updating, i.e., all registers must be
reinitialized for a change to any one register.
ECC
Core
Data Available
Reverse Order Forward Order
Data Available
.
.
.
.
.
.
X
0
Y0
R-1
Y
K-1
X.
.
.
.
.
.
Y0
X0
R-1
Y
K-1
X
Last Byte Out
First Byte Out
First
Byte
In
Last
Byte
In
. . . . . .
X1
Y1
Y0X0R-2
YR-1
YK-2
XK-1
X
INPUT
BUFFER OUTPUT
BUFFER
Page 6 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
2.6.1 INITIALIZATION REGISTERS
BYTE 1, ERASURE MULTIPLIER:
[7:0] M ultiplier value that must be pr ogrammed
as shown in Appendix A. The table shows a
value to be programmed corresponding to
the block length selected.
BYTE 2, ERROR THRESHOLD:
[4:0] T he threshold for d etermining
uncorrectability of a data block, and the
number of check bytes allocated for
correction only purposes. When not using
erasur es, set to th e sa me value as BYT E 3,
CHECK BYTES. Minimum value of 0x02
sets the Thresho ld to 2 and 0x14 s ets to the
maximum, 20.
[6:5] Reserved. Set to 0.
[7] Reserved. Must be set to 1.
BYTE 3, CHECK BYTES:
[4:0] Number of check bytes in RS code, R.
Minimum setting of 0x02 indicates two
check bytes for R = 2 and 0x14 indicates the
maximum of 20.
[6:5] Reserved. Set to 0.
[7] Reserved. Must be set to 1.
BYTE 4, MESSAGE BYTES:
[7:0] Number of message bytes in code, K.
Minimum sett ing of 0x01 ind ic ate s 1 byte,
setting to 0xFD indicates the maximum 253
message bytes.
BYTE 5, BLOCK LENGTH:
[7:0] Number of bytes in block, N. Setting to
0x03 indicates 3 bytes, setting to 0xFF
indicates 255 bytes.
BYTE 6, CONTROL BYTE:
[0] RESERVED Reserved. Set to 0.
[1] NOPAR Parity Symbol Control
0 Check bytes are output
following the message bytes.
1 Check bytes are not output
following the message bytes.
Correcti on will be done
regardl ess depending upo n the
bit 4, RAW, setting.
[2] CRCTS Correction Control
0 Outputs correction vectors; to
obtain corrected data,
externa lly XOR t he co rr ectio n
vector with the corresponding
message or check byte.
1 Outputs corrected data
[3] FOR Forward Order Control
0 Outputs the block in reverse
order
1 Outputs the block in forward
order
[4] RAW Raw Data
0 Outputs corrections or corrected
data p er t he CRCTS bi t
1 Outputs uncorrected, raw input
data or 0 ’s depe nding upon t he
CRCTS bit setting (See tabl e
below). NOPAR bit and
CHECK BYTE register
settings are ignored.
[5] ERC Erasure Rejection Control. This
bit is only used by the device
when the Erasures exceed the
ERROR THRESHOLD or R
settings. This bit is ignored
when the Erasures are less than
or equal to ERROR
THRESHOLD or R.
0 If Erasure s are greate r than th e
ERROR THRESHOLD or R
then erasures are discarded and
full correction is performed.
The block is flagge d
uncorrectable and the output
CRTN will be high during the
last output byte of the block.
1 If Erasures are greater than
ERROR THRESHOLD or R
then erasures are discarded and
full correction is performed.
The output CRTN will be hig h
only when the block is
uncorrectable.
[7:6] Reserved, Set to 0.
RAW CRCTS Output
0 0 Correction vectors
0 1 Correct ed dat a
10 Zero
1 1 Uncorrected raw input data
PS4013B-0600 Page 7 of 24
Advanced Hardware Architectures, Inc.
2.7 ENCODE, DECODE OR PASS-THROUGH OPERATIONS
The device performs three functions: encoding,
decoding and pass-through. As an encoder the device
outputs the message block followed by “corrected”
check bytes. As a decoder, the device outputs the
corrected message bytes or correction vectors with or
without check bytes following the message. In pass-
through operation, the device passes the input data as
it is received. In all three operations, the input block
flows through the Input Buffer into the ECC module
and out of the Output Buffer. Latencies for all three
operations are the same.
The device is initialized for the three operations
as shown in the table below.
Table 1: Initialization Register Settings for Encode, Decode and Pass-Through Operations
As an encoder, the device is used with the
Erasure s feature enabled in the fo llowing sequence .
(Asserting the ERASE signal high enables the
Erasure feature.)
1) After initia li zat ion, the devi ce recei ves the
message dat a followed by “dummy” check
bytes. “Dummy” check bytes are clocked
into the device with the ERASE signal
asserted. The number of “dummy” chec k
bytes must equal R.
2) The ECC core processes the block by
“correcting” the check bytes and feeding
the codeword into the Output Buffer in
reverse order.
3) The block is then made available on the
output bus, DO. The state of the output
RDYON determines the availability of
data. ERR signal is asserted while the
“corrected check bytes” are output on the
output bus, DO. CRTN is asserted low
during the last byte out of the chip
indicating that the previous block did not
exceed th e erro r threshold.
As a decoder, the device works similar to the
encode operation in the following sequence.
1) Following init ializa ti on, th e syst em clocks
the message data and the check bytes into
the Input Buffer. ERASE signal may be
asserted as desired by the system. State of
the output signal, RDYIN determines the
chip’s abili ty to a ccept dat a input on the DI
bus.
2) The ECC Core processes the block by
performing necessary corrections, and
feeds the codeword into the Output Buffer
in reverse orde r.
3) The data is available on the output port. The
state of the output signal, RDYON
determines the availability of valid data. An
output byte which has been corrected is
indicated by the device asserting ERR.
CR T N may be high or low d epending upon
the THRESHOLD Register and ERC bit
programmed and the errors encountered.
INITIALIZATION
REGISTER BIT(S) ENCODE DECODE PASS-THROUGH
ERASURE MULTIPLIER [7:0] Appendix A value Appendix A value Appendix A value
ERROR THRESHOLD [7:0] Set to R R or less R
CHECK BYTES [7:0] Set to R R R
MESSAGE BYTES [7:0] Set to the Nu mber
of Message Bytes
in block, K KK
BLOCK LENGTH [7:0] Set to the total of
Message and
Check bytes, N NN
CONTROL BYTE
0 (RESV) 0 0 0
1 (NOPAR) 0 System specific 0
2 (CRCTS) 1 System specific 1
3 (FOR) System specific System specific System specific
4 (RAW) 0 0 1
5 (ERC) 0 System specific 0
[7:6] Reserved 0 0 0
Page 8 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
In pass-through operation, data flows through
the device similar to the encode and decode
operations. During initialization the device is
programmed as shown above. Check Bytes are
programmed in the range of 0x02 to 0x14. The
Block le ngth he re i s the sum of Mes sage Byt es an d
Check Bytes like encode and decode modes of
operation even though the device passes through the
block of data unchanged.
1) Following initialization, the system clocks
the codeword into th e Inp ut Bu ffer.
2) The codeword is processed by the ECC
module and passed on to th e Output Buf fer
without cor rection.
3) The uncorrect ed codeword is available at
the output port. State of the RDYON
determines the availability of valid data.
The ERASE input is ignored during the
Input phase and ERR and CRTN outputs
are not valid .
Caveat: The device has no provisions for indicating
the sta rt and /or en d of mess age or c heck byt es. It is
the syst em designer s respon sibility t o keep tr ack of
message and check bytes transitions, if required.
2.8 BUFFERS
The Input Port contains a single-ported 367x9
buffer. The Output Port contains a single-ported
256x9 buffer. These buffers store input and output
data during the correction process and help maintain
the desired system data rate. A Reset operation as
describe d in th e Initialization Sequence sect ion
clears the buffers.
The use of internal buffers is restricted per the
rules defined in Section 2.9 Data Rates and
Latencies. These rules define the limitations of
using the buffers to temporarily store more than one
block. It is highly recommended that the system
designer clearly understand these rules prior to
designing the system.
The Input Buffer receives input data on the DI bus
when the ECC module is in the calculation o r in data-
out phases at the desired system rate. The ability of the
Input Buffer to accept dat a i s in dic ated by RDYIN.
The Output Buffer accepts corrected data from the
ECC during t h e data- o ut pha se. RDYON is asser t e d
low when the Output Buffer is able to output data.
Data flow through the device may occur in burst
or cont inuous ra te s. The number o f c locks per b yte
used to input or output determines burst or
continuous operating conditions. Figure 4 shows the
two operations.
Burst operation permits data to be clocked in
and out of the device at the maximum rate, i.e., 1
clock pe r by te. I n burst opera tion, consecu tive d ata
blocks are clocked into the device following a
processing latency period. Data is input into the
Input Buffer and processed through the ECC core.
After a processing latency period the entire block of
data is transferred to the Output Buffer. While the
Output Buffer is being e mpti ed, t he Input Buffer is
simultaneously filled with the following block at the
maximum rate. Input and output rates are controlled
by the clock speed and clocks/byte.
Continuous oper ation requi res a mini mum of 4
clocks/byte depending upon the block size.
Maximum data transfer rates for continuous rate
vary accordingly. Blocks may be processed
continuously through the device. If the chip is
operate d with cont inuous da ta strea ms, the RDYIN
and RDYON pins will always be active (after the
initial latency). Therefore, they need not be used.
Caveat: Syst em desi gner sho uld be awa re that data
is put into the Output B uffer in reverse order.
Therefor e, RDYON may become inact ive bet ween
blocks i n forward order if d ata i s output faster t ha n
Output Buffer is filled.
2.9 DATA RATES AND LATENCIES
This section describes data rates and processing
latencies for burst and continuous operations.
Processing latencies are the same in encode, decode
or pass-through operations. The number of clocks
used to clock in and out of the device determines the
operation. The input and output rates need not be the
same. No registers are required to program the
device for either operation.
Continuous block flow is achieved by using th e
appropriate number of clocks per byte and block
length. Alternatively, data flow into and out of the
device is controlled using control signals, DSIN and
DSON.
2.9.1 BURST OPERATION
Maximum processing latency , in forward order ,
expressed in number of clocks, for burst operation is
determined by: N × Ci + R + 60 + N
Definitions:
Ci=input clock rate per byte. If Ci= 1, use a value
for Ci of 2 in the latency equation
N=block length
R=number of check bytes
Processi ng Latency = Delay from first input byte to
first output byte
In reverse order, processing latency is
approximately N clocks less than above.
For a 50 MHz system using 1 clock per byte,
latencies and data rates for forward order output are
shown in the table for burst operation. Input and
Outp ut Burst Ra tes in all cases will be 50 MBytes/
PS4013B-0600 Page 9 of 24
Advanced Hardware Architectures, Inc.
sec. Note: Other frequency operations may be
derived similarly.
Output Buffer may be used to hold data from
one block while the Input Buffer is being filled with
the foll owing bl ock . Two rules list ed in th e cav eats
are required to accomplish this. These are illustrated
in Figure 4.
Caveats:
1. Output of block i must start coincident with or
before the input of block i + 1.
2. Output of block i must be complete:
Processi ng Latency − N − 8 clocks
after the start of block i + l on the input.
Table 2: Burst Operation Using 50 MHz Clock and 1 Clock/Byte, Forward Order Output
2.9.2 CONTINUOUS OPERATION
Multiple blocks of data may be processed
through the device continuously as shown in Figure
4. Consecutive blocks are input into the device at
the rate of Ci clocks/byte. The output data stream
may or may not be continuous depending on
whether parity is being output (controlled by
NOPAR) and the choice of Co. Continuous
operation is described by several equations. The
following terms are used in these equations:
Ci- Input clock rate per byte: Ci ≥ 4 for
continuous operation
Co- Output clock rate per byte: Co ≥ 2
Cm- Minimum of Ci and Co: If Ci < Co then
Cm=Ci else Cm=Co
N - Reed-Solomon block length
K - Reed-Solomon message length
R - Reed-Solomon parity length (R = N − K)
L - Output data length: If parity is being output
from the chip (NOPAR = 0), L = N; else if
the parity is not be ing output (NOPAR = 1)
L = K
A. Conditions for Continuous Operation
The allowable input and output data rates are
related to the Reed-Solomon block length by the
followi ng two inequali ties. Ci, Co, N and K must be
chosen so that these equations are satisfied.
Equation 1:
Equation 2:
B. Processing Latency
Processing latency is the time from the beginning
of a block on the input to the block being ready for
output. Maximum processing latency, expressed in
number of clocks, for continuous operation is:
Equation 3:
C. Start and End of Output
Similar to the b urst o peration, Output Buffer
may be used to temporarily “hold” data from one
block while the In put B uffer is being filled.
How ever, these co nditi ons must be satisfied: the
output of a data block must start after the latency
equation (Equation 3) is satisfied, but before the
maximum dela y is reac hed. The maxi mum delay is :
Equation 4:
CHECK BYTES ‘R’ = 20 CHECK BYTES ‘R’ = 2
BLOCK
LENGTHS ‘N’ MAXIMUM
LATENCY
(# of clocks)
MAXIMUM
LATENCY
(µsecs)
AVERAGE
RATE
(MBytes/sec)
MAXIMUM
LATENCY
(# of clocks)
MAXIMUM
LATENCY
(µsecs)
AVERAGE
RATE
(MBytes/sec)
25 155 3.10 8.06 137 2.74 9.13
50 230 4.60 10.88 212 4.24 11.79
100 380 7.60 13.13 362 7.24 13.75
150 530 10.64 14.13 512 10.24 14.63
200 680 13.60 14.75 662 13.28 15.13
255 845 16.88 15.13 827 16.56 15.38
Average Rate N
Maximum Latency µsec()
----------------------------------------------------------------=
R60 NC
m
×
Cm1–
-----------------++
Ci
---------------------------------------- N367≤+
N1–()Ci
×R48 NC
i
×
Ci1–
--------------- NC
m
×
Cm1–
-----------------++ +≥
Latency N1–()Ci
×=60RNC
m
×
Cm1–
-----------------+++
maximum_delay 3 NC
i
×× LC
oNC
i
×
Ci1–
---------------–×–=
if maximum_delay
Ci
--------------------------------------------- 367, then maximum_delay 367 Ci
×=≥
if maximum_delay
Ci
--------------------------------------------- 2 N, then maximum_delay×2NC
i
××=>
Page 10 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
Data of one block must be fully emptied L ×Co clocks after the start of empty process.
All of the conditions on the maximum delay given in Equation 4 must be satisfied. If any are not, the
output data s tr ea m wil l begin t o inhibit ECC pr oce ssi ng. Eventua ll y t h i s wil l c aus e t h e in put buffer to over
fill and RDYIN to become inactive.
Figure 4: Burst and Continuous Operations
(Note: Blocks are shown from right to left as they are input into and output from the chip in Forward Order.
Block i is the first input block, block i + 1 is sec ond in pu t block . XK − 1 is the first input message byte of a block. Yo
is the last input check symbol of a block. Notes 1 and 2 in burst operation are described in Section 2.9.1 Burst
Operation - Caveats.)
For a 50 MHz syste m using the required clock s per byt e, maximum latenci es and da ta ra tes for forward
order out put are sh own in the table fo r con ti nuou s oper at io n. Input and Output rat es ar e ass umed t he same
in this table. Note: Other frequency operations are also possible.
Table 3: Continuous Operation Using 50 MHz Clock and Specified Clocks/Byte, Forward
Output Order
For Intelsat IESS-308, Rev F, Inner FEC Rates, use Table 4 for a system with 50 MHz clock.
Note: Other frequency operations are also possible.
CHECK BYTES ‘R’ = 20 CHECK BYTES ‘R’ = 2
BLOCK
LENGTHS ‘N’MINIMUM
REQUIRED
(clocks/byte)
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(µsecs)
MINIMUM
REQUIRED
(clocks/byte)
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(µsecs)
25 6 8.34 5.08 5 10.0 4.26
50 5 10.00 7.75 5 10.0 7.39
100 4 12.50 12.18 4 12.5 11.82
150 4 12.50 17.52 4 12.5 17.16
200 4 12.50 22.86 4 12.5 22.50
225 4 12.50 25.52 4 12.5 25.16
255 4 12.50 28.72 4 12.5 28.36
Input Data:
Output Data:
Block i+3 Block i+2 Block i+1 Block i
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y0Y0Y0Y0
Block i+3 Block i+2 Block i+1 Block i
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y0Y0Y0Y0
K-1
X
K-1
XK-1
X
K-1
X
K-1
X
K-1
XK-1
X
K-1
X
Burst Operation
Continuous Operation
Block iBlock i+1
Input Data:
Output Data:
Processing Latency
Block i+1 Block i
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . .
Y0Y0
Y0
K-1
X
. . . . . . . . . .
Y0 K-1
X
K-1
X
K-1
X
21
PS4013B-0600 Page 11 of 24
Advanced Hardware Architectures, Inc.
T able 4: Continuous Operation for IESS-308 Codes Using 50 MHz Clock and Specified Clocks/Byte,
Forward Output Order
Appendix B shows a spreadsheet table of block lengths vs. latencies for a 50 MHz clock system.
2.10 REED-SOLOMON (ECC) MODULE AND ERROR RATE PERFORMANCE
The module implements a full error correcting
Reed-So lom on (RS) decoder w hose func tion is to
perform the necessary corrections on the input
blocks. Th e code used by the decoder i s ca pab le of
generati ng co rrections for up to 10 (t = 10) byte-
errors in an RS block o ver the block length between
R + 1 to 255 bytes. The number of message bytes in
an RS block, K, is equal to the RS block length
minus R (K = N − R). The RS code implemented
uses the primitive polynomial
P(x) = x8 + x7 + x2 + x + 1
to generate GF(256). The generator polynomial for
the code is:
An RS block consists of message and
redundan cy bytes. Th e number o f message b ytes in
the block, K, is programmable during initialization.
The number of check bytes is R and can be
programmed during initialization to be 2 through 20
in increments of 1.
The ECC Module may be programmed to
output corrections or corrected data. If
“corrections” is selected, to obtain corrected data,
externally XOR the output correction vector with
the corresponding message or check byte. For
example, if “corrections” is selected for a block of
200 bytes with errors in locations 100, 123, 153, 176
and 199; output block will be 0’s f or all locations
except for those positions. The bytes outpu t at these
positions are referred to as correction vectors and
are XOR’d exte rnally with the message by tes to
obtain the correct value. If the output of the
AHA4013B is programmed to output corrected
data, t h e c orr ec tion vect or is appli ed internal l y and
the corrected data is output.
The Symbol Error Rate Performance of the
Reed-Solomon code used is shown in Figure 5.
Figure 5: Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes
BLOCK
LENGTHS ‘N’MESSAGE
LENGTH ‘K’ERROR
CAPABILITY ‘t’MINIMUM
REQUIRED
(clocks/byte)
MAXIMUM
DATA RATE
(MBytes/sec)
MAXIMUM
LATENCY
(# of clocks)
MAXIMUM
LATENCY
(µsecs)
126 112 7 4 12.5 742 14.84
194 178 8 4 12.5 1107 22.14
208 192 8 4 12.5 1181 23.62
219 201 9 4 12.5 1242 24.82
225 205 10 4 12.5 1276 25.52
Gx() xαi
–()
i 120=
119 R+
∏
=
t=1
t=3
t=5
t=8
t=10
10
-0 -3
10
-4
10
-5
10
-6
10
-7
10
-8
1010
-1
10
-0
10
-2
-4
10
-6
10
-8
10
-10
10
-12
10
-14
10
-16
10
10
-2
P
P
Page 12 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
The most common measures of performance for
Reed-Solomon code are PUE, PSE, and CBER. PSE is
the probability of symbol errors and is the ratio of
the number of received symbol errors to the total
number of received symbols. In the AHA4013B
device t he symbol l engt h, m, i s e qual to 8 b it s. PUE
is the probability of an uncorrectable error and is the
ratio of the number of uncorrectabl e code blocks to
the total number of received code blocks. An
uncorrectable error occurs when more than t
receiv ed symbols are in e rror . CBER is the Correct ed
Bit Error Rate. The CBER is the reciprocal of
expected number of correct bits between errors.
If input noise is random, .
If with , and
.
The figure shows probability of symbol error
and uncorr ectable error for bloc k size (N) of 255. It
shows the ability of various levels of Reed-Solomon
error correction to restore the inte grity of the
corrupted data. For example, using 255 byte blocks,
if 1 out of 1000 of the received bytes have one or
more bit errors, RS correction with t = 5 will restore
the data to 1 error in 2 million blocks (510 million
bytes).
For a detailed discussio n on error rate
perfor mance of Reed -Solomon c ode, ref er to AHA
Application Note, Primer: Reed-Solomon Error
Correction Codes (ECC), (ANRS01).
2.11 DETERMINING DECODER
PERFORMANCE BOUNDARIES
AHA4013B supports a programmable feature
that allows a system designer to determine the
channel performanc e. This prog ra mmab le feature,
referred to as error threshold, P, sets a number of
errors to be allowed by the chip prior to flagging the
block uncorrectable. Erasure Rejection Control bit
of the Control Byte register determines the
condition of CRTN output pin.
P and R are both independently selectable by
the use r duri ng the In itiali zation Con trol Sequ ence.
The various configurations of P and R are described
as follows:
P > R This is not a sensible choice since this
implies that more check bytes are allocated
for (correction-only) purposes than there
are t otal check byt es (for bot h correct ion
and detection). The device will work as if P
was set equal to R.
P = R This configuration maximizes the ability to
correct errors, particularly if R itself has
been chosen to be its maximum value of 20.
This is the usual choice. This situation
causes t he CRTN output t o fl ag a message
block as uncorrectable at an error level
exceeding that of which the device is
capable.
P < R This incr eases the level of error de tection
capabil ity. This s ituatio n causes the CRTN
output to flag a message block as
uncorrectable at an error level below that of
which the device is capable.
Caveat: Output block may be corrupted if a block
exceeds the correction ability of the ECC module.
2.12 ERASURES
The chip is capable of utilizing erasure
information. R erasures may be corrected in any
block assuming there are no unmarked errors.
The correction capability is: E + 2e ≤ R
Where E = number of era sur es (mar ked err or s)
e = number of unmarked errors
R= number of check symbols
If there are more than P or R erasures the
erasure information is discarded, and full error
correction is attempted. The chip can be
programmed to either call such a block
uncorre cta ble or not. I f pr ogr ammed no t to call t he
block uncorrectable (ERC bit set to 1), the ECC will
utilize the full error correction capability to decide if
the block is correctable.
3.0 OPERATIONAL DESCRIPTION
This section describes the relationship of
associated signals for various functions of the chip.
3.1 CLOCK
The clock input to the chip must meet the timing
requirements shown in Figure 6. The chip is entirely
static thu s allowing the clock to sto p in either the
active or inactive state for an indefinite period
without loss o f stored information .
CBER PUE
mN×
---------------=
PSE 810
4–
×=t5=
PUE 10 7–
=
CBER 10 7–
8255×
------------------4.910
11–
×==
PS4013B-0600 Page 13 of 24
Advanced Hardware Architectures, Inc.
Figure 6: CLK Characteristic s
All timing diagrams in this specification use the clock at the CLK pin as the reference point.
3.2 INITIALIZATION
This secti on describe s the Rese t and In it ializat io n Sequence timing . For a detai le d disc uss ion on these
sequences, refer to Section 2.6 Reset and Initialization Sequence.
Figure 7: Initialization and Reset Timing
Initialization bytes are strobed into the device
while RSTN a nd DSIN ar e low d uring risi ng edges
of CL K. The RST N must be active low for at least
two clocks bef ore th e first init ializatio n byt e is
strobed in and remain active for at least one clock
after the final byte. Initialization register data may
be strobed at a minimum of 1 clock per byte. After
power-on the init ializing r egisters’ contents are
undefined.
For a detailed d escription of the Ini tialization
Registers, refer to Section 2.6 Reset and
Initialization Sequence.
3.3 DATA INPUT
The chip latches the input data on the DI pins on
the rising edge of the CLK when DSIN and RDYIN
are both active. The two figures below show the
timing diagrams for buffer Ready and buffer Not
Ready conditions.
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 CLK rise time 5 nsec
2 CLK high time 8 nsec
3 CLK fall time 5 nsec
4 CLK low time 8 nsec
5 CL K period 20 nsec
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 RSTN and DSIN setup time 7 nsec
2 RSTN and DSIN hold time 0 nsec
3 RSTN and DSIN assertion 2 Clock cycles
CLK
1234
5
1
112 2
23 6145
CLK
DI
DSIN
RSTN
at least 2
cloc k cy cles Input 6 bytes data for initialization
RESET
at least 1
clock cycle
Data
at least 2
clock cycles
3
INITIALIZE
DSON
Page 14 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
Figure 8: Data Input - Buffer Always Ready
If RSTN is low during write, message bytes are treated as being part of the initialization sequence. If
RSTN is high, the data is treated as being part of RS block. In the example above ERASE is asserted high
in four sa mple clocks.
Figure 9: Data Input - Buffer Not Ready
Any input data clocked while RDYIN is inactive are ignored. This is shown in Figure 9.
3.4 DATA OUTPUT
The DO pins are dr iven from a register clocked
on the rising edge of CLK.
Valid data on the DO pins is indicated by
RDYON being active. When RDYON is inactive,
data on the DO pins is undefined, and DSON is
ignored. The DSON signal acknowledges receiving
the data and is used by the device to internally
increment the address counter and output the next
locati on in the buffe r. This data output ti ming is
shown in Figure 10.
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DI, ERAS E an d DSI N setup tim e 7 nsec
2 DI, ERASE and DSIN hold time 0 nsec
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DI, ERAS E an d DSI N setup tim e 7 nsec
2 DI, ERASE and DSIN hold time 0 nsec
3 RDYIN output delay 13 nsec
1
1
22
2
2
22
2
1
1
11
1
valid valid valid valid valid
CLK
DI
DSIN
RDYIN
3
3
3
3
RSTN
PS4013B-0600 Page 15 of 24
Advanced Hardware Architectures, Inc.
Figure 10: Data Output
CRTN is valid f or a n RS blo ck when the firs t message byt e, XK−1, is str obe d out of the chip . Figure 11
shows Rever se Order output . In thi s opera tion, CRTN is vali d on the l ast by te of t he block from the Output
Buffer. In this example only message bytes are output, no check bytes.
Figure 11: CRTN Timing - Reverse Order Output
Note: CRTN is active (low) if RS block m is correctable. If the number of errors detected in block m exceeds the
error threshold, P, CRTN is inactive (high).
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DSON setup time 8 nsec
2 DSON hold time 2 nsec
3 DO output delay 3 13 nsec
4 RDYON output delay 3 13 nsec
NUMBER DESCRIPTION MINIMUM MAXIMUM UNITS
1 DSON setup time 7 nsec
2 DSON hold time 2 nsec
3 DO output delay 3 13 nsec
4 RDYON, CRTN output delay 3 13 nsec
valid
CLK
DO , ERR
DSON
RDYON
3
valid valid valid valid
333
12 111111 122 222 22
444
CLK
DO
DSON
RDYON
3333
12 111111 122 222 22
444
VALID
See Note
CRTN 4
Block m
Byte XK-3
Block m
Byte XK-2
Block m
Byte XK-1
Block m+1
Byte X1
Block m+1
Byte X0
error
correctable
Page 16 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
4.0 SIGNAL SPECIFICATIONS
4.1 INPUT SPECIFI CATIONS
N/A = Not Applicable
(Refer to Section 4.5 DC Electrical Characteristics for pad specifications)
4.2 OUTPUT SPECIFICATIONS
(Refer to Section 4.5 DC Electrical Characteristics for pad specifications)
4.3 POWER & GROUND PINS
PIN
NUMBER SIGNAL
NAME SELF LOAD
(maximum in pF) TSETUP
(min in nsec) THOLD
(min in nsec) STROBE
43 DI[7] 10 7 0 CLK
44 DI[6] 10 7 0 CLK
1DI[5] 10 7 0 CLK
2DI[4] 10 7 0 CLK
3DI[3] 10 7 0 CLK
4DI[2] 10 7 0 CLK
5DI[1] 10 7 0 CLK
6DI[0] 10 7 0 CLK
42 DSIN 10 7 0 CLK
33 DSON 10 8 2 CLK
35 RSTN 10 7 0 CLK
41 CLK 10 N/A N/A N/A
34 ERASE 10 7 0 CLK
PIN
NUMBER SIGNAL
NAME LOAD CAP
(maximum in pF) TDEL
(min in nsec) TDEL
(max in nsec) STROBE
REF
26 DO[7] 60 3 13 CLK
24 DO[6] 60 3 13 CLK
23 DO[5] 60 3 13 CLK
22 DO[4] 60 3 13 CLK
21 DO[3] 60 3 13 CLK
20 DO[2] 60 3 13 CLK
19 DO[1] 60 3 13 CLK
18 DO[0] 60 3 13 CLK
31 RDYON 60 3 13 CLK
32 RDYIN 60 3 13 CLK
28 CRTN 60 3 13 CLK
27 ERR 60 3 13 CLK
PIN NUMBER SIGNAL NAME
8, 10, 11, 16, 17, 29, 30, 37, 40 GND
7, 9, 12, 15, 25, 36, 38, 39 VDD
PS4013B-0600 Page 17 of 24
Advanced Hardware Architectures, Inc.
4.4 AC ELECTRICAL CHARACTERISTICS
CLO C K RATE
Symbol Characteristic Min Max Units Test Conditi ons
Fclock Clock fr equency 0 50 MHz
Tlow Clock low time 8 nsec Vil to Vil
Thigh Clock high time 8 nsec Vih to Vih
Trise Clock rise time 5 nsec Vil to Vih
Tfall Clock fal l ti me 5 n sec Vil to Vih
INPUTS
Symbol Characteristic Min Max Units Test Conditions
Tsetup Input setup time 7 nsec See Notes 1 and 3
Thold Input hold time 0 nsec See Notes 1 and 2
Notes:
1) Setup and hold times measured from a Vih on the clock input pin.
2) DSON has a 2 nsec hold time.
3) DSON has a 8 nsec setup time.
OUTPUTS
Symbol Characteristic Min Max Units Test Conditions
Tout DO[7:0] Outpu t dela y 3 13 nsec See Note
Tout RDYON, RDYIN, ERR, CRTN
Output delay 3 13 nsec See Note
Note: Output delay measured from Vih on the clock input pin to Vol/Voh on the signal pin. The output loads for
the AC test are given in Section 4.2 Output Specifications.
Page 18 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
4.5 DC ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM STRESS RATINGS
Symbol Characteristic Min Max Units Test Conditions
Tstg Storage temperature -55 150 deg C
Vdd Supply voltage -0.5 6.0 V
Vin Input voltage Vss-0.5 Vdd+0.5 V
Package: 44-pin PLCC (JEDEC Standard)
OPERATING CONDITIONS
Symbol Characteristic Min Max Units Test Conditions
Vdd Supply voltage 4.75 5.25 V
Idd Supply current 1.0 mA Static; Clock
stopped externally
Idd Supply current 185 mA Dynamic
Ta Operating tempe ra tur e 0 70 deg C
P Power 0.89 W
INPUTS
Symbol Characteristic Min Max Units Test Conditions
Vih Input high voltage 2.0 Vdd V
Vil Input low voltage Vss 0.8 V 50 MHz
Iil Input leakage -10 10 µΑ 0<Vin<Vdd
Cin Capacitance 10 pF Not 100% tested
OUTPUTS
Symbol Characteristic Min Max Units Test Conditions
Voh Output high voltage 2.4 Vdd V Ioh=8mA
Vol Output low voltage Vss 0.4 V Iol=8mA
Ioh Output high current -8 mA Voh=2.4V
Iol Output low current 8 mA Vol=0.4V
PS4013B-0600 Page 19 of 24
Advanced Hardware Architectures, Inc.
5.0 PACKAGING
PLCC Dimensio ns Inches
(Millimeters)
Packaging
Complete Package Dr awin g Availabl e Upon Request.
AB
min/max C
min/max D
min/max E
min F
±G
±
.050
(1.27) .685/.695
(17.40/17.65) .650/.656
(16.51/16.66) .165/.180
(4.19/4.57) .020
(0.51) .002
(0.051) .0035
(0.089)
F = Lead Planarity
C
Pin 1 Identification
YYWWD-( CO UNT RY OF ORIGIN)
LLLLL
B
A
D
E
G = Lead Skew
YYWWD = Data Code
LLLL = Lead Skew
Note:
AHA4013B-050 PJC
Page 20 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
6.0 ORDERING INFORMATION
6.1 AVAILABLE PARTS
6.2 PART NUMBERING
Device Number:
4013B
Packa ge Material Codes:
P Plastic
Package Type Codes:
J J - Leaded Chip Carrier
Test Specifications:
C Commercial 0°C to +70°C
7.0 RELATED TECHNICAL PUBLICATIONS
PART NUMBER DESCRIPTION
AHA4013B-050 PJC 12.5 MBytes/sec Reed-Solomon Error Correction Device
AHA 4013 B- 050 P J C
Manufacturer Device
Number Revision
Level Speed
Designation Package
Material Package Type Test
Specification
PART NUMBER DESCRIPTION
PB4013B AHA Product Brief – AHA4013 12.5 MBytes/sec Reed-Solomon Error
Correction Device
PS4011C AHA Product Specification – AHA4011C 10 MBytes/s ec Reed-Solomon Er ror
Correction Device
PS4012B AHA P roduct Speci ficatio n – AHA4012B 1.5 MBytes/sec Reed-Solomon Error
Correction Device
ABRS03 AHA Application Brief – AHA4011 and AHA4012 Device Differences
ABRS04 AHA Application Brief – Reed-Solomon Evaluation Software Version 3.0
ABRS06 AHA Application Brief – AHA4011 and AHA4013 Device Differences
ABRS09 AHA Application Brief – AHA4013A and AHA4013B Device Differences
ABSTD1 AHA Application Brief – AHA Data Compression and Forward Error Correction
Standards
ANRS01 AHA Application Note – Pr imer: Re ed-S olomon Er ror Corr ecti on Codes ( ECC)
ANRS02 AHA Application Note – Interl eaving for Burst Erro r Correctio n
ANRS03 AHA Application Note – Reed-Solomon Evaluation Software Version 3.0
ANRS05 AHA Application Note – Serial I/O Interface to AHA4011/AHA4012
RSEVAL Reed-Solomon Evaluation Software Version 3.0 (Windows)
IESS-308,
Appendix F Concatenation of Reed-Solomon (RS) Outer Coding with the Existing Inner FEC
(Not available from AHA)
PS4013B-0600 Page 21 of 24
Advanced Hardware Architectures, Inc.
APPENDIX A
Table of Elements
BLOCK
SIZE ‘N’HEX
VALUE BLOCK
SIZE ‘N’HEX
VALUE BLOCK
SIZE ‘N’HEX
VALUE BLOCK
SIZE ‘N’HEX
VALUE
11223448
510 620 740 880
9871089119512ad
13 dd 14 3d 15 7a 16 f4
17 6f 18 de 19 3b 20 76
21 ec 22 5f 23 be 24 fb
25 71 26 e2 27 43 28 86
29 8b 30 91 31 a5 32 cd
33 1d 34 3a 35 74 36 e8
37 57 38 ae 39 db 40 31
41 62 42 c4 43 f 44 1e
45 3c 46 78 47 f0 48 67
49 ce 50 1b 51 36 52 6c
53 d8 54 37 55 6e 56 dc
57 3f 58 7e 59 fc 60 7f
61 fe 62 7b 63 f6 64 6b
65 d6 66 2b 67 56 68 ac
69 df 70 39 71 72 72 e4
73 4f 74 9e 75 bb 76 f1
77 65 78 ca 79 13 80 26
81 4c 82 98 83 b7 84 e9
85 55 86 aa 87 d3 88 21
89 42 90 84 91 8f 92 99
93 b5 94 ed 95 5d 96 ba
97 f3 98 61 99 c2 100 3
101 6 102 c 103 18 104 30
105 60 106 c0 107 7 108 e
109 1c 110 38 111 70 112 e0
113 47 114 8e 115 9b 116 b1
117 e5 118 4d 119 9a 120 b3
121 e1 122 45 123 8a 124 93
125 a1 126 c5 127 d 128 1a
129 34 130 68 131 d0 132 27
133 4e 134 9c 135 bf 136 f9
137 75 138 ea 139 53 140 a6
141 cb 142 11 143 22 144 44
145 88 146 97 147 a9 148 d5
149 2d 150 5a 151 b4 152 ef
153 59 154 b2 155 e3 156 41
157 82 158 83 159 81 160 85
161 8d 162 9d 163 bd 164 fd
165 7d 166 fa 167 73 168 e6
169 4b 170 96 171 ab 172 d1
173 25 174 4a 175 94 176 af
177 d9 178 35 179 6a 180 d4
181 2f 182 5e 183 bc 184 ff
185 79 186 f2 187 63 188 c6
Page 22 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
For exam ple , for a block si ze of 205 , the v alu e to be programed in Byte 1 of the Initi al iz at ion Regi ste r
is 0xc7.
/*This is a C progr am to g enerat e Table of Element s. Pas s a va lue of bloc k leng th, N i n deci mal to th is,
and obtain the Element value in hex.*/
int alpha(n)
int n;
{
int i,b,c;
c=01;
for (i =1; i< n;i++) {
b=c<<1;
if (b>0377)
b=b^0607;
c=b;
}
return c;
}
main()
{int i;
printf("Enter N--> ") ;
scanf("%d",&i);
if(i <1 || i>255)
printf("1<=N<=255");
elseprintf("\nN = %d\tALPHA = %2x\n\n", i, alpha(i));
}
189 b 190 16 191 2c 192 58
193 b0 194 e7 195 49 196 92
197 a3 198 c1 199 5 200 a
201 14 202 28 203 50 204 a0
205 c7 206 9 207 12 208 24
209 48 210 90 211 a7 212 c9
213 15 214 2a 215 54 216 a8
217 d7 218 29 219 52 220 a4
221 cf 222 19 223 32 224 64
225 c8 226 17 227 2e 228 5c
229 b8 230 f7 231 69 232 d2
233 23 234 46 235 8c 236 9f
237 b9 238 f5 239 6d 240 da
241 33 242 66 243 cc 244 1f
245 3e 246 7c 247 f8 248 77
249 ee 250 5b 251 b6 252 eb
253 51 254 a2 255 c3
BLOCK
SIZE ‘N’HEX
VALUE BLOCK
SIZE ‘N’HEX
VALUE BLOCK
SIZE ‘N’HEX
VALUE BLOCK
SIZE ‘N’HEX
VALUE
PS4013B-0600 Page 23 of 24
Advanced Hardware Architectures, Inc.
APPENDIX B
AHA4013B Data Rate Calculations in Continuous Operation
Assumptions and Equations:
1) 50 MHz Clock is used.
2) Input Rate (Ci) = Ou tput Rate (Co)
3) Latency =
4) Data Rate = 50 MHz/Ci clocks/byte
5) GOOD or BAD based on inequality equation:
(5)
6) GOOD or BAD based on inequality equation:
(6)
7) Check symbols are input into and output from the chip along with message symbols.
Note: The following tables show examples of Data Rates and Latencies for various block sizes. Other block sizes
are also possi ble.
CLOCKS
/BYTE NTMAXIMUM LATENCY DATA RATE
(MB/sec) EQUATION 5 EQUATION 6
CLOCKS µSECONDS
4 25 10 209 4.18 12.50 GOOD BAD
4 50 10 343 6.86 12.50 GOOD BAD
4 53 10 359 7.18 12.50 GOOD BAD
4 75 10 476 9.52 12.50 GOOD GOOD
4 100 10 609 12.16 12.50 GOOD GOOD
4 126 7 742 14.88 12.50 GOOD GOOD
4 194 8 1107 22.16 12.50 GOOD GOOD
4 208 8 1181 23.60 12.50 GOOD GOOD
4 219 9 1242 24.88 12.50 GOOD GOOD
4 200 10 1143 22.88 12.50 GOOD GOOD
4 225 10 1276 25.52 12.50 GOOD GOOD
4 250 10 1409 28.16 12.50 GOOD GOOD
4 255 10 1436 28.72 12.50 GOOD GOOD
CLOCKS
/BYTE NTMAXIMUM LATENCY DATA RATE
(MB/sec) EQUATION 5 EQUATION 6
CLOCKS µSECONDS
4 25 5 199 3.98 12.50 GOOD BAD
4 50 5 333 6.66 12.50 GOOD GOOD
4 75 5 466 9.36 12.50 GOOD GOOD
4 100 5 599 12.00 12.50 GOOD GOOD
4 125 5 733 14.64 12.50 GOOD GOOD
4 150 5 866 17.36 12.50 GOOD GOOD
4 175 5 999 20.00 12.50 GOOD GOOD
4 200 5 1133 22.64 12.50 GOOD GOOD
4 225 5 1266 25.36 12.50 GOOD GOOD
4 250 5 1399 28.00 12.50 GOOD GOOD
4 255 5 1426 28.56 12.50 GOOD GOOD
CiN1–()R60+()NCi
Ci1–
--------------
×++×
R60 NCm
Cm1–
----------------
×++
Ci
------------------------------------------------- N367≤+
N1–()Ci
×R48 NCi
Ci1–
--------------×NCm
Cm1–
----------------×++ +≥
Page 24 of 24 PS4013B-0600
Advanced Hardware Arc h itectur es, Inc.
CLOCKS
/BYTE NTMAXIMUM LATENCY DATA RATE
(MB/sec) EQUATION 5 EQUATION 6
CLOCKS µSECONDS
4 25 3 195 3.90 12.50 GOOD BAD
4 50 3 329 6.58 12.50 GOOD GOOD
4 75 3 462 9.28 12.50 GOOD GOOD
4 100 3 595 11.92 12.50 GOOD GOOD
4 125 3 729 14.56 12.50 GOOD GOOD
4 150 3 862 17.28 12.50 GOOD GOOD
4 175 3 995 19.92 12.50 GOOD GOOD
4 200 3 1129 22.56 12.50 GOOD GOOD
4 225 3 1262 25.28 12.50 GOOD GOOD
4 250 3 1395 27.92 12.50 GOOD GOOD
4 255 3 1422 28.48 12.50 GOOD GOOD
CLOCKS
/BYTE NTMAXIMUM LATENCY DATA RATE
(MB/sec) EQUATION 5 EQUATION 6
CLOCKS µSECONDS
4 25 1 191 3.82 12.50 GOOD BAD
4 50 1 325 6.50 12.50 GOOD GOOD
4 75 1 458 9.20 12.50 GOOD GOOD
4 100 1 591 11.84 12.50 GOOD GOOD
4 125 1 725 14.48 12.50 GOOD GOOD
4 150 1 858 17.20 12.50 GOOD GOOD
4 175 1 991 19.84 12.50 GOOD GOOD
4 200 1 1125 22.48 12.50 GOOD GOOD
4 225 1 1258 25.20 12.50 GOOD GOOD
4 250 1 1391 27.84 12.50 GOOD GOOD
4 255 1 1418 28.40 12.50 GOOD GOOD