ADC141S626CIMMX - Texas Instruments High-Performance Analog

ADC141S626

ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power

A/D Converter

Literature Number: SNAS434A

January 27, 2009

ADC141S626

14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power

A/D Converter

General Description

The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling

Analog-to-Digital (A/D) converter. The converter is based on

a successive-approximation register (SAR) architecture

where the differential nature of the analog inputs is main-

tained from the internal sample-and-hold circuits throughout

the A/D converter to provide excellent common-mode signal

rejection. The ADC141S626 features an external reference

that can be varied from 1.0V to VA. It also features a zero-

power track mode where the ADC is consuming the minimum

amount of supply current while the internal sampling capacitor

is tracking the applied analog input voltage.

The serial data output is binary 2's complement and is com-

patible with several standards, such as SPI™, QSPI™, MI-

CROWIRE™, and many common DSP serial interfaces. The

conversion result is clocked out by the serial clock input and

is the result of the conversion currently in progress; thus,

ADC141S626 has no latency.

The ADC141S626 may be operated with independent analog

(VA) and digital input/output (VIO) supplies. VA and VIO can

range from 2.7V to 5.5V and can be set independent of each

other. This allows a user to maximize performance and min-

imize power consumption by operating the analog portion of

the ADC at a VA of 5V while communicating with a 3V con-

troller on the digital side. With a 3V source, the power con-

sumption when operating at 200 kSPS is 2.0 mW. With a 5V

source, the power consumption when operating at 250 kSPS

is 4.8 mW. The power consumption drops down to 4 µW and

13 µW respectively when the ADC141S626 enters acquisition

(power-down) mode. The differential input, low power con-

sumption, and small size make the ADC141S626 ideal for

direct connection to bridge sensors and transducers in battery

operated systems or remote data acquisition applications.

Operation is guaranteed over the temperature range of

−40°C to +85°C and clock rates of 0.9 MHz to 4.5 MHz. The

ADC141S626 is available in a 10-lead MSOP package.

Features

■True Differential Inputs

■Guaranteed performance from 50 kSPS to 250 kSPS

■External Reference

■Zero-Power Track Mode

■Wide Input Common-Mode Voltage Range

■Operating Temperature Range of −40°C to +85°C

■SPI™/QSPI™/MICROWIRE™/DSP compatible Serial

Interface

Key Specifications

■Conversion Rate 50 kSPS to 250 kSPS

■INL ± 0.95 LSB (max)

■DNL ± 0.95 LSB (max)

■SNR 82 dBc (max)

■THD − 90 dBc (typ)

■ENOB 13.3 bits (min)

■Power Consumption

■— 200 kSPS, 3V 2.0 mW (typ)

— 250 kSPS, 5V 4.8 mW (typ)

— Power-Down, 3V 4 µW (typ)

— Power-Down, 5V 13 µW (typ)

Applications

■Automotive Navigation

■Portable Systems

■Medical Instruments

■Instrumentation and Control Systems

■Motor Control

■Direct Sensor Interface

Connection Diagram

30041305

TRI-STATE® is a trademark of National Semiconductor Corporation.

MICROWIRE™ is a trademark of National Semiconductor Corporation.

QSPI™ and SPI™ are trademarks of Motorola, Inc.

ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter

Ordering Information

Order Code Temperature Range Description Top Mark

ADC141S626CIMM −40°C to +85°C 10-Lead MSOP Package, 1000 Units Tape & Reel X94C

ADC141S626CIMMX −40°C to +85°C 10-Lead MSOP Package, 3500 Units Tape & Reel X94C

ADC141S626EB Evaluation Board

Block Diagram

30041302

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

1VREF

Voltage Reference Input. A voltage reference between 1V and VA must be applied to this

input. VREF must be decoupled to GND with a minimum ceramic capacitor value of

0.1 µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µFcapacitor is

recommended for enhanced performance.

2 +IN Non-Inverting Input. +IN is the positive analog input for the differential signal applied to

the ADC141S626.

3 −IN Inverting Input. −IN is the negative analog input for the differential signal applied to the

ADC141S626.

4 GND Ground. GND is the ground reference point for all signals applied to the ADC141S626.

5 GND Ground. GND is the ground reference point for all signals applied to the ADC141S626.

6 CS Chip Select Bar. CS must be active LOW during an SPI conversion, which begins on the

falling edge of CS. The ADC141S626 is in acquisition mode when CS is HIGH.

7DOUT

Serial Data Output. The conversion result is provided on DOUT. The serial data output

word is comprised of 2 null bits followed by 14 data bits (MSB first). During a conversion,

the data is output on the falling edges of SCLK and is valid on the subsequent rising

edges.

8 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.

9VIO

Digital Input/Output Power Supply Input. A voltage source between 2.7V and 5.5V must

be applied to this input. VIO must be decoupled to GND with a ceramic capacitor value of

0.1 µF in parallel with a bulk capacitor value of 1.0 µF to 10 µF.

10 VA

Analog Power Supply Input. A voltage source between 2.7V and 5.5V must be applied to

this input. VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in

parallel with a bulk capacitor value of 1.0 µF to 10 µF.

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ADC141S626

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage VA−0.3V to 6.5V

Digital I/O Supply Voltage VIO −0.3V to 6.5V

Voltage on Any Analog Input Pin to

GND −0.3V to (VA + 0.3V)

Voltage on Any Digital Input Pin to

GND −0.3V to (VIO + 0.3V)

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current (Note 3) ±50 mA

Power Consumption at TA = 25°C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

Charge Device Model

4000V

300V

1250V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40°C ≤ TA ≤ +85°C

Supply Voltage, VA+2.7V to +5.5V

Supply Voltage, VIO +2.7V to +5.5V

Reference Voltage, VREF 1.0V to VA

Analog Input Pins Voltage Range 0 to VA

Differential Analog Input Voltage −VREF to +VREF

Input Common-Mode Voltage, VCM See Figure 11 (Sect 2.3)

Digital Input Pins Voltage Range 0 to VIO

Clock Frequency 0.9 MHz to 4.5 MHz

Package Thermal Resistance

Package θJA

10-lead MSOP 240°C / W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications.

Refer to www.national.com/packaging. (Note 6)

ADC141S626 Converter Electrical Characteristics (Note 7)

The following specifications apply for VA = VIO = VREF = +2.7V to 5.5V and fSCLK = 0.9 to 3.6 MHz or VA = VIO = VREF = +4.5V to

5.5V and fSCLK = 3.6 to 4.5 MHz; fIN = 20 kHz and CL = 25 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to

TMAX; all other limits are at TA = 25°C.

Symbol Parameter Conditions Typical Limits Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 14 Bits

INL Integral Non-Linearity ±0.5 ±0.95 LSB (max)

DNL Differential Non-Linearity ±0.5 ±0.95 LSB (max)

OE Offset Error −1 ±5 LSB (max)

FSE Positive Full-Scale Error −3 ±7 LSB (max)

Negative Full-Scale Error 0.5 ±4 LSB (max)

GE Positive Gain Error −1.5 ±6 LSB (max)

Negative Gain Error 1.5 ±6 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio VA = VIO = VREF = +3V, −0.1 dBFS 81.9 80.1 dBc (min)

VA = VIO = VREF = +5V, −0.1 dBFS 84.2 82 dBc (min)

SNR Signal-to-Noise Ratio VA = VIO = VREF = +3V, −0.1 dBFS 82 80.2 dBc (min)

VA = VIO = VREF = +5V, −0.1 dBFS 84.3 82 dBc (min)

THD Total Harmonic Distortion VA = VIO = VREF = +3V, −0.1 dBFS −102 dBc

VA = VIO = VREF = +5V, −0.1 dBFS −102 dBc

SFDR Spurious-Free Dynamic Range VA = VIO = VREF = +3V, −0.1 dBFS 97 dBc

VA = VIO = VREF = +5V, −0.1 dBFS 101 dBc

ENOB Effective Number of Bits VA = VIO = VREF = +3V, −0.1 dBFS 13.3 13.0 bits (min)

VA = VIO = VREF = +5V, −0.1 dBFS 13.7 13.3 bits (min)

FPBW −3 dB Full Power Bandwidth Output at 70.7%FS with

FS Input

Differential

Input 26 MHz

Single-Ended

Input 22 MHz

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ADC141S626

Symbol Parameter Conditions Typical Limits Units

ANALOG INPUT CHARACTERISTICS

VIN Differential Input Range −VREF V (min)

+VREF V (max)

IDCL DC Leakage Current VIN = VREF or VIN = -VREF ±1 µA (max)

CINA Input Capacitance In Acquisition Mode 30 pF

In Conversion Mode 3 pF

CMRR Common Mode Rejection Ratio See the Specification Definitions for the

test condition 76 dB

DIGITAL INPUT CHARACTERISTICS

VIH Input High Voltage VIO = +2.7V to 5.5V 1.9 2.3 V (min)

VIL Input Low Voltage VIO = +2.7V to 5.5V 1.0 0.7 V (max)

IIN Input Current VIN = 0V or VA ±1 µA (max)

CIND Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA VA − 0.05 VA − 0.2 V (min)

ISOURCE = 1 mA VA − 0.16 V

VOL Output Low Voltage ISINK = 200 µA 0.01 0.4 V (max)

ISINK = 1 mA 0.05 V

IOZH, IOZL TRI-STATE Leakage Current Force 0V or VA ±1 µA (max)

COUT TRI-STATE Output Capacitance Force 0V or VA24pF (max)

Output Coding Binary 2'S Complement

POWER SUPPLY CHARACTERISTICS

VAAnalog Supply Voltage Range 2.7 V (min)

5.5 V (max)

VIO

Digital Input/Output Supply Voltage

Range (Note 9) 2.7 V (min)

5.5 V (max)

VREF Reference Voltage Range 1.0 V (min)

VAV (max)

IVA (Conv) Analog Supply Current, Conversion

Mode

fSCLK = 3.6 MHz, VA = 3V, fS = 200

kSPS, fIN = 20 kHz 540 760 µA (max)

fSCLK = 4.5 MHz, VA = 5V, fS = 250

kSPS, fIN = 20 kHz 740 970 µA (max)

IVIO

(Conv)

Digital I/O Supply Current, Conversion

Mode

fSCLK = 3.6 MHz, VA = 3V, fS = 200

kSPS, fIN = 20 kHz 90 190 µA (max)

fSCLK = 4.5 MHz, VA = 5V, fS = 250

kSPS, fIN = 20 kHz 170 260 µA (max)

IVREF

(Conv) Reference Current, Conversion Mode

fSCLK = 3.6 MHz, VA = 3V, fS = 200

kSPS, fIN = 20 kHz 25 60 µA (max)

fSCLK = 4.5 MHz, VA = 5V, fS = 250

kSPS, fIN = 20 kHz 45 80 µA (max)

IVA (PD) Analog Supply Current, Power Down

Mode (CS high)

fSCLK = 4.5 MHz, VA = 5V 8 µA

fSCLK = 0 (Note 8) 23µA (max)

IVIO (PD) Digital I/O Supply Current, Power Down

Mode (CS high)

fSCLK = 4.5 MHz, VA = 5V 3 µA

fSCLK = 0 (Note 8) 0.1 0.3 µA (max)

IVREF (PD) Reference Current, Power Down Mode

(CS high)

fSCLK = 4.5 MHz, VA = 5V 0.1 µA

fSCLK = 0 (Note 8) 0.1 0.2 µA (max)

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ADC141S626

Symbol Parameter Conditions Typical Limits Units

PWR

(Conv) Power Consumption, Conversion Mode

fSCLK = 3.6 MHz, fS = 200 kSPS, fIN = 20

kHz, VA = VIO = VREF = 3.0V 2.0 3.0 mW

fSCLK = 4.5 MHz, fS = 250 kSPS, fIN = 20

kHz, VA = VIO = VREF = 5.0V 4.8 6.5 mW

PWR

(PD)

Power Consumption, Power Down Mode

(CS high)

fSCLK = 0, VA = VIO = VREF = 3.0V

(Note 8) 34µW (max)

fSCLK = 0, VA = VIO = VREF = 5.0V

(Note 8) 13 17 µW (max)

PSRR Power Supply Rejection Ratio See the Specification Definitions for the

test condition −85 dB

AC ELECTRICAL CHARACTERISTICS

fSCLK Maximum Clock Frequency VA = VIO = VREF = +2.7V to 5.5V 4.8 4.5 MHz (min)

fSCLK Minimum Clock Frequency 0.9 MHz (max)

fSMaximum Sample Rate 250 kSPS (min)

tACQ Acquisition/Track Time 667 ns (min)

tCONV Conversion/Hold Time 15 SCLK cycles

tAD Aperture Delay See the Specification Definitions 6 ns

ADC141S626 Timing Specifications (Note 7)

The following specifications apply for VA = VIO = VREF= +2.7V to 5.5V and fSCLK = 0.9 to 4.5 MHz, CL = 25 pF, Boldface limits

apply for TA = TMIN to TMAX: all other limits TA = 25°C.

Symbol Parameter Conditions Typical Limits Units

tCSS CS Setup Time prior to an SCLK rising edge 36ns (min)

1/fSCLK - 3 1/fSCLK - 6 ns (max)

tDH DOUT Hold Time after an SCLK falling edge 10 6ns (min)

tDA DOUT Access Time after an SCLK falling edge 28 40 ns (max)

tDIS

DOUT Disable Time after the rising edge of CS

(Note 11) 10 20 ns (max)

tCS Minimum CS Pulse Width 5 20 ns (min)

tEN DOUT Enable Time after the falling edge of CS 32 51 ns (max)

tCH SCLK High Time 67 89 ns (min)

tCL SCLK Low Time 67 89 ns (min)

trDOUT Rise Time 7 ns

tfDOUT Fall Time 7 ns

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values

for maximum power dissipation listed above will be reached only when the ADC141S626 is operated in a severe fault condition (e.g. when input or output pins

are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge

device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality

Level).

Note 8: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 9: The value of VIO is independent of the value of VA. For example, VIO could be operating at 5V while VA is operating at 3V or VIO could be operating at 3V

while VA is operating at 5V.

Note 10: While the maximum sample rate is fSCLK/18, the actual sample rate may be lower than this by having the CS rate slower than fSCLK/18.

Note 11: tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit.

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ADC141S626

Timing Diagrams

30041301

FIGURE 1. ADC141S626 Single Conversion Timing Diagram

30041308

FIGURE 2. Timing Test Circuit

30041306

FIGURE 3. DOUT Rise and Fall Times

30041311

FIGURE 4. DOUT Hold and Access Times

30041310

FIGURE 5. Valid CS Assertion Times

30041312

FIGURE 6. Voltage Waveform for tDIS

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ADC141S626

Specification Definitions

APERTURE DELAY is the time between the first falling edge

of SCLK and the time when the input signal is sampled for

conversion.

COMMON MODE REJECTION RATIO (CMRR) is a measure

of how well in-phase signals common to both input pins are

rejected.

To calculate CMRR, the change in output offset is measured

while the common mode input voltage is changed from 2V to

3V.

CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)

CONVERSION TIME is the time required, after the input volt-

age is acquired, for the ADC to convert the input voltage to a

digital word.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital

waveform is high to the total time of one period. The specifi-

cation here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion or SINAD. ENOB is defined as (SINAD − 1.76) /

6.02 and says that the converter is equivalent to a perfect

ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It is the difference between Positive Full-

Scale Error and Negative Full-Scale Error and can be calcu-

lated as:

Gain Error = Positive Full-Scale Error − Negative Full-Scale

Error

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from ½ LSB

below the first code transition through ½ LSB above the last

code transition. The deviation of any given code from this

straight line is measured from the center of that code value.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC141S626 is guaranteed not

to have any missing codes.

NEGATIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions from negative full scale to the next code and −VREF + 1

LSB

NEGATIVE GAIN ERROR is the difference between the neg-

ative full-scale error and the offset error.

OFFSET ERROR is the difference between the differential

input voltage at which the output code transitions from code

0000h to 0001h and 1 LSB.

POSITIVE FULL-SCALE ERROR is the difference between

the differential input voltage at which the output code transi-

tions to positive full scale and VREF minus 1 LSB.

POSITIVE GAIN ERROR is the difference between the pos-

itive full-scale error and the offset error.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well a change in the analog supply voltage is rejected.

PSRR is calculated from the ratio of the change in offset error

for a given change in supply voltage, expressed in dB. For the

ADC141S626, VA is changed from 4.5V to 5.5V.

PSRR = 20 LOG (ΔOutput Offset / ΔVA)

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below one-half the sampling frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the desired signal amplitude

to the amplitude of the peak spurious spectral component be-

low one-half the sampling frequency, where a spurious spec-

tral component is any signal present in the output spectrum

that is not present at the input and may or may not be a har-

monic.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the

rms total of the first five harmonic components at the output

to the rms level of the input signal frequency as seen at the

output, expressed in dB. THD is calculated as

where Af1 is the RMS power of the input frequency at the out-

put and Af2 through Af6 are the RMS power in the first 5

harmonic frequencies.

THROUGHPUT TIME is the minimum time required between

the start of two successive conversion.

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ADC141S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS,

TA = +25°C, and fIN = 20 kHz unless otherwise stated.

DNL - 250 kSPS

30041321

INL - 250 kSPS

30041322

DNL vs. VA

30041323

INL vs. VA

30041324

DNL vs. VREF

30041318

INL vs. VREF

30041319

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ADC141S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS,

TA = +25°C, and fIN = 20 kHz unless otherwise stated.

DNL vs. SCLK FREQUENCY

30041325

INL vs. SCLK FREQUENCY

30041326

DNL vs. TEMPERATURE

30041329

INL vs. TEMPERATURE

30041330

SINAD vs. VA

30041333

THD vs. VA

30041332

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ADC141S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS,

TA = +25°C, and fIN = 20 kHz unless otherwise stated.

SINAD vs. VREF

30041337

THD vs. VREF

30041336

SINAD vs. SCLK FREQUENCY

30041341

THD vs. SCLK FREQUENCY

30041340

SINAD vs. INPUT FREQUENCY

30041349

THD vs. INPUT FREQUENCY

30041348

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ADC141S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS,

TA = +25°C, and fIN = 20 kHz unless otherwise stated.

SINAD vs. TEMPERATURE

30041372

THD vs. TEMPERATURE

30041371

VA CURRENT vs. VA

30041335

VA CURRENT vs. SCLK FREQUENCY

30041355

VA CURRENT vs. TEMPERATURE

30041354

VREF CURRENT vs. VREF

30041334

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ADC141S626

Typical Performance Characteristics VA = VIO = VREF = +5V, fSCLK = 4.5 MHz, fSAMPLE = 250 kSPS,

TA = +25°C, and fIN = 20 kHz unless otherwise stated.

VREF CURRENT vs. SCLK FREQUENCY

30041352

VREF CURRENT vs. TEMPERATURE

30041351

VIO CURRENT vs. VIO

30041344

VIO CURRENT vs. SCLK FREQUENCY

30041342

VIO CURRENT vs. TEMPERATURE

30041343

SPECTRAL RESPONSE - 250 kSPS

30041314

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ADC141S626

Functional Description

The ADC141S626 is a 14-bit, 50 kSPS to 250 kSPS sampling

Analog-to-Digital (A/D) converter. The converter uses a suc-

cessive approximation register (SAR) architecture based up-

on capacitive redistribution containing an inherent sample-

and-hold function. The differential nature of the analog inputs

is maintained from the internal sample-and-hold circuits

throughout the A/D converter to provide excellent common-

mode signal rejection.

The ADC141S626 operates from independent analog and

digital supplies. The analog supply (VA) can range from 2.7V

to 5.5V and the digital input/output supply (VIO) can range

from 2.7V to 5.5V. The ADC141S626 utilizes an external ref-

erence (VREF), which can be any voltage between 1V and

VA. The value of VREF determines the range of the analog in-

put, while the reference input current (IREF) depends upon the

conversion rate.

The analog input is presented to two input pins: +IN and –IN.

Upon initiation of a conversion, the differential input at these

pins is sampled on the internal capacitor array. The inputs are

disconnected from the internal circuitry while a conversion is

in progress. The ADC141S626 features a zero-power track

mode where the ADC is consuming the minimum amount of

supply current while the internal sampling capacitor is track-

ing the applied analog input voltage. Zero-power track mode

is exercised by bringing chip select bar (CS) high or low after

the conversion is complete (after the 16th falling edge of the

serial clock).

The ADC141S626 communicates with other devices via Se-

rial Peripheral Interface (SPI™) , a synchronous serial inter-

face that operates using three pins: chip select bar (CS), serial

clock (SCLK), and serial data out (DOUT). The external SCLK

controls data transfer and serves as the conversion clock. The

duty cycle of SCLK is essentially unimportant, provided the

minimum clock high and low times are met. The minimum

SCLK frequency is set by internal capacitor leakage. Each

conversion requires 18 SCLK cycles to complete. If less than

14 bits of conversion data are required, CS can be brought

high at any point during the conversion. This procedure of

terminating a conversion prior to completion is commonly re-

ferred to as short cycling.

The digital conversion result is clocked out by the SCLK input

and is provided serially, most significant bit (MSB) first, at the

DOUT pin. The digital data that is provided at the DOUT pin is

that of the conversion currently in progress and thus there is

no pipe line delay.

1.0 REFERENCE INPUT (VREF)

The externally supplied reference voltage (VREF) sets the

analog input range. The ADC141S626 will operate with

VREF in the range of 1V to VA.

Operation with VREF below 1V is also possible with slightly

diminished performance. As VREF is reduced, the range of

acceptable analog input voltages is reduced. Assuming a

proper common-mode input voltage (VCM), the differential

peak-to-peak input range is limited to (2 x VREF). See Section

2.3 for more details.

Reducing VREF also reduces the size of the least significant

bit (LSB). The size of one LSB is equal to [(2 x VREF) / 2n],

which is 16,384 where n is 14 bits. When the LSB size goes

below the noise floor of the ADC141S626, the noise will span

an increasing number of codes and overall performance will

suffer. For example, dynamic signals will have their SNR de-

grade, while D.C. measurements will have their code uncer-

tainty increase. Since the noise is Gaussian in nature, the

effects of this noise can be reduced by averaging the results

of a number of consecutive conversions.

Additionally, since offset and gain errors are specified in LSB,

any offset and/or gain errors inherent in the A/D converter will

increase in terms of LSB size as VREF is reduced.

VREF and analog inputs (+IN and -IN) are connected to the

capacitor array through a switch matrix when the input is

sampled. Hence, IREF, I+IN, and I-IN are a series of transient

spikes that occur at a frequency dependent on the operating

sample rate of the ADC141S626.

IREF changes only slightly with temperature. See the curves,

“Reference Current vs. SCLK Frequency” and “Reference

Current vs. Temperature” in the Typical Performance Curves

section for additional details.

2.0 ANALOG SIGNAL INPUTS

The ADC141S626 has a differential input where the effective

input voltage that is digitized is (+IN) − (−IN). By using this

differential input, small signals common to both inputs are re-

jected. As shown in Figure 7, noise is immune at low frequen-

cies where the common-mode rejection ratio (CMRR) is 90

dB. As the frequency increases to 1 MHz, the CMRR rolls off

to 40 dB . In general, operation with a fully differential input

signal or voltage will provide better performance than with a

single-ended input. However, if desired, the ADC141S626

can be presented with a single-ended input.

30041375

FIGURE 7. Analog Input CMRR vs. Frequency

The current required to recharge the input sampling capacitor

will cause voltage spikes at +IN and −IN. Do not try to filter

out these noise spikes. Rather, ensure that the transient set-

tles out during the acquisition period.

2.1 Differential Input Operation

As shown in Figure 8 for a fully differential input signal, a pos-

itive full scale output code (01 1111 1111 1111b or 1FFFh or

8191d) will be obtained when (+IN) − (−IN) is greater than or

equal to (VREF − 1 LSB). A negative full scale code (10 0000

0000 0000b or 2000h or -8192d) will be obtained when (+IN)

− (−IN) is less than or equal to (−VREF + 1 LSB). This ignores

gain, offset and linearity errors, which will affect the exact dif-

ferential input voltage that will determine any given output

code. Both inputs should be biased at a common mode volt-

13 www.national.com

ADC141S626

age (VCM), which will be thoroughly discussed in Section 2.3.

Figure 9 shows the ADC141S626 being driven by a full-scale

differential source.

30041399

FIGURE 8. ADC Output vs. Input for a Differential Input

Operation

30041380

FIGURE 9. Differential Input

2.2 Single-Ended Input Operation

For single-ended operation, the non-inverting input (+IN) of

the ADC141S626 can be driven with a signal that has a peak-

to-peak range that is equal to or less than (2 x VREF). The

inverting input (−IN) should be biased at a stable VCM that is

halfway between these maximum and minimum values. In

order to utilize the entire dynamic range of the

ADC141S626, VREF is limited to VA / 2. This allows +IN a

maximum swing range of ground to VA. Figure 10 shows the

ADC141S626 being driven by a full-scale single-ended

source.

30041381

FIGURE 10. Single-Ended Input

Since the design of the ADC141S626 is optimized for a dif-

ferential input, the performance degrades slightly when driven

with a single-ended input. Linearity characteristics such as

INL and DNL typically degrade by 0.1 LSB and dynamic char-

acteristics such as SINAD typically degrade by 2 dB. Note that

single-ended operation should only be used if the perfor-

mance degradation (compared with differential operation) is

acceptable.

2.3 Input Common Mode Voltage

The allowable input common mode voltage (VCM) range de-

pends upon VA and VREF used for the ADC141S626. The

ranges of VCM are depicted in Figure 11 and Figure 12. Note

that these figures only apply to a VA of 5V. Equations for cal-

culating the minimum and maximum VCM for differential and

single-ended operations are shown in Table 1.

30041361

FIGURE 11. VCM range for Differential Input operation

30041362

FIGURE 12. VCM range for single-ended operation

TABLE 1. Allowable VCM Range

Input Signal Minimum VCM Maximum VCM

Differential VREF / 2 VA − VREF / 2

Single-Ended VREF VA − VREF

www.national.com 14

ADC141S626

3.0 SERIAL DIGITAL INTERFACE

The ADC141S626 communicates via a synchronous 3-wire

serial interface as shown in Figure 1 or re-shown in Figure

13 for convenience. CS, chip select bar, initiates conversions

and frames the serial data transfers. SCLK (serial clock) con-

trols both the conversion process and the timing of serial data.

DOUT is the serial data output pin, where a conversion result

is sent as a serial data stream, MSB first.

A serial frame is initiated on the falling edge of CS and ends

on the rising edge of CS. The ADC141S626's DOUT pin is in

a high impedance state when CS is high and is active when

CS is low; thus. CS acts as an output enable.

The ADC141S626 samples the differential input upon the as-

sertion of CS. Assertion is defined as bringing the CS pin to

a logic low state. For the first 15 periods of the SCLK following

the assertion of CS, the ADC141S626 is converting the ana-

log input voltage. On the 16th falling edge of SCLK, the

ADC141S626 enters acquisition (tACQ) mode. For the next

three periods of SCLK, the ADC141S626 is operating in ac-

quisition mode where the ADC input is tracking the analog

input signal applied across +IN and -IN. During acquisition

mode, the ADC141S626 is consuming a minimal amount of

power.

The ADC141S626 can enter conversion mode (tCONV) under

three different conditions. The first condition involves CS go-

ing low (asserted) with SCLK high. In this case, the

ADC141S626 enters conversion mode on the first falling edge

of SCLK after CS is asserted. In the second condition, CS

goes low with SCLK low. Under this condition, the

ADC141S626 automatically enters conversion mode and the

falling edge of CS is seen as the first falling edge of SCLK. In

the third condition, CS and SCLK go low simultaneously and

the ADC141S626 enters conversion mode. While there is no

timing restriction with respect to the falling edges of CS and

SCLK, there is a minimum and maximum setup time require-

ments for the falling edge of CS with respect to the rising edge

of SCLK. See Figure 5 in the Timing Diagram section for more

information.

3.1 CS Input

The CS (chip select bar) input is active low and is TTL and

CMOS compatible. The ADC141S626 enters conversion

mode when CS is asserted and the SCLK pin is in a logic low

state. When CS is high, the ADC141S626 is always in acqui-

sition mode and thus consuming the minimum amount of

power. Since CS must be asserted to begin a conversion, the

sample rate of the ADC141S626 is equal to the assertion rate

of CS.

Proper operation requires that the fall of CS not occur simul-

taneously with a rising edge of SCLK. If the fall of CS occurs

during the rising edge of SCLK, the data might be clocked out

one bit early. Whether or not the data is clocked out early

depends upon how close the CS transition is to the SCLK

transition, the device temperature, and the characteristics of

the individual device. To ensure that the MSB is always

clocked out at a given time (the 3rd falling edge of SCLK), it is

essential that the fall of CS always meet the timing require-

ment specified in the Timing Specification table.

3.2 SCLK Input

The SCLK (serial clock) is used as the conversion clock to

shift out the conversion result. SCLK is TTL and CMOS com-

patible. Internal settling time requirements limit the maximum

clock frequency while internal capacitor leakage limits the

minimum clock frequency. The ADC141S626 offers guaran-

teed performance with the clock rates indicated in the elec-

trical table.

The ADC141S626 enters acquisition mode on the 16th falling

edge of SCLK during a conversion frame. Assuming that the

LSB is clocked into a controller on the 16th rising edge of

SCLK, there is a minimum acquisition time period that must

be met before a new conversion frame can begin. Other than

the 16th rising edge of SCLK that was used to latch the LSB

into a controller, there is no requirement for the SCLK to tran-

sition during acquisition mode. Therefore, it is acceptable to

idle SCLK after the LSB has been latched into the controller.

3.3 Data Output

The data output format of the ADC141S626 is two’s comple-

ment as shown in Figure 8. This figure indicates the ideal

output code for a given input voltage and does not include the

effects of offset, gain error, linearity errors, or noise. Each

data output bit is output on the falling edges of SCLK. The

1st and 2nd SCLK falling edges clock out leading zeros while

the 3rd to 16th SCLK falling edges clock out the conversion

result, MSB first.

While most receiving systems will capture the digital output

bits on the rising edges of SCLK, the falling edges of SCLK

may be used to capture the conversion result if the minimum

hold time for DOUT is acceptable. See Figure 4 for DOUT hold

(tDH) and access (tDA) times.

DOUT is enabled on the falling edge of CS and disabled on the

rising edge of CS. If CS is raised prior to the 16th falling edge

of SCLK, the current conversion is aborted and DOUT will go

into its high impedance state. A new conversion will begin

when CS is driven LOW.

30041301

FIGURE 13. ADC141S626 Single Conversion Timing Diagram

15 www.national.com

ADC141S626

Applications Information

OPERATING CONDITIONS

We recommend that the following conditions be observed for

operation of the ADC141S626:

−40°C ≤ TA ≤ +85°C

+2.7V ≤ VA ≤ +5.5V

+2.7V ≤ VIO ≤ +5.5V

1V ≤ VREF ≤ VA

0.9 MHz ≤ fSCLK ≤ 4.5 MHz

VCM: See Section 2.3

4.0 POWER CONSUMPTION

The architecture, design, and fabrication process allow the

ADC141S626 to operate at conversion rates up to 250 kSPS

while consuming very little power. The ADC141S626 con-

sumes the least amount of power while operating in acquisi-

tion (power-down) mode. For applications where power

consumption is critical, the ADC141S626 should be operated

in acquisition mode as often as the application will tolerate.

To further reduce power consumption, stop the SCLK while

CS is high.

4.1 Short Cycling

Short cycling refers to the process of halting a conversion af-

ter the last needed bit is outputted. Short cycling can be used

to lower the power consumption in those applications that do

not need a full 14-bit resolution, or where an analog signal is

being monitored until some condition occurs. In some circum-

stances, the conversion could be terminated after the first few

bits. This will lower power consumption in the converter since

the ADC141S626 spends more time in acquisition mode and

less time in conversion mode.

Short cycling is accomplished by pulling CS high after the last

required bit is received from the ADC141S626 output. This is

possible because the ADC141S626 places the latest con-

verted data bit on DOUT as it is generated. If only 10-bits of the

conversion result are needed, for example, the conversion

can be terminated by pulling CS high after the 10th bit has

been clocked out.

4.2 Burst Mode Operation

Normal operation of the ADC141S626 requires the SCLK fre-

quency to be 18 times the sample rate and the CS rate to be

the same as the sample rate. However, in order to minimize

power consumption in applications requiring sample rates be-

low 250 kSPS, the ADC141S626 should be run with an SCLK

frequency of 4.5 MHz and a CS rate as slow as the system

requires. When this is accomplished, the ADC141S626 is op-

erating in burst mode. The ADC141S626 enters into acquisi-

tion mode at the end of each conversion, minimizing power

consumption. This causes the converter to spend the longest

possible time in acquisition mode. Since power consumption

scales directly with conversion rate, minimizing power con-

sumption requires determining the lowest conversion rate that

will satisfy the requirements of the system.

5.0 PCB LAYOUT AND CIRCUIT CONSIDERATIONS

For best performance, care should be taken with the physical

layout of the printed circuit board. This is especially true with

a low VREF or when the conversion rate is high. At high clock

rates there is less time for settling, so it is important that any

noise settles out before the conversion begins.

5.1 Analog and Digital Power Supplies

Any ADC architecture is sensitive to spikes on the power sup-

ply, reference, and ground pins. These spikes may originate

from switching power supplies, digital logic, high power de-

vices, and other sources. Power to the ADC141S626 should

be clean and well bypassed. A 0.1 µF ceramic bypass ca-

pacitor and a 1 µF to 10 µF capacitor should be used to

bypass the ADC141S626 supply, with the 0.1 µF capacitor

placed as close to the ADC141S626 package as possible.

Since the ADC141S626 has both the VA and VIO pins, the user

has three options on how to connect these pins. The first op-

tion is to tie VA and VIO together and power them with the same

power supply. This is the most cost effective way of powering

the ADC141S626 but is also the least ideal. As stated previ-

ously, noise from VIO can couple into VA and adversely affect

performance. The other two options involve the user powering

VA and VIO with separate supply voltages. These supply volt-

ages can have the same amplitude or they can be different.

They may be set independent of each other to any value be-

tween 2.7V and 5.5V.

Best performance will typically be achieved with VA operating

at 5V and VIO at 3V. Operating VA at 5V offers the best linearity

and dynamic performance when VREF is also set to 5V; while

operating VIO at 3V reduces the power consumption of the

digital logic. Operating the digital interface at 3V also has the

added benefit of decreasing the noise created by charging

and discharging the capacitance of the digital interface pins.

5.2 Voltage Reference

The reference source must have a low output impedance and

needs to be bypassed with a minimum capacitor value of 0.1

µF. A larger capacitor value of 1 µF to 10 µF placed in parallel

with the 0.1 µF is preferred. While the ADC141S626 draws

very little current from the reference on average, there are

higher instantaneous current spikes at the reference.

VREF of the ADC141S626, like all A/D converters, does not

reject noise or voltage variations. Keep this in mind if VREF is

derived from the power supply. Any noise and/or ripple from

the supply that is not rejected by the external reference cir-

cuitry will appear in the digital results. The use of an active

reference source is recommended. The LM4040 and LM4050

shunt reference families and the LM4132 and LM4140 series

reference families are excellent choices for a reference

source.

5.3 PCB Layout

Capacitive coupling between the noisy digital circuitry and the

sensitive analog circuitry can lead to poor performance. The

solution is to keep the analog circuitry separated from the

digital circuitry and the clock line as short as possible. Digital

circuits create substantial supply and ground current tran-

sients. The logic noise generated could have significant im-

pact upon system noise performance. To avoid performance

degradation of the ADC141S626 due to supply noise, avoid

using the same supply for the VA and VREF of the

ADC141S626 that is used for digital circuitry on the board.

Generally, analog and digital lines should cross each other at

90° to avoid crosstalk. However, to maximize accuracy in high

resolution systems, avoid crossing analog and digital lines al-

together. It is important to keep clock lines as short as possi-

ble and isolated from ALL other lines, including other digital

lines. In addition, the clock line should also be treated as a

transmission line and be properly terminated. The analog in-

put should be isolated from noisy signal traces to avoid cou-

pling of spurious signals into the input. Any external

component (e.g., a filter capacitor) connected between the

www.national.com 16

ADC141S626

converter's input pins and ground or to the reference input pin

and ground should be connected to a very clean point in the

ground plane.

A single, uniform ground plane and the use of split power

planes are recommended. The power planes should be lo-

cated within the same board layer. All analog circuitry (input

amplifiers, filters, reference components, etc.) should be

placed over the analog power plane. All digital circuitry should

be placed over the digital power plane. Furthermore, the GND

pins on the ADC141S626 and all the components in the ref-

erence circuitry and input signal chain that are connected to

ground should be connected to the ground plane at a quiet

point. Avoid connecting these points too close to the ground

point of a microprocessor, microcontroller, digital signal pro-

cessor, or other high power digital device.

6.0 APPLICATION CIRCUITS

The following figures are examples of the ADC141S626 in

typical application circuits. These circuits are basic and will

generally require modification for specific circumstances.

6.1 Data Acquisition

Figure 14 shows a typical connection diagram for the

ADC141S626 operating at VA of +5V. VREF is connected to a

4.1V shunt reference, the LM4040-4.1, to define the analog

input range of the ADC141S626 independent of supply vari-

ation on the +5V supply line. The VREF pin should be de-

coupled to the ground plane by a 0.1 µF ceramic capacitor

and a tantalum capacitor of 10 µF. It is important that the 0.1

µF capacitor be placed as close as possible to the VREF pin

while the placement of the tantalum capacitor is less critical.

It is also recommended that the VA and VIO pins of the

ADC141S626 be de-coupled to ground by a 0.1 µF ceramic

capacitor in parallel with a 10 µF tantalum capacitor.

30041363

FIGURE 14. Low cost, low power Data Acquisition System

6.2 Bridge Sensor Application

Figure 15 shows an example of interfacing a bridge sensor to

the ADC141S626. The application assumes that the bridge

sensor requires buffering and amplification to fully utilize the

dynamic range of the ADC and thus optimize the performance

of the entire signal path. The amplification stage consists of

the LMP7702, a dual precision amplifier, and some gain set-

ting passive components. The amplification stage offers the

benefit of high input impedance and high amplification capa-

bility. On the other hand, it offers no common-mode rejection

of common-mode noise or DC-voltage coming from the bridge

sensor.

The DAC081S101, a digital-to-analog converter (DAC), is

used to bias the bridge sensor. The DAC provides a mean for

dynamically adjusting the gain of the bridge sensor relative to

actual maximum and minimum output conditions. Another op-

tion for biasing the bridge sensor would be powering it from

the same +5V power supply voltage as the VA pin on the AD-

C141S626. This option has the benefit of providing the ideal

common-mode input voltage for the ADC141S626 while

keeping design complexity and cost to a minimum. However,

any fluctuation in the +5V supply will still be visible in the con-

verted result. The LM4132-4.1, a 4.1V series reference, is

used as the reference voltage in the application. The

ADC141S626, DAC081S101, and the LM4132-4.1 are all

powered from the same +5V voltage source.

17 www.national.com

ADC141S626

30041366

FIGURE 15. Interfacing the ADC141S626 to a Bridge Sensor

6.3 Current Sensing Application

Figure 16 shows an example of interfacing a current trans-

ducer to the ADC141S626. The current transducer converts

an input current into a voltage that is converted by the ADC.

Since the output voltage of the current transducer is single-

ended and centered around a common-mode voltage (VCM)

of 2.5V, the ADC141S626 is configured with the output of the

transducer driving the non-inverting input and VCM of the

transducer driving the inverting input. The output of the trans-

ducer has an output range of ±2V around VCM of 2.5V. As a

result, a series reference voltage of 2.0V is connected to the

ADC141S626. This will allow all of the codes of the

ADC141S626 to be available for the application. This config-

uration of the ADC141S626 is referred to as a single-ended

application of a differential ADC. All of the elements in the

application are conveniently powered by the same +5V power

supply, keeping circuit complexity and cost to a minimum.

30041338

FIGURE 16. Interfacing the ADC141S626 to a Current Transducer

www.national.com 18

ADC141S626

Physical Dimensions inches (millimeters) unless otherwise noted

10-Lead MSOP

Order Number ADC141S626CIMM

NS Package Number MUB10A

19 www.national.com

ADC141S626

Notes

ADC141S626 14-Bit, 50 kSPS to 250 kSPS, Differential Input, Micro Power A/D Converter

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