8 Megabit High Speed CMOS SRAM
DPS1MX8MKN3-A
DESCRIPTION:
The DPS1MX8MKN3-A High Speed SRAM
‘’STACK’’ devices are a revolutionary new memory
subsystem using Dense-Pac Microsystems’ ceramic
Stackable Leadless Chip Carriers (SLCC) mounted
on a co-fired ceramic substrate having side-brazed
leads. The device packs 8-Megabits of low-power
CMOS static RAM in a 600-mil-wide, 32-pin
dual-in-line package.
The DPS1MX8MKN3-A STACK devices contain
two 512K x 8 SRAM die, each packaged in a
hermetically sealed SLCC, making the devices
suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Stack’’ family of devices offer
a higher board density of memory than available
with conventional through-hole, surface mount or
hybrid techniques.
FEATURES:
•Organizations Available: 1Meg x 8
•Access Times: 20*, 25, 30, 35, 45ns
•Fully Static Operation
- No clock or refresh required
•Single +5V Power Supply, ±10% Tolerance
•TTL Compatible
•Common Data Inputs and Outputs
•Low Data Retention Voltage: 2.0V min.
•Package Available: 32 Pin DIP
*Commercial and Industrial Grade only.
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
PIN NAMES
A0 - A18 Address
I/O0 - I/O7Data Input / Output
CE0, CE1Low Chip Enables
WEWrite Enable
VDD Power (+5.0V)
VSS Ground
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DC OPERATING CHARACTERISTICS: Over Operating Ranges
SymbolCharacteristicsTest ConditionTyp.
(†)CIM/BUnit
Min.Max.Min.Max.Min.Max.
IINInput
Leakage CurrentVIN = 0V to VDD - -10 +10 -10 +10 -10 +10 µA
IOUTOutput
Leakage CurrentVI/O = 0V to VDD ,
CE = VIH or WE = VIL- -20 +20 -20 +20 -20 +20 µA
ICC Operating
Supply CurrentCycle = min., Duty = 100%,
IOUT = 0mA145 230 240 240 mA
ISB1Full Standby
Supply CurrentVIN ≥ VDD -0.2V or
VIN ≤ VSS +0.2V2 20 20 30 mA
ISB2Standby Current (TTL)CE = VIH40 120 120 120 mA
IDR3Data Retention
Supply Current (3.0V)VDR = 3V, CE ≥ VDR -0.2V300 1000 2000 4000 µA
IDR2Data Retention
Supply Current (2.0V)VDR = 2V, CE ≥ VDR -0.2V200 600 1600 360 µA
VOLOutput LOW VoltageIOL = 8.0mA-0.4 0.4 0.4V
VOHOutput HIGH VoltageIOH = -4.0mA-2.4 2.4 2.4V
† Typical measurement made at +25°C, Cycle = min., VDD = 5.0V.
TRUTH TABLE
ModeCEWEI/O PinSupply
Current
Not SelectedHXHIGH-ZStandby
ReadLHDOUTActive
WriteL L DINActive
H = HIGH L = LOW X = Don’t Care
ABSOLUTE MAXIMUM RATING3
SymbolParameterMax.Unit
TSTCStorage Temperature-65 to +150 ºC
TBIASTemperature Under Bias-55 to +125 ºC
VDD Supply Voltage1-0.5 to +7.0V
VI/OInput/Output Voltage1-0.5 to VDD +0.5V
CAPACITANCE4: TA = +25ºC, F = 1.0MHz
SymbolParameterMax.UnitCondition
CADR Address Input18
pFVIN2 = 0V
CCEChip Enable12
CWEWrite Enable18
CI/OData Input/Output22
DC OUTPUT CHARACTERISTICS
SymbolParameterConditionsMin.Max.Unit
VOHHIGH VoltageIOH= -4mA2.4V
VOLLOW VoltageIOL=8mA0.4V
RECOMMENDED OPERATING RANGE 3
SymbolCharacteristicMin.Typ.Max.Unit
VDD Supply Voltage4.5 5.0 5.5V
VIHInput HIGH Voltage2.2VDD+0.3V
VILInput LOW Voltage-0.520.8V
TAOperating
Temperature
M/B-55 +25 +125 ºC
I-40 +25 +85
C-0+25 +70
AC TEST CONDITIONS
Input Pulse Levels0V to 3.0V
Input Pulse Rise and Fall Times5ns*
Input and Output Timing Reference Levels1.5V
OUTPUT LOAD
LoadCLParametric Measured
1 100pFexcept tLZ, tHZ and tWHZ
2 5pFtLZ, tHZ and tWHZ
Figure 1. Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
255Ω
CL*
DOUT
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Data Retention AC Characteristics 8
SymbolParameterTest ConditionMin.Typ.Max.Unit
VDR VDD for Data RetentionCE ≥ VDR -0.2V2.0- - V
VCDR Chip Disable to Data
Retention TimeSee Data Retention Waveform0- - ns
tROperating Recovery TimeSee Data Retention Waveform5- - ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over Operating Ranges
No.SymbolParameter20ns*25ns30ns35ns45nsUnit
Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.
1tRCRead Cycle Time20 25 30 35 45 ns
2tAA Address Cycle Time20 25 30 35 45 ns
3tCOChip Enable Output Valid20 25 30 35 45 ns
4tCLZChip Enable to Output in LOW-Z 4, 633333ns
5tCHZChip Enable to Output in HIGH-Z 4, 58 10 15 20 25 ns
6tOHOutput Hold from Address Change45555ns
AC OPERATING CONDITION AND CHARACTERISTIC READ CYCLE: Over Operating Ranges 6, 7
No.SymbolParameter20ns*25ns30ns35ns45nsUnit
Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.
7tWCWrite Cycle Time20 25 30 35 45 ns
8tAWAddress Valid to End of Write13 15 20 25 35 ns
9tCWChip Enable to End of Write13 15 20 25 35 ns
10 tASAddress Setup Time ** 00000ns
11 tWPWrite Pulse Width13 15 20 25 35 ns
12 tWRWrite Recovery Time00000ns
13 tWHZWrite Enable to Output in HIGH-Z 4, 50 8 0 10 0 12 0 15 0 20 ns
14 tDWData to Write Time Overlap9 10 12 15 20 ns
15 tDHData Hold from Write Time00000ns
16 tOWOutput Active from End of Write33333ns
* Available in Commercial and Industrial Grade Only.
** Valid for both Read and Write Cycles.
DATA RETENTION WAVEFORM: CE Controlled.
VDD
4.5V
2.3V
VDR1
CE
0V
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WRITE CYCLE 1: CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
READ CYCLE
ADDRESS
CE
DATA I/O
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WRITE CYCLE 2: WE Controlled. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTE:
1.All voltages are with respect to VSS.
2.-2.0V min. for pulse width less than 20ns (VIL min. = -0.5V
at DC level).
3.Stresses greater than those under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4.This parameter is guaranteed and not 100% tested.
5.Transition is measured at the point of ±500mV from steady
state voltage.
6.When CE is LOW and WE is HIGH, I/O pins are in the
output state, and input signals of opposite phase to the
outputs must not be applied.
7.The outputs are in a high impedance state when WE is
LOW.
8.CE and WE can initiate and terminate WRITE Cycle.
WAVEFORM KEY
Data ValidTransition fromTransition fromData Undefined
HIGH to LOWLOW to HIGHor Don’t Care
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* Customer to be notified of changes to the die.
ORDERING INFORMATION
MECHANICAL DRAWING
Dense-Pac Microsystems, Inc.
7321 Lincoln Way, Garden Grove, California 92841-1431
(714) 898-0007 u (800) 642-4477 u FAX: (714) 897-1772 u http://www.dense-pac.com
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