FUJITSU SEMICONDUCTOR DATA SHEET DS05-13103-2E Memory FRAM CMOS 1 M Bit (128 K x 8) MB85R1001 DESCRIPTIONS The MB85R1001 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 131,072 words x 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Unlike SRAM, MB85R1001 is able to retain data without back-up battery. The memory cells used for the MB85R1001 has improved at least 1010 times of read/write access, significantly outperforming FLASH memory and E2PROM in endurance. The MB85R1001 used a pseudo - SRAM interface compatible with conventional asynchronous SRAM. FEATURES * * * * * Bit configuration : 131,072 words x 8bits Read/write endurance : 1010 times Operating power supply voltage : 3.0 V to 3.6 V Operating temperature range : -20 C to +85 C 48-pin, TSOP (1) plastic package PACKAGE 48-pin plastic TSOP(1) (FPT-48P-M25) MB85R1001 PIN ASSIGNMENTS (TOP VIEW) A11 A9 N.C. A8 A13 WE CE2 A15 N.C. VCC N.C. N.C. GND N.C. N.C. VCC N.C. A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OE N.C. GND A10 CE1 N.C. I/O8 I/O7 I/O6 I/O5 I/O4 VCC N.C. I/O3 I/O2 I/O1 N.C. N.C. N.C. A0 A1 GND A2 A3 (FPT-48P-M25) PIN DESCRIPTIONS Pin name A0 to A16 2 Function Address In I/O1 to I/O8 Data Input/Output CE1 Chip Enable 1 in CE2 Chip Enable 2 in WE Write Enable in OE Output Enable in VCC Power Supply GND Ground MB85R1001 BLOCK DIAGRAM to * * * Address Latch. A0 Row Dec. Ferro Capacitor Cell A16 Column Dec. intCE2 S/A intCE2 CE2 intOE intWE intCE2 intCEB WE I/O1 to I/O8 OE I/O8 CE1 * * intCEB to I/O1 FUNCTION TRUTH TABLE Operation Mode Standby Pre-charge Read Read (Pseudo SRAM, OE control) CE1 CE2 WE OE H X X X X L X X X X H H H L H L L Supply Current High-Z Standby (ISB) Dout H H Write I/O1 to I/O8 H L Operation (ICC) H L Din Write (Pseudo SRAM, WE control) L H Output Disable L H H H H High-Z L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance : Latch address at falling edge, : Latch address at rising edge 3 MB85R1001 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Min Max Unit Supply Voltage VCC -0.5 +4.0 V Input Voltage VIN -0.5 VCC+0.5 V VOUT -0.5 VCC+0.5 V Ambient Temperature TA -20 +85 C Storage Temperature Tstg -40 +125 C Output Voltage WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min (VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Value Unit Typ Max Supply Voltage VCC 3.0 3.3 3.6 V Input Voltage (high) VIH VCC x 0.8 VCC + 0.5 V Input Voltage (low) VIL -0.5 0.8 V Operating Temperature TA -20 +85 C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 4 MB85R1001 ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS Parameter Symbol Test Condition (VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Value Unit Min Typ Max Input Leakage Current |ILI| VIN = 0 V to VCC 10 A Output Leakage Current |ILO| VOUT = 0 V to VCC, CE1 = VIH or OE = VIH 10 A Supply Current ICC CE1 = 0.2 V, CE2 = VCC-0.2 V, Iout = 0 mA*1 10 mA 10 100 A 0.8 x VCC V 0.4 V CE1 VCC-0.2 V Standby Current ISB CE2 0.2 V*2 OE VCC-0.2 V, WE VCC-0.2 V*2 Output Voltage (high) VOH IOH = -2.0 mA Output Voltage (low) VOL IOL = 2.0 mA *1 : Iout : Output current *2 : All other inputs (CE1, CE2, OE, WE) should be at CMOS levels, i.e., H VCC - 0.2 V, L 0.2 V. 5 MB85R1001 2. AC CHARACTERISTICS * AC TEST CONDITIONS Supply Voltage Operating Temperature Input Voltage Amplitude Input Rising Time Input Falling Time Input Evaluation Level Output Evaluation Level Output Impedance : 3.0 V to 3.6 V : -20 C to +85 C : 0.3 V to 2.7 V : 10 ns : 10 ns : 2.0 V / 0.8 V : 2.0 V / 0.8 V : 50 pF (1) Read Operation (VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Parameter Symbol Value Min Max Unit Read Cycle Time tRC 250 ns CE1 Active Time tCA1 210 2,000 ns OE Active Time tRP 210 2,000 ns Pre-charge Time tPC 40 ns Address Setup Time tAS 10 ns Address Hold Time tAH 50 ns OE Setup Time tES 10 ns CE1 Access Time tCE1 100 ns CE2 Access Time tCE2 100 ns OE Access Time tOE 100 ns OE Output Floating Time tOHZ 25 ns (2) Write Operation (VCC = 3.0 V to 3.6 V, TA = -20 C to +85 C) Parameter 6 Symbol Value Min Max Unit Write Cycle Time tWC 250 ns CE1 Active Time tCA1 210 2,000 ns CE2 Active Time tCA2 210 2,000 ns Pre-charge Time tPC 40 ns Address Setup Time tAS 10 ns Address Hold Time tAH 50 ns Write Pulse Width tWP 210 ns Data Setup Time tDS 10 ns Data Hold Time tDH 50 ns Write Setup Time tWS 0 ns MB85R1001 (3) Power ON/OFF Sequence Value Symbol Min Typ Max CE1 LEVEL holding time in Power OFF tpd 85 ns CE1 LEVEL holding time in Power ON tpu 85 ns Power interval * tpi 0.5 s Parameter Units * : Condition for power detection circuit to function 3. Pin Capacitance (f = 1 MHz, TA = +25 C) Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition Value Unit Min Typ Max VIN = GND 10 pF VOUT = GND 10 pF 4. Reliability Data retention 10 years (TA = 0 C to +55 C) Access endurance 1010 times (TA = -20 C to +85 C) 7 MB85R1001 TIMING DIAGRAMS 1. Read Cycle Timing * CE1, CE2 Control tRC tCA1 tCE1 tPC CE1 CE2 tCE2 tAS A0 to A16 tAH Valid tES tRP OE tOHZ tOE High-Z Valid I/O1 to I/O8 * OE Control tRC tCA1 tPC CE1 CE2 tCA2 tAS A0 to A16 tAH Valid tRP OE tOHZ tOE I/O1 to I/O8 8 High-Z Valid MB85R1001 2. Write Cycle Timing * CE1, CE2 Control tWC tCA1 tPC CE1 CE2 tCA2 tAS A0 to A16 tAH Valid tWS tWP WE OE tDS tDH Valid Data In * WE Control tWC tCA1 tPC CE1 CE2 tCA2 tAS A0 to A16 tAH Valid WE tWP OE tDS Data In tDH Valid 9 MB85R1001 POWER ON/OFF SEQUENCE tpd tpi tpu VCC VCC CE2 CE2 3.0 V 3.0 V VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) CE2 0.2 V GND GND CE1 > VCC x 0.8* CE1 : Don't Care CE1 > VCC x 0.8* CE1 * : CE1 (Max) < VCC + 0.5 V CE1 NOTES ON USE After IR reflow, the hold of data that was written before IR reflow is not guaranteed. ORDERING INFOMATION Part number MB85R1001PFTN 10 Package 48-pin plastic TSOP(1) (FPT-48P-M25) Remarks MB85R1001 PACKAGE DIMENTION Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP(1) (FPT-48P-M25) 0.100.05 (Stand off) (.004.002) LEAD No. 1 48 0.50(.020) INDEX +0.05 0.22 -0.04 +.002 .009 -.002 *1 12.000.10 (.472.004) 24 0.10(.004) M 25 1.130.07 (Mounting height) (.044.003) 14.000.20(.551.008) Details of "A" part *2 12.400.10(.488.004) "A" 0~8 +0.05 0.08(.003) C 0.145 -0.03 +.002 .006 -.001 0.25(.010) 0.600.15 (.024.006) 2003 FUJITSU LIMITED F48043S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. 11 MB85R1001 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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