ISLA216P13IR1Z - Intersil Corporation

1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

16-Bit, 250MSPS/200MSPS/130MSPS ADC

ISLA216P

The ISLA216P is a family of low power, high performance

16-bit analog-to-digital converters. Designed with Intersil’s

proprietary FemtoCharge™ technology on a standard CMOS

process, the family supports sampling rates of up to

250MSPS. The ISLA216P is part of a pin-compatible portfolio

of 12 to 16-bit A/Ds with maximum sample rates ranging from

130MSPS to 500MSPS.

A serial peripheral interface (SPI) port allows for extensive

configurability, as well as fine control of various parameters

such as gain and offset.

Digital output data is presented in selectable LVDS or CMOS

formats. The ISLA216P is available in a 72-contact QFN

package with an exposed paddle. Operating from a 1.8V

supply, performance is specified over the full industrial

temperature range (-40°C to +85°C).

Key Specifications

• SNR @ 250/200/130MSPS

• 75.0/76.6/77.5dBFS fIN = 30MHz

• 72.1/72.6/72.4dBFS fIN = 363MHz

• SFDR @ 250/200/130MSPS

•87/91/96dBc f

IN = 30MHz

• 81/80/82dBc fIN = 363MHz

• Total Power Consumption = 786mW @ 250MSPS

Features

• Single Supply 1.8V Operation

• Clock Duty Cycle Stabilizer

• 75fs Clock Jitter

• 700MHz Bandwidth

• Programmable Built-in Test Patterns

•Multi-ADC Support

• SPI Programmable Fine Gain and Offset Control

• Support for Multiple ADC Synchronization

• Optimized Output Timing

• Nap and Sleep Modes

• 200µs Sleep Wake-up Time

• Data Output Clock

• DDR LVDS-Compatible or LVCMOS Outputs

• User-accessible Digital Temperature Monitor

Applications

• Radar Array Processing

• Software Defined Radios

• Broadband Communications

• High-Performance Data Acquisition

• Communications Test Equipment

DIGITAL

ERROR

CORRECTION

VINP

VINN

CLOCK

MANAGEMENT

SHA

16-BIT

250 MSPS

ADC

CLKP

CLKN

SPI

CONTROL

CSB

SCLK

SDIO

OVSS

AVSS AVDD

CLKOUTP

CLKOUTN

D[14:0]P

D[14:0]N

OVDD

CLKDIV

RLVDS

SDO

–

VCM

RESETN

CLKDIVRSTP

CLKDIVRSTN

NAPSLP

Pin-Compatible Family

MODEL RESOLUTION

SPEED

(MSPS)

ISLA216P25 16 250

ISLA216P20 16 200

ISLA216P13 16 130

ISLA214P50 14 500

ISLA214P25 14 250

ISLA214P20 14 200

ISLA214P13 14 130

ISLA212P50 12 500

ISLA212P25 12 250

ISLA212P20 12 200

ISLA212P13 12 130

April 15, 2011

FN7574.1

ISLA216P

2FN7574.1

April 15, 2011

Pin Configuration - LVDS MODE

ISLA216P

(72 LD QFN)

TOP VIEW

AVDD

SDIO

72 71 70 69 68 67 66 65 64 63 62 61

SCLK

CSB

SDO

OVSS

D0P

D0N

OVDD

OVSS

60 59

D2P

D2N

DNC

D6P

D6N

DNC

CLKOUTP

CLKOUTN

RLVDS

OVSS

D8P

D8N

DNC

NAPSLP

VCM

AVSS

AVDD

AVSS

VINN

VINP

AVSS

AVDD

AVSS

19 20 21 22 23 24 25 26 27 28 29 30 31 32

AVDD

CLKP

CLKN

CLKDIVRSTP

CLKDIVRSTN

OVSS

OVDD

DNC

D14N

D14P

OVDD

CLKDIV

IPTAT

DNC

RESETN

33 34 35 36

DNC

D12N

D12P

D10P

D10N

DNC

58 57

DNC

56 55

D4P

D4N

Connect Thermal Pad to AVSS

Thermal Pad Not Drawn to Scale,

Consult Mechanical Drawing

for Physical Dimensions

Pin Descriptions - 72 Ld QFN, LVDS Mode

PIN NUMBER LVDS PIN NAME LVDS PIN FUNCTION

1, 2, 17, 28, 29, 33, 34, 37,

38, 41, 42, 49, 50, 53, 54,

57, 58

DNC Do Not Connect

6, 13, 19, 20, 21, 70, 71, 72 AVDD 1.8V Analog Supply

5, 7, 12, 14 AVSS Analog Ground

27, 32, 62 OVDD 1.8V Output Supply

26, 45, 61, 65 OVSS Output Ground

3 NAPSLP Tri-Level Power Control (Nap, Sleep modes)

ISLA216P

3FN7574.1

April 15, 2011

4 VCM Common Mode Output

8, 9 VINN Analog Input Negative

10, 11 VINP Analog Input Positive

15 CLKDIV Tri-Level Clock Divider Control

16 IPTAT Temperature Monitor (Output current proportional to absolute temperature)

18 RESETN Power On Reset (Active Low)

22, 23 CLKP, CLKN Clock Input True, Complement

24, 25 CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement

30 D14N DDR Logical Bits 14, 15 Complement

31 D14P DDR Logical Bits 14, 15 True

35 D12N DDR Logical Bits 12, 13 Complement

36 D12P DDR Logical Bits 12, 13 True

39 D10N DDR Logical Bits 10, 11 Complement

40 D10P DDR Logical Bits 10, 11 True

43 D8N DDR Logical Bits 8, 9 Complement

44 D8P DDR Logical Bits 8, 9 True

46 RLVDS LVDS Bias Resistor (Connect to OVSS with 1%10kΩ)

47, 48 CLKOUTN, CLKOUTP LVDS Clock Output Complement, True

51 D6N DDR Logical Bits 6, 7 Complement

52 D6P DDR Logical Bits 6, 7 True

55 D4N DDR Logical Bits 4, 5 Complement

56 D4P DDR Logical Bits 4, 5 True

59 D2N DDR Logical Bits 2, 3 Complement

60 D2P DDR Logical Bits 2, 3 True

63 D0N DDR Logical Bits 0, 1 Complement

64 D0P DDR Logical Bits 0, 1 True

66 SDO SPI Serial Data Output

67 CSB SPI Chip Select (active low)

68 SCLK SPI Clock

69 SDIO SPI Serial Data Input/Output

Exposed Paddle AVSS Analog Ground

Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued)

PIN NUMBER LVDS PIN NAME LVDS PIN FUNCTION

ISLA216P

4FN7574.1

April 15, 2011

Pin Configuration - CMOS MODE

ISLA216P

(72 LD QFN)

TOP VIEW

AVDD

SDIO

72 71 70 69 68 67 66 65 64 63 62 61

SCLK

CSB

SDO

OVSS

DNC

OVDD

OVSS

60 59

DNC

CLKOUT

DNC

RLVDS

OVSS

DNC

NAPSLP

VCM

AVSS

AVDD

AVSS

VINN

VINP

AVSS

AVDD

AVSS

19 20 21 22 23 24 25 26 27 28 29 30 31 32

AVDD

CLKP

CLKN

CLKDIVRSTP

CLKDIVRSTN

OVSS

OVDD

DNC

D14

OVDD

CLKDIV

IPTAT

DNC

RESETN

33 34 35 36

DNC

D12

D10

DNC

58 57

DNC

56 55

DNC

Connect Thermal Pad to AVSS

Consult Mechanical Drawing

for Physical Dimensions

Thermal Pad Not Drawn to Scale,

Pin Descriptions - 72 Ld QFN, CMOS Mode

PIN NUMBER CMOS PIN NAME CMOS PIN FUNCTION

1, 2, 17, 28, 29, 30, 33, 34,

35, 37, 38, 39, 41, 42, 43,

47, 49, 50, 51, 53, 54, 55,

57, 58, 59, 63

DNC Do Not Connect

6, 13, 19, 20, 21, 70, 71, 72 AVDD 1.8V Analog Supply

5, 7, 12, 14 AVSS Analog Ground

27, 32, 62 OVDD 1.8V Output Supply

26, 45, 61, 65 OVSS Output Ground

3 NAPSLP Tri-Level Power Control (Nap, Sleep modes)

ISLA216P

5FN7574.1

April 15, 2011

4 VCM Common Mode Output

8, 9 VINN Analog Input Negative

10, 11 VINP Analog Input Positive

15 CLKDIV Tri-Level Clock Divider Control

16 IPTAT Temperature Monitor (Output current proportional to absolute temperature)

18 RESETN Power On Reset (Active Low)

22, 23 CLKP, CLKN Clock Input True, Complement

24, 25 CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement

31 D14 DDR Logical Bits 14, 15

36 D12 DDR Logical Bits 12, 13

40 D10 DDR Logical Bits 10, 11

44 D8 DDR Logical Bits 8, 9

46 RLVDS LVDS Bias Resistor (Connect to OVSS with 1%10kΩ)

48 CLKOUT CMOS Clock Output

52 D6 DDR Logical Bits 6, 7

56 D4 DDR Logical Bits 4, 5

60 D2 DDR Logical Bits 2, 3

64 D0 DDR Logical Bits 0, 1

66 SDO SPI Serial Data Output

67 CSB SPI Chip Select (active low)

68 SCLK SPI Clock

69 SDIO SPI Serial Data Input/Output

Exposed Paddle AVSS Analog Ground

Pin Descriptions - 72 Ld QFN, CMOS Mode (Continued)

PIN NUMBER CMOS PIN NAME CMOS PIN FUNCTION

Ordering Information

PART NUMBER

(Notes 1, 2)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISLA216P13IRZ ISLA216P13 IRZ -40°C to +85°C 72 Ld QFN L72.10x10E

ISLA216P20IRZ ISLA216P20 IRZ -40°C to +85°C 72 Ld QFN L72.10x10E

ISLA216P25IRZ ISLA216P25 IRZ -40°C to +85°C 72 Ld QFN L72.10x10E

Coming Soon

ISLA216P13IR1Z ISLA216P13 IR1Z -40°C to +85°C 48 Ld QFN TBD

Coming Soon

ISLA216P20IR1Z ISLA216P20 IR1Z -40°C to +85°C 48 Ld QFN TBD

Coming Soon

ISLA216P25IR1Z ISLA216P25 IR1Z -40°C to +85°C 48 Ld QFN TBD

ISLA216IR72EV1Z Evaluation Board (72 pin QFN ADC)

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216P. For more information on MSL please see techbrief TB363.

ISLA216P

6FN7574.1

April 15, 2011

Table of Contents

Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Device Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

A/D Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Clock Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

ISLA216P

7FN7574.1

April 15, 2011

Absolute Maximum Ratings Thermal Information

AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V

OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V

AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V

Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V

Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V

Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V

Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V

Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . . 23 0.9

48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . . 24 1.0

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,

OVDD = 1.8V, TA= -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).

Boldface limits apply over the operating temperature range, -40°C to +85°C.

PARAMETER SYMBOL CONDITIONS

ISLA216P25 ISLA216P20 ISLA216P13

UNITS

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

DC SPECIFICATIONS (Note 6)

Analog Input

Full-Scale Analog Input

Range

VFS Differential 1.95 2.0 2.2 1.95 2.0 2.2 1.95 2.0 2.2 VP-P

Input Resistance RIN Differential 300 300 300 Ω

Input Capacitance CIN Differential 9 9 9 pF

Full Scale Range Temp.

Drift

AVTC Full Temp 180 180 180 ppm/°C

Input Offset Voltage VOS -5.0 -1.7 5.0 -5.0 -1.7 5.0 -5.0 -1.7 5.0 mV

Common-Mode Output

Voltage

VCM 0.94 0.94 0.94 V

Common-Mode Input

Current (per pin)

ICM 5.2 5.2 5.2 µA/MSPS

Clock Inputs

Inputs Common Mode

Voltage

0.9 0.9 0.9 V

CLKP,CLKN Input Swing 1.8 1.8 1.8 V

Power Requirements

1.8V Analog Supply

Voltage

AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

1.8V Digital Supply

Voltage

OVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

1.8V Analog Supply

Current

IAVDD 372 397 342 360 293 310 mA

1.8V Digital Supply

Current (Note 6)

IOVDD 3mA LVDS 64 73 58 68 50 58 mA

Power Supply Rejection

Ratio

PSRR 30MHz, 50mVP-P signal

on AVDD

-65 -65 -65 dB

ISLA216P

8FN7574.1

April 15, 2011

Total Power Dissipation

Normal Mode PD2mA LVDS 771 706 603 mW

3mA LVDS 786 846 720 770 616 662 mW

CMOS 760 685 580 mW

Nap Mode PD88 103 83 99 77 94 mW

Sleep Mode PDCSB at logic high 7 19 719 719 mW

Nap/Sleep Mode

Wakeup Time

Sample Clock Running 200 400 630 µs

AC SPECIFICATIONS

Differential Nonlinearity DNL fIN = 30MHz

No Missing Codes

-0.99 ±0.35 -0.99 ±0.25 -0.99 ±0.25 LSB

Integral Nonlinearity INL fIN = 30MHz ±10 ±6 ±5 LSB

Minimum Conversion

Rate (Note 7)

fS MIN 40 40 40 MSPS

Maximum Conversion

Rate

fS MAX 250 200 130 MSPS

Signal-to-Noise Ratio

(Note 8)

SNR fIN = 30MHz 75.0 76.6 77.5 dBFS

fIN = 105MHz 71.7 74.9 74.8 76.4 75.5 76.9 dBFS

fIN = 190MHz 74.2 75.3 75.3 dBFS

fIN = 363MHz 72.1 72.6 72.4 dBFS

fIN = 461MHz 71.1 71.1 70.8 dBFS

fIN = 605MHz 69.2 69.2 68.9 dBFS

Signal-to-Noise and

Distortion

(Note 8)

SINAD fIN = 30MHz 74.7 76.5 77.4 dBFS

fIN = 105MHz 70.0 74.1 73.2 76.1 72.6 76.1 dBFS

fIN = 190MHz 73.1 74.7 74.6 dBFS

fIN = 363MHz 71.6 71.7 71.9 dBFS

fIN = 461MHz 69.2 68.6 67.9 dBFS

fIN = 605MHz 65.7 64.9 66.3 dBFS

Effective Number of Bits

(Note 8)

ENOB fIN = 30MHz 12.12 12.42 12.56 Bits

fIN = 105MHz 11.34 12.02 11.87 12.35 11.77 12.35 Bits

fIN = 190MHz 11.85 12.12 12.10 Bits

fIN = 363MHz 11.60 11.62 11.65 Bits

fIN = 461MHz 11.20 11.10 10.99 Bits

fIN = 605MHz 10.62 10.49 10.72 Bits

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,

OVDD = 1.8V, TA= -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).

Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

PARAMETER SYMBOL CONDITIONS

ISLA216P25 ISLA216P20 ISLA216P13

UNITS

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

ISLA216P

9FN7574.1

April 15, 2011

Spurious-Free Dynamic

Range

(Note 8)

SFDR fIN = 30MHz 87 91 96 dBc

fIN = 105MHz 74 83 74 89 72 83 dBc

fIN = 190MHz 81 84 83 dBc

fIN = 363MHz 81 80 82 dBc

fIN = 461MHz 73 72 70 dBc

fIN = 605MHz 67 67 67 dBc

Spurious-Free Dynamic

Range Excluding H2, H3

(Note 8)

SFDRX23 fIN = 30MHz 89 91 99 dBc

fIN = 105MHz 80 92 82 93 82 96 dBc

fIN = 190MHz 88 92 96 dBc

fIN = 363MHz 83 87 94 dBc

fIN = 461MHz 82 85 91 dBc

fIN = 605MHz 79 82 89 dBc

Intermodulation

Distortion

IMD fIN = 70MHz 94 92 88 dBFS

fIN = 170MHz 87 87 87 dBFS

Word Error Rate WER 10-12 10-12 10-12

Full Power Bandwidth FPBW 700 700 700 MHz

NOTES:

5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.

7. The DLL Range setting must be changed for low-speed operation.

8. Minimum specification guaranteed when calibrated at +85°C.

Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,

OVDD = 1.8V, TA= -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).

Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

PARAMETER SYMBOL CONDITIONS

ISLA216P25 ISLA216P20 ISLA216P13

UNITS

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

MIN

(Note 5) TYP

MAX

(Note 5)

Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.

PARAMETER SYMBOL CONDITIONS

MIN

(Note 5) TYP

MAX

(Note 5) UNITS

INPUTS

Input Current High (RESETN) IIH VIN = 1.8V 0110 µA

Input Current Low (RESETN) IIL VIN = 0V -25 -12 -7 µA

Input Current High (SDIO) IIH VIN = 1.8V 4 12 µA

Input Current Low (SDIO) IIL VIN = 0V -600 -415 -300 µA

Input Current High (CSB) IIH VIN = 1.8V 40 58 75 µA

Input Current Low (CSB) IIL VIN = 0V 5 10 µA

Input Voltage High (SDIO, RESETN) VIH 1.17 V

Input Voltage Low (SDIO, RESETN) VIL 0.63 V

Input Current High (CLKDIV) (Note 9) IIH 16 25 34 µA

Input Current Low (CLKDIV) IIL -34 -25 -16 µA

Input Capacitance CDI 4pF

ISLA216P

10 FN7574.1

April 15, 2011

LVDS INPUTS (CLKDIVRSTP,CLKDIVRSTN)

Input Common Mode Range VICM 825 1575 mV

Input Differential Swing (peak to peak, single-ended) VID 250 450 mV

CLKDIVRSTP Input Pull-down Resistance RIpd 100 kΩ

CLKDIVRSTN Input Pull-up Resistance RIpu 100 kΩ

LVDS OUTPUTS

Differential Output Voltage (Note 10) VT3mA Mode 612 mVP-P

Output Offset Voltage VOS 3mA Mode 1120 1150 1200 mV

Output Rise Time tR240 ps

Output Fall Time tF240 ps

CMOS OUTPUTS

Voltage Output High VOH IOH = -500µA OVDD - 0.3 OVDD - 0.1 V

Voltage Output Low VOL IOL = 1mA 0.1 0.3 V

Output Rise Time tR1.8 ns

Output Fall Time tF1.4 ns

NOTES:

9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending

on desired function.

10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.

Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

PARAMETER SYMBOL CONDITIONS

MIN

(Note 5) TYP

MAX

(Note 5) UNITS

Timing Diagrams

FIGURE 1A. LVDS

CLKN

CLKP

INP

INN

CLKOUTN

CLKOUTP

tCPD

LATENCY = L CYCLES

tDC

tPD

ODD

N-L

EVEN

N-L

ODD

N-L+1

EVEN

N-L+1

EVEN

N-1

ODD

EVEN

D[14/12/…/2/0]N

D[14/12/…/2/0]P

ISLA216P

11 FN7574.1

April 15, 2011

FIGURE 1B. CMOS

FIGURE 1. TIMING DIAGRAMS

Timing Diagrams

CLKN

CLKP

INP

INN

CLKOUT

tCPD

LATENCY = L CYCLES

tDC

tPD

ODD

N-L

EVEN

N-L

ODD

N-L+1

EVEN

N-L+1

EVEN

N-1

ODD

EVEN

D[14/12/…/2/0]

Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.

PARAMETER SYMBOL CONDITION

MIN

(Note 5) TYP

MAX

(Note 5) UNITS

ADC OUTPUT

Aperture Delay tA114 ps

RMS Aperture Jitter jA75 fs

Input Clock to Output Clock Propagation

Delay

tCPD AVDD, OVDD = 1.7V to 1.9V,

TA= -40°C to +85°C

1.65 2.4 3ns

tCPD AVDD, OVDD = 1.8V, TA= +25°C 1.9 2.3 2.75 ns

Relative Input Clock to Output Clock

Propagation Delay (Note 13)

dtCPD AVDD, OVDD = 1.7V to 1.9V,

TA= -40°C to +85°C

-450 450 ps

Input Clock to Data Propagation Delay tPD 1.65 2.4 3.5 ns

Output Clock to Data Propagation Delay,

LVDS Mode

tDC Rising/Falling Edge -0.1 0.16 0.5 ns

Output Clock to Data Propagation Delay,

CMOS Mode

tDC Rising/Falling Edge -0.1 0.2 0.65 ns

Synchronous Clock Divider Reset Setup

Time (with respect to the positive edge of

CLKP)

tRSTS 0.4 0.06 ns

Synchronous Clock Divider Reset Hold Time

(with respect to the positive edge of CLKP)

tRSTH 0.02 0.35 ns

Synchronous Clock Divider Reset Recovery

Time

tRSTRT DLL recovery time after

Synchronous Reset

52 µs

Latency (Pipeline Delay) L 10 cycles

ISLA216P

12 FN7574.1

April 15, 2011

Overvoltage Recovery tOVR 1cycles

SPI INTERFACE (Notes 11, 12)

SCLK Period tCLK Write Operation 16 cycles

tCLK Read Operation 16 cycles

CSB↓ to SCLK↑ Setup Time tSRead or Write 28 cycles

CSB↑ after SCLK↑ Hold Time tHWrite 5cycles

Data Valid to SCLK↑ Setup Time tDS Write 6cycles

Data Valid after SCLK↑ Hold Time tDH Read or Write 4cycles

Data Valid after SCLK↓ Time tDVR Read 5cycles

NOTES:

11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled

proportionally for lower sample rates. ADC sample clock must be running for SPI communication.

12. The SPI may operate asynchronously with respect to the ADC sample clock.

13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is

specified over the full operating temperature and voltage range.

Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)

PARAMETER SYMBOL CONDITION

MIN

(Note 5) TYP

MAX

(Note 5) UNITS

Typical Performance Curves

All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA= +25°C,

AIN =-2dBFS, f

IN = 105MHz, fSAMPLE = 250MSPS.

FIGURE 2. SNR AND SFDR vs fIN FIGURE 3. HD2 AND HD3 vs fIN

FIGURE 4. SNR AND SFDR vs AIN FIGURE 5. HD2 AND HD3 vs AIN

0 100 200 300 400 500 600

SNR (dBFS) AND SFDR (dBc)

INPUT FREQUENCY (MHz)

SFDR @ 130MSPS

SFDR @ 250MSPS

SNR @ 130MSPS

SNR @ 250MSPS

-105

-100

-95

-90

-85

-80

-75

-70

-65

0 100 200 300 400 500 600

HD2 AND HD3 MAGNITURE (dBc)

INPUT FREQUENCY (MHz)

HD2 @ 250MSPS

HD3 @ 250MSPS

HD2 @ 130MSPS

HD3 @ 130MSPS

100

-60-50-40-30-20-10 0

SNR AND SFDR

INPUT AMPLITUDE (dBFS)

SNR(dBc)

SFDR(dBfs)

SNR(dBfs)

SFDR(dBc)

-110

-100

-90

-80

-70

-60

-50

-40

-60 -50 -40 -30 -20 -10 0

HD2 AND HD3 MAGNITUDE

INPUT AMPLITUDE (dBFS)

HD3 (dBc)

HD2 (dBfs)

HD3 (dBfs)

HD2 (dBc)

ISLA216P

13 FN7574.1

April 15, 2011

FIGURE 6. SNR AND SFDR vs fSAMPLE FIGURE 7. HD2 AND HD3 vs fSAMPLE

FIGURE 8. POWER vs fSAMPLE IN 3mA LVDS MODE FIGURE 9. DIFFERENTIAL NONLINEARITY

FIGURE 10. INTEGRAL NONLINEARITY FIGURE 11. SNR AND SFDR vs VCM

Typical Performance Curves

All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA= +25°C,

AIN =-2dBFS, f

IN = 105MHz, fSAMPLE = 250MSPS. (Continued)

70 90 110 130 150 170 190 210 230 250

SAMPLE RATE (MSPS)

SFDR

SNR

SNR (dBFS) AND SFDR (dBc)

-105

-100

-95

-90

-85

-80

-75

70 90 110 130 150 170 190 210 230 250

SAMPLE RATE (MSPS)

HD2 AND HD3 MAGNITUDE (dBc)

450

500

550

600

650

700

750

800

40 60 80 100 120 140 160 180 200 220 240

SAMPLE RATE (MSPS)

TOTAL POWER (mW)

CMOS

LVDS

0 10,000 20,000 30,000 40,000 50,000 60,000

-1.5

-1.0

-0.5

0.5

1.0

1.5

CODES

DNL (LSBs)

-20

-15

-10

-5

30,00010,000 20,000 40,000 50,000 60,000

CODES

INL (LSBs)

0.75 0.85 0.95 1.05 1.15

INPUT COMMON MODE (V)

SNR (dBFS) AND SFDR (dBc)

SNR

SFDR

ISLA216P

14 FN7574.1

April 15, 2011

FIGURE 12. NOISE HISTOGRAM FIGURE 13. SINGLE-TONE SPECTRUM @ 105MHz

FIGURE 14. SINGLE-TONE SPECTRUM @ 190MHz FIGURE 15. SINGLE-TONE SPECTRUM @ 363MHz

FIGURE 16. TWO-TONE SPECTRUM

(F1 = 70MHz, F2 = 71MHz AT -7dBFS)

FIGURE 17. TWO-TONE SPECTRUM

(F1 = 170MHz, F2 = 171MHz AT -7dBFS)

Typical Performance Curves

All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA= +25°C,

AIN =-2dBFS, f

IN = 105MHz, fSAMPLE = 250MSPS. (Continued)

5000

10000

15000

20000

25000

32696 32700 32704 32708 32712 32716 32720 32724

CODE

NUMBER OF HITS

020 40 60 80 100 120

-120

-100

-80

-60

-40

-20

FREQUENCY (MHz)

AMPLITUDE (dBFS)

AIN = -2 dBFS

SNR = 75.4 dBFS

SFDR = 82 dBc

SINAD = 74.5 dBFS

020 40 60 80 100 120

-120

-100

-80

-60

-40

-20

FREQUENCY (MHz)

AMPLITUDE (dBFS)

AIN = -2 dBFS

SNR = 74.5 dBFS

SFDR = 81 dBc

SINAD = 73.67 dBFS

020 40 60 80 100 120

-120

-100

-80

-60

-40

-20

FREQUENCY (MHz)

AMPLITUDE (dBFS)

AIN = -2 dBFS

SNR = 72.4 dBFS

SFDR = 80 dBc

SINAD = 71.3 dBFS

020 40 60 80 100 120

-120

-100

-80

-60

-40

-20

FREQUENCY (MHz)

IMD2

IMD3

2nd Harmonics

3rd Harmonics

AMPLITUDE (dBFS)

IMD3 = -94dBFS

020 40 60 80 100 120

-120

-100

-80

-60

-40

-20

FREQUENCY (MHz)

AMPLITUDE (dBFS)

IMD3 = -87dBFS

IMD2

IMD3

2nd Harmonics

3rd Harmonics

ISLA216P

15 FN7574.1

April 15, 2011

Theory of Operation

Functional Description

The ISLA216P25 is based upon a 16-bit, 250MSPS A/D converter

core that utilizes a pipelined successive approximation

architecture (Figure 18). The input voltage is captured by a

Sample-Hold Amplifier (SHA) and converted to a unit of charge.

Proprietary charge-domain techniques are used to successively

compare the input to a series of reference charges. Decisions

made during the successive approximation operations determine

the digital code for each input value. Digital error correction is also

applied, resulting in a total latency of 10 clock cycles. This is

evident to the user as a latency between the start of a conversion

and the data being available on the digital outputs.

Power-On Calibration

As mentioned previously, the cores perform a self-calibration at

start-up. An internal power-on-reset (POR) circuit detects the

supply voltage ramps and initiates the calibration when the

analog and digital supply voltages are above a threshold. The

following conditions must be adhered to for the power-on

calibration to execute successfully:

• A frequency-stable conversion clock must be applied to the

CLKP/CLKN pins

• DNC pins must not be connected

• SDO has an internal pull-up and should not be driven externally

• RESETN is pulled low by the ADC internally during POR.

External driving of RESETN is optional.

• SPI communications must not be attempted

A user-initiated reset can subsequently be invoked in the event

that the above conditions cannot be met at power-up.

After the power supply has stabilized the internal POR releases

RESETN and an internal pull-up pulls it high, which starts the

calibration sequence. If a subsequent user-initiated reset is

desired, the RESETN pin should be connected to an open-drain

driver with an off-state/high impedance state leakage of less

than 0.5mA to assure exit from the reset state so calibration can

start.

The calibration sequence is initiated on the rising edge of

RESETN, as shown in Figure 19. Calibration status can be

determined by reading the cal_status bit (LSB) at 0xB6. This bit is

‘0’ during calibration and goes to a logic ‘1’ when calibration is

complete. The data outputs produce 0xCCCC during calibration;

this can also be used to determine calibration status.

While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is

set low. Normal operation of the output clock resumes at the

next input clock edge (CLKP/CLKN) after RESETN is de-asserted.

At 250MSPS the nominal calibration time is 200ms, while the

maximum calibration time is 550ms.

FIGURE 18. A/D CORE BLOCK DIAGRAM

DIGITAL

ERROR

CORRECTION

SHA

1.25V

INP

INN

CLOCK

GENERATION

2.5- BIT

FLASH

6- STAGE

1.5-BIT/ STAGE

3- STAGE

1-BIT/ STAGE

3-BIT

FLASH

LVDS/ LVCMOS

OUTPUTS

–

FLASH

2.5-BIT

ISLA216P

16 FN7574.1

April 15, 2011

User Initiated Reset

Recalibration of the A/D can be initiated at any time by driving

the RESETN pin low for a minimum of one clock cycle. An

open-drain driver with a drive strength in its high impedance

state of less than 0.5mA is recommended, as RESETN has an

internal high impedance pull-up to OVDD. As is the case during

power-on reset, RESETN and DNC pins must be in the proper

state for the calibration to successfully execute.

The performance of the ISLA216P25 changes with variations in

temperature, supply voltage or sample rate. The extent of these

changes may necessitate recalibration, depending on system

performance requirements. Best performance will be achieved

by recalibrating the A/D under the environmental conditions at

which it will operate.

A supply voltage variation of <100mV will generally result in an

SNR change of <0.5dBFS and SFDR change of <3dBc.

In situations where the sample rate is not constant, best results

will be obtained if the device is calibrated at the highest sample

rate. Reducing the sample rate by less than 80MSPS will typically

result in an SNR change of <0.5dBFS and an SFDR change of

<3dBc.

Figures 20 through 25 show the effect of temperature on SNR

and SFDR performance with power on calibration performed at

-40°C, +25°C, and +85°C. Each plot shows the variation of

SNR/SFDR across temperature after a single power on

calibration at -40°C, +25°C and +85°C. Best performance is

typically achieved by a user-initiated power on calibration at the

operating conditions, as stated earlier. However, it can be seen

that performance drift with temperature is not a very strong

function of the temperature at which the power on calibration is

performed; also note that SFDR performance typically improves

as the analog input level moves away from full-scale as Figure 4

shows.

FIGURE 19. CALIBRATION TIMING

CLKP

CLKN

CLKOUTP

CALIBRATION

BEGINS

CALIBRATION

COMPLETE

CALIBRATION

TIME

RESETN

CAL_STATUS

BIT

Temperature Calibration

FIGURE 20. TYPICAL SNR PERFORMANCE vs TEMPERATURE,

DEVICE CALIBRATED AT -40°C, fIN = 105MHz, -2dBFS

FIGURE 21. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,

DEVICE CALIBRATED AT -40°C, fIN = 105MHz, -2dBFS

-40-35-30-25-20

130MSPS 200MSPS

250MSPS

TEMPERATURE (°C)

SNR (dBFS)

-40 -35 -30 -25 -20

250MSPS 200MSPS

130MSPS

TEMPERATURE (°C)

SFDR (dBc)

ISLA216P

17 FN7574.1

April 15, 2011

Analog Input

A single fully differential input (VINP/VINN) connects to the

sample and hold amplifier (SHA) of each unit A/D. The ideal

full-scale input voltage is 2.0V, centered at the VCM voltage of

0.94V as shown in Figure 26.

Best performance is obtained when the analog inputs are driven

differentially. The common-mode output voltage, VCM, should be

used to properly bias the inputs as shown in Figures 27 through

29. An RF transformer will give the best noise and distortion

performance for wideband and/or high intermediate frequency

(IF) inputs. Two different transformer input schemes are shown in

Figures 27 and 28.

FIGURE 22. TYPICAL SNR PERFORMANCE vs TEMPERATURE,

DEVICE CALIBRATED AT +25°C, fIN = 105MHz, -2dBFS

FIGURE 23. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,

DEVICE CALIBRATED AT +25°C, fIN = 105MHz, -2dBFS

FIGURE 24. TYPICAL SNR PERFORMANCE vs TEMPERATURE,

DEVICE CALIBRATED AT +85°C, fIN = 105MHz, -2dBF

FIGURE 25. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,

DEVICE CALIBRATED AT +85°C, fIN = 105MHz, -2dBFS

Temperature Calibration (Continued)

5 1015202530354045

250MSPS

200MSPS

130MSPS

TEMPERATURE (°C)

SNR (dBFS)

5 1015202530354045

130MSPS

200MSPS

250MSPS

TEMPERATURE (°C)

SFDR (dBc)

65 67 69 71 73 75 77 79 81 83 85

250MSPS

130MSPS

200MSPS

TEMPERATURE (°C)

SNR (dBFS)

65 70 75 80 85

250MSPS

200MSPS

130MSPS

TEMPERATURE (°C)

SFDR (dBc)

FIGURE 26. ANALOG INPUT RANGE

1.0

1.8

0.6

0.2

1.4

VINP

VINN

VCM

0.94V

1.0V FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE

APPLICATIONS

ADT1-1WT

0.1µF

A/D

VCM

ADT1-1WT

1000pF

FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR

HIGH IF APPLICATIONS

A/D

VCM

1000pF

TX-2-5-1

ADTL1-12

ISLA216P

18 FN7574.1

April 15, 2011

This dual transformer scheme is used to improve common-mode

rejection, which keeps the common-mode level of the input

matched to VCM. The value of the shunt resistor should be

determined based on the desired load impedance. The

differential input resistance of the ISLA216P25 is 300Ω.

The SHA design uses a switched capacitor input stage (see

Figure 42), which creates current spikes when the sampling

capacitance is reconnected to the input voltage. This causes a

disturbance at the input which must settle before the next

sampling point. Lower source impedance will result in faster

settling and improved performance. Therefore a 2:1 or 1:1

transformer and low shunt resistance are recommended for

optimal performance.

A differential amplifier, as shown in the simplified block diagram

in Figure 29, can be used in applications that require

DC-coupling. In this configuration, the amplifier will typically

dominate the achievable SNR and distortion performance.

Intersil’s new ISL552xx differential amplifier family can also be

used in certain AC applications with minimal performance

degradation. Contact the factory for more information.

Clock Input

The clock input circuit is a differential pair (see Figure 43).

Driving these inputs with a high level (up to 1.8VP-P on each

input) sine or square wave will provide the lowest jitter

performance. A transformer with 4:1 impedance ratio will

provide increased drive levels. The clock input is functional with

AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the

lowest possible aperture jitter, it is recommended to have high

slew rate at the zero crossing of the differential clock input

signal.

The recommended drive circuit is shown in Figure 30. A duty

range of 40% to 60% is acceptable. The clock can be driven

single-ended, but this will reduce the edge rate and may impact

SNR performance. The clock inputs are internally self-biased to

AVDD/2 to facilitate AC coupling.

A selectable 2x or 4x frequency divider is provided in series with

the clock input. The divider can be used in the 2x mode with a

sample clock equal to twice the desired sample rate or in 4x

mode with a sample clock equal to four times the desired

sample rate. This allows the use of the Phase Slip feature, which

enables synchronization of multiple ADCs. The Phase Slip feature

can be used as an alternative to using the CLKDIVRST pins to

synchronize ADCs in a multiple ADC system.

The clock divider can also be controlled through the SPI port,

which overrides the CLKDIV pin setting. See “SPI Physical

Interface” on page 23. A delay-locked loop (DLL) generates

internal clock signals for various stages within the charge

pipeline. If the frequency of the input clock changes, the DLL may

take up to 52μs to regain lock at 250MSPS. The lock time is

inversely proportional to the sample rate.

The DLL has two ranges of operation, slow and fast. The slow

range can be used for sample rates between 40MSPS and

100MSPS, while the default fast range can be used from

80MSPS to the maximum specified sample rate.

Jitter

In a sampled data system, clock jitter directly impacts the

achievable SNR performance. The theoretical relationship

between clock jitter (tJ) and SNR is shown in Equation 1 and is

illustrated in Figure 31.

FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT

A/D

TABLE 1. CLKDIV PIN SETTINGS

CLKDIV PIN DIVIDE RATIO

AVSS 2

Float 1

AVDD 4

FIGURE 30. RECOMMENDED CLOCK DRIVE

TC4-19G2+

1000pF

CLKP

CLKN

0.01µF 200

1000pF

SNR 20 log10

2πfINtJ

-------------------

⎝⎠

⎛⎞

=(EQ. 1)

ISLA216P

19 FN7574.1

April 15, 2011

This relationship shows the SNR that would be achieved if clock

jitter were the only non-ideal factor. In reality, achievable SNR is

limited by internal factors such as linearity, aperture jitter and

thermal noise. Internal aperture jitter is the uncertainty in the

sampling instant shown in Figure1A. The internal aperture jitter

combines with the input clock jitter in a root-sum-square fashion,

since they are not statistically correlated, and this determines

the total jitter in the system. The total jitter, combined with other

noise sources, then determines the achievable SNR.

Voltage Reference

A temperature compensated internal voltage reference provides

the reference charges used in the successive approximation

operations. The full-scale range of each A/D is proportional to the

reference voltage. The nominal value of the voltage reference is

1.25V.

Digital Outputs

Output data is available as a parallel bus in

LVDS-compatible(default) or CMOS modes. In either case, the data

is presented in double data rate (DDR) format. Figures 1A and 1B

show the timing relationships for LVDS and CMOS modes,

respectively.

Additionally, the drive current for LVDS mode can be set to a

nominal 3mA(default) or a power-saving 2mA. The lower current

setting can be used in designs where the receiver is in close

physical proximity to the A/D. The applicability of this setting is

dependent upon the PCB layout, therefore the user should

experiment to determine if performance degradation is

observed.

The output mode can be controlled through the SPI port, by

writing to address 0x73, see “Serial Peripheral Interface” on

page 23.

An external resistor creates the bias for the LVDS drivers. A 10kΩ,

1% resistor must be connected from the RLVDS pin to OVSS.

Power Dissipation

The power dissipated by the ISLA216P25 is primarily dependent

on the sample rate and the output modes: LVDS vs CMOS and

DDR vs SDR. There is a static bias in the analog supply, while the

remaining power dissipation is linearly related to the sample

rate. The output supply dissipation changes to a lesser degree in

LVDS mode, but is more strongly related to the clock frequency in

CMOS mode.

Nap/Sleep

Portions of the device may be shut down to save power during

times when operation of the A/D is not required. Two power saving

modes are available: Nap, and Sleep. Nap mode reduces power

dissipation to <103mW while Sleep mode reduces power

dissipation to <19mW.

All digital outputs (Data, CLKOUT and OR) are placed in a high

impedance state during Nap or Sleep. The input clock should

remain running and at a fixed frequency during Nap or Sleep, and

CSB should be high. Recovery time from Nap mode will increase

if the clock is stopped, since the internal DLL can take up to 52µs

to regain lock at 250MSPS.

By default after the device is powered on, the operational state is

controlled by the NAPSLP pin as shown in Table 2.

The power-down mode can also be controlled through the SPI

port, which overrides the NAPSLP pin setting. Details on this are

contained in “Serial Peripheral Interface” on page 23.

Data Format

Output data can be presented in three formats: two’s

complement(default), Gray code and offset binary. The data

format can also be controlled through the SPI port, by writing to

address 0x73. Details on this are contained in “Serial Peripheral

Interface” on page 23.

Offset binary coding maps the most negative input voltage to

code 0x000 (all zeros) and the most positive input to 0xFFF (all

ones). Two’s complement coding simply complements the MSB

of the offset binary representation.

When calculating Gray code the MSB is unchanged. The

remaining bits are computed as the XOR of the current bit

position and the next most significant bit. Figure 32 shows this

operation.

FIGURE 31. SNR vs CLOCK JITTER

tj = 100ps

tj = 10ps

tj = 1ps

tj = 0.1ps

10 BITS

12 BITS

14 BITS

100

1M 10M 100M 1G

SNR (dB)

INPUT FREQUENCY (Hz)

TABLE 2. NAPSLP PIN SETTINGS

NAPSLP PIN MODE

AVSS Normal

Float Sleep

AVDD Nap

FIGURE 32. BINARY TO GRAY CODE CONVERSION

1415 13 01BINARY

1415 13 0GRAY CODE

• • • •

ISLA216P

20 FN7574.1

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Converting back to offset binary from Gray code must be done

recursively, using the result of each bit for the next lower bit as

shown in Figure 33.

Mapping of the input voltage to the various data formats is

shown in Table 3.

Clock Divider Synchronous Reset

An output clock (CLKOUTP, CLKOUTN) is provided to facilitate

latching of the sampled data. This clock is at half the frequency

of the sample clock, and the absolute phase of the output clocks

for multiple A/Ds is indeterminate. This feature allows the phase

of multiple A/Ds to be synchronized (refer to Figure 34), which

greatly simplifies data capture in systems employing multiple

A/Ds.

The reset signal must be well-timed with respect to the sample

clock (See “Switching Specifications” on page 11).

TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING

INPUT

VOLTAGE OFFSET BINARY

TWO’S

COMPLEMENT GRAY CODE

–Full Scale 0000 0000 0000

0000

1000 0000 0000

0000

0000 0000 0000

0000

–Full Scale

+ 1LSB

0000 0000 0000

0001

1000 0000 0000

0001

0000 0000 0000

0001

Mid–Scale 1000 0000 0000

0000

0000 0000 0000

0000

1100 0000 0000

0000

+Full Scale

– 1LSB

1111 1111 1111

1110

0111 1111 1111

1110

1000 0000 0000

0001

+Full Scale 1111 1111 1111

1111

0111 1111 1111

1111

1000 0000 0000

0000

1415 13 01

BINARY 1415 13 0

GRAY CODE • • • •

• • • •

ISLA216P

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FIGURE 34. SYNCHRONOUS RESET OPERATION

s1 s2

s0 s3

s1 s2

s0 s3

CLKDIVRSTP

ADC1 OUTPUT DATA

ADC1 CLKOUTP

ADC2 CLKOUTP

(phase 1)

ADC2 CLKOUTP

(phase 2)

L+td

tRSTH

tRSTS

tRSTRT

ADC2 OUTPUT DATA

ANALOG INPUT

SAMPLE CLOCK

INPUT

NOTES:

13. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td.

14. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.

CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.

15. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.

(Note 15)

(Note 14)

(Note 13)

ISLA216P

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FIGURE 35. MSB-FIRST ADDRESSING

CSB

SCLK

SDIO R/W W1 W0 A12 A11 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0A10

FIGURE 36. LSB-FIRST ADDRESSING

CSB

SCLK

SDIO R/WW1W0A12A11A1A0 D7D6D5D4D3D2D1

D0A2

FIGURE 37. SPI WRITE

tHI tCLK

tLO

R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0

tDHW

tDSW

SPI WRITE

CSB

SCLK

SDIO

FIGURE 38. SPI READ

(3 WIRE MODE)

(4 WIRE MODE)

W1 W 0 A 1 2 A9 A2 A1 D7 D6 D3 D2 D1

D7 D3 D2 D1 D0

WRITING A READ COMMAND READING DATA

tDVR

SPI READ

tCLK

tDHW

tDSW

CSB

SCLK

SDIO

SDO

A11 A10

R/W

ISLA216P

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Serial Peripheral Interface

A serial peripheral interface (SPI) bus is used to facilitate

configuration of the device and to optimize performance. The SPI

bus consists of chip select (CSB), serial clock (SCLK) serial data

output (SDO), and serial data input/output (SDIO). The maximum

SCLK rate is equal to the A/D sample rate (fSAMPLE) divided by 16

for both write operations and read operations. At fSAMPLE =

250MHz, maximum SCLK is 15.63MHz for writing and read

operations. There is no minimum SCLK rate.

The following sections describe various registers that are used to

configure the SPI or adjust performance or functional parameters.

Many registers in the available address space (0x00 to 0xFF) are

not defined in this document. Additionally, within a defined

reserved. Undefined registers and undefined values within defined

registers are reserved and should not be selected. Setting any

reserved register or value may produce indeterminate results.

SPI Physical Interface

The serial clock pin (SCLK) provides synchronization for the data

transfer. By default, all data is presented on the serial data

input/output (SDIO) pin in three-wire mode. The state of the SDIO

pin is set automatically in the communication protocol

(described in the following). A dedicated serial data output pin

(SDO) can be activated by setting 0x00[7] high to allow operation

in four-wire mode.

The SPI port operates in a half duplex master/slave

configuration, with the ISLA216P25 functioning as a slave.

Multiple slave devices can interface to a single master in

three-wire mode only, since the SDO output of an unaddressed

device is asserted in four wire mode.

The chip-select bar (CSB) pin determines when a slave device is

being addressed. Multiple slave devices can be written to

concurrently, but only one slave device can be read from at a

given time (again, only in three-wire mode). If multiple slave

devices are selected for reading at the same time, the results will

be indeterminate.

The communication protocol begins with an instruction/address

phase. The first rising SCLK edge following a high-to-low

transition on CSB determines the beginning of the two-byte

instruction/address command; SCLK must be static low before

the CSB transition. Data can be presented in MSB-first order or

LSB-first order. The default is MSB-first, but this can be changed

by setting 0x00[6] high. Figures 35 and 36 show the appropriate

bit ordering for the MSB-first and LSB-first modes, respectively. In

MSB-first mode, the address is incremented for multi-byte

transfers, while in LSB-first mode it’s decremented.

In the default mode, the MSB is R/W, which determines if the

data is to be read (active high) or written. The next two bits, W1

and W0, determine the number of data bytes to be read or

written (see Table 4). The lower 13 bits contain the first address

for the data transfer. This relationship is illustrated in Figure 37,

and timing values are given in “Switching

Specifications Boldface limits apply over the operating

temperature range, -40°C to +85°C.” on page 11.

After the instruction/address bytes have been read, the

appropriate number of data bytes are written to or read from the

A/D (based on the R/W bit status). The data transfer will

continue as long as CSB remains low and SCLK is active. Stalling

of the CSB pin is allowed at any byte boundary

(instruction/address or data) if the number of bytes being

transferred is three or less. For transfers of four bytes or more,

CSB is allowed to stall in the middle of the instruction/address

bytes or before the first data byte. If CSB transitions to a high

state after that point the state machine will reset and terminate

the data transfer.

FIGURE 39. 2-BYTE TRANSFER

CSB

SCLK

SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD 2

CSB STALLING

FIGURE 40. N-BYTE TRANSFER

CSB

SCLK

SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD N

LAST LEGAL

CSB STALLING

ISLA216P

24 FN7574.1

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Figures 39 and 40 illustrate the timing relationships for 2-byte

and N-byte transfers, respectively. The operation for a 3-byte

transfer can be inferred from these diagrams.

SPI Configuration

ADDRESS 0X00: CHIP_PORT_CONFIG

Bit ordering and SPI reset are controlled by this register. Bit order

can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB

first) to accommodate various micro controllers.

Bit 7 SDO Active

Bit 6 LSB First

Setting this bit high configures the SPI to interpret serial data

as arriving in LSB to MSB order.

Bit 5 Soft Reset

Setting this bit high resets all SPI registers to default values.

Bit 4 Reserved

This bit should always be set high.

Bits 3:0 These bits should always mirror bits 4:7 to avoid

ambiguity in bit ordering.

ADDRESS 0X02: BURST_END

If a series of sequential registers are to be set, burst mode can

improve throughput by eliminating redundant addressing. The

burst is ended by pulling the CSB pin high. Setting the burst_end

address determines the end of the transfer. During a write

operation, the user must be cautious to transmit the correct

number of bytes based on the starting and ending addresses.

Bits 7:0 Burst End Address

This register value determines the ending address of the burst

data.

Device Information

ADDRESS 0X08: CHIP_ID

ADDRESS 0X09: CHIP_VERSION

The generic die identifier and a revision number, respectively, can

be read from these two registers.

Device Configuration/Control

A common SPI map, which can accommodate single-channel or

multi-channel devices, is used for all Intersil A/D products.

ADDRESS 0X20: OFFSET_COARSE_ADC0

ADDRESS 0X21: OFFSET_FINE_ADC0

The input offset of the A/D core can be adjusted in fine and

coarse steps. Both adjustments are made via an 8-bit word as

detailed in Table 5. The data format is twos complement.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the

back to the same register.

ADDRESS 0X22: GAIN_COARSE_ADC0

ADDRESS 0X23: GAIN_MEDIUM_ADC0

ADDRESS 0X24: GAIN_FINE_ADC0

Gain of the A/D core can be adjusted in coarse, medium and fine

steps. Coarse gain is a 4-bit adjustment while medium and fine

are 8-bit. Multiple Coarse Gain Bits can be set for a total

adjustment range of ±4.2%. (‘0011’ ≅ -4.2% and ‘1100’ ≅+4.2%)

It is recommended to use one of the coarse gain settings (-4.2%,

-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the

registers at 0x0023 and 0x24.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the

back to the same register.

TABLE 4. BYTE TRANSFER SELECTION

[W1:W0] BYTES TRANSFERRED

00 1

01 2

10 3

11 4 or more

TABLE 5. OFFSET ADJUSTMENTS

PARAMETER

0x20[7:0]

COARSE OFFSET

0x21[7:0]

FINE OFFSET

Steps 255 255

–Full Scale (0x00) -133LSB (-47mV) -5LSB (-1.75mV)

Mid–Scale (0x80) 0.0LSB (0.0mV) 0.0LSB

+Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV)

Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV)

TABLE 6. COARSE GAIN ADJUSTMENT

0x22[3:0] core 0

0x26[3:0] core 1

NOMINAL COARSE GAIN ADJUST

(%)

Bit3 +2.8

Bit2 +1.4

Bit1 -2.8

Bit0 -1.4

ISLA216P

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ADDRESS 0X25: MODES

Two distinct reduced power modes can be selected. By default,

the tri-level NAPSLP pin can select normal operation, nap or

sleep modes (refer to“Nap/Sleep” on page 19). This functionality

can be overridden and controlled through the SPI. This is an

indexed function when controlled from the SPI, but a global

function when driven from the pin. This register is not changed by

a Soft Reset.

ADDRESS 0X26: OFFSET_COARSE_ADC1

ADDRESS 0X27: OFFSET_FINE_ADC1

The input offset of A/D core#1 can be adjusted in fine and

coarse steps in the same way that offset for core#0 can be

adjusted. Both adjustments are made via an 8-bit word as

detailed in Table 5. The data format is two’s complement.

The default value of each register will be the result of the

self-calibration after initial power-up. If a register is to be

incremented or decremented, the user should first read the register

value then write the incremented or decremented value back to the

same register.

ADDRESS 0X28: GAIN_COARSE_ADC1

ADDRESS 0X29: GAIN_MEDIUM_ADC1

ADDRESS 0X2A: GAIN_FINE_ADC1

Gain of A/D core #1 can be adjusted in coarse, medium and fine

steps in the same way that core #0 can be adjusted. Coarse gain is

a 4-bit adjustment while medium and fine are 8-bit. Multiple

Coarse Gain Bits can be set for a total adjustment range of ±4.2.

Global Device Configuration/Control

ADDRESS 0X71: PHASE_SLIP

The output data clock is generated by dividing down the A/D input

sample clock. Some systems with multiple A/Ds can more easily latch

the data from each A/D by controlling the phase of the output data

clock. This control is accomplished through the use of the phase_slip

SPI feature, which allows the rising edge of the output data clock to be

advanced by one input clock period, as shown in the Figure 41.

Execution of a phase_slip command is accomplished by first writing a

'0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address

0x71.

ADDRESS 0X72: CLOCK_DIVIDE

The ISLA216P25 has a selectable clock divider that can be set to

divide by two or one (no division). By default, the tri-level CLKDIV

pin selects the divisor This functionality can be overridden and

controlled through the SPI, as shown in Table 9. This register is

not changed by a Soft Reset.

ADDRESS 0X73: OUTPUT_MODE_A

The output_mode_A register controls the physical output format

of the data, as well as the logical coding. The ISLA216P25 can

present output data in two physical formats: LVDS(default) or

LVCMOS. Additionally, the drive strength in LVDS mode can be set

high (default,3mA or low (2mA).

Data can be coded in three possible formats: two’s

complement(default), Gray code or offset binary. See Table 11.

This register is not changed by a Soft Reset.

TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS

PARAMETER

0x23[7:0]

MEDIUM GAIN

0x24[7:0]

FINE GAIN

Steps 256 256

–Full Scale (0x00) -2% -0.20%

Mid–Scale (0x80) 0.00% 0.00%

+Full Scale (0xFF) +2% +0.2%

Nominal Step Size 0.016% 0.0016%

TABLE 8. POWER-DOWN CONTROL

VALUE

0x25[2:0]

POWER DOWN MODE

000 Pin Control

001 Normal Operation

010 Nap Mode

100 Sleep Mode TABLE 9. CLOCK DIVIDER SELECTION

VALUE

0x72[2:0]

CLOCK DIVIDER

000 Pin Control

001 Divide by 1

010 Divide by 2

other Not Allowed

TABLE 10. OUTPUT MODE CONTROL

VALUE

0x73[7:5]

OUTPUT MODE

000 LVDS 3mA (Default)

001 LVDS 2mA

100 LVCMOS

FIGURE 41. PHASE SLIP

ADC Input

Clock (500MHz)

Output Data

Clock (250MHz)

No clock_slip

Output Data

Clock (250MHz)

1 clock_slip

Output Data

Clock (250MHz)

2 clock_slip

2ns 4ns

2ns

ISLA216P

26 FN7574.1

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ADDRESS 0X74: OUTPUT_MODE_B

Bit 6 DLL Range

This bit sets the DLL operating range to fast (default) or slow.

Internal clock signals are generated by a delay-locked loop (DLL),

which has a finite operating range. Table 12 shows the allowable

sample rate ranges for the slow and fast settings.Note that Bit 4

at 0x74 is reserved and must not change value. A user writing to

Bit 6 should first read 0x74 to determine proper value to write

back to Bit 4 when writing to 0x74

ADDRESS 0XB6: CALIBRATION STATUS

The LSB at address 0xB6 can be read to determine calibration

status. The bit is ‘0’ during calibration and goes to a logic ‘1’

when calibration is complete.This register is unique in that it can

be read after POR at calibration, unlike the other registers on

chip, which can’t be read until calibration is complete.

DEVICE TEST

The ISLA216P25 can produce preset or user defined patterns on

the digital outputs to facilitate in-situ testing. A user can pick

from preset built-in patterns by writing to the output test mode

field [7:4] at 0xC0 or user defined patterns by writing to the user

test mode field [2:0] at 0xC0. The user defined patterns should

be loaded at address space 0xC1 through 0xD0, see the “SPI

Memory Map” on page 28 for more detail.The predefined

patterns are shown in Table 13. The test mode is enabled

asynchronously to the sample clock, therefore several sample

clock cycles may elapse before the data is present on the output

bus.

ADDRESS 0XC0: TEST_IO

Bits 7:4 Output Test Mode

These bits set the test mode according to Table 13. Other

values are reserved.User test patterns loaded at 0xC1 through

0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a

pattern depth value to [2:0] at 0xC0. See “SPI Memory Map”

on page 28.

Bits 2:0 User Test Mode

The three LSBs in this register determine the test pattern in

combination with registers 0xC1 through 0xD0. Refer to the

“SPI Memory Map” on page 28.

ADDRESS 0XC1: USER_PATT1_LSB

ADDRESS 0XC2: USER_PATT1_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 1.

ADDRESS 0XC3: USER_PATT2_LSB

ADDRESS 0XC4: USER_PATT2_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 2

ADDRESS 0XC5: USER_PATT3_LSB

ADDRESS 0XC6: USER_PATT3_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 3

ADDRESS 0XC7: USER_PATT4_LSB

ADDRESS 0XC8: USER_PATT4_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 4.

ADDRESS 0XC9: USER_PATT5_LSB

ADDRESS 0XCA: USER_PATT5_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 5.

ADDRESS 0XCB: USER_PATT6_LSB

ADDRESS 0XCC: USER_PATT6_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 6

ADDRESS 0XCD: USER_PATT7_LSB

ADDRESS 0XCE: USER_PATT7_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 7.

TABLE 11. OUTPUT FORMAT CONTROL

VALUE

0x73[2:0]

OUTPUT FORMAT

000 Two’s Complement (Default)

010 Gray Code

100 Offset Binary

TABLE 12. DLL RANGES

DLL RANGE MIN MAX UNIT

Slow 40 100 MSPS

Fast 80 250 MSPS

TABLE 13. OUTPUT TEST MODES

VALUE

0xC0[7:4]

OUTPUT TEST MODE WORD 1 WORD 2

0000 Off

0001 Midscale 0x8000 N/A

0010 Positive Full-Scale 0xFFFF N/A

0011 Negative Full-Scale 0x0000 N/A

0100 Reserved N/A N/A

0101 Reserved N/A N/A

0110 Reserved N/A N/A

0111 Reserved

1000 User Pattern user_patt1 user_patt2

1001 Reserved N/A N/A

1010 Ramp N/A N/A

ISLA216P

27 FN7574.1

April 15, 2011

ADDRESS 0XCF: USER_PATT8_LSB

ADDRESS 0XD0: USER_PATT8_MSB

These registers define the lower and upper eight bits,

respectively, of the user-defined pattern 8.

Digital Temperature Sensor

ADDRESS 0X4B: TEMP_COUNTER_HIGH

Bits [2:0] of this register hold the 3 MSBs of the 11-bit

temperature code.

Bit [7] of this register indicates a valid temperature_counter read

was performed. A logic ‘1’ indicates a valid read.

ADDRESS 0X4C: TEMP_COUNTER_LOW

Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit

temperature code.

ADDRESS 0X4D: TEMP_COUNTER_CONTROL

Bit [7] Measurement mode select bit, set to ‘1’ for recommended

PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and

not recommended.

Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.

Bit [5] Temperature counter power down bit. Set to ‘1’ to

power-down temperature counter.

Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.

Bit [3:1] Three bit frequency divider field. Sets temperature

counter update rate. Update rate is proportional to ADC sample

clock rate and divide ratio. A ‘101’ updates the temp counter

every ~ 66µs (for 250MSPS). Faster updates rates result in lower

precision.

Bit [0] Select sampler bit. Set to ‘0’.

This set of registers provides digital access to an PTAT or

IPTAT-based temperature sensor, allowing the system to

estimate the temperature of the die, allowing easy access to

information that can be used to decide when to recalibrate the

A/D as needed.

The nominal transfer function of the temperature counter is

Codes (in decimal) = 0.56*T(°C) + 618. This corresponds to

approximately a 65 LSB increase from -40° to +85°C.

A typical temperature measurement can occur as follows:

1. Write ‘0xCA’ to address 0x4D - enable temp counter,

divide=’101’

2. Wait ≥ 132µs (at 250Msps) - longer wait time ensures the

sensor completes one valid cycle.

3. Write ‘0x20’ to address 0x4D - power down, disable temp

counter-recommended between measurements. This

ensures that the output does not change between MSB and

LSB reads.

4. Read address 0x4B (MSBs)

5. Read address 0x4C (LSBs)

6. Record temp code value

7. Write ‘0x20’ to address 0x4D - power-down, disable temp

counter. Contact the factory for more information if needed.

ISLA216P

28 FN7574.1

April 15, 2011

SPI Memory Map

ADDR.

(Hex) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)

DEF. VALUE

(HEX)

SPI Config/Control

00 port_config SDO Active LSB First Soft Reset Mirror (bit5) Mirror (bit6) Mirror (bit7) 00h

01 Reserved Reserved

02 burst_end Burst end address [7:0] 00h

03-07 Reserved Reserved

DUT Info

08 chip_id Chip ID # Read only

09 chip_version Chip Version # Read only

0A-0F Reserved Reserved

Device Config/Control

10-1F Reserved Reserved

20 offset_coarse_adc0 Coarse Offset cal. value

21 offset_fine_adc0 Fine Offset cal. value

22 gain_coarse_adc0 Reserved Coarse Gain cal. value

23 gain_medium_adc0 Medium Gain cal. value

24 gain_fine_adc0 Fine Gain cal. value

25 modes_adc0 Reserved Power Down Mode ADC0 [2:0]

000 = Pin Control

001 = Normal Operation

010 = Nap

100 = Sleep

Other codes = Reserved

00h

NOT reset by

Soft Reset

26 offset_coarse_adc1 Coarse Offset cal. value

27 offset_fine_adc1 Fine Offset cal. value

28 gain_coarse_adc1 Reserved Coarse Gain cal. value

29 gain_medium_adc1 Medium Gain cal. value

2A gain_fine_adc1 Fine Gain cal. value

2B modes_adc1 Reserved Power Down Mode ADC1 [2:0]

000 = Pin Control

001 = Normal Operation

010 = Nap

100 = Sleep

Other codes = Reserved

00h

NOT reset by

Soft Reset

2C-2F Reserved Reserved

33-4A Reserved Reserved

4B temp_counter_high Temp Counter [10:8] Read only

4C temp_counter_low Temp Counter [7:0] Read only

4D temp_counter_control Enable PD Reset Divider [2:0] Select 00h

4E-6F Reserved Reserved

70 skew_diff Differential Skew 80h

71 phase_slip Reserved Next Clock

Edge

00h

72 clock_divide Clock Divide [2:0]

000 = Pin Control

001 = divide by 1

010 = divide by 2

100 = divide by 4

Other codes = Reserved

00h

NOT reset by

Soft Reset

ISLA216P

29 FN7574.1

April 15, 2011

Device Config/Control

73 output_mode_A Output Mode [7:5]

000 = LVDS 3mA (Default)

001 = LVDS 2mA

100 = LVCMOS

Other codes = Reserved

Output Format [2:0]

000 = Two’s Complement (Default)

010 = Gray Code

100 = Offset Binary

Other codes = Reserved

00h

NOT reset by

Soft Reset

74 output_mode _B DLL Ra nge

0 = Fast

1 = Slow

Default=’0’

Reserved 00h

NOT reset by

Soft Reset

75-B5 Reserved Reserved

B6 cal_status Calibration

Done

Read Only

B7-BF Reserved

Device Test

C0 test_io Output Test Mode [7:4] User Test Mode [2:0]

0 = user pattern 1 only

1 = cycle pattern 1,3

2 = cycle pattern 1,3,5

3 = cycle pattern 1,3,5,7

4-7 = NA

00h

0 = Off (Note 14)

1 = Midscale Short

2 = +FS Short

3 = -FS Short

4 = Reserved (Note15)

5-6 = Reserved

7 = Reserved (Note16)

8 = User Pattern (1 to 4 deep)

9 = Reserved

10 = Ramp

11-15 = Reserved

C1 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00

C2 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

C3 user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h

C4 user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

C5 user_patt3_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h

C6 user_patt3_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

C7 user_patt4_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h

C8 user_patt4_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

C9 user_patt5_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h

CA user_patt5_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

CB user_patt6_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h

CC user_patt6_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

CD user_patt7_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h

CE user_patt7_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

CF user_patt8_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h

D0 user_patt8_msb B15 B14 B13 B12 B11 B10 B9 B8 00h

D1-FF Reserved Reserved

NOTES:

14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of

calibration. This behavior can be used as an option to determine calibration state.

15. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs on DDR Outputs.

16. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs on DDR Outputs.

SPI Memory Map (Continued)

ADDR.

(Hex) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)

DEF. VALUE

(HEX)

ISLA216P

30 FN7574.1

April 15, 2011

Equivalent Circuits

FIGURE 42. ANALOG INPUTS FIGURE 43. CLOCK INPUTS

FIGURE 44. TRI-LEVEL DIGITAL INPUTS FIGURE 45. DIGITAL INPUTS

FIGURE 46. LVDS OUTPUTS FIGURE 47. CMOS OUTPUTS

AVDD

INP

INN

AVDD CSAMP

9pF

CSAMP

9pF TO

CHARGE

PIPELINE

CHARGE

PIPELINE

E1 E3

300

AVDD

CLKP

CLKN

AVDD

CLOCK-PHASE

GENERATION

AVDD

11k 18k

AVDD

INPUT

AVDD

AVDD AVDD

SENSE

LOGIC

75k

75k75k

280

INPUT

OVDD

280

LOGIC

20k

OVDD

(20k PULL-UP

ON RESETN

ONLY)

D[14:0]P

OVDD

2mA OR

3mA

2mA OR

3mA

DATA

D[14:0]N

OVDD

D[14:0]

OVDD

DATA

ISLA216P

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7574.1

April 15, 2011

For additional products, see www.intersil.com/product_tree

A/D Evaluation Platform

Intersil offers an A/D Evaluation platform which can be used to

evaluate any of Intersil’s high speed A/D products. The platform

consists of a FPGA based data capture motherboard and a family

of A/D daughtercards. This USB based platform allows a user to

quickly evaluate the A/D’s performance at a user’s specific

application frequency requirements. More information is

available at

http://www.intersil.com/converters/adc_eval_platform/

Layout Considerations

Split Ground and Power Planes

Data converters operating at high sampling frequencies require

extra care in PC board layout. Many complex board designs

benefit from isolating the analog and digital sections. Analog

supply and ground planes should be laid out under signal and

clock inputs. Locate the digital planes under outputs and logic

pins. Grounds should be joined under the chip.

Clock Input Considerations

Use matched transmission lines to the transformer inputs for the

analog input and clock signals. Locate transformers and

terminations as close to the chip as possible.

Exposed Paddle

The exposed paddle must be electrically connected to analog

ground (AVSS) and should be connected to a large copper plane

using numerous vias for optimal thermal performance.

Bypass and Filtering

Bulk capacitors should have low equivalent series resistance.

Tantalum is a good choice. For best performance, keep ceramic

bypass capacitors very close to device pins. Longer traces will

increase inductance, resulting in diminished dynamic

performance and accuracy. Make sure that connections to

ground are direct and low impedance. Avoid forming ground

loops.

LVDS Outputs

Output traces and connections must be designed for 50Ω (100Ω

differential) characteristic impedance. Keep traces direct and

minimize bends where possible. Avoid crossing ground and

power-plane breaks with signal traces.

LVCMOS Outputs

Output traces and connections must be designed for 50Ω

characteristic impedance.

Unused Inputs

Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will

not be operated do not require connection to ensure optimal A/D

performance. These inputs can be left floating if they are not

used. Tri-level inputs (NAPSLP) accept a floating input as a valid

state, and therefore should be biased according to the desired

functionality.

Definitions

Analog Input Bandwidth is the analog input frequency at which

the spectral output power at the fundamental frequency (as

determined by FFT analysis) is reduced by 3dB from its full-scale

low-frequency value. This is also referred to as Full Power

Bandwidth.

Aperture Delay or Sampling Delay is the time required after the

rise of the clock input for the sampling switch to open, at which

time the signal is held for conversion.

Aperture Jitter is the RMS variation in aperture delay for a set of

samples.

Clock Duty Cycle is the ratio of the time the clock wave is at logic

high to the total time of one clock period.

Differential Non-Linearity (DNL) is the deviation of any code width

from an ideal 1 LSB step.

FIGURE 48. VCM_OUT OUTPUT

Equivalent Circuits (Continued)

VCM

AVDD

0.94V +

–

ISLA216P

32 FN7574.1

April 15, 2011

Effective Number of Bits (ENOB) is an alternate method of

specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it

is calculated as: ENOB = (SINAD - 1.76)/6.02

Gain Error is the ratio of the difference between the voltages that

cause the lowest and highest code transitions to the full-scale

voltage less than 2 LSB. It is typically expressed in percent.

I2E The Intersil Interleave Engine. This highly configurable

circuitry performs estimates of offset, gain, and sample time

skew mismatches between the core converters, and updates

analog adjustments for each to minimize interleave spurs.

Integral Non-Linearity (INL) is the maximum deviation of the

A/D’s transfer function from a best fit line determined by a least

squares curve fit of that transfer function, measured in units of

LSBs.

Least Significant Bit (LSB) is the bit that has the smallest value or

weight in a digital word. Its value in terms of input voltage is

VFS/(2N-1) where N is the resolution in bits.

Missing Codes are output codes that are skipped and will never

appear at the A/D output. These codes cannot be reached with

any input value.

Most Significant Bit (MSB) is the bit that has the largest value or

weight.

Pipeline Delay is the number of clock cycles between the

initiation of a conversion and the appearance at the output pins

of the data.

Power Supply Rejection Ratio (PSRR) is the ratio of the observed

magnitude of a spur in the A/D FFT, caused by an AC signal

superimposed on the power supply voltage.

Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS

signal amplitude to the RMS sum of all other spectral

components below one half the clock frequency, including

harmonics but excluding DC.

Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS

signal amplitude to the RMS sum of all other spectral

components below one-half the sampling frequency, excluding

harmonics and DC.

SNR and SINAD are either given in units of dB when the power of

the fundamental is used as the reference, or dBFS (dB to full

scale) when the converter’s full-scale input power is used as the

reference.

Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS

signal amplitude to the RMS value of the largest spurious

spectral component. The largest spurious spectral component

may or may not be a harmonic.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISLA216P

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE REVISION CHANGE

4/15/11 FN7574.1 -Updated Ordering Information by Changing Eval board name from ISLA216P25EVAL TO ISLA216IR72EV1Z and

updating description

-Electrical Specifications Table change:

DC Specifications ->Analog Input->Common-Mode Input Current (per pin) -> TYP "10.8" to "5.2"

Added CMOS Power Typical Specs under Total Power Dissipation ->Normal Mode

Digital Specifications Table ->Input Capacitance->TYP "3" to "4"

Digital Specifications Table ->LVDS INPUTS (CLKRSTP, CLKRSTN) TO LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)

-Updated temperature calibration curves

-Added clkdiv description in Clock Input Section

-Removed '2-wire mode' text in "Address 0x02:Burst_End" section

-Updated Bit6 at Address 0x74:Output_Mode_B section

1/13/11 FN7574.0 Initial Release

ISLA216P

33 FN7574.1

April 15, 2011

Package Outline Drawing

L72.10x10E

72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 11/09

EXPOSED

8.500 REF. (4X)

6.000 REF.

7.150 REF.

4.150 REF.

3.000

0.100 AMC B

A0.100 M C B

PIN #1

INDEX AREA

PAD AREA

REF.

located within the zone indicated. The pin #1 indentifier may be

Unless otherwise specified, tolerance : Decimal ± 0.10

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.015mm and 0.30mm from the terminal tip.

Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ANSI Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "Z"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

R0.115 TYP.

R0.200

SEATING

PLANE

R0.200 MAX.

ALL AROUND

10.00 ±0.10

0.500 ±0.100

C0.190X45°

(0.350)

(1.500) 0.450

0.190~0.245

0.650 ±0.050

0.025 ±0.020

0.23 ±0.050

0.50

0.85 ±0.050

11° 9.75 ±0.10

9.75

(4X) 0.15

INDEX AREA

PIN 1

10.00 A

10.00

9.75

ALL AROUND

(4X 9.70)

(4.15 REF)

(4X 8.50)

( 72X 0 .23) ( 72X 0 .70)

(7.15)

(6.00)

(3.00 )

C0.400X45° (4X)

(0.125 ALL AROUND)

A0.100 CMB

0.050 M C

0.080

0.100 C

DETAIL "X"

DETAIL "Y"

Angular ±2.50°

Package outline compliant to JESD-M0220.