International Rectifier • 233 Kansas Street
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CA 90245 USA
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IRDCiP2005A-A
IRDCiP2005A-A: 1MHz, 65A DC, 80A Peak,
Dual Phase, Sync Buck Converter using iP2005
Overview
This reference design is capable of delivering a current of
65A DC or 80A peak (with heatsink) at an ambient
temperature of 45ºC and airflow of 300LFM. Figures 1–19
provide performance graphs, thermal images, and
waveforms. The shunt resistors are added for load line
preciseness and can be changed to DCR sensing for higher
efficiency. Figures 19-23, and Table 1 are provided to
engineers as design references for implementing a dual
phase iP2005 solution. The components installed on this
demo board were selected based on operation at an input
voltage of 12V and at a switching frequency of 1MHz.
Changes from these set points may require optimizing the
control loop and/or adjusting the values of input/output filters
in order to meet the user’s specific application requirements.
Refer to the iP2005 datasheet for more information.
Demo board Quick Start Guide
Initial Settings:
V
OUT
is set to 1.25V, but can be adjusted from 0.8375V to 1.6V by changing the settings of VID0 through VID5 according to the
OnSemi data sheet of NCP5318.
Power Up Procedure:
1. Apply drive power supply across Vdd and PGND.
2. Apply input voltage across VIN and PGND.
3. Turn on the enable signal through the DIP switch (SW1-pin 8).
4. Apply load and adjust to desired level. See recommendations below.
5. Install/uninstall a jumper to JMP3 to turn on and turn off current transient load (65A step)*
* Note: the transient current load is a resistive load and the voltage across it is measured instead of current due to ESL limitations.
For more details, please refer to figure 11 through 15.
IRDCiP2005A-A Recommended Operating Conditions
(refer to the iP2005 datasheet for maximum operating conditions)
Input voltage: 9.5 – 13.2V
Output voltage: 0.8375 -1.6V
Switching Freq: 1MHz
02/04/2008
IRDCiP2005A-A_______ ___
Output current: This reference design is capable of delivering a continuous current of 65A (with heatsink) or 80A
repetitive pulse current load (50A DC + 10% duty 30A DC) at an ambient temperature of 45ºC and
an airflow of 300LFM.
Output Current Vs. Power Loss
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
25.0
26.0
27.0
28.0
29.0
30.0
31.0
32.0
33.0
34.0
35.0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Output current (amps)
Power Loss (W)
Vo = 1.0V
Vo = 1.25V
Vo = 1.5V
Fig. 1 Power Loss vs.
Output Current for Vin=12V
Fsw=1MHz, Vdd=5V, Ta=45dgC,
Airflow=300LFM, with Heat Sink
Output Current Vs. Efficiency
60%
61%
62%
63%
64%
65%
66%
67%
68%
69%
70%
71%
72%
73%
74%
75%
76%
77%
78%
79%
80%
81%
82%
83%
84%
85%
86%
87%
88%
89%
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Output current (amps)
Efficiency (%)
Vo = 1.0V
Vo = 1.25V
Vo = 1.5V
Fig. 2 Efficiency vs. Output
Current for Vin=12V
Fsw=1MHz, Vdd=5V, Ta=45dgC,
Airflow=300LFM, with Heat Sink
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1.12
1.14
1.16
1.18
1.2
1.22
1.24
0 204060801
Io (A)
Vo (V
00
)
Load Line when
Vin=12V,
Vdd=5V,
Ta=25degC,
Fsw=1MHz
Fig. 3 Load Line RLL = 1.2 mΩ
Phase Margin= 108 deg
Fc= 25.3 kHz
Conditions:
Vin=12V
Vo=1.25V
Io=60A
Fsw=1MHz
Fig. 4 Bode Plot
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Fig. 5 Thermal Graph 1
Fsw=1MHz, Vdd=5V, Ta=45 ºC,
Airflow=300LFM, Vin=12V,
Vo=1.25V, Io=65A, with heat sink
Fig. 6 Thermal Graph 2
Fsw=1MHz, Vdd=5V, Ta=45 ºC,
Airflow=300LFM, Vin=12V,
Vo=1.25V, Io=50A+30A (pulse),
with heat sink
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Vin
En Fig. 7 Power-Up
Sequence
Vin=12V
Vo=1.25V
Io=20A
Fsw=1MHz
Vo
Fig. 8 Power-Down
Sequence
Vin=12V
Vo=1.25V
Io=10A
Fsw=1MHz
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Vo_pp=17.2mV
Fig. 9 Output Voltage
Ripple
Vin=12V
Vo=1.25V
Io=50A
Fsw=1MHz
Vin=12V
Vo=1.25V
Io=20A
Fsw=1MHz Fig. 10 Over-Voltage
Protection
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Transient Load Overview
Many of today’s high performance CPU’s can easily draw transient currents with slew rate greater than 1000A/µs. Unfortunately,
replicating and demonstrating such a load event with such a high current slew rate on an evaluation board is not a trivial task. The
smallest amount of stray inductance can quickly limit the slew rate of your load design and cause large voltage spikes. For
example, a stray inductance of 30pH will create 30mV of over/undershoot for a given transient event with a slew rate of 1000A/µs.
Such an over/undershoot may already exceed the amount of voltage variation allowed in your design. A new approach over a
traditional load design needs to be implemented.
This reference design has an embedded load that is capable of delivering a 65A current step at slew rate of 1000A/µs. The load
design uses a parallel network of very small, low charge MOSFETs, 0402 capacitors, and 0603 load resistors (see Figure 1). This
new approach greatly minimizes the parasitic inductance through the use of low ESL components and by distributing the switching
current amongst many high speed switching MOSFETs. The pulsed current is run at a duty cycle of less than 2% which results in
very little power dissipation and minimal device temperature rise. The net result closely replicates the dynamic load response of a
high performance CPU.
Validating the current waveform could only be done by measuring the voltage drop differentially across the load resistors during
the switching event. Placing a current probe is not an option due to the ESL adder. Since the resistive load is a passive element,
current flowing through the resistor is in phase with the voltage across the resistor. If the voltage across the resistive element
changes at a rate of 1000V/µs, one can assume the current is changing at the same rate (1000A/µs).
Figures 12, 14 & 15 show the validation of the load design for this particular demonstration tool. Four MOSFETs stages were used
to create a 65A load step at a minimum of slew rate of 1000A/µs. The parallel network of load resistors in this design creates an
equivalent impedance of 9mΩ. Differentially measuring the voltage drop across the load resistors of each MOSFET stage yields a
voltage change of approximately 0.575V. Using Ohm’s law we approximately get 65A of total load current (see Figure 12).
Zooming in at the rising and falling edges of the load step, we can then measure the slew rate of the load step. In this particular
design, we are achieving about40ns rise and fall times for 40A change which translate to about 1000A/µs (see Figures 14 & 15).
Fig. 11 Embedded High Slew Rate Load Design
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Fig. 12 Transient Load Current Fig. 13 Vout under Transient Load
80mV droop, 1.2mΩ load
line requirement met
65A Step
di/dt=42A/44nS≈1000A/uS di/dt=-42A/40nS≈-1000A/uS
Fig. 14 Zoom-in rising edge of load Fig. 15 Zoom-in falling edge of load
Vsw
1
Vsw
2
Vo
Fig. 16 Transient load step-up Fig. 17 Transient load step-down
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Adjusting the Over-Current Limit
R10 and R12 are the resistors used to adjust the over-current int. The trip point corresponds to the peak inductor curren
ov
R10+R12 = (70.5 X I
Limit
-90) ohm
More details can be found in On-Semi data sheet of NCP5318.
Mechanical Drawings
trip po t,
therefer to equation below to determine R10 and R12 values given er current limit:
Fig. 19 Heat Sink Photo
Fig. 20 Mechanical Outline Drawing of Heatsink
Current
(
50A/10mV
)
Vo Fig. 18 Over-C
Protection
urrent
IRDCiP2005A-A_______ ___
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Fig. 21 Top Layer View
Fig. 22 Bottom Layer View
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Fig. 23 Reference Design Schematic
IRDCiP2005A-A_______ ___
Table 1: Reference Design Bill of Materials
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Refer to the following documents for more details and guidelines detailed guidelines for design:
iP2005A datasheet: Specifications and user guides about International Rectifier’s integrated
power modules used in this reference design
NCP5318 datasheet: Specifications and user guides about the On-Semi multiphase buck
controller used in this reference design
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier’s
iPowIR Technology BGA and LGA and Packages
This paper discusses optimization of the layout design for mounting iPowIR BGA and LGA packages on
printed circuit boards, accounting for thermal and electrical performance and assembly considerations.
Topics discussed includes PCB layout placement, and via interconnect suggestions, as well as soldering,
pick and place, reflow, inspection, cleaning and reworking recommendations.
AN-1030: Applying iPOWIR Products in Your Thermal Environment
This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the
operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product.
AN-1047: Graphical solution for two branch heatsinking Safe Operating Area
Detailed explanation of the dual axis SOA graph and how it is derived.
Use of this design for any application should be fully verified by the customer. International Rectifier
cannot guarantee suitability for your a pplications, and is not liable for any result of usage for such
applications including, without limitation, personal or property d amage or violation of third party
intellectual property rights.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
