○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays
1/23
© 2015 ROHM Co., Ltd. All rights reserved.
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TSZ22111・14・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
0.7V to VCC-1V, 3A 1ch
Ultra-Low Dropout Linear Regulator
BD3512MUV
General Description
BD3512MUV is an ultra-low dropout linear chipset
regulator, which operates at a very low input supply. It
offers ideal performance in low input to output voltage
applications. The input-to-output voltage difference is
minimized by using a built-in N-Channel power
MOSFET with a maximum ON-Resistance of
RON=100mΩ. By lowering the dropout voltage, the
regulator achieves high output current of up to
IOUTMAX=3.0A, thereby, reducing conversion loss, making
it comparable to a switching regulator and its power
transistor, choke coil, and rectifier diode constituents. It
is a low-cost design and is available in significantly
downsized package profiles. An external resistor sets
the output voltage which ranges from 0.65V to 2.7V,
while the NRCS (soft start) function enables a controlled
output voltage ramp-up, which can be programmed to
anything the power supply sequence is required.
Features
Incorporates High-Precision Reference Voltage
Circuit (0.65V±1%)
Built-in VCC Undervoltage Lockout Circuit
(VCC=3.80V)
NRCS (Soft-start) Function Reduces the
Magnitude of In-rush Current
Built-in N-Channel MOSFET
Built-in Current Limit Circuit (3.0A min)
Built-in Thermal Shutdown (TSD) Circuit (Timer
latch)
Tracking Function
Key Specifications
IN Input Voltage Range: 0.7V to VCC-1V
VCC Input Voltage Range: 4.3V to 5.5V
Output Voltage Range: 0.65V to 2.7V
Output Current: 3.0A (Max)
ON-Resistance: 65mΩ(Typ)
Standby Current: 0μA (Typ)
Operating Temperature: -10°C to +100°C
Package W(Typ) x D(Typ) x H(Max)
Applications
Notebook and Desktop computers, LCD-TV, DVD,
Digital appliances
Typical Application Circuit and Block Diagram
VQFN020V4040
4.00mm x 4.00mm x 1.00mm
Reference
Block
VIN
UVLOLATCH
Current
Limit
EN
VCC
VCC
VCC
VCC
EN
UVLO1
UVLO2
VREF
GND
CL
UVLO1
UVLO2
TSD
SCP
EN
UVLO1
CL
VCC
VREF
X 0.7
SCP
NRCS
6
7
2
20
NRCS
TSD
NRCS x 0.3
VREF x 0.4
FB
SCP/TSD
LATCH
LATCH
EN
UVLO1
EN/UVLO
NRCS
VD
IN
OUT
FB
IN
OUT
R2
R1
R2
R1
19
18
17
16
15
14
13
12
11
10
9
8
C1
C2
C3
CNRCS
CSCP
1
CFB
5
VDD
3
POWER
GOOD
4
PG
PGDLY
Datashee
t
Datashee
t
2/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Pin Configuration
Pin Descriptions
Pin No.
Pin Name
PIN Function
1
GND1
Ground pin 1
2
SCP
SCP delay time setting capacitor
connection pin
3
PGDLY
PGOOD delay setting
capacitor connection pin
4
PG
Power good pin
5
VDD
Power supply pin
6
VCC
Power supply pin
7
EN
Enable input pin
8
VD
IN input voltage detect pin
9
IN1
Input voltage pin 1
10
IN2
Input voltage pin 2
11
IN3
Input voltage pin 3
12
IN4
Input voltage pin 4
13
IN5
Input voltage pin 5
14
OUT1
Output voltage pin 1
15
OUT 2
Output voltage pin 2
16
OUT 3
Output voltage pin 3
17
OUT 4
Output voltage pin 4
18
OUT 5
Output voltage pin 5
19
FB
Reference voltage feedback pin
20
NRCS
In-rush current protection (NRCS)
capacitor connection pin
bottom
FIN
Connected to heat sink and GND
(Note) Please short N.C to the GND line.
Description of Blocks
1. AMP
This is an error amplifier, which compares the reference voltage (0.65V) to FB voltage to drive the output N-Channel FET.
Frequency optimization aids in attaining rapid transient response, and to support the use of ceramic capacitors on the
output. AMP output voltage ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and
the output of the N-Channel FET switches to OFF state.
2. EN
The EN block controls the ON and OFF state of the regulator via the EN logic input pin. During OFF state, circuit voltage
stabilizes at 0μA which minimizes the current consumption during standby mode. The FET is switched ON to enable the
discharge of NRCS and OUT, thereby draining the excess charge and preventing the load side of an IC from
malfunctioning. Since there is no electrical connection required (e.g. between the VCC pin and the ESD prevention
diode), module operation is independent of the input sequence.
3. UVLO
To prevent malfunctions that can occur during sudden decrease in VCC, the UVLO circuit switches the output to OFF
state, and (like the EN block) discharges NRCS and OUT. Once the UVLO threshold voltage (TYP3.80V) is reached, the
power-ON reset is triggered and the output is restored.
4. CURRENT LIMIT
During ON state, it monitors the output current of the IC against the current limit value. When the output current exceeds
this value, this block lowers the output current to protect the load of the IC. When it overcomes the overcurrent state,
output voltage is restored to allowable value.
5. NRCS (Non Rush Current on Start-up)
The soft start function is enabled by connecting an external capacitor between the NRCS pin and ground. Output
ramp-up can be set to any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves
as a constant current source about 20μA (TYP) to charge the external capacitor. Capacitors with low susceptibility
(0.001µF to 1µF) to temperature are recommended, in order to assure a stable soft-start time.
16
17
18
19
20
1
2
3
4
5
10
9
8
7
6
15
14
13
12
11
IN5
IN4
IN3
VDD
PG
PGDLY
SCP
GND1
IN2
IN1
VD
EN
VCC
OUT3
OUT 4
OUT 5
FB
NRCS
FIN
TOP VIEW
OUT1
OUT2
3/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
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TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Description of Blocks –continued
6. TSD (Thermal Shut down)
The shutdown (TSD) circuit is automatically latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus protecting the IC against “thermal runaway” and heat damage. Since the
TSD circuit is designed only to shut down the IC in the occurrence of extreme heat, it is important that the Tj(max)
parameter should not be exceeded in the thermal design, in order to avoid potential problems with the TSD.
7. IN
The IN line acts as the major current supply line, and is connected to the output N-Channel FET drain. Since there is no
electrical connection (such as between the VCC pin and the ESD protection diode) required, IN operates independent of
the input sequence. However, since an output N-Channel FET body diode exists between IN and OUT, a VIN-VOUT
electric (diode) connection is present. Therefore, when output is switched ON or OFF, reverse current may flow from
OUT to IN.
8. PGOOD
It determines the status of the output voltage. This is an open-drain pin, which is connected to VCC pin through the
pull-up resistance (100kΩ or so). When the output voltage ranges from VOUT x 0.9 to VOUT x 1.1(TYP), the status is high.
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Limit
Unit
Input Voltage 1
VCC
6.0 (Note 1)
V
Input Voltage 2
VIN
6.0 (Note 1)
V
Input Voltage 3
VDD
6.0 (Note 1)
V
Input Voltage 4
VVD
1
V
Maximum Output Current
IOUT
3 (Note 1)
A
Enable Input Voltage
VEN
6.0
V
PGOOD Input Voltage
VPGOOD
6.0
V
Power Dissipation 1
Pd1
0.34 (Note 2)
W
Power Dissipation 2
Pd2
0.70 (Note 3)
W
Power Dissipation 3
Pd3
2.21 (Note 4)
W
Power Dissipation 4
Pd4
3.56 (Note 5)
W
Operating Temperature Range
Topr
-10 to +100
°C
Storage Temperature Range
Tstg
-55 to +125
°C
Maximum Junction Temperature
Tjmax
+150
°C
(Note 1) Should not exceed Pd.
(Note 2) Derating in done 2.7mV/°C for operating above Ta ≥ 25°C no heat sink
(Note 3) Derating in done 5.6mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 1-layer glass epoxy board(copper foil area : 10.29mm2)
(Note 4) Derating in done 17.7mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : front and reverse 10.29mm2 , 2nd and 3rd
5505mm2)
(Note 5) Derating in done 28.5mV/°C for operating above Ta ≥ 25°C
PCB size:74.2mm x 74.2mm x 1.6mm when mounted on a 4-layer glass epoxy board(copper foil area : each 5505mm2)
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions (Ta=25°C)
Parameter
Symbol
Min
Max
Unit
Input Voltage 1
VCC
4.3
5.5
V
Input Voltage 2
VIN
0.7
VCC-1 (Note 6)
V
Input Voltage 3
VDD
4.5
5.5
V
Output Voltage Setting Range
VOUT
VFB
2.7
V
Enable Input Voltage
VEN
-0.3
+5.5
V
(Note 6) VCC and IN do not have to be implemented in the order listed.
4/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Electrical Characteristics
(Unless otherwise specified, Ta=25°C, VCC=5V, VEN=3V, VIN=1.7V, R1=3.9kΩ, R2=3.3kΩ)
Parameter
Symbol
Limit
Unit
Conditions
Min
Typ
Max
Circuit Current
ICC
-
1.4
2.2
mA
VCC Shutdown Mode Current
IST
-
0
10
µA
VEN=0V
Maximum Output Current
IOUT
3.0
-
-
A
Output Voltage Temperature
Coefficient
Tcvo
-
0.01
-
%/°C
Feedback Voltage 1
VFB1
0.643
0.650
0.657
V
Feedback Voltage 2
VFB2
0.637
0.650
0.663
V
IOUT=0A to 3A
Tj=-10°C to +100°C
Line Regulation 1
Reg.l1
-
0.1
0.5
%/V
VCC=4.3V to 5.5V
Line Regulation 2
Reg.l2
-
0.1
0.5
%/V
VIN=1.5V to 3.3V
Load Regulation
Reg.L
-
0.5
10
mV
IOUT=0A to 3A
Minimum dropout voltage
dVo
-
65
100
mV
IOUT=1A,VIN=1.2V
Standby Discharge Current
IDEN
1
-
-
mA
VEN=0V, VOUT=1V
[ENABLE]
Enable Pin
Input Voltage High
VENHI
2
-
-
V
Enable Pin
Input Voltage Low
VENLOW
-0.2
-
+0.8
V
Enable Input Bias Current
IEN
-
6
10
µA
VEN=3V
[FEEDBACK]
Feedback Pin Bias Current
IFB
-100
0
+100
nA
[NRCS]
NRCS Charge Current
INRCS
14
20
26
µA
VNRCS=0.5V
NRCS Standby Voltage
VSTB
-
0
50
mV
VEN=0V
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage
VCCUVLO
3.5
3.8
4.1
V
VCC: Sweep-up
VCC Undervoltage Lockout
Hysteresis Voltage
VCCHYS
100
160
220
mV
VCC: Sweep-down
VD Undervoltage Lockout
Threshold Voltage
VDUVLO
VREF x 0.6
VREF x 0.7
VREF x 0.8
V
VD: Sweep-up
[SCP]
SCP Startup Voltage
VOUTSCP
VOUT x 0.3
VOUT x 0.4
VOUT x 0.5
V
SCP Threshold Voltage
VSCPTH
1.05
1.15
1.25
V
SCP Charge Current
ISCP
1.4
2
2.6
µA
SCP Standby Voltage
VSCPSTBY
-
-
50
mV
[PGOOD]
Low-side Threshold Voltage
VTHPGL
VOUT x
0.87
VOUT x 0.9
VOUT x 0.93
V
High-side Threshold Voltage
VTHPGH
VOUT x
1.07
VOUT x 1.1
VOUT x 1.13
V
PGDLY Charge Current
IPGDLY
1.4
2.0
2.6
µA
(Note)
Ron
RPG
-
0.1
-
kΩ
(Note) PGOOD delay time is determined using the formula below:
sec
AI 23.1pFC
tPGDLY
PGDLY
5/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Typical Waveforms
Figure 4. Transient Response
(3A to 0A)
COUT=22μF, CFB=1000pF
Figure 1. Transient Response
(0A to 3A)
COUT=22μF, CFB=1000pF
VOUT
IOUT
1A/div
50mV/div
IOUT=0A to 3A/3µsec
3.0A
t(10µsec/div)
Figure 2. Transient Response
(0A to 3A)
COUT=100μF
VOUT
IOUT
1A/div
50mV/div
IOUT=0A to 3A/3µsec
3.0A
t(4µsec/div)
Figure 3. Transient Response
(0A to 3A)
COUT=100μF, CFB=1000pF
VOUT
IOUT
3.0A
50mV/div
1A/div
IOUT=0A to 3A/3µsec
t(4µsec/div)
IOUT
VOUT
3.0A
50mV/div
1A/div
IOUT=3A to 0A/3µsec
t(40µsec/div)
6/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Typical Waveforms – continued
Figure 5. Transient Response
(3A to 0A)
COUT=100μF
VOUT
50mV/div
IOUT
1A/div
IOUT=3A to 0A/3µsec
3.0A
t(100µsec/div)
Figure 6. Transient Response
(3A to 0A)
COUT=100μF, CFB=1000pF
VOUT
50mV/div
IOUT
1A/div
3.0A
IOUT=3A to 0A/3µsec
t(100µsec/div)
Figure 7. Waveform at Output Start
t(100µsec/div)
500mV/div
VOUT
2V/div
1V/div
VNRCS
VEN
Figure 8. Waveform at Output OFF
2V/div
1V/div
VNRCS
VOUT
500mV/div
VEN
t(2msec/div)
7/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Typical Waveforms – continued
Figure 9. Input Sequence
Figure 10. Input Sequence
Figure 12. Input Sequence
VCC
2V/div
2V/div
5V/div
1V/div
VEN
VIN
VOUT
VCC to VIN to VEN
2V/div
2V/div
5V/div
1V/div
VCC
VEN
VIN
VOUT
VIN to VCC to VEN
5V/div
2V/div
2V/div
1V/div
VCC to VEN to VIN
VOUT
VIN
VEN
VCC
Figure 11. Input Sequence
5V/div
2V/div
2V/div
1V/div
VEN to VCC to VIN
VOUT
VIN
VEN
VCC
9/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Typical Performance Curves
Figure 15. Output Voltage vs Temperature
Output Voltage : VOUT (V)
Temperature : Ta [°C]
1.23
1.22
1.21
1.20
1.19
1.18
1.17
-50 -25 0 25 50 75 100 125 150
Figure 16. Circuit Current vs Temperature
-50 -25 0 25 50 75 100 125 150
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
Temperature : Ta [°C]
Circuit Current : ICC (mA)
Figure 17. ISTB vs Temperature
-50 -25 0 25 50 75 100 125 150
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Temperature : Ta [°C]
ISTB [µA]
Figure 18. IINSTB vs Temperature
-50 -25 0 25 50 75 100 125 150
50
45
40
35
30
25
20
15
10
5
0
Temperature : Ta [°C]
IINSTB [µA]
10/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
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TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Typical Performance Curves – continued
Figure 19. NRCS Charge Current vs Temperature
-50 -25 0 25 50 75 100 125 150
24
22
20
18
16
14
12
Temperature : Ta [°C]
NRCS Charge Current : INRCS (µA)
Figure 20. Enable Input Bias Current vs Temperature
-50 -25 0 25 50 75 100 125 150
10
9
8
7
6
5
4
3
2
1
0
Enable Input Bias Current : IEN (µA)
Temperature : Ta [°C]
Figure 21. ON-Resistance vs Temperature
(VCC=5V/VOUT=1.2V)
-50 -25 0 25 50 75 100 125 150
80
70
60
50
40
30
20
10
0
ON-Resistance : RON [mΩ]
Temperature : Ta [°C]
Figure 22. ON-Resistance vs Temperature
(VCC=5V/VOUT=1.5V)
-50 -25 0 25 50 75 100 125 150
80
70
60
50
40
30
20
10
0
ON-Resistance : RON [mΩ]
Temperature : Ta [°C]
11/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Typical Performance Curves – continued
Figure 23. ON-Resistance vs Supply Voltage
3 5 7
50
45
40
35
Supply Voltage : VCC [V]
ON-Resistance : RON [mΩ]
VOUT=2.5V
VOUT=1.8V
VOUT=1.7V
VOUT=1.5V
VOUT=1.2V
12/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Timing Chart
EN ON/OFF
VCC ON/OFF
IN
VCC
EN
NRCS
OUT
t
Startup
0.65V(typ)
VOUT x 0.9V(typ)
60µs(typ)
PGOOD
(typ@ C=100pF)
IN
VCC
EN
NRCS
OUT
t
Hysteresis
UVLO
Startup
0.65V(typ)
VOUT x 0.9V(typ)
60us (typ@100pF)
PGOOD
14/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Application Information
1. Evaluation Board
Component
Rating
Manufacturer
Product Name
Component
Rating
Manufacturer
Product Name
U1
-
ROHM
BD3512MUV
R8
3.9kΩ
ROHM
MCR03EZPF3901
C2
100pF
MURATA
CRM1882C1H101JA01
R9
3.3kΩ
ROHM
MCR03EZPF3301
C3
100pF
MURATA
CRM1882C1H101JA01
C9
10µF
KYOCERA
CM21B106M06A
R4
100kΩ
ROHM
MCR03EZPF1003
C16
22µF
KYOCERA
CM316B226M06A
C5
0.1µF
KYOCERA
CM05104K10A
R18
3.3kΩ
ROHM
MCR03EZPF3301
C6
1µF
KYOCERA
CM105B105K06A
R19
3.9kΩ
ROHM
MCR03EZPF3901
R7
0Ω
-
Jumper
V20
0.01µF
MURATA
GRM188B11H102KA01
■
■
BD3512MUV Evaluation Board Schematic
■
■
BD3512MUV Evaluation Board Standard Component List
16
17
18
19
20
1
2
3
4
5
10
9
8
7
6
15
14
13
12
11
OUT3
OUT4
OUT5
FB
NRCS
VIN
C9
C10
C11
C12
1
JP9
VINS
R9
R8
VD
EN
R7
VCC
VCC
C7
H
L
SW1
C6
VDD
C5
JP4B
PG
VCC
R4
JP4
VPG
C3
C2
PGDLY
SCP
GND1
GND2
SGND
C20
NRCS
FB
R19
R18
C18
JP18
VO_S
C15
C16
VO
R14
C14
RLD
U2
U1
RF1
RF2
INF
JPF1
JPF2
VCC
INV
RF2
CF
U3
1
1
1
1
1
1
GND1
SCP
PGDLY
PG
VDD
VCC
EN
VD
IN1
IN2
OUT2
OUT1
IN5
IN4
IN3
1
1
1
1
1
1
1
1
1
15/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
2. Recommended Circuit Example
■
■
BD3512MUV Evaluation Board Layout
Silk Screen (Bottom)
Bottom Layer
Silk Screen (Top)
Middle Layer_1
Middle Layer_2
TOP Layer
Vo (1.2V/3A)
C16
C20
R19
R18
16
17
18
19
20
1
2
3
4
5
15
14
13
12
11
10
9
8
7
6
C9
VIN
C6
VCC
VEN
R4
VPGOOD
VDD
C5
CFB
C2
C3
R9
R8
16/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
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TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
Component
Recommended
Value
Programming Notes and Precautions
R18/R19
3.3kΩ/3.9kΩ
IC output voltage can be set by the formula VFB X (R18+R19)/R19 using the values for the
internal reference output voltage (VFB) and the output voltage resistors (R18, R19). Select
resistance values that will avoid the impact of the FB bias current (±100nA). The
recommended total resistance value is 10KΩ.
R4
100kΩ
This is the pull-up resistance for open-drain pin. It is recommended to set the value about
100kΩ.
C16
22µF
To assure output voltage stability, please be certain that OUT1 to OUT5 pins and the GND
pins are connected. Output capacitors play a role in loop gain phase compensation and in
mitigating output fluctuation during rapid changes in load level. Insufficient capacitance
may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate
output voltage fluctuation under rapid load change conditions. While a 22µF ceramic
capacitor is recommended, actual stability is highly dependent on temperature and load
conditions. Also, note that connecting different types of capacitors in series may result in
insufficient total phase compensation, thus causing oscillation. Please confirm operation
across a variety of temperature and load conditions.
C6/C5
1µF/0.1µF
Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC,VDD) input pins. If the impedance of this power supply were to increase, input
voltage (VCC,VDD) could become unstable, leading to oscillation or lowering ripple rejection
function. While a low-ESR 1µF/0.1µF capacitor with minimal susceptibility to temperature
is recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. Please confirm operation across a variety of temperature
and load conditions.
C9
10µF
Input capacitors reduce the output impedance of the voltage supply source connected to
the (IN) input pins. If the impedance of this power supply were to increase, input voltage
(VIN) could become unstable, leading to oscillation or lowering ripple rejection function.
While a low-ESR 10µF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. Please confirm operation across a variety of temperature and
load conditions.
C20
0.01µF
The Non-Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (IN to OUT) and affects output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or when
the UVLO function is deactivated. The temporary reference voltage is proportional to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportional to this reference voltage. Capacitors with low susceptibility to temperature
are recommended to ensure a stable soft-start time.
CFB
1000pF
This component is employed when the C16 capacitor causes, or may cause, oscillation. It
provides more precise internal phase compensation.
17/23
BD3512MUV
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TSZ02201-0J2J0A601120-1-2
02.Nov.2015 Rev.001
3. Heat Loss
In thermal design, consider the temperature range wherein the IC is guaranteed to operate and apply appropriate
margins. The temperature conditions that need to be considered are listed below:
(1) Ambient temperature (Ta) should not be higher than 100°C.
(2) Chip junction temperature (Tj) should not be higher than 150°C.
The chip’s junction temperature can be determined as follows:
It is recommended to layout multiple VIAs, for heat radiation, in the GND pattern of reverse (of IC) when there is the
GND pattern in the inner layer (in using multi-layer substrate). This package is so small (size: 4.0mm x 4.0mm) to layout
the VIA at the bottom of IC. Spreading the pattern and increasing the number of VIA, as shown in the figure below,
enable to achieve most heat radiation characteristics. It is recommended that the size and number of VIA are designed
suitable for the actual application (see figure below).
Most heat loss in BD3512MUV occurs at the output N-Channel FET. Power loss is determined by multiplying the total
VIN-VOUT voltage by the output current. Be sure to confirm the system input-to-output voltage and the output current
conditions in relation to the heat dissipation characteristics of the IN and OUT in the design. Considering that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3512MUV) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VIN)- Output voltage (VOUT) (VOUT ≈ VREF) x IOUT(Ave)
For instance, VIN=1.5V, VOUT=1.25V, IOUT(Ave) = 3A,
① Calculation based on ambient temperature (Ta)
WajTaTj
IC only
1-layer board(copper foil area : 10.29mm2)
4-layer board(copper foil area : front and reverse 10.29mm2 , 2nd and 3rd 5505mm2)
4-layer board(copper foil area : each 5505mm2)
Substrate size: 74.2 x 74.2 x 1.6mm3 (substrate with thermal via)
<Reference values>
θj-a:VQFN020V4040 367.6°C/W
178.6°C/W
56.6°C/W
35.1°C/W
W
AVVWnconsumptioPower
75.0
0.325.15.1
18/23
BD3512MUV
© 2015 ROHM Co., Ltd. All rights reserved.
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TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
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Power Dissipation
I/O Equivalent Circuits
① 4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=35.1°C/W
② 4 layers (Copper foil area front and reverse : 10.29mm2、
2nd and 3rd : 5505mm2)
θj-a=56.6°C/W
③ 1 layer (Copper foil area : 10.29m2)
θj-a=178.6°C/W
④ IC only.
θj-a=367.6°C/W
PGOOD
VCC
OUT1
OUT2
1kΩ
OUT3
OUT4
OUT5
NRCS
VCC
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
IN1
IN2
IN3
IN4
IN5
VCC
FB
1kΩ
400kΩ
EN
Power Dissipation:Pd [W]
Ambient temperature:Ta [°C]
0
25
50
75
100
125
150
0
2.0
3.0
4.0
②2.21W
①3.56W
1.0
③0.70W
④0.34W
105
19/23
BD3512MUV
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TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
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Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6. Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8. Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
20/23
BD3512MUV
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Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Figure 24. Example of monolithic IC structure
13. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
14. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. The IC should be
powered down and turned ON again to resume normal operation because the TSD circuit keeps the outputs at the
OFF state even if the TJ falls below the TSD threshold.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
15. Output Pin
In the event that load containing a large inductance component is connected to the output terminal, and generation of
back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.
TSD on Temperature [°C] (typ)
BD3512MUV
175
N N
P+PN N
P+
P Substrate
GND
NP+N N
P+
NP
P Substrate
GND GND
Parasitic
Elements
Pin A
Pin A
Pin B Pin B
B C
EParasitic
Elements
GND
Parasitic
Elements
CB
E
Transistor (NPN)Resistor
N Region
close-by
Parasitic
Elements
OUTPUT PIN
(Example)
21/23
BD3512MUV
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TSZ22111・15・001
TSZ02201-0J2J0A601120-1-2
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Ordering Information
Marking Diagram
B
D
3
5
1
2
M
U
V
-
E 2
Part Number
Package
MUV: VQFN020V4040
Packaging and forming specification
E2: Emboss tape reel opposite draw-out side: 1 pin
VQFN020V4040 (TOP VIEW)
D 3 5 1 2
Part Number Marking
LOT Number
1PIN MARK
Datasheet
Datasheet
Notice-PGA-E Rev.00
2
© 2015 ROHM Co., Ltd. All rights reserved.
Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for applicatio n in ordinar y elec tronic eq uipm ents (such as AV equipment ,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred b y you or third parties arisin g from the use of an y ROHM’s Prod ucts for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN USA EU CHINA
CLASSⅢ CLASSⅢ CLASSⅡb CLASSⅢ
CLASSⅣ CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe d esign against the physical injur y, damage to any property, which
a failure or malfunction of our Products may cause. T he following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
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product performance, reliabili ty, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
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[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
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[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flu x (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radi ation-proof design.
5. Please verify and confirm ch aracteristics of the final or mounted products in using the Pro ducts.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depen ding on ambient temperature. W hen used in sealed area, confirm that it is the us e in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant co ndition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogen ous (chlori ne, bromine, etc.) flu x is used, the residue of flux may negativel y affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM represe ntative in advance.
For details, please refer to ROHM Mounting specification
Datasheet
Datasheet
Notice-PGA-E Rev.00
2
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise you r own indepen dent verificatio n and judgmen t in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please t ake special care under dry condit ion (e.g. Grounding of human body / equipment / sol der iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportati on
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to s ea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderabilit y of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommen de d storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive s t ress applied when dropping of a carton.
4. Use Products within the specified tim e after opening a humidity barrier bag. Baking is required before using Products of
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When disposing Products pl ease dispose them properly us ing an authorized industr y waste company.
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ROHM, its affiliated companies or third parties.
DatasheetDatasheet
Notice – WE Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
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