REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
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a
AD7810
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
2.7 V to 5.5 V, 2.3 ␮s, 10-Bit
ADC in 8-Lead microSOIC/DIP
FUNCTIONAL BLOCK DIAGRAM
CLOCK
OSC
DOUT
SCLK
VREF
AGND
VDD
VIN+
VIN–
CONVST
SERIAL
PORT
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
AD7810
COMP
VDD/3
FEATURES
10-Bit ADC with 2.3 ␮s Conversion Time
Small Footprint 8-Lead microSOIC Package
Specified Over a –40ⴗC to +105ⴗC Temperature Range
Inherent Track-and-Hold Functionality
Operating Supply Range: 2.7 V to 5.5 V
Specifications at 2.7 V to 5.5 V
Microcontroller-Compatible Serial Interface
Optional Automatic Power-Down
at End of Conversion
Low Power Operation
270 ␮W at 10 kSPS Throughput Rate
2.7 mW at 100 kSPS Throughput Rate
Analog Input Range: 0 V to VREF
Reference Input Range: 0 V to VDD
APPLICATIONS
Low Power, Hand-Held Portable Applications that
Require Analog-to-Digital Conversion with 10-Bit
Accuracy; e.g., Battery Powered Test Equipment,
Battery-Powered Communications Systems
GENERAL DESCRIPTION
The AD7810 is a high speed, low power, 10-bit A/D con-
verter that operates from a single 2.7 V to 5.5 V supply. The
part contains a 2.3 µs successive approximation A/D converter,
with inherent track/hold functionality, a pseudo differential
input and a high speed serial interface that interfaces to most
microcontrollers. The AD7810 is fully specified over a tem-
perature range of –40°C to +105°C.
By using a technique that samples the state of the CONVST
(convert start) signal at the end of a conversion, the AD7810
may be used in an automatic power-down mode. When used in
this mode, the AD7810 automatically powers down at the end
of a conversion and “wakes up” at the start of a new conversion.
This feature significantly reduces the power consumption of the
part at lower throughput rates. The AD7810 can also operate in
a high speed mode where the part is not powered down between
conversions. In this high speed mode of operation, the conver-
sion time of the AD7810 is 2.3 µs. The maximum throughput
rate is dependent on the speed of the serial interface of the
microcontroller.
The part is available in a small 8-lead, 0.3" wide, plastic dual-
in-line package (mini-DIP); in an 8-lead, small outline IC
(SOIC); and in an 8-lead microSOIC package.
PRODUCT HIGHLIGHTS
1. Complete, 10-Bit ADC in 8-Lead Package
The AD7810 is a 10-bit 2.3 µs ADC with inherent track/hold
functionality and a high speed serial interface—all in an
8-lead microSOIC package. V
REF
may be connected to V
DD
to eliminate the need for an external reference. The result is
a high speed, low power, space saving ADC solution.
2. Low Power, Single Supply Operation
The AD7810 operates from a single 2.7 V to 5.5 V supply
and typically consumes only 9 mW of power while convert-
ing. The power dissipation can be significantly reduced at
lower throughput rates by using the automatic power-down
mode, e.g., at a throughput rate of 10 kSPS the power
consumption is only 270 µW.
3. Automatic Power-Down
The automatic power-down mode, whereby the AD7810
powers down at the end of a conversion and “wakes up”
before the next conversion, means the AD7810 is ideal for
battery powered applications. See Power vs. Throughput
Rate section.
4. Serial Interface
An easy to use, fast serial interface allows connection to most
popular microprocessors with no external circuitry.
–2– REV. B
AD7810–SPECIFICATIONS
Parameter Y Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE f
IN
= 30 kHz, f
SAMPLE
= 350 kHz
Signal to (Noise + Distortion) Ratio
1
58 dB min
Total Harmonic Distortion
1
–64 dB max
Peak Harmonic or Spurious Noise –64 dB max
Intermodulation Distortion
2
fa = 48 kHz, fb = 48.5 kHz
2nd Order Terms –67 dB typ
3rd Order Terms –67 dB typ
DC ACCURACY
Resolution 10 Bits
Relative Accuracy
1
±1 LSB max
Differential Nonlinearity (DNL)
1
±1 LSB max
Offset Error
1
±2 LSB max
Gain Error
1
±2 LSB max
Minimum Resolution for Which
No Missing Codes Are Guaranteed 10 Bits
ANALOG INPUT
Input Voltage Range 0 V min
V
REF
V max
Input Leakage Current
2
±1µA max
Input Capacitance
2
15 pF max
REFERENCE INPUTS
2
V
REF
Input Voltage Range 1.2 V min
V
DD
V max
Input Leakage Current ±3µA max
Input Capacitance 20 pF max
LOGIC INPUTS
2
V
INH
,
Input High Voltage 2.0 V min
V
INL
, Input Low Voltage 0.4 V max
Input Current, I
IN
±1µA max Typically 10 nA, V
IN
= 0 V to V
DD
Input Capacitance, C
IN
8 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
2.4 V min I
SOURCE
= 200 µA
Output Low Voltage, V
OL
0.4 V max I
SINK
= 200 µA
High Impedance Leakage Current ±10 µA max
High Impedance Capacitance 15 pF max
CONVERSION RATE
Conversion Time 2.3 µs max
Track/Hold Acquisition Time
1
100 ns max See DC Acquisition Time Section
POWER SUPPLY
V
DD
2.7–5.5 Volts For Specified Performance
I
DD
3.5 mA max Sampling at 350 kSPS and Logic
Power Dissipation 17.5 mW max Inputs at V
DD
or 0 V. V
DD
= 5 V
Power-Down Mode
I
DD
1µA max V
DD
= 5 V; V
DD
= 3 V
Power Dissipation 5 µW max
Automatic Power Down
1 kSPS Throughput 27 µW max
10 kSPS Throughput 270 µW max
100 kSPS Throughput 2.7 mW max
NOTES
1
See Terminology section.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
(GND = 0 V, VREF = VDD. All specifications –40ⴗC to +105ⴗC unless otherwise noted.)
AD7810
–3–
REV. B
Timing Characteristics
1, 2
Parameter V
DD
= 5 V ⴞ 10% V
DD
= 3 V ⴞ 10% Unit Conditions/Comments
t
1
2.3 2.3 µs (max) Conversion Time Mode 1 Operation (High Speed Mode)
t
2
20 20 ns (min) CONVST Pulsewidth
t
3
25 25 ns (min) SCLK High Pulsewidth
t
4
25 25 ns (min) SCLK Low Pulsewidth
t
53
5 5 ns (min) CONVST Rising Edge to SCLK Rising Edge Set-Up Time
t
63
10 10 ns (max) SCLK Rising Edge to D
OUT
Data Valid Delay
t
73
5 5 ns (max) Data Hold Time after Rising Edge SCLK
t
83, 4
20 20 ns (max) Bus Relinquish Time after Falling Edge of SCLK
10 10 ns (min)
t
POWER UP
1.5 1.5 µs (max) Power-Up Time after Rising Edge of CONVST
NOTES
1
Sample tested to ensure compliance.
2
See Figures 14, 15 and 16.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD
= 5 V ± 10% and
0.4 V or 2 V for V
DD
= 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(–40ⴗC to +105ⴗC, VREF = VDD, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND
(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(D
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Analog Inputs
(V
IN+
, V
IN–
) . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W
Lead Temperature Soldering (10 sec) . . . . . . . . . . . 260°C
I
OL
200␮A
I
OH
200␮A
1.6V
C
L
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing Specifications
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Linearity Temperature Package Package Branding
Model Error (LSB) Range Description Options Information
AD7810YN ±1 LSB –40°C to +105°C Plastic DIP N-8
AD7810YR ±1 LSB –40°C to +105°C Small Outline IC (SOIC) SO-8
AD7810YRM ±1 LSB –40°C to +105°C microSOIC RM-8 C1Y
AD7810
–4–REV. B
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1CONVST Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion.
A rising edge on the CONVST pin enables the serial port of the AD7810. This is useful in multi-
package applications where a number of devices share the same serial bus. The state of this pin at
the end of conversion also determines whether the part is powered down or not. See Operating
Modes section of this data sheet.
2V
IN+
Positive input of the pseudo differential analog input.
3V
IN–
Negative input of the pseudo differential analog input.
4 GND Ground reference for analog and digital circuitry.
5V
REF
External reference is connected here.
6D
OUT
Serial data is shifted out on this pin.
7 SCLK Serial Clock. An external serial clock is applied here.
8V
DD
Positive Supply Voltage 2.7 V to 5.5 V.
PIN CONFIGURATION
DIP/SOIC
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD7810
CONVST
VIN+
VIN–
GND
VDD
SCLK
DOUT
VREF
THROUGHPUT – kSPS
10
1
0.01030
POWER – mW
10
0.1
20 40 50
Figure 2. Power vs. Throughput
Typical Performance Characteristics
FREQUENCY BINS
–115
dBs
–95
1
23
45
67
89
111
133
155
177
199
221
243
265
287
309
331
353
375
397
419
441
463
485
507
529
551
573
595
617
639
661
683
705
727
749
771
793
815
837
859
881
903
925
947
969
991
1013
–75
–55
–35
–15 2048 POINT FFT
SAMPLING 357.142kSPS
FIN = 30kHz
Figure 3. AD7810 SNR
AD7810
–5–
REV. B
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels in
the digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 10-bit converter, this is 62 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7810 it is defined as:
THD dB
()
=20 log V
2
2
+V
3
2
+V
4
2
+V
5
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
62
are the rms amplitudes of the second through
the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms values of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7810 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of differ-
ent significance. The second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
fundamental expressed in dBs.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
This is the deviation of the last code transition (1111 . . . 110)
to (1111 . . . 111) from the ideal (i.e., V
REF
– 1 LSB) after the
offset error has been adjusted out.
Track/Hold Acquisition Time
Track/hold acquisition time is the time required for the output of
the track/hold amplifier to reach its final value, within ±1/2 LSB,
after the end of conversion (the point at which the track/hold
returns to track mode). It also applies to situations where there
is a step input change on the input voltage applied to the V
IN+
input of the AD7810. It means that the user must wait for the
duration of the track/hold acquisition time, after the end of conver-
sion or after a step input change to V
IN+
, before starting another
conversion to ensure that the part operates to specification.
AD7810
–6–REV. B
CIRCUIT DESCRIPTION
Converter Operation
The AD7810 is a successive approximation analog-to-digital
converter based around a charge redistribution DAC. The ADC
can convert analog input signals in the range 0 V to V
DD
. Fig-
ures 4 and 5 below show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A; the comparator is held in a
balanced condition; and the sampling capacitor acquires the
signal on V
IN+
.
V
DD
/3
V
IN
+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
ACQUISITION
PHASE SW2
A
SW1
B
V
IN
–
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to Position B, causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 11 shows the ADC transfer function.
V
DD
/3
V
IN
+
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE SW2
A
SW1
B
V
IN
–
Figure 5. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7810. The
serial interface is implemented using two wires; the rising edge
of CONVST enables the serial interface—see Serial Interface
section for more details. V
REF
is connected to a well decoupled
V
DD
pin to provide an analog input range of 0 V to V
DD
. When
V
DD
is first connected, the AD7810 powers up in a low current
mode, i.e., power-down. A rising edge on the CONVST input
will cause the part to power up—see Operating Modes. If power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power perfor-
mance. See Power vs. Throughput Rate section of the data sheet.
D
OUT
SCLK
V
REF
AGND
V
DD
V
IN
+
V
IN
–
CONVST
SUPPLY
2.7V TO 5.5V
0V TO V
REF
INPUT
AD7810
0.1␮F10␮FTWO WIRE
SERIAL
INTERFACE
␮C/␮P
Figure 6. Typical Connection Diagram
Analog Input
Figure 7 shows an equivalent circuit of the analog input struc-
ture of the AD7810. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 200 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
The maximum current these diodes can conduct without caus-
ing irreversible damage to the part is 20 mA. The capacitor C2
is typically about 4 pF and can be primarily attributed to pin
capacitance. The resistor R1 is a lumped component made up of
the on resistance of a multiplexer and a switch. This resistor is
typically about 125 Ω. The capacitor C1 is the ADC sampling
capacitor and has a capacitance of 3.5 pF.
VDD
VIN+
C1
3.5pF
R1
125⍀
VDD/3
D2
D1
C2
4pF
CONVERT PHASE – SWITCH OPEN
ACQUISITION PHASE – SWITCH CLOSED
Figure 7. Equivalent Analog Input Circuit
The analog input of the AD7810 is made up of a pseudo differ-
ential pair. V
IN+
pseudo differential with respect to V
IN–
. The
signal is applied to V
IN+
, but in the pseudo differential scheme
the sampling capacitor is connected to V
IN–
during conversion
(see Figure 8). This input scheme can be used to remove offsets
that exist in a system. For example, if a system had an offset of
0.5 V, the offset could be applied to V
IN–
and the signal applied
to V
IN+
. This has the effect of offsetting the input span by 0.5 V.
It is only possible to offset the input span when the reference
voltage (V
REF
) is less than V
DD
– V
OFFSET
.
V
DD
/3
V
IN
+
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
SAMPLING
CAPACITOR
CONVERSION
PHASE SW2
V
IN
–
CHARGE
REDISTRIBUTION
DAC
V
OFFSET
V
IN
(+)
V
OFFSET
Figure 8. Pseudo Differential Input Scheme
AD7810
–7–
REV. B
When using the pseudo differential input scheme, the signal on
V
IN–
must not vary by more than a 1/2 LSB during the conver-
sion process. If the signal on V
IN–
varies during conversion, the
conversion result will be incorrect. For single-ended operation,
V
IN–
is always connected to AGND. Figure 9 shows the AD7810
pseudo differential input being used to make a unipolar dc cur-
rent measurement. A sense resistor is used to convert the current
to a voltage and the voltage, is applied to the differential input
as shown.
VDD
RSENSE
RL
VIN+
VIN–
AD7810
Figure 9. DC Current Measurement Scheme
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends on the falling edge of the CONVST signal. At the
end of a conversion there is a settling time associated with the
sampling circuit. This settling time lasts approximately 100 ns.
The analog signal on V
IN+
is also being acquired during this
settling time; therefore, the minimum acquisition time needed is
approximately 100 ns.
Figure 10 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R2 repre-
sents the source impedance of a buffer amplifier or resistive
network; R1 is an internal multiplexer resistance and C1 is the
sampling capacitor.
C1
3.5pF
R1
125⍀
VIN+
R2
Figure 10. Equivalent Sampling Circuit
During the acquisition phase, the sampling capacitor must be
charged to within a 1/2 LSB of its final value. The time it takes
to charge the sampling capacitor (t
CHARGE
) is given by the fol-
lowing formula:
t
CHARGE
= 7.6 × (R2 + 125 Ω) × 3.5 pF
For small values of source impedance, the settling time associated
with the sampling circuit (100 ns) is, in effect, the acquisition
time of the ADC. For example, with a source impedance (R2)
of 10 Ω, the charge time for the sampling capacitor is approxi-
mately 4 ns. The charge time becomes significant for source
impedances of 2 kΩ and greater.
AC Acquisition Time
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of source impedance will cause the THD
to degrade at high throughput rates. In addition, better perfor-
mance can generally be achieved by using an external 1 nF
capacitor on V
IN+
.
ADC TRANSFER FUNCTION
The output coding of the AD7810 is straight binary. The
designed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = V
REF
/1024. The
ideal transfer characteristic for the AD7810 is shown in Figure
11 below.
000...010
000...001
000...000
ADC CODE
0V +V
REF
–1LSB
ANALOG INPUT
111...111
111...110
111...000
011...111
1LSB
1LSB = V
REF
/1024
Figure 11. Transfer Characteristic
AD7810
–8–REV. B
POWER-UP TIMES
The AD7810 has a 1.5 µs power-up time. When V
DD
is first
connected, the AD7810 is in a low current mode of operation.
In order to carry out a conversion, the AD7810 must first be
powered up. The ADC is powered up by a rising edge on the
CONVST pin. A conversion is initiated on the falling edge of
CONVST. Figure 12 shows how to power up the AD7810 when
V
DD
is first connected or after the AD7810 is powered down
using the CONVST pin.
Care must be taken to ensure that the CONVST pin of the
AD7810 is logic low when V
DD
is first applied.
MODE 1 (CONVST IDLES HIGH)
VDD
MODE 2 (CONVST IDLES LOW)
VDD
< 1␮s
tPOWER-UP
1.5␮s
tPOWER-UP
1.5␮s
CONVST
CONVST
Figure 12. Power-Up Times
POWER VS. THROUGHPUT RATE
By operating the AD7810 in Mode 2, the average power con-
sumption of the AD7810 decreases at lower throughput rates.
Figure 13 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power per-
formance for the AD7810. As the throughput rate is reduced, the
device remains in its power-down state longer and the average
power consumption over time drops accordingly.
t
CYCLE
100␮s @ 10kSPS
CONVST
t
CONVERT
2.3␮s
POWER-DOWN
t
POWER-UP
1.5␮s
Figure 13. Automatic Power-Down
For example, if the AD7810 is operated in a continuous sampling
mode with a throughput rate of 10 kSPS, the power consump-
tion is calculated as follows. The power dissipation during normal
operation is 9 mW, V
DD
= 3 V. If the power-up time is 1.5 µs
and the conversion time is 2.3 µs, the AD7810 can be said to
dissipate 9 mW for 3.8 µs (worst case) during each conversion
cycle. If the throughput rate is 10 kSPS, the cycle time is
100 µs and the average power dissipated during each cycle is
(3.8/100) × (9 mW) = 342 µW. Figure 2 shows a graph of
Power vs. Throughput.
OPERATING MODES
Mode 1 Operation (High Speed Sampling)
When the AD7810 is used in this mode of operation, the part is
not powered down between conversions. This mode of opera-
tion allows high throughput rates to be achieved. The timing
diagram in Figure 14 shows how this optimum throughput rate
is achieved by bringing the CONVST signal high before the end
of the conversion. The AD7810 leaves its tracking mode and
goes into hold on the falling edge of CONVST. A conversion is
also initiated at this time. The conversion takes 2.3 µs to complete.
At this point, the result of the current conversion is latched into the
serial shift register, and the state of the CONVST signal checked.
The CONVST signal should be high at the end of the conversion
to prevent the part from powering down.
AB
t
2
D
OUT
CURRENT CONVERSION RESULT
t
1
SCLK
CONVST
Figure 14. Mode 1 Operation Timing
The serial port on the AD7810 is enabled on the rising edge of
the CONVST signal (see Serial Interface section). As explained
earlier, this rising edge should occur before the end of the con-
version process if the part is not to be powered down. A serial
read can take place at any stage after the rising edge of CONVST.
If a serial read is initiated before the end of the current con-
version process (i.e., at time “A”), the result of the previous
conversion is shifted out on the D
OUT
pin. It is possible to allow
the serial read to extend beyond the end of a conversion. In this
case the new data will not be latched into the output shift regis-
ter until the read has finished. The dynamic performance of the
AD7810 typically degrades by up to 3 dBs while reading during
a conversion. If the user waits until the end of the conversion
process, i.e., 2.3 µs after falling edge of CONVST (Point “B”),
before initiating a read, the current conversion result is shifted out.
AD7810
–9–
REV. B
t
POWER-UP
1.5␮s
AB
DOUT
SCLK
t
1
CONVST
CURRENT CONVERSION RESULT
Figure 15. Mode 2 Operation Timing
Mode 2 Operation (Automatic Power-Down)
When used in this mode of operation, the part automatically
powers down at the end of a conversion. This is achieved by
leaving the CONVST signal low until the end of the conversion.
Because it takes approximately 1.5 µs for the part to power up
after it has been powered down, this mode of operation is in-
tended to be used in applications where slower throughput rates
are required, i.e., in the order of 100 kSPS. The timing diagram
in Figure 15 shows how to operate the part in this mode. If the
AD7810 is powered down, the rising edge of the CONVST
pulse causes the part to power up. When the part has powered
up (≈ 1.5 µs after the rising edge of CONVST), the CONVST
signal is brought low, and a conversion is initiated on this falling
edge of the CONVST signal. The conversion takes 2.3 µs and
after this time, the conversion result is latched into the serial
shift register and the part powers down. Therefore, when the
part is operated in Mode 2, the effective conversion time is
equal to the power-up time (1.5 µs) and the SAR conversion
time (2.3 µs).
NOTE: Although the AD7810 takes 1.5 µs to power up after the
rising edge of CONVST, it is not necessary to leave CONVST
high for 1.5 µs after the rising edge before bringing it low to
initiate a conversion. If the CONVST signal goes low before 1.5 µs
in time has elapsed, then the power-up time is timed out inter-
nally and a conversion is then initiated. Hence the AD7810 is
guaranteed to have always powered up before a conversion is
initiated—even if the CONVST pulsewidth is < 1.5 µs. If the
CONVST width is > 1.5 µs, then a conversion is initiated on
the falling edge.
As in the case of Mode 1 operation, the rising edge of the
CONVST pulse enables the serial port of the AD7810 (see
Serial Interface section). If a serial read is initiated soon after
this rising edge (Point “A”), i.e., before the end of the conver-
sion, the result of the previous conversion is shifted out on pin
D
OUT
. In order to read the result of the current conversion, the
user must wait at least 2.3 µs after the falling edge of CONVST
before initiating a serial read. The serial port of the AD7810 is
still functional even though the AD7810 has been powered down.
NOTE: Serial read should not cross the next rising edge of
CONVST.
Because it is possible to do a serial read from the part while it
is powered down, the AD7810 is powered up only to do the
conversion and is immediately powered down at the end of a
conversion. This significantly improves the power consumption
of the part at slower throughput rates—see Power vs. Through-
put Rate section.
SERIAL INTERFACE
The serial interface of the AD7810 consists of three wires, a
serial clock input SCLK, serial port enable CONVST and a
serial data output D
OUT
(see Figure 16). The serial interface
is designed to allow easy interfacing to most microcontrollers,
e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any
gluing logic. When interfacing to the 8051, the SCLK must be
inverted. The Microprocessor Interface section explains how to
interface to some popular microcontrollers.
Figure 16 shows the timing diagram for a serial read from the
AD7810. The serial interface works with both a continuous and
a noncontinuous serial clock. The rising edge of the CONVST
signal resets a counter, which counts the number of serial clocks
to ensure the correct number of bits are shifted out of the serial
shift registers. The SCLK is ignored once the correct number of
bits have been shifted out. In order for another serial transfer to
take place, the counter must be reset by the falling edge of the
10th SCLK. Data is clocked out from the D
OUT
line on the first
rising SCLK edge after the rising edge of the CONVST signal
and on subsequent SCLK rising edges. D
OUT
enters its high
impedance state again on the falling edge of the 10th SCLK.
In multipackage applications, the CONVST signal can be used
as a chip select signal. The serial interface will not shift data out
until it receives a rising edge on the CONVST pin.
CONVST
DOUT
SCLK
t8
12 3 45 6 78 910
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB9 DB8
t3
t4
t7
t6
t5
Figure 16. AD7810 Serial Interface Timing
AD7810
–10–REV. B
MICROPROCESSOR INTERFACING
The serial interface on the AD7810 allows the parts to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7810 with some of the
more common microcontroller serial interface protocols.
AD7810 to PIC16C6x/7x
The PIC16C6x Synchronous Serial Port (SSP) is configured
as an SPI Master with the Clock Polarity Bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See PIC16/17 Microcontroller User Manual. Figure
17 shows the hardware connections needed to interface to the
PIC16/PIC17. In this example I/O port RA1 is being used to
pulse CONVST and enable the serial port of the AD7810. This
microcontroller transfers only eight bits of data during each
serial transfer operation, therefore, two consecutive read opera-
tions are needed.
SCLK
DOUT
SCK/RC3
SDO/RC5
RA1
AD7810*PIC16C6x/7x*
CONVST
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Interfacing to the PIC16/PIC17
AD7810 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 0), Clock Polarity Bit
(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. A connection diagram is shown in
Figure 18.
SCLK
DOUT
SCLK/PD4
MISO/PD2
PA0
AD7810*MC68HC11*
CONVST
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. Interfacing to the MC68HC11
AD7810 to 8051
The AD7810 requires a clock synchronized to the serial data;
therefore, the 8051 serial interface must be operated in Mode
0. In this mode serial data enters and exits through RXD, and a
serial clock is output on TXD (half duplex). Figure 19 shows
how the 8051 is connected to the AD7810. However, because
the AD7810 shifts data out on the rising edge of the serial
clock, the serial clock must be inverted.
SCLK
DOUT
TXD
RXD
P1.1
AD7810*8051*
CONVST
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Interfacing to the 8051 Serial Port
It is possible to implement a serial interface using the data ports
on the 8051 (or any microcontroller). This would allow direct
interfacing between the AD7810 and 8051 to be implemented.
The technique involves “bit banging” an I/O port (e.g., P1.0)
to generate a serial clock and using another I/O port (e.g., P1.1)
to read in data, see Figure 20.
SCLK
DOUT
P1.0
P1.1
P1.2
AD7810*8051*
CONVST
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the 8051 Using I/O Ports
AD7810
–11–
REV. B
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8
14
5
0.430 (10.92)
0.348 (8.84)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
8-Lead Small Outline
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
85
41
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8°
0°
0.0196 (0.50)
0.0099 (0.25) x 45°
8-Lead microSOIC
(RM-8)
85
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33°
27°
0.120 (3.05)
0.112 (2.84)
C01311a–0–10/00 (rev. B)
PRINTED IN U.S.A.