© Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.Publication# 21915 Rev: B Amendment/0
Issue Date: May 2000
Am186™CC
High-Performance, 80C186-Compatible
16-Bit Embedded Communications Controller
DISTINCTIVE CHARACTERISTICS
nE86™ family of x86 embedded processors
offers improved time-to-market
– Software migration (backwards- and upwards-
compatible)
– World-class development tools, applications, and
system software
nSerial Communications Peripherals
– Fo ur High-le vel D ata Link Contro l (HDLC) channels
– Four independent Time Slot Assigners (TSAs)
– Physical interface for HDLC channels can be raw
DCE, PCM Highway, or GCI (IOM-2)
– USB peripheral controller
– High-Speed UART with autobaud
–UART
– Synchronous serial interface (SSI)
– SmartDMA™ channels (8) to support USB/HDLC
nSystem Peripherals
– Three programmable 16-bit timers
– Hardware watchdog timer
– General-purpose DMA (4 channels)
– Programmable I/O (48 PIO signals)
– Interrupt Controller (36 maskable interrupts)
nMemory and Peripheral Interface
– Integrated DRAM controller
– Glueless interface to RAM/ROM/Flash memory
(55-ns Flash memory required for zero-wait-state
operation at 50 MHz)
– Fourteen chip selects (8 peripherals, 6 memory)
– External bus mastering support
– Multiple xed and nonm ultiplex ed address/ data b us
– Programmable bus sizing
– 8-bit boot option
nAvailable in the following package
– 160-pin plastic quad flat pack (PQFP)
– 25-, 40-, and 50-MHz operating frequencies
– Low-voltage operation, VCC = 3.3 V ± 0.3 V
– Commercial and industrial temperature rating
– 5-V-tolerant I/O (3.3-V output levels)
GENERAL DESCRIPTION
The Am186™CC embedded communications
controller is the first member in the AMD Comm86™
product family. The Am186CC controller is a cost-
effective, high-performance microcontroller solution for
communications applications. This highly integrated
microcontroller enables customers to save system
costs and increase performance over 8-bit
microcontrollers and other 16-bit microcontrollers.
The Am186CC communications controller offers the
advantages of the x86 development environment’s
widely available native development tools, applications,
and system software. Additionally, the controller uses
the industry-standard 186 instruction set that is part of
the AMD E86™ family, which continually offers
instruction-set-compatible upgrades. Built into the
Am186CC controller is a wide range of
communications features required in many
communications applications, including High-level
Data Link Control (HDLC) and the Universal Serial Bus
(USB).
AMD offers complete solutions with the Am186CC
controller. A customer development platform board is
available. Reference designs under development
include a low-end router with Integrated Services
Digital Network (ISDN), Ethernet, USB, Plain Old
Telephone Service (POTS), and an ISDN Terminal
Adapter featuring USB. AMD and its FusionE86SM
Partners offer boards, schematics, drivers, protocol
stacks, and routing software for these reference
designs to enable fast time to market.
2Am186™CC Communications Controller Data Sheet
ORDERING INFORMATION
–25 = 25 MHz
–40 = 40 MHz
–50 = 50 MHz
TEMPERATURE RANGE
SPEED OPTION
DEVICE NUMBER/DESCRIPTION
LEAD FORMING
\W=Trimmed and Formed
Valid combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Valid Combinations
PACKAGE TYPE
K=160-Pin Plastic Quad Flat Pack (PQFP)
Am186CC high-performance 80C186-compatible
16-bit embedded communications controller
–50 K C \W
Valid Combinations
Am186CC–25
Am186CC–40
Am186CC–50 KC\W
Am186CC–25
Am186CC–40 KI\W
Am186CC
C = Am186CC Commercial (TC=0C to +100C)
I = Am186CC Industrial (TA=–40C to +85C)
where: TC= case temperature
where: TA= ambient temperature
Am186™CC Communications Controller Data Sheet 3
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
General Description ..................................................................................................................... 1
Ordering Information .................................................................................................................... 2
Logic Diagram by Interface .......................................................................................................... 6
Logic Diagram by Defaul t Pin Function ........ .................. ......... .. ......... ......... .. ......... ......... .. ......... . 7
Pin Connection Diagram—160-Pi n PQFP Package ................ .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .... 8
Pin and Signal Tables .................................................................................................................. 9
Signal Descriptions ............................................................................................................... 13
Architectural Overview ............................................................................................................... 28
Detailed Description .............................................................................................................. 28
Am186 Embedded CPU .................. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 29
Memor y Or ga n i za t i on .. .. ............. .. .. .............. .. .. ............. ... .. ............. .. .. ....... .. ... ............. .. .. .....29
I/O Space .............................................................................................................................. 29
Serial Communications Support ...... .................. ......... .. ......... ......... .. ......... ......... .. ......... .. ...... 30
Universal Serial Bus......................................................................................................... 30
Four HDLC Channels and Four TSAs....... .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. . 31
General Circui t Interface .................................................................................................. 31
Eight SmartDMA™ Channels........................................................................................... 31
Two Asynchronous Serial Ports......... ......... .. ......... ......... .. ......... ......... .. ......... ......... .. ....... 31
Synchronous Serial Port................................................................................................... 32
System Peripher als .... ............................ ......... .. ......... ......... .. ......... ......... .. ......... .. ......... ........ 32
Interrupt Controller ........................................................................................................... 32
Four General-Pur pose DMA Channels ....................... .. ......... ............................ ......... .. ... 32
48 Programmable I/O Signals.......... ......... ......... .. ......... ............................ .................. ..... 32
Three Programmable Timers ........................................................................................... 32
Hardware Watchdog Timer .............................................................................................. 33
Memory and Peripheral Interface .......................................................................................... 33
System Interfaces............................................................................................................. 33
DRAM Support................................................................................................................. 34
Chip Selects..................................................................................................................... 34
Clock Control ................................................................................................................. ........ 35
In-Circ uit Emulator Support .................... .. ......... ......... .. ......... ......... .. ......... .................. ......... . 37
Applications ............................................................................................................................... 37
Clock Generati on and Control ....... ......... .. ......... ......... .. ......... ......... .. ......... ......... .. ......... ............40
Features ................................................................................................................................ 40
System Clock ........................................................................................................................ 40
USB Clock .... .................... .................... .................... ....... ........ ....... .................... ................... 40
Clock Sharing by System and USB ................. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 41
Crystal-Driven Clock Source ................................................................................................. 42
External Clock Source ........................................................................................................... 43
Static Operation .................................................................................................................... 43
PLL Bypass Mode ................. .. .. .. .. .. .............. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .... 43
UART Baud Clock .......... .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............. 43
Power Supply Operation ............................................................................................................ 44
Power Supply Connections ................................................................................................... 44
Input/Out put Circuitry ....... ......... ......... .. ......... .. ......... ......... .. ......... ......... .. ......... ......... .. .......... 44
PIO Supply Current Limit ............ ......... .. ......... ......... .. ......... ......... .. ......... ......... .. ......... ..........44
Absolute Maximum Ratings .......................................................................................................45
Operating Ranges .......... ....... ....... ........ ....... .................... ....... ........ ....... .................... ....... .......... 45
Driver Characteristics—Universal Serial Bus ............................................................................ 45
DC Characteristics over Commercial and Industrial Operating Ranges .................................... 46
Capacitance ................................................................................................................... ............ 46
4Am186™CC Communications Controller Data Sheet
Maximum Load Derating ............................................................................................................ 47
Power Supply Current ................................................................................................................ 47
Thermal Charact e ristics ...... ......... ......... ......... ................... ......... ......... .................. ......... ............ 48
PQFP Package ..................................................................................................................... 48
Commercial and Industrial Switching Characteristics and Waveforms ...................................... 49
Switching Characteristics over Commercial and Industrial Operating Ranges ....................... ...............58
Appendix A—Pin Tables............................................................................................................A-1
Pin List Table Column Definitions ......................................................................................A-11
Appendix B—Physical Dimensions: PQR160, Plastic Quad Flat Pack (PQFP) ............. ...........B-1
Appendix C—Customer Support ............................................................................................... C -1
Related AMD Products—E86™ Family Devices ..................................................................C -1
Relate d D o c um e nt s .................. .. .. .............. .. .. ............. .. ... ...... .. ... ............. .. .. .............. .. .. ......C-2
Am18 6 CC /CH/CU Mic r o co ntrolle r C u st o m er D e v el o p m en t P la tf o rm .... .. ............. .. ... ..........C -2
Third-Party Development Support Products .......... .. ..... ... ... ..... ... ..... .. ... ..... ... ..... ... ... ..... .. ...... .. ... ...C-2
Customer Service .................................................................................................................C-2
Hotline and World Wide Web Support. ............................................................................ C-2
Corporate Applications Hotline........................................................................................ C-2
World Wide Web Home Page ......................................................................................... C-3
Documentation and Literature... .................. ......... .. ......... ......... .. ......... ......... .. ......... ........ C-3
Literature Ordering.......................................................................................................... C-3
Index................................................................................................................................... Index-1
LIST OF FIGURES
Figure 1. Am186CC Controller Block Diagram ..................................................................... 28
Figure 2. Two-Component Address Example ...................................................................... 30
Figure 3. Am186CC Controller Address Bus — Default Operation ...................................... 35
Figure 4. Am186CC Controller—Address Bus Disable In Effect .......................................... 36
Figure 5. ISDN Terminal Adapter System Application ......................................................... 38
Figure 6. ISDN to Ethernet Low-End Router System Application ........................................ 38
Figure 7. 32-Channel Linecard Syst em Appli cation ........................ .. ......... ......... .. ......... ...... 39
Figure 8. System and USB Clock Generation ...................................................................... 41
Figure 9. Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies . 42
Figure 10. External Interface to Support Clocks—Fundamental Mode Crystal ...................... 42
Figure 11. External Interface to Support Clocks—External Clock Source ............................. 43
Figure 12. UART and High-Speed UART Clocks ...... .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 43
Figure 13. Typical Icc Versus Frequency ........ ......... .. ......... ......... .. ......... .. ......... ......... .. ......... . 47
Figure 14. Thermal Resistance(C/Watt) ............................................................................... 48
Figure 15. Thermal Characteristics Equations ....................................................................... 48
Figure 16. Key to Switching Waveforms ................................................................................ 49
Figure 17. Read Cycle Waveforms ... ......... .. ......... .. ......... ............................ ......... .. ......... ...... 60
Figure 18. Write Cycle Waveforms ......................................................................................... 63
Figure 19. Software Halt Cycle Waveforms ........................................................................... 64
Figure 20. Peripheral Timing Waveforms ............................................................................... 65
Figure 21. Reset Waveforms .................................................................................................. 66
Figure 22. Signals Related to Reset (System PLL in 1x or 2x Mode) ............ .................. ...... 67
Figure 23. Signals Related to Reset (System PLL in 4x Mode) .. ............................ ......... .. .... 67
Figure 2 4 . Synch r o n ous R e ad y Wa v e fo rms ................. .. ... ............. .. .. .............. .. .. ....... .. .. ....... 68
Figure 25. Asynchronous Ready Waveforms ........ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 69
Figure 26. Entering Bus Hold Waveforms .............................................................................. 70
Figure 27. Exiting Bus Hold Waveforms ................................................................................. 70
Figure 28. System Clock Timing Waveforms—Active Mode (PLL 1x Mode) ........ .. .. ............ . 72
Figure 29. USB Clock Timing Waveforms .............................................................................. 72
Figure 30. GCI Bus Waveforms ............................................................................................. 73
Am186™CC Communications Controller Data Sheet 5
Figure 31. PCM Highway Waveforms (Timing Slave) ............................................................ 75
Figure 32. PCM Highway Waveforms (Timing Master) .......................................................... 76
Figure 33. DCE Transmit Waveforms .................................................................................... 77
Figure 34. DCE Receive Waveforms ..................................................................................... 77
Figure 35. USB Data Signal Rise and Fall Times .................................................................. 78
Figure 36. USB Receiver Jitt er Tolerance ............ ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 78
Figure 37. Synchronous Serial Interface Waveforms ............................................................. 79
Figure 38. DRAM Read Cycle without Wait-States Waveform ............................................... 80
Figure 39. DRAM Read Cycle with Wait-States Waveform .................................................... 81
Figure 40. DRAM Write Cycle without Wait-States Waveform ............................................... 81
Figure 41. DRAM Write Cycle with Wait-States Waveform .................................................... 82
Figure 42. DRAM Refresh Cycle Waveform ........................................................................... 82
LIST OF TABLES
Table 1. PQFP Pin Assignments—Sorted by Pin Number .................................................. 10
Table 2. PQFP Pin Assignments—Sorted by Signal Name ........... .. .. ............ .. .. .. .. ............ . 11
Table 3. Signal Description Table Definitions ............. .. ......... ......... .. ......... .................. ........ 13
Table 4. Signal Descriptions ... .. ......... ......... .. ......... ......... .. ......... .. ......... ......... .. ......... ......... . 14
Table 5. Segment Register Sele ction Rules ..... ......... .. ......... ......... .. ......... .................. ........ 30
Table 6. Cryst al Parameters .......... ....... ....... ....... ........ ....... .. ....... ........ ....... ....... ....... ............ 42
Table 7. Typica l Power Consumption Calculati on....................... .. ......... .................. ............ 47
Table 8. Thermal Characteristics (C/Watt) ........................................................................ 48
Table 9. Alphabetical Key to Switching Parameter Symbols .............. .. .. .. .. ............ .. .. .. .. .. .. 50
Table 10. Numerical Key to Swit ching Parameter Symbols .................. .. ......... ......... .. ......... . 54
Table 11. Read Cycle Timing ........... ......... ............................ ......... .. ......... ......... .. ......... .. ...... 58
Table 12. Write Cycle Timing ........ ................ .. ......... ......... .. ......... ......... .. ......... ......... .. ......... . 61
Table 13. Software Halt Cycle Timing ................................................................................... 64
Table 14. Peripheral Timi ng ............ ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 65
Table 15. Reset Timing ............... .................. ......... .. ......... ......... .. ......... ......... .. ......... ............ 66
Table 16. External Ready Cycle Timi ng ................. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 68
Table 17. Bus Hold Timing ........ .. .. .. .............. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 69
Table 18. System Clocks Timing ............ .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 71
Table 19. USB Clocks Timing .............................. .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 72
Table 20. GCI Bus Timing ............. ......... .. ......... .. ......... ......... .. ......... ......... .. ......... ......... .. ...... 73
Table 21. PCM Highway Timing (Timing Slave) ........ .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ . 74
Table 22. PCM Highway Timing (Timing Master) .......... ......... .. ......... ......... .. ......... ......... .. .... 76
Table 23. DCE Interface Timing ................................. .. ......... ......... .. ......... ......... .. ......... ........ 77
Table 24. USB Timing ..................................... ......... .. ......... ......... .. ......... ......... .. ......... ..........78
Table 25. SSI Timing .......... .. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............. 79
Table 26. DRAM Timing ................ .. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. .. 80
Table 27. Power-On Reset (POR) Pin Defaults ...................................................................A-2
Table 28. Multiplexed Signal Trade-of fs ........ ......... ......... .. ......... ............................ .. ......... ...A-5
Table 29. PIOs Sorted by PIO Number .................... .. ......... .. ......... ......... .. ......... ......... .. .......A-8
Table 30. PIOs Sorted by Signal Name ............... .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............A-9
Table 31. Reset Configuration Pins (Pinstraps) ........... ......... ......... .. ......... ......... .. ......... .....A-10
Table 32. CPU PLL Modes .................................................................................................A-10
Table 33. USB PLL Modes......... .. .. .. ............ .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ............ .. .. .. .. .A-10
Table 34. Pin List Table Definitions....................... .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ..........A-11
Table 35. Pin List Summary ................. .. .. ............ .. .. .. .. .. ............ .. .. .. .. .. ............ .. .. .. .. ..........A-12
6Am186™CC Communications Controller Data Sheet
LOGIC DIAGRAM BY INTERFACE1
CLKOUT INT8–INT0 Interrupts
Reset/ RES NMI
Clocks RESOUT
X1 LCS Chip
Selects
X2 MCS3–MCS0
PCS7–PCS0
Address and
Address/Data
Buses
A19–A0 UCS
AD15–AD0
CAS0 DRAM
Control
Bus Status and
Control
ALE CAS1
ARDY RAS0
BHE RAS1
BSIZE8
DEN DCE_RXD_A, B, C, D
DCE Interface
(HDLC A–D)1
Notes:
1. Because of multiplexing, not all interfaces are available at once. Refer to Table 28, “Multiplexed Signal Trade-offs,” on
page A-5.
DS DCE_TXD_A, B, C, D
DRQ1–DRQ0 DCE_RCLK_A, B, C, D
DT/R DCE_TCLK_A, B, C, D
HLDA DCE_CTS_A, B, C, D
HOLD DCE_RTR_A, B, C, D
RD
S2–S0 PCM_RXD_A, B, C , D
PCM Interface
(HDLC A–D)1
S6 PCM_TXD_A, B , C, D
SRDY PCM_CLK_A, B, C, D
WHB PCM_FSC_A, B, C, D
WLB PCM_TSC_A, B, C , D
WR GCI_DD_A GCI Interface
(HDLC A)1
Programmable
Timers
PWD GCI_DU_A
TMRIN1–TMRIN0 GCI_DCL_A
TMROUT1–TMROUT0 GCI_FSC_A
Debug QS1–QS0 USBD+
Universal
Serial Bus
(USB)
USBD–
Synchronous
Serial Interface
SDEN USBSCI
SCLK USBSOF
SDATA USBX1
USBX2
Asynchronous
Serial Interface
(UART)
RXD_U
TXD_U UDMNS
USB External
Transceiver
Interface
CTS_U UDPLS
RTR_U UTXDMNS
UTXDPLS
High-Speed UART
RXD_HU UXVOE
TXD_HU UXVRCV
CTS_HU
RTR_HU {ADEN}
Configuration
Pinstraps
{CLKSEL1}
UART Clock UCLK {CLKSEL2}
{ONCE}
Programmable I/O
(PIO) PIO47–PIO0 {UCSX8}
{USBSEL1}
{USBSEL2}
{USBXCVR}
9/
4/
8/
20
16
4/
4/
2/4/
4/
4/
4/
3/4/
4/
4/
4/
4/
2/
2/
2/
Am186™CC Communications Controller Data Sheet 7
LOGIC DIAGRAM BY DEFAULT PIN FUNCTION1
Notes:
1. Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate pins trap pins.
CLKOUT
Reset/ RES
Clocks RESOUT DCE_RXD_A [GCI_DD_A ] [PCM_RXD_A ] HDLC A
(DCE)
X1 DCE_TXD_A [GCI_DU_A] [PCM_TXD_A]
X2 DCE_RCLK_A [GCI_DCL_A] [PCM_CLK_A ]
DCE_TCLK_A [GCI_FSC_A] [PCM_FSC_A]
Address and
Address/Data Buses A19–A0
AD15–AD0 PIO0 [TMRIN1]
Bus Status and
Control
ALE [PIO3 3 ] PIO1 [TMROUT1] Pr og r am ma b le
I/O (PIO)
ARDY [PIO8] PIO2 [PCS5]
BHE [PIO34] {ADEN}PIO3 [P CS4 ] {CLKSEL2}
BSIZE8 PIO4 [MCS0] {UCSX8}
DEN [DS] [PIO30] PIO5 [MCS3 ] [RAS1]
DRQ1 PIO6 [INT8] [PWD]
DT/R [PIO29] PIO7 [INT7]
HLDA {CLKSEL1} PIO8 [ARDY ]
HOLD
RD PIO9 [DRQ0 ]
S0 {U SBXCV R}PIO10 [SDE N]
S1 PIO11 [SCLK]
S2 PIO12 [SDATA]
S6
SRDY [PIO 3 5 ] PIO16 [RXD_HU]
WHB PIO17 [DCE_CTS_A] [PCM_TSC_A]
WLB PIO18 [DC E_RTR_A]
WR [PIO1 5 ] PIO19 [INT6]
PIO20 [TXD_U] [DCE_TXD_D] [PCM_TXD_D]
Debug QS1–QS0 PIO21 [UCLK] [USBSOF] [USBSCI]
PIO22 [DCE_RCLK _C] [PCM_CLK_C ]
High-Speed UART TXD_HU PIO23 [DCE_TCLK_C] [PCM_FSC_C]
PIO24 [CTS_U] [DCE_TCLK_D] [PCM_FSC_D]
Chip
Selects
LCS [RAS0]PIO25 [R TR_U ] [DCE_RCLK_D] [PCM_CLK_D]
MCS1 [CAS 1 ]PIO26 [RXD_U] [DCE_RXD_D] [PCM_RXD_D ]
MCS2 [CAS 0]PIO27 [TMRIN0]
PCS0 [PIO13] {USBSEL1} PIO28 [TMROUT0]
PCS1 [PIO14] {USBSEL2}
PCS2 PIO31 [P C S 7 ]
PCS3 PIO32 [P C S 6 ]
UCS {ONCE}PIO36 [DCE_RXD_B] [PCM_RXD_B]
Universal Serial Bus
(USB)
USBD+ [UDPLS] PIO37 [DCE_TXD_B] [PCM_TXD_B]
USBD– [UDMNS] PIO38 [DCE_CTS_B] [PCM_TSC_B]
USBX1 PIO39 [DCE_RTR_B]
USBX2 PIO40 [DCE_RCLK_B] [PCM_CLK_B]
PIO41 [DCE_TCLK_B] [PCM_FSC_B]
Interrupts INT5–INT0 PIO42 [DCE_RXD_C] [PCM_RXD_C]
NMI PIO43 [DCE_TXD_C] [PCM_TXD_C]
PIO44 [DCE_CTS_C] [PCM_TSC_C]
PIO45 [DCE_RT R_C]
PIO46 [CTS_HU] [DCE_CTS_D] [PCM_TSC_D]
PIO47 [RTR_HU] [DCE_RT R_D]
No Conn ect ion
RSVD_104 [UXVRCV]
RSVD_103 [UXVOE]
RSVD_102 [UTXD M N S]
RSVD_101 [UTXDPLS]
20
16
6/
8Am186™CC Communications Controller Data Sheet
PIN CONNECTION DIAGRAM—160-PIN PQFP PACKAGE
VCC
TXD_U/DCE_TXD_D/PCM_TXD_D
RXD_U/DCE_RXD_D/PCM_RXD_D
CTS_U/DCE_TCLK_D/PCM_FSC_D
RTR_U/DCE_RCLK_D/PCM_CLK_D
VSS
DCE_TXD_C/PCM_TXD_C
DCE_RXD_C/PCM_RXD_C
DCE_CTS_C/PCM_TSC_C
DCE_RTR_C
DCE_RCLK_C/PCM_CLK_C
DCE_TCLK_C/PCM_FSC_C
VCC
INT8/PWD
INT7
INT6
TMRIN1
TMROUT1
TMRIN0
TMROUT0
VSS
DCE_TXD_B/PCM_TXD_B
DCE_RXD_B/PCM_RXD_B
DCE_CTS_B/PCM_TSC_B
DCE_RTR_B
DCE_RCLK_B/PCM_CLK_B
DCE_TCLKB/PCM_FSC_B
VCC
UCS {ONCE}
LCS/RAS0
VSS
MCS3/RAS1
MCS2/CAS0
MCS1/CAS1
MCS0 {UCSX8}
VCC
DRQ0
DCE_CTS_A/PCM_TSC_A
DCE_RTR_A
VSS
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
1V
SS VCC 120
2 SDEN DCE_TXD_A/GCI_DU_A/PCM_TXD_A 119
3 SCLK DCE_RXD_A/GCI_DD_A/PCM_RXD_A 118
4 SDATA DCE_RCLK_A/GCI_DCL_A/PCM_CLK_A 117
5PCS0
{USBSEL1} DCE_TCLK_A/GCI_FSC_A/PCM_FSC_A 116
6PCS1
{USBSEL2} NMI 115
7PCS2 RES 114
8PCS3 INT5 113
9PCS4
{CLKSEL2} INT4 112
10 PCS5 INT3 111
11 PCS6 INT2 110
12 VCC INT1 109
13 PCS7 VSS 108
14 ARDY INT0 107
15 SRDY VCC 106
16 WR DRQ1 105
17 DT/R RSVD_104/UXVRCV 104
18 DEN/DS RSVD_103/UXVOE 103
19 ALE RSVD_102/UTXDMNS 102
20 BHE {ADEN} RSVD_101/UTXDPLS 101
21 VSS VSS 100
22 UCLK/USBSOF/USBSCI HOLD 99
23 RTR_HU/DCE_RTR_D HLDA {CLKSEL1} 98
24 CTS_HU/DCE_CTS_D/PCM_TSC_D RD 97
25 RXD_HU WLB 96
26 TXD_HU WHB 95
27 VCC BSIZE8 94
28 AD0 AD15 93
29 AD8 AD7 92
30 A0 VCC 91
31 A1 A19 90
32 A2 A18 89
33 VSS A17 88
34 AD1 AD14 87
35 AD9 AD6 86
36 A3 A16 85
37 A4 A15 84
38 AD2 VSS 83
39 AD10 VSS_USB 82
40 VCC USBD+/UDPLS 81
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VSS
A5
A6
A7
A8
AD3
AD11
VCC
A9
A10
AD4
AD12
VSS
S6
S2
S1
S0 {USBXCVR }
RESOUT
VCC
CLKOUT
VSS
QS0
QS1
A11
A12
AD5
AD13
VCC
A13
A14
VSS
VSS_A
X1
X2
USBX1
USBX2
VCC_A
VCC
VCC_USB
USBD-/UDMNS
Am186™CC Communications Controller Data Sheet 9
PIN AND SIGNAL TABLES
Table 1 on page 10 and Table 2 on page 11 show the
pins sorted by pin number and signal name,
respectively.
Table 4 on page 14 contains the signal descriptions
(grouped alphabetically and by function). The table
include s columns listing the multiplexed functions and
I/O type. Table 3 on page 13 shows terms used in
Table 4.
Refer to A ppe ndi x A, “P in Tables,” on pag e A -1 for a n
additional group of tables with the following
information:
nPower-on reset (POR) pin defaults including pin
numbers and multiplexed functions—Table 27 on
page A-2.
nMultiplexed signal trade-offs—Table 28 on
page A-5.
nProgrammable I/O (PIO) pins ordered by PIO pin
number and multiplexed signal name, respectively,
includ ing columns listing multiplexed functions and
pin configurations following system reset—Table 29
on page A-8 and Table 30 on page A-9.
nPinstraps and pinstrap options—Table 31 on
page A-10.
nPin an d signal summ ary sh owing signal na me and
alternate function, pin number, I/O type, load
values, POR default function, reset state, POR
default operation, hold state, and voltage—Table 35
on page A-12.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
10 Am186™CC Communications Controller Data Sheet
Table 1. PQFP Pin Assignments—Sorted by Pin Number1
Pin No. Name—Left Side Pin No. Name—Bottom Side Pin No. Name—Right Side Pin No. Name—To p Side
1V
SS 41 VSS 81 USBD+/UDPLS 121 VSS
2SDEN 42A5 82V
SS_USB 122 DCE_RTR_A
3 SCLK 43 A6 83 VSS 123 DCE_CTS_A/
PCM_TSC_A
4 SDATA 44 A7 84 A15 124 DRQ0
5PCS0
{USBSEL1} 45 A8 85 A16 125 VCC
6PCS1 {USBSEL2} 46 AD3 86 AD6 126 MCS0 {UCSX8}
7PCS2 47 AD11 87 AD14 127 MCS1/CAS1
8PCS3 48 VCC 88 A17 128 MCS2/CAS0
9PCS4 {CLKSEL2} 49 A9 89 A18 129 MCS3/RAS1
10 PCS5 50 A10 90 A19 130 VSS
11 PCS6 51 AD4 91 VCC 131 LCS/RAS0
12 VCC 52 AD12 92 AD7 132 UCS {ONCE}
13 PCS7 53 VSS 93 AD15 133 VCC
14 ARDY 54 S6 94 BSIZE8 134 DCE_TCLK_B/
PCM_FSC_B
15 SRDY 55 S2 95 WHB 135 DCE_RCLK_B/
PCM_CLK_B
16 WR 56 S1 96 WLB 136 DCE_RTR_B
17 DT/R 57 S0 {USBXCVR}97RD 137 DCE_CTS_B/
PCM_TSC_B
18 DEN/DS 58 RESOUT 98 HLD A {CLKSEL1} 138 DCE_RXD_B/
PCM_RXD_B
19 ALE 59 VCC 99 HOLD 139 DCE_TXD_B/
PCM_TXD_B
20 BHE {A DEN } 60 CLKOUT 100 VSS 140 VSS
21 VSS 61 VSS 101 RSVD_101/UTXDPLS 141 TMROUT0
22 UCLK/USBSOF/USBSCI 62 QS0 102 RSVD_102/UTXDMNS 142 TMRIN0
23 RTR_HU/DCE_RTR_D 63 QS1 103 RSVD_103/UXVOE 143 TMROUT1
24 CTS_HU/DCE_CTS_D/
PCM_TSC_D 64 A11 104 RSVD_104/UXVRCV 144 TMRIN1
25 RXD_HU 65 A12 105 DRQ1 145 INT6
26 TXD_HU 66 AD5 106 VCC 146 INT7
27 VCC 67 AD13 107 INT0 147 INT8/PWD
28 AD0 68 VCC 108 VSS 148 VCC
29 AD8 69 A13 109 INT1 149 DCE_TCLK_C/
PCM_FSC_C
30 A0 70 A14 110 INT2 150 DCE_RCLK_C/
PCM_CLK_C
31 A1 71 VSS 111 INT3 151 DCE_RTR_C
32 A2 72 VSS_A 112 INT4 152 DCE_CTS_C/
PCM_TSC_C
33 VSS 73 X1 113 INT5 153 DCE_RXD_C/
PCM_RXD_C
34 AD1 74 X2 114 RES 154 DCE_TXD_C/
PCM_TXD_C
35 AD9 75 USBX1 115 NMI 155 VSS
36 A3 76 USBX2 116 DCE_TCLK_A/
GCI_FSC_A/
PCM_FSC_A
156 RTR_U/
DCE_RCLK_D/
PCM_CLK_D
37 A4 77 VCC_A 117 DCE_RCLK_A /
GCI_DCL_A/
PCM_CLK_A
157 CTS_U/
DCE_TCLK_D/
PCM_FSC_D
Am186™CC Communications Controller Data Sheet 11
38 AD2 78 VCC 118 DCE_RXD_A/GCI_DD_A/
PCM_RXD_A 158 RXD_U/DCE_RXD_D/
PCM_RXD_D
39 AD10 79 VCC_USB 119 DCE_TXD_A/GCI_DU_A/
PCM_TXD_A 159 TXD_U/DCE_TXD_D/
PCM_TXD_D
40 VCC 80 USBD–/UDMNS 120 VCC 160 VCC
Notes:
1. See Table 29, “PIOs Sorted by PIO Number,” on page A-8 for PIOs sorted by PIO number.
Table 2. PQFP Pin Assignments—Sorted by Signal Name1
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
A0 30 CLKOUT 60 MCS3/RAS1 129 USBD–/UDMNS 80
A1 31 CTS_HU/DCE_CTS_D/
PCM_TSC_D 24 NMI 115 USBX1 75
A2 32 CTS_U/DCE_TCLK_D/
PCM_FSC_D 157 PCS0 {USBSE L1} 5 USBX2 76
A3 36 DCE_CTS_A/PCM_TSC_A 123 PCS1 {USBSEL2} 6 VCC 12
A4 37 DCE_CTS_B/
PCM_TSC_B 137 PCS2 7V
CC 27
A5 42 DCE_CTS_C/PCM_TSC_C 152 PCS3 8V
CC 40
A6 43 DCE_RCLK_A/
GCI_DCL_A/PCM_CLK_A 117 PCS4 {CLKSEL2} 9 VCC 48
A7 44 DCE_RCLK_B/
PCM_CLK_B 135 PCS5 10 VCC 59
A8 45 DCE_RCLK_C/PCM_CLK_C 150 PCS6 11 VCC 68
A9 49 DCE_RTR_A 122 PCS7 13 VCC 78
A10 50 DCE_RTR_B 136 QS0 62 VCC 91
A11 64 DCE_RTR_C 151 QS1 63 VCC 106
A12 65 DCE_RXD_A/GCI_DD_A/
PCM_RXD_A 118 RD 97 VCC 120
A13 69 DCE_RXD_B/
PCM_RXD_B 138 RES 114 VCC 125
A14 70 DCE_RXD_C/
PCM_RXD_C 153 RESOUT 58 VCC 133
A15 84 DCE_TCLK_A/
GCI_FSC_A/PCM_FSC_A 116 RSVD_104/UXVRCV 104 VCC 148
A16 85 DCE_TCLK_B/
PCM_FSC_B 134 RSVD_103/UXVOE 103 VCC 160
A17 88 DCE_TCLK_C/
PCM_FSC_C 149 RSVD_102/UTXDMNS 102 VCC_A 77
A18 89 DCE_TXD_A/GCI_DU_A/
PCM_TXD_A 119 RSVD_101/UTXDPLS 101 VCC_USB 79
A19 90 DCE_TXD_B/
PCM_TXD_B 139 RTR_HU/DCE_RTR_D 23 VSS 1
AD0 28 DCE_TXD_C/
PCM_TXD_C 154 RTR_U/DCE_RCLK_D/
PCM_CLK_D 156 VSS 21
AD1 34 DEN/DS 18 RXD_HU 25 VSS 33
AD2 38 DRQ0 124 RXD_U/DCE_RXD_D/
PCM_RXD_D 158 VSS 41
AD3 46 DRQ1 105 S0 {USBXCV R}57V
SS 53
AD4 51 DT/R 17 S1 56 VSS 61
AD5 66 H LDA {CLKSEL1} 98 S2 55 VSS 71
AD6 86HOLD 99S6 54V
SS 83
AD7 92 INT0 107 SCLK 3 VSS 100
AD8 29 INT1 109 SDATA 4 VSS 108
AD9 35 INT2 110 SDEN 2 VSS 121
AD10 39 INT3 111 SRDY 15 VSS 130
Table 1. PQFP Pin Assignments—Sorted by Pin Number1 (Continued)
Pin No. Name—Left Side Pin No. Name—Bottom Side Pin No. Name—Right Side Pin No. Name—To p Side
12 Am186™CC Communications Controller Data Sheet
AD11 47 INT4 112 TMRIN0 142 VSS 140
AD12 52 INT5 113 TMRIN1 144 VSS 155
AD13 67 INT6 145 TMROUT0 141 VSS_A 72
AD14 87 INT7 146 TMROUT1 143 VSS_USB 82
AD15 93 INT8/PWD 147 TXD_HU 26 WHB 95
ALE 19 LCS/RAS0 131 TXD_U/DCE_TXD_D/
PCM_TXD_D 159 WLB 96
ARDY 14 MCS0 {UCSX8} 126 UCLK/USBSOF/USBSCI 22 WR 16
BHE {ADEN}20MCS1/CAS1 127 UCS {ONCE} 132 X1 73
BSIZE8 94 MCS2/CAS0 128 USBD+/UDPLS 81 X2 74
Notes:
1. For PIOs sorted by signal name, refer to Table 30, “PIOs Sorted by Signal Name,” on page A-9.
Table 2. PQFP Pin Assignments—Sorted by Signal Name1 (Continued)
Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Am186™CC Communications Controller Data Sheet 13
Signal Descriptions
Table 4 on page 14 contains a description of the
Am186CC controller signals. Table 3 describes the
terms used in Table 4. The signals are organized
alphabetically within the following functional groups:
nBus interface/general-purpose
DMA request (page 14)
nClocks/reset/watchdog timer (page 17)
nNo connects (page 18)
nPower and ground (page 19)
nDebug support (page 19)
nChip selects (page 19)
nDRAM (page 20)
nInterrupts (page 21)
nProgrammable I/O (PIOs) (page 22)
nProgrammable timers (page 22)
nAsynchr onous ser ial p or ts (UA RT and High-Spee d
UART) (page 22)
nSynchronous serial interface (SSI) (page 23)
nHDLC synchronous communications: channels
A–D for Data Communications Equipment (DCE),
Pulse-Code Modulation (PCM), and General Circuit
Interface (GCI) interfaces (page 23)
nUniversal serial bus (USB) (page 26)
For pinstraps, refer to Table 31, “Reset Configuration
Pins (Pinstraps),” on page A-10.
Table 3. Signal Description Table Definitions
Term Definition
General terms
[ ] Pin alternate function; a pin defaults to the
signal named without the brackets
{ } Reset c onfiguration pin ( pinstrap)
pin Refers to the physical wire
reset An
external or power-on reset
is ca used by
asserting RES. An
internal res et
is in itiated by
the watchdog timer. A
system reset
is one that
resets the Am186CC controller (the CPU plus
the int ernal peripher als) as well as an y exte rnal
periphera ls connect ed to RESOUT. An e xternal
reset alw ays causes a system reset; an internal
reset can optionally cause a system reset.
signal Refers to the electrical signal that flows across
a pin
SIGNAL A line over a signal name indicates that the
signal is active Low; a signal name without a
line is active High.
Signal types
B Bidirectional
HHigh
LS Programmable to hold l ast state of pin
O Totem pole output
OD Open drain output
OD-O Open drain output or totem pole output
PD Internal pulldown resistor
PU Internal pullup resistor
STI Schmitt trigger Input
STI-OD Schmitt trigger input or open drain output
TS Three-state output
14 Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions
Signal Name Multiplexed
Signal(s) Type Description
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A19–A0 — O Address B us s up pli es no nm ultiplex ed mem ory or I/ O a ddr ess es to the sy ste m
one half of a CLK O UT peri od ea rlier th an the multiplexed addre ss an d data bus
(AD15–AD0). During bus-hold or reset conditions, the address bus is three-
stated with pul ldowns.
When the lo wer or upper chip-select regions are configured for DRAM mode, the
A19–A0 bus provides the row and column addresses at the appropriate times.
The upper and lo w e r me mo ry chip-se lec t ranges can be ind ivi dually c onf igu r ed
for DRAM mode.
AD15–AD0 — B Ad dress an d Data B us time-m ulti ple xed pins suppl y memory or I /O add resses
and data to the system. This bus can supply an address to the system during the
first period of a bus cycle (t1). It transmits (write cycle) or receives (read cycle)
data to or from the system during the remainin g periods of that cy cle (t2, t3, and
t4). The address phase of these pins can be disabled—see the {ADEN} pin
description in Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.
During a reset condition, the address and data bus is three-stated with
pulldowns, and during a bus hold it is three-stated.
In addition, during a re set the state of the address and data bus pins (AD15–
AD0) is latched into the Reset Configuration (RESCON) register. This feature
can be used to provide software with information about the external system at
reset time.
ALE [PIO33] O Address Latch En able indic ates to the s ystem that a n addre ss ap pears on the
address and data bus (AD15–AD0). The address is guaranteed valid on the
falling edge of ALE.
ALE is thr ee-stated and has a pulldown resistor during bus-hold or reset
conditions.
ARDY [PIO8] STI Asynchronous Ready is a true asynchronous ready that indicates to the
Am186CC controller that the addressed memory space or I/O device will
complete a data transfer. The ARDY pin is asynchronous to CLKOUT and is
active High. To guarantee the number of wa it states inserted, ARDY or SRDY
must be synchronized to CLKOUT. If the falling edge of ARDY is not
synchron iz ed to C LKOUT as sp ecifi ed, an a dditio nal cl oc k period c an be a dded.
To alwa ys as sert the ready condition to the m icrocontro ller , tie ARDY and SRDY
High. If the system does not use ARDY, tie the pin Low to yield control to SRDY.
Am186™CC Communications Controller Data Sheet 15
BHE [PIO34]
{ADEN}OBus High Enable: During a memory access, BHE and the least-significant
address bit (AD0) indicate to the system which bytes of the data bus (upper,
lower, or both) participate in a bus cycle. The BHE and AD0 p ins are enco ded as
follows:
BHE is asserted during t1 and remains asserted through t3 and tW. BHE does not
require latchi ng. BH E is three-stated with a pullup during bus-hold and reset
conditions.
WLB and WHB implement the functionality of BHE and AD0 for high and low byte
write enables, and th ey have timing app ropriate fo r us e with th e nonm ul tipl exed
bus in terface.
BHE also signal s DRAM refresh cycle s when using the m ultiple xe d address and
data (AD) bus. A refresh cycle is indicated when both BHE and AD0 are High.
During refres h cy cles , t he AD bus is driv e n during the t 1 pha se an d three -state d
during the t2, t3, and t4 phases. The v alue driv en on the A b us is unde fined during
a refresh cycle. For this reason, th e A0 signal cannot be used in place of the AD0
signal to determine refresh cycles.
BSIZE8 —OBus Size 8 is asserted during t1–t4 to indic ate an 8- bit cycle , or is deasserted to
indicate a 16-bit cycle.
DEN [DS]
[PIO30] OData Enable supplies an output enable to an external data-bus transceiv er. DEN
is asserted during memory and I/O cycles. DEN is deasserted when DT/R
change s state. D EN is three-stated with a pullup during bus-hold or reset
conditions.
[DS]DEN
PIO30 OData Strobe provides a signal where the write cycle timing is identical to the read
cycle timing. When used with other control signals, [DS] provides an interface for
68K-type peripherals without the need for additional system interface logic.
When [DS] is asserted, addresses are valid. When [DS] is asser ted on writes,
data is v alid. W hen [D S] is asserted on rea ds, dat a can be driv en on the AD bu s.
Following a reset, this pin is configured as DEN. The pin is then configured by
software to operate as [DS].
DT/R [PIO29] O Data T ransmit or Receive indicates which direction data should flow through an
external data-bus transceiver. When DT/R is asserted High, th e Am186CC
controller transmits data. When this pin is deasserted Low, the controller
receives data. DT/R is three-stated with a pullup during a bus-hold or reset
condition.
DRQ1
[DRQ0]
—
PIO9
STI
STI
DMA Requests 1 and 0 indicate to the Am186CC controller that an ex ternal
device is ready for a DMA channel to perform a transfer. DRQ1–[DRQ0] are
level-triggered and internally synchronized. DRQ1–[DRQ0] are not latched and
must remain active until serviced.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Data Byte Encoding
BHE AD0 Type of Bus Cycle
00Word transfer
0 1 High byte transfer (bits 15–8)
1 0 Low byte transfer (bits 7–0)
11Refresh
16 Am186™CC Communications Controller Data Sheet
HLDA {CLKSEL1} O Bus-Hold Acknowledge is asserted to indicate to an external bus master that
the Am186CC controller has relinquished control of the local bus. When an
external bus master requests control of the local bus (by asserting HOLD), the
microcon troller complet es the bus cycle in pro gress, the n relinquishes control of
the bus to the external bus mas ter b y asse rting H LD A and three -statin g S2–S0,
AD15–AD0, S6, and A19–A0. The following are also three-stated and have
pullups: UCS, LCS, MCS 3–MCS0, PCS7–PCS0, DEN, RD, WR , BHE, WHB,
WLB, and DT/R. ALE is three-stated and has a pulldown.
When the external bus master has finished using the local bus, it indicates this
to the Am186CC controller by deasserting HOLD. The controller responds by
deasserting HLDA.
If the Am186CC controller requires access to the bus (for example, for refresh),
the controlle r deasserts HLDA before the e xternal bus master deasserts HOLD.
The external bus master must be able to deassert HOLD and allow the controller
access to the bus. See the timing diagrams for bus hold on page 70.
HOLD — STI Bus-Hold Request indicates to the Am186CC controller that an external bus
master needs control of the local bus.
The Am186CC controller’s HOLD latenc y time —the time between HOLD
request and HOLD acknowledge—is a function of the activity occurring in the
processo r whe n the HOL D req ues t i s rec eived. A HOLD requ es t i s sec on d o nl y
to DRAM refresh requests in priority of activity requests received by the
processo r . This impl ies that if a HOLD request is receiv ed just as a DMA tr ansfer
begins, the HOLD latency can be as great as four bus cycles. This occurs if a
DMA word transfer operation is taking place from an odd address to an odd
address. This is a total of 16 clock cycles or more if wait states are required. In
addition, if locked transfers are performed, the HOLD latency time is increased
by the length of the locked transfer. HOLD latency is also potentially increased
by DRAM r efreshes.
The board designer is responsible for properly terminating the HOLD input.
For more information, see the HLDA pin description.
RD —ORead Strobe in dicates to the s ystem that the Am18 6CC controlle r is performing
a memory or I/O read cycle. RD is guaranteed to not be asserted before the
address and data bus is three-stated during the address-to-data transition. RD
is three-stated with a pullup during bus-hold or reset conditions.
S6 — O Bus Cycle Status Bit 6: This signal is asserted during t1–t4 to indicate a DMA-
initiated bus cycle or a refresh cycle. S6 is three-stated during bus hold and
three-stated with a pulldown during reset.
SRDY [PIO35] STI Synchronous Ready indicates to the Am186CC controller that the addressed
memory space or I/O de vice will complete a data transfer . The SRD Y pin accepts
an active High input synchronized to CLKOUT.
Using SRDY instead of ARDY allows a relaxed system timing because of the
elimination of the one-half clock period required to internally synchronize ARD Y.
To alwa ys assert the ready co ndition to the micr ocontroller , tie SRD Y High. If the
system does not use SRDY, tie th e pin L ow to yield control t o ARDY.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Am186™CC Communications Controller Data Sheet 17
S2
S1
S0
—
—
{USBXCVR}
OBus Cycle Sta tus 2–0 indicate to the syst e m th e ty pe of bus cycle in prog ress.
S2 can be used as a logical memory or I/O indicator, and S1 can be used as a
data transmit or receive indicator. S2–S0 are three-stated during bus hold and
three-st ated with a pull up during rese t. The S2–S0 pins a re encoded as follow s:
WHB
WLB
—
—
O
O
Write Hi gh Byte and Write Low Byte indicate to th e syst em which bytes of the
data bus (upper, lower, or both) participate in a writ e cycle. In 80C186
microcontroller des ig ns, this inf ormation is provided by BHE , AD0, and WR.
However, by using WHB and WLB, the standard system interface logic and
external address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical AND of BHE and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WLB is asserted with AD7–AD0. WLB is the logical AND of AD0 and WR. This
pin is three-stated with a pullup during bus-hold or reset conditions.
WR [PIO15] O Write Strobe indicates to the s ys tem th at the data o n the b u s is to be written to
a memory or I/O device. WR is three-stated with a pullup during bus-hold or reset
conditions.
CLOCKS/RESET/WATCHDOG TIMER
CLKOUT — O Clock Output su pplies the clo c k to the sy stem . Dependi ng on the v alues of the
CPU mode select pi ns tr aps, {CLKSEL1} and {CLKSEL2}, CLKOUT oper ate s at
either the PLL frequency or the source input frequency during PLL Bypass
mode. (See Tabl e 31, “Reset Configuration Pins (Pinstraps),” on page A-10.)
CLKOUT remains active during bus-ho ld or reset conditions.
The DISCL K bit in the SYSCON register can be set to disable the CLKOUT
signal. Refer to the
Am186™CC/CH/CU Microcontrollers Register Set Manual
(order #21916).
All synchronous AC timing specifications not associated with SSI, HDLCs,
UARTs, and the USB are synchronous to CLKOUT.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Bus Status Pins
S2 S1 S0 Bus Cycle
0 0 0 Reserved
0 0 1 Read data from I/O
0 1 0 Write data to I/O
011Halt
1 0 0 Instruction fetch
1 0 1 Read data from memory
1 1 0 Write data to memory
1 1 1 None (passive)
18 Am186™CC Communications Controller Data Sheet
RES —STIReset requires the Am186CC controller to perform a reset. When RES is
asserted, the controller immediately terminates its present activity, clears its
internal logic , and on the deassertion of RES , tr ansfers CPU control to the re set
address FFFF0h.
RES must be asserted for at least 1 ms to allow the internal circuits to stabilize.
RES can be asserted asynchronously to CLK OUT because RES is synchronized
internally. For proper initialization, VCC must be within specifications, and
CLKOUT mus t be s tab le fo r more t han four CLKOU T periods during wh ich RES
is asserted.
If RES is asserted while the watchdog timer is pe rforming a w atchdog-timer reset,
the external reset take s preceden ce o ver the watchdog-timer reset. This means
that the RESOUT signal asserts as with any external reset and the WDTCON
register will not ha ve the RSTFLA G bit set. In addition, the con troller will e xit reset
based on the external reset timing, i.e., 4.5 cloc k s after the deas sertion of RES
rather than 216 clocks after the w atc hdog time r timeout occ urred.
The Am186CC controller begins fetching instructions approximately 6.5
CLKOUT periods after RES is de as serted. Th is in put is p r o v id ed w ith a Schmitt
trigger to facilitate power-on RES generation via an RC network.
RESOUT — O Reset Out indicates that the Am186CC controller is being reset (either
externally or internally), and the signal can be used as a system reset to reset
any external peripherals connected to RESOUT.
During an external reset, RESOUT remains active (High) for two clocks after
RES is deas serted. Th e controll er e xits rese t and begin s the first v al id bus cycle
approximately 4.5 clocks after RES is deasserted.
[UCLK] [USBSOF]
[USBSCI]
PIO21
STI UART Clock c an be used in stead of the processor cloc k as the sou rce cloc k for
either the UART or the High-Speed UART. The source clock for the UART and
the High-Speed UART are selected independently and both can use the same
source.
USBX1
USBX2
—
—
STI
O
USB Controller Crystal Input (USBX1) and USB Controller Crystal Output
(USBX2) pro vide c onnections for a fun damental mode, p arallel -resonant crystal
used by the internal USB oscillator circuit.
If the CPU crystal is used to generate the USB clock, USBX1 must be pulled down.
X1
X2
—
—
STI
O
CPU Crystal Input (X1) and CPU Crystal Output (X2 ) prov ide conne ctions fo r
a fundamental mode, parallel-resonant crystal used by the internal oscillator
circuit. If an e xternal oscillat or is used, inject t he signal direc tly into X1 and l eav e
X2 floating.
PINSTRAPS (See Table 31, “Reset Configuration Pins (Pinstra ps),” on page A-10.)
RESERVED
RSVD_101
RSVD_102
RSVD_103
RSVD_104
UTXDPLS
UTXDMNS
UXVOE
UXVRCV
—
—
—
—
RSVD_101–RSVD_104 are reserved unless pinstrap {USBXCVR} is sampled
Low on the rising edge of RESET. When reserved, these pins should not be
connected.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Am186™CC Communications Controller Data Sheet 19
POWER AND GROUND
VCC (15) —STIDigital Power Supply pins supply power (+3.3 ± 0.3 V) to the Am186CC
co ntroller logic.
VCC _A (1) — STI Analog Power Supply pin supplies power (+3.3 ± 0.3 V) to the oscillators and
PLLs.
VCC _USB (1) — STI USB Power Supply pin supplies power (+3.3 ± 0.3 V) to the USB block.
VSS (15) — STI Digital Ground pins connect the Am186CC controller logic to the system
ground.
VSS _A (1) — STI Analog Ground pin connects the oscillators and PLLs to the system ground.
VSS _USB (1) — STI USB Ground pin connects the USB block to the system ground.
DEBUG SUPPORT
QS1–QS0 — O Queue Status 1–0 values provide information to the system concerning the
interaction of the CPU and the instruction queue. The pins have the following
meanings:
The following signals are also used by emulators: A19–A0, AD15–AD0, {ADEN}, ALE, ARDY, BHE, BSIZE8, CAS1–CAS0,
CLKOUT, {CLKSEL2–CLKSEL1}, HLDA, HOLD, LCS, MCS3–MCS0, NMI, {ONCE}, QS1–QS0, RAS1–RAS0, RD, RES,
RESOUT, S2–S0, S6, SRDY, UCS, {UCSX8}, VCC, WHB, WLB, WR. See the
Am186™ CC/ CH/ CU Mi crocontrol ler s User’s
Manual
, order #21914, for more information.
CHIP SELECTS
LCS [RAS0]OLower Memory Chip Select indicates to the syst em that a mem ory ac cess i s in
progress to the lower memory block. The base address and size of the lower
memory block are programmable up to 512 Kbyte. LCS ca n b e c on f ig ured fo r 8-
bit or 16-bit bus size. LCS is three-stated with a pullup resistor during bus-hold
or reset conditions.
[MCS3]
MCS2
MCS1
[MCS0]
[RAS1]
PIO5
[CAS0]
[CAS1]
{UCSX8}
PIO4
OMidrange Memory Chip Selects 3–0 indicate to the system that a memory
access is in progress to the corresponding region of the midrange memory block.
The base address and size of the midrange memory block are programmable.
The midrange chip selects can be configured for 8-bit or 16-bit bus size. The
midrange chip selects are three-stated with pullup resistors during bus-hold or
reset conditions.
[MCS0] can be programmed as the chip select for the entire middle chip select
address range.
Unli ke the U CS and LCS chip sele cts that oper ate relativ e to the earlier tim ing of
the nonm ultipl e xed A address b us , the MC S out puts as sert with the multi plexed
AD address and data bus timing.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Queue Status Pins
QS1 QS0 Queue Operation
0 0 None
0 1 First opcode byte fetched from queue
1 0 Queue was initialized
1 1 Subsequent byte fetched from queue
20 Am186™CC Communications Controller Data Sheet
[PCS7]
[PCS6]
[PCS5]
[PCS4]
PCS3
PCS2
PCS1
PCS0
PIO31
PIO32
PIO2
PIO3
{CLKSEL2}
—
—
[PIO14]
{USBSEL2}
[PIO13]
{USBSEL1}
OPeripheral Chip Selects 7–0 indicate to the system that an access is in
progress to the corresp onding region of the peripher al addre ss b loc k (eith er I/O
or memory address space). The b ase address of th e peripheral address b lock i s
progr a mmable. PCS7–PCS0 are three-stated with pullup resistors during bus-
hold or reset conditions.
Unli ke the U CS and LCS chip sele cts that oper ate relativ e to the earlier tim ing of
the nonmultiplexed A address bus, the PCS outputs assert with the multiplexed
AD address and data bus timing.
UCS {ONCE}OUpper Memory Chip Select indi cates to the system that a m emory access is in
progress to the upper memor y block. The base address and size of the upper
memory block are programmable up to 512 Kbytes. UCS is three-stated with a
weak pullup during bus-hold or reset conditions.
The UCS can be configured fo r an 8-bit or 16-bit bus size out of reset . For
additional information, see the {UCSX8} pin description in Table 31, “Reset
Configuration Pins (Pinstraps),” on page A-10.
After reset, UCS is active for the 6 4-Kbyte me mory rang e from F0000h to FFFFFh,
including the re set addres s of FFFF0h.
DRAM
[CAS1]
[CAS0]
MCS1
MCS2
OColumn Address Strobes 1–0: When either the upper or lower chip select
regions are configured for DRAM, these pins provide the column address strobe
signals to the DRAM. The CAS signals can be used to perform byte writes in a
manne r simi lar to W H B and WLB, respectively (i.e., [CAS0] corresponds to the
low byte (WLB) and [CAS1] corresponds to the high byte (WHB)).
[RAS1][MCS3]
PIO5 ORow Address Strobe 1: When the upper chip select region is configured to
DRAM, this pin provides the row address strobe signal to the upper DRAM bank.
[RAS0]LCS ORow Address Strobe 0: When the lower chip sele ct region is configured to
DRAM, this pin provide s the row addres s strobe sign al to the low er DRAM ban k.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Am186™CC Communications Controller Data Sheet 21
INTERRUPTS
NMI —STINonmaskable Interrupt indicates to the Am186CC controller that an interrupt
request has occurred. The NMI signal is the highest priority hardware interrupt and
cannot be mask ed. The controll er a lways transfers p rogram execution to the
location specified b y th e nonmas kable interrupt v ector in the controller’s interrupt
vector tab l e whe n NMI is asserted.
Although NMI is the highest priority interrupt source, it does not participate in the
priority resoluti on proces s of the mask able interrupts. Th ere is no bit as sociated
with NMI in the interrupt in-service or interrupt request registers. This means that
a new NMI request can interrupt an executing NMI interrupt service routine. As
with al l hardw are interrupts , th e inte rrupt flag (IF) is cleared whe n the process or
takes the interrupt, disabling the maskable interrupt sources. However, if
maskable interrupts are re-enabled by software in the NMI interrupt service
routine ( for example, via the STI instruction) , the fact that an NMI is c urrently in
service does no t have a n y effe ct on the priority resolution of m ask able interrupt
requests . For this reas on, it is stro ngl y advised th at the inter rupt se rvice rou tin e
for NMI should not enable the maskable interrupts.
An NMI transition from Low to High is latched and synchronized internally, and it
initiates the interrupt at the next instruction boundary . To guarantee that the interrupt
is recognized, the NMI pin must be asserted for at least one CLKOUT period.
The board designer is responsible for properly terminating the NMI input.
[INT8]
[INT7]
[INT6]
INT5–INT0
[PWD]
PIO6
PIO7
PIO19
—
STI
STI
STI
STI
Maskable Interrupt Requests 8–0 indicate to the Am186CC controller that an
external interrupt request has occurred. If the individual pin is not masked, the
controller transfers program execution to the location specified by the associated
interrupt vector in the controller’s interrupt vector table.
Interrupt requests are synchronized internally and can be edge-triggered or
level-triggered. The interrupt polarity is programmable. To guarantee interrupt
recognition for edge-triggered interrupts, the user should hold the interrupt
source for a minimum of five system clocks. A second interrupt from the same
source is not recognized until after an acknowledge of the first.
The board designer is responsible for properly terminating the INT8–INT0 inputs.
Also configurable as interrupts are PIO5, PIO15, PIO27, PIO29, PIO30, PIO33, PIO34, and PIO35. (See the
Am186™CC/CH/CU Microcontrollers User’s Manual
, order #21914 for more information.)
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
22 Am186™CC Communications Controller Data Sheet
PROGRAMMABLE I/O (PIOS)
PIO47–PIO0 (For multiplexed
signals see Table
29, “PIOs Sorted
by PIO Number,”
on page A-8 and
Table 30, “PIOs
Sorted by Signal
Name,” on page
A-9.)
BShared Programmable I/O pins can be programmed with the following
attributes: PIO function (enabled/disabled), direc tion (input/outpu t), and weak
pullup or pulldown.
After a res et, th e PIO pins default to v arious c onfigu ratio ns . The colu mn e ntitled
“Pin Configuration Following System Reset” in Table 29 on page A-8 and
Table 30 on page A-9 lists the defaults for the PIOs. Most of the PIO pins are
configured as PIO in puts w ith pull up after reset. See Tabl e 35 on pa ge A-12 for
detailed termination information fo r all pins . Th e s ys tem in iti ali zation c ode m u st
reconfigure any PIO pins as requ ire d.
PIO5, PIO15, PIO27, PIO29, PIO30, and PIO33–PIO35 are capabl e of
generating an interrupt on the shared interrupt channel 14.
The multiplexed signals ALE, ARD Y, BHE, DEN, DT/R, PCS1–PCS0, SRDY, and
WR default to non-PIO operation at reset.
The following PIO signals are multiple xed wi th alternate signals that can be used
by emulators: PIO8, PIO15, PIO33, PIO34, and PIO35. Consi der any emulator
requirements for the alternate signals before using these pins as PIOs.
PROGRAMMABLE TIMERS
[PWD] [INT8]
PIO6 STI Pulse-W idth Demodulator: If pulse-wid th demodulation is enable d, [PWD]
processe s a s ignal th rough t he Schmitt trigge r inpu t. [PWD ] is used int ernally to
drive [TMRIN0] and [INT8], and [PWD] is inverted internally to drive [TMRIN1]
and an additional internal interrupt. If interrupts are enabled and Timer 0 and
Timer 1 are prop erly config ured, the pulse wid th of the al ternating [PWD] sig nal
ca n be calculated by comparing the values in Timer 0 and Timer 1.
In PWD mode , the sign als [TMRIN0]/ PIO27 and [TMRIN 1]/PIO0 can be us ed as
PIOs. If they are not used as PIOs they are ignored internally.
The addit ional internal inter rupt used in PWD mode uses the sa me inter rupt
channel as [INT7]. If [INT7] is to be used, it must be assigned to the shared
interrupt channel.
[TMRIN1]
[TMRIN0]
PIO0
PIO27
STI
STI
Timer Inputs 1–0 supply a clock or control signal to the internal Am186CC
controller timers. After internally synchronizing a Low-to-High transition on
[TMRIN1]–[TMRIN0], the microcontroller increments the timer. [TMRIN1]–
[TMRIN0] must be tied High if not being used. When PIO is enabled for one or
both, the pin is pulled High internally.
[TMRIN1]–[TMRIN0] are driven internally by [INT8]/[PWD] when pulse-width
demodulation functionality is enabled. The [TMRIN1]–[TMRIN0] pins can be
used as PIOs when pulse-width demodulation is enabled.
[TMROUT1]
[TMROUT0]
PIO1
PIO28
O
O
Timer Outputs 1–0 su pply the system w ith either a singl e pulse or a contin uous
waveform with a programmable duty cycle. [TMROUT1]–[TMROUT0] are three-
stated during bus-hold or reset conditions.
ASYNCHRONOUS SERIAL PORTS (UART AND HIGH-SPEED UART)
UART
[RXD_U] DCE_RXD_D
[PCM_RXD_D]
PIO26
STI Receive Data UART is the asynchronous serial receiv e data signal that supplies
data from the asynchronous serial por t to the microcontroller.
[TXD_U] [DCE_TXD_D]
[PCM_TXD_D]
PIO20
OTransmit Data UART is the asynchronous serial transmit data signal that
su pplie s data to the asynchronous serial port fr om th e micr ocont roller
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Am186™CC Communications Controller Data Sheet 23
[CTS_U] [DCE_TCLK_D]
[PCM_FSC_D]
PIO24
STI Clear-T o-Send UART provides the Clear-to-Send signal from the asynchronous
serial port when hardware flow control is enabled for the port. The [CTS_U]
signal gates the transmission of data from the serial port transmit shift register.
When [CTS_U] is asser ted, the transmitter begins transmission of a frame of
data, if an y is available . If [CTS_U ] is deasserted, the tr ansmitte r holds the data
in the s erial port tran smit shift register. The value of [CTS_U] is checked only at
the beginning of the transmission of the frame. [CTS_U] and [RTR_U] form the
hardware handshaking interface for the UART.
[RTR_U] DCE_RCLK_D
[PCM_CLK_D]
PIO25
OReady-To-Receive UART provides the Ready-to-Receive signal for the
asynchronous serial port when hardware flo w control is enabled for the port. The
[RTR_U] sig nal is asserted when th e associated se rial port receiv e data re gister
does not contain valid, unread data. [CTS_U] and [RTR_U] form the hardware
handshaking interface for the UART.
High-Speed UART
[RXD_HU] PIO16 STI Receive Data High-Speed UART is the asynchronous serial receive data signal
that supplies data from the high-speed serial port to the controller.
TXD_HU —OTransmit Data High-Speed UART is the asynchronous serial transmit data
signal that supplies data to the high-speed serial port from the microcontroller.
[CTS_HU] [DCE_CTS_D]
[PCM_TSC_D]
PIO46
STI Clear-To-Send High-Speed UART provides the Clear-to-Send signal from the
high-spee d as ynchrono us se rial port when hard ware flow co ntrol is enab led for
the port. The [CTS_HU] sign al gates the tr ansmission of data from t he serial port
transmit shift register. When [CTS_HU] is asserted, the transmitter begins
transmission of a frame of data, if any is available. If [CTS_HU] is deasserted,
the transmitter holds the data in the serial port transmit shift register. The value
of [CTS_HU ] is checked only at the beginning of the transmission of the frame.
[CTS_HU] and [R TR_HU] form the hardware handshaking interface for the High-
Speed UART.
[RTR_HU] [DCE_RTR_D]
PIO47 OReady-T o-Receive High-Speed UART provides the Ready-to-Receive signal to
the high-spe ed asynch ronous serial port when hardw are flow control is en able d
for the port. The [RTR_HU] signal is asserted when the associated serial port
receive data register does not contain valid, unread data. [CTS_HU] and
[RTR_HU] form the hardware handshaking interface for the High-Speed UART.
SYNCHRONOUS SERIAL INTERFACE (SSI)
[SCLK] PIO11 O Serial Clock provides the clock for the synchronous serial interface to allow
synchronous transfers between the Am186CC controller and a slave device.
[SDATA] PIO12 B Serial Data is used to transmit and receive data between the Am186CC
controller and a slave device on the synchronous serial interface.
[SDEN] PIO10 O Serial Data Enable enab l es data tr ansfe rs on the syn chron ous serial in terface .
HIGH-LEVEL DATA LINK CONTROL SYNCHRONOUS COMMUNICATION INTERFACES
HDLC Channel A (DCE)
DCE_RXD_A [GCI_DD_A]
[PCM_RXD_A] STI DCE Receive Data Channel A is the serial data input pin for the channel A DCE
interface.
DCE_TXD_A [GCI_DU_A]
[PCM_TXD_A] OD-O DCE Transmit Data Channel A is the serial data output pin for the channel A
DCE interface.
DCE_RCLK_A [GCI_DCL_A]
[PCM_CLK_A] STI DCE Receive Clock Channel A provides the receive clock to the channel A
DCE int erface. If the same cl ock is to be used for both tran smit and rec eive , then
this pin should be tied to the DCE_TCLK_A pin externally.
The DCE func tion is the de fault at reset, so th e board desig ner is responsib le for
properly terminating the DCE_RCLK_A input.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
24 Am186™CC Communications Controller Data Sheet
DCE_TCLK_A [GCI_FSC_A]
[PCM_FSC_A] STI DCE Transmit Clock Channel A provides the transmit clock to the channel A
DCE int erface. If the same cl ock is to be used for both tran smit and rec eive , then
this pin should be tied to the DCE_RCLK_A pin externally.
The DCE func tion is the de fault at reset, so th e board desig ner is responsib le for
properly terminating the DCE_TCLK_A input.
[DCE_CTS_A] [PCM_TSC_A]
PIO17 STI DCE Clear To Send Channel A indicates to the channel A DCE interface that
an external serial interface is ready to receive data. [DCE_CTS_A] and
[DCE_RTR_A] provide the handshaking for DCE Channel A.
[DCE_RTR_A]PIO18 O DCE Rea dy to Recei ve Channel A indica tes to an e xternal serial in terface that
the internal channel A DCE interf ace is rea dy to accept data. [DCE_CTS_A ] and
[DCE_RTR_A] provide the handshaking for the channel A DCE interface.
HDLC Channel B (DCE)
[DCE_RXD_B] [PCM_RXD_B]
PIO36 STI DCE Receive Data Channel B is the serial data input pin for the channel B DCE
interface.
[DCE_TXD_B] [PCM_TXD_B]
PIO37 OD-O DCE Transmit Data Channel B is the serial data output pin for the channel B
DCE interface.
[DCE_RCLK_B] [PCM_CLK_B]
PIO40 STI DCE Receive Clock Channel B provides the receive clock to the channel B
DCE interfa ce . If th e same cloc k is to be u sed for b oth tr ansm it an d rece iv e , this
pin should be tied to the [DCE_TCLK_B] pin externally.
[DCE_TCLK_B] [PCM_FSC_B]
PIO41 STI DCE Transmit Clock Channel B provides the transmit clock to the channel B
DCE interfa ce . If th e same cloc k is to be u sed for b oth tr ansm it an d rece iv e , this
pin should be tied to the [DCE_RCLK_B] pin externally.
[DCE_CTS_B] [PCM_TSC_B]
PIO38 STI DCE Clear To Send Channel B indicates to the channel B DCE interface that
an external serial interface is ready to receive data. [DCE_CTS_B] and
[DCE_RTR_B] provide the handshaking for the channel B DCE interface.
[DCE_RTR_B] PIO39 O DCE Rea dy to Receive Ch annel B indica tes to an e xternal serial in terface that
the internal channel B DCE interf ace is rea dy to accept data. [DCE_CTS_B ] and
[DCE_RTR_B] provide the handshaking for the channel B DCE interface.
HDLC Channel C (DCE)
[DCE_RXD_C] [PCM_RXD_C]
PIO42 STI DCE Recei ve Data Channel C is the serial data input pin for the channel C DCE
interface.
[DCE_TXD_C] [PCM_TXD_C]
PIO43 OD-O DCE Transmit Data Channel C is the serial data output pin for the channel C
DCE interface.
[DCE_RCLK_C] [PCM_CLK_C]
PIO22 STI DCE Receive Clock Channel C provides the receive clock to the channel C
DCE interfa ce . If th e same cloc k is to be u sed for b oth tr ansm it an d rece iv e , this
pin should be tied to the [DCE_TCLK_C] pin externally.
[DCE_TCLK_C] [PCM_FSC_C]
PIO23 STI DCE Transmit Clock Channel C provides the transmit clock to the channel C
DCE interfa ce . If th e same cloc k is to be u sed for b oth tr ansm it an d rece iv e , this
pin should be tied to the [DCE_RCLK_C] pin externally.
[DCE_CTS_C] [PCM_TSC_C]
PIO44 STI DCE Clear T o Send Channel C indicates to the chann el C DCE interface that an
external serial interface is ready to receiv e data. [DCE_CTS_C] and
[DCE_RTR_C] provide the hand shaki ng for the channel C DCE interface.
[DCE_RTR_C] PIO45 O DCE Ready to Receive Channel C indicates t o an e xternal serial interfa ce that
the internal channel C DCE is ready to accept data. [DCE_CTS_C] and
[DCE_RTR_C] provide the handshaking for the channel C DCE interface.
HDLC Channel D (DCE)
DCE_RXD_D [RXD_U] (UART)
[PCM_RXD_D]
PIO26
STI DCE Recei ve Data Channel D is the serial data input pin for the channel D DCE
interface.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
Am186™CC Communications Controller Data Sheet 25
[DCE_TXD_D] [TXD_U] (UART)
[PCM_TXD_D]
PIO20
OD-O DCE Transmit Data Channel D is the serial data output pin for the channel D
DCE interface.
DCE_RCLK_D [RTR_U] (UART)
[PCM_CLK_D]
PIO25
STI DCE Receive Clock Channel D provides the receive clock to the channel D
DCE int erface. If the same cl ock is to be used for both tran smit and rec eive , then
this pin should be tied to the [DCE_TCLK_D] pin externally.
[DCE_TCLK_D] [CTS_U] (UART)
[PCM_FSC_D]
PIO24
STI DCE Transmit Clock Channel D provides the transmit clock to the channel D
DCE int erface. If the same cl ock is to be used for both tran smit and rec eive , then
this pin should be tied to the DCE_RCLK_ D pin exter n ally.
[DCE_CTS_D] [CTS_HU] (High-
Speed UART)
[PCM_TSC_D]
PIO46
STI DCE Clear To Send Channel D indicates to the channel D DCE interface that
an external serial interface is ready to receive data. [DCE_CTS_D] and
[DCE_RTR_D] provide the handshaking for DCE Channel D.
[DCE_RTR_D] [RTR_HU] (High-
Speed UART)
PIO47
ODCE Ready To Receive Chann el D indic ates to an e xternal serial interface that
the internal channel D DCE interface is ready to accept data. [DCE_CTS_D] and
[DCE_RTR_D] provide the handshaking for the channel D DCE interface.
HDLC Channel A (PCM)
[PCM_RXD_A] DCE_RXD_A
[GCI_DD_A] STI PCM Receive Data Channel A is the serial data input pin for the channel A PCM
Highway interface.
[PCM_TXD_A] DCE_TXD_A
[GCI_DU_A] O-LS-
OD PCM Transmit Data Channel A is the serial data output pin for the channel A
PCM Highway interface.
[PCM_CLK_A] DCE_RCLK_A
[GCI_DCL_A] STI PCM Clock is the single transmit and receive data clock pin for the channel A
PCM Highway interface.
[PCM_FSC_A] DCE_TCLK_A
[GCI_FSC_A] STI PCM Frame Synchronization Clock provides the Frame Synchronization Clock
input (usually 8 kHz) for the channel A PCM Highway interface.
[PCM_TSC_A] [DCE_CTS_A]
PIO17 OD PCM Time Slot Control A enables an external buffer device when channel A
PCM Highw ay data is presen t on the [PCM _TXD_A] output pin in PC M Highwa y
mode.
HDLC Channel B (PCM)
[PCM_RXD_B] [DCE_RXD_B]
PIO36 STI PCM Receive Data Channel B is the serial data input pin for the channel B PCM
Highway interface.
[PCM_TXD_B] [DCE_TXD_B]
PIO37 O-LS-
OD PCM Transmit Data Channel B is the serial data output pin for the channel B
PCM Highway interface.
[PCM_CLK_B] [DCE_RCLK_B]
PIO40 STI PCM Clock is the single transmit and receive data clock pin for the channel B
PCM Highway interface.
[PCM_FSC_B] [DCE_TCLK_B]
PIO41 STI PCM Frame Synchronization Clock provides the Frame Synchronization Clock
input (usually 8 kHz) for the channel B PCM Highway interface.
[PCM_TSC_B] [DCE_CTS_B]
PIO38 OD PCM Time Slot Control B enables an ex ternal buffer device when channel B
PCM Highw ay data is presen t on the [PCM _TXD_B] output pin in PC M Highwa y
mode.
HDLC Channel C (PCM)
[PCM_RXD_C] [DCE_RXD_C]
PIO42 STI PCM Receive Data Channel C is the serial data input pin for the channel C PCM
Highway interface.
[PCM_TXD_C] [DCE_TXD_C]
PIO43 O-LS-
OD PCM Transmit Data Channel C is the serial data output pin for the channel C
PCM Highway interface.
[PCM_CLK_C] [DCE_RCLK_C]
PIO22 STI-
OPCM Clock: For PCM Highway operation, [PCM_CLK_C ] is the single transmit
and receive data clock input pin for the channel C PCM Highway interface.
[PCM_CLK_C] becomes a clock source output when the GCI to PCM Highway
clock and fra me synchronization conversion are enabled.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
26 Am186™CC Communications Controller Data Sheet
[PCM_FSC_C] [DCE_TCLK_C]
PIO23 BPCM Frame Synchronization Clock: For PCM Highway operation,
[PCM_FSC_C] pro vi des the Frame Sync hronizati on Cloc k in put (usu ally 8 kHz)
for the channel C PCM Highway interface. [PCM_FSC_C] becomes a frame
synchronization source output when the GCI to PCM Highway clock and frame
synchronization conversion are enabled.
[PCM_TSC_C] [DCE_CTS_C]
PIO44 OD PCM Time Slot Control C enables an external buffer device when channel C
PCM Highw ay da ta is present on the [PC M_TXD_C] output pin in PCM Highw a y
mode.
HDLC Channel D (PCM)
[PCM_RXD_D] [ RXD_U] (UART)
DCE_RXD_D
PIO26
STI PCM Receive Data Channel D is the serial data input pin for the channel D PCM
Highway interface.
[PCM_TXD_D] [TXD_U] (UART)
[DCE_TXD_D]
PIO20
O-LS-
OD PCM Transmit Data Channel D is the serial data output pin for the channel D
PCM Highway interface.
[PCM_CLK_D] [RTR_U] (UART)
DCE_RCLK_D
PIO25
STI PCM Clock is the single transmit and receive data clock pin for the channel D
PCM Highway interface.
[PCM_FSC_D] [CTS_U] (UART)
[DCE_TCLK_D]
PIO24
STI PCM Frame Synchronization Clock provides the Frame Synchronization Clock
input (usually 8 kHz) for the channel D PCM Highway interface.
[PCM_TSC_D] [CTS_HU] (High-
Speed UART)
[DCE_CTS_D]
PIO46
OD PCM Time Slot Control D enables an external buffer device when channel D
PCM Highw ay da ta is present on the [PC M_TXD_D] output pin in PCM Highw a y
mode.
HDLC Channel A (GCI)
[GCI_DD_A] DCE_RXD_A
[PCM_RXD_A] B-
OD GCI Data Downstream is the serial data input pin for the channel A GCI
interface.
[GCI_DU_A] DCE_TXD_A
[PCM_TXD_A] B-
OD GCI Data Upstream is the serial data output pin for the channel A GCI interface.
[GCI_DCL_A] DCE_RCLK_A
[PCM_CLK_A] STI GCI Data Clo ck is the singl e trans mit and re ceiv e chann el A GCI da ta cloc k inpu t
generated by an upstream device. The data clock frequency must be twice the data rate.
[GCI_FSC_A] DCE_TCLK_A
[PCM_FSC_A] STI GCI Frame Synchronization Clock provides the 8-kHz F rame Synch ronization
Clock input for the channel A GCI interface generated by an upstream device.
UNIVERSAL SERIAL BUS
[UDMNS]
[UDPLS]
USBD–
USBD+
STI
STI
USB External Transceiver Gated Differential Plus and USB External
Transceiver Gated Differential Minus are inputs from the external USB
transceiver used to detect single-ended zero and error conditions. The signals
have the following meanings:
USBD+
USBD–
[UDPLS]
[UDMNS]
B
B
USB Differential Plus and USB Differential Minus form the bidirectional
electrical data interface for the USB port. The pins form a differential pair that
can be connected to a physical USB connector without an external transceiver.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
USB External Transceiver Signals
UDPLS UDMNS Status
0 0 Single-Ended Zero (SE0)
0 1 Full sp eed
10Reserved
1 1 Error
Am186™CC Communications Controller Data Sheet 27
[USBSCI] [UCLK]
[USBSOF]
PIO21
STI USB Sample Clock Input is used to synchronize an external clock to the
internal USB peripheral controller for isochronous transfers.
[USBSOF] [UCLK]
[USBSCI]
PIO21
OUSB Start of Frame is a 1-kHz frame pulse used to synchronize USB
isochronous transfers to an exter nal device on a frame-by-frame basis.
UTXDMNS RSVD_102 O USB External Transceiver Differential Minus is an output that drives the
external transceiver differential driver minus input.
UTXDPLS RSVD_101 O USB External Transceiver Differential Plus is an output that drives the
external transceiver differential driver plus input.
UXVOE RSVD_103 O USB External Transceiv er Transm it Outpu t Ena ble is an output that enables
the external tra ns cei ver. UXVOE signal s th e external transceiver that USB data
is being ou tput by the Am 186CC USB controller. When Low , this pin enab les the
transceiver output; when High, this pin enables the receiver.
UXVRCV RSVD_104 STI USB External Transce iver Differ ential Receiver is a d ata input received from
the external transceiver differential receiver.
Table 4. Signal Descriptions (Continued)
Signal Name Multiplexed
Signal(s) Type Description
28 Am186™CC Communications Controller Data Sheet
ARCHITECTURAL OVERVIEW
The architectural goal of the Am186CC microcontroller
is to provide co mprehensive communica tions features
on a processor running the widely known x86
instruction set. The Am186CC microcontroller
combines four HDLC channels, a USB peripheral
controller, and general communications peripherals
with the Am1 86 microcontr oller. This highly integrated
microcontroller provides system cost and performance
advantages for a wide range of communications
applications. Figure 1 is a block diagram of the
Am186CC microcontroller, followed by sections
providing an overview of the features of the Am186CC
microcontroller.
Figure 1. Am186CC Controller Block Diagram
Detailed Description
nUniversal Serial Bus (USB) peripheral controller
works with a wide variety of USB devices
– Implements high-speed 12-Mbit/s device function
– Allows an unlimited number of de vice descriptors
– Supports a total of six endpoints: one control
endpoint; one interrupt endpoint; four data
endpoints that can be either bulk or isochronous,
IN or OUT
– Two data endpoints have 16-byte FIFOs; two
data endpoints have 64-byte FIFOs
– Fully integrated dif ferential dri ver directl y
supports the USB interface (D+, D–)
– Special ized har dware su pports adaptive
isochronous data streams
– Gene r al - pu rpose DMA an d Sm artDMA™
channels supported
nFour independent High-level Data Link Control
(HDLC) channels support a wide range of
external interfaces
– External interface connection for HDLCs can be
PCM Highway, GCI, or raw DCE
– Data rate of up to 10 Mbit/s
– Receive and transmit FIFOs
– Support for HDLC, Synchronous Data Link
Control (SDLC), Line Access Procedure
Balanced (LAP-B), Line Access Procedure D
(LAP-D), Point-to-Point Protocol (PPP), and
v.120 (support of v.110 in transparent mode)
– Two dedicated buffer descriptor ring SmartDMA
channels per HDLC
– One independent time-slot assigner per HDLC
– Clear to Send/Ready to Receive (CTS/RTR)
hardware handshaking and auto-enable
operation
– Collision detection for multidrop applications
– Transparency mode
– Address comparison on receive
– Flag or mark idle operation
SmartDMA
General-
Purpose
DMA (4)
Physical
Interface
Raw DCE
PCM
Serial Communications Peripherals
TSA
TSA
TSA
TSA
Muxing
Glueless
Interface
to RAM/ROM DRAM
Controller
Am186
CPU Chip
Selects (48) Watchdog
Timer
Interrupt
Controller UART High-Speed
UART with
Autobaud USB Synchronous
HDLC
HDLC
HDLC
HDLC
(14)
Highway
GCI (IOM-2)
(17 Ext.
Sources)
PIOs Serial
Interface (SSI)
Timers
(3)
System PeripheralsMemory Peripherals
Channels
(8)
Am186™CC Communications Controller Data Sheet 29
nFour independent Time Slot Assigners (TSAs)
provide flexible time slot allocation
– Allows isolation of T ime Division Multiple x e d (TDM)
time slot of choice from a v ariety of TDM carriers
– Up to 4096 sequential bits isolated
– TDM bus can have up to 512 8-bit time slots
– Start bit and stop bit times identify isolated
portion of TDM frame
– 12-bit counters define the start/stop bit times as
the number of bits after frame synchronization
– Entire frame do wn t o 1 bit per fr ame can b e isolated
n12 Direct Memory Access (DMA) channels
– Eight buffer descriptor ring SmartDMA channels
for the four HDLC channels and, optionally, USB
bulk and isochronous endpoints
– Four general-purpose DMAs support the two
integrated asynchronous serial ports and/or USB
endpoints. Two DMA channels have external
DMA request inputs
nHigh-speed asynchronous serial interface
provides enhanced UART functions
– Capable of sustained operation at 460 Kbaud
– 7-, 8-, or 9-bit data transfers
– FIFOs to support high-speed operation
– DMA support available
– A utomatic baud rate detection that allows
emulation of a Hayes AT-compatible modem
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
nAsynchronous serial interface (UART)
– 7-, 8-, or 9-bit data transfers
– DMA support available
– Independent baud generator with clock input
source programmable to use CPU or external
clock input pin
nGeneral Circuit Interface (GCI) provides IOM-2
Terminal Mode connection
– Glueless connection between the Am186CC
microcontroller and GCI-based ISDN transceiver
devices, such as the Am79C30/Am79C32
– Four-p in GC I conne ct ion
– Terminal mode operation
– Slave mode with pin reversal
– Telecom IC (TIC) bus support for D channel
arbitration and collision detection
– Support for one Monitor and two Command/
Indicate channels
– Clock and Frame Sync conversion for PCM
Highway coder-decod er s (code cs )
nSynchronous Serial Interface (SSI) provides
half-duplex, bidirectional interface to high-
speed peripherals
– Useful with many telecommunication interface
perip herals such as code cs , line interface units,
and tranceivers
– Selectable device-select polarity
– Selectab le bit shift order on transmit and receive
– Glueless connection to AMD Subscriber Line
Audio Processing Cir c uit (SLAC™) devices
nClocking options offer high flexibility
– Separate crystal oscillator inputs for system and
USB clock sources
– CPU can run in 1x, 2x, or 4x mode
– USB can run in 2x or 4x mode
– USB can run from system clock if ru nning at
48 MHz, allowing entire system to run from one
12-MHz or 24-MHz crystal
Am186 Embedded CPU
All members of the Am186 family, including the
Am186CC microcontroller, are compatible with the
original industr y-standard 186 par ts, and build on the
same core set of 186 registers, I/O space, address
generation, instructi on set, segme nts, data types, and
addressing modes.
Memory Organization
Memory is organized in sets of segments. Each
segme nt is a li near co ntiguous sequence of 64K (216)
8-bit bytes. Memory is addressed using a two-
component address consisting of a 16-bit segment
value and a 16-bit offset. The 16-bit segment values
are contained in one of four internal segment registers
(CS, DS, SS, or ES). The physical address is
calculated by shifting the segment value left by 4 bits
and adding the 16-bit offset value to yield a 20-bit
physical address (see Figure 2 on page 30). This
allows for a 1-Mbyte physical address size.
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For speed and compact instruction encoding, the
segment register used for physical address generation
is implied by the addressing mode used (see Table 5
on page 30).
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN, INS and OUT, OUTS)
address the I/O space with either an 8-bit port address
specified in the instr uction, or a 16-bit por t address in
the DX register. Eight-bit port addresses are zero-
extended such that A15–A8 are Low.
30 Am186™CC Communications Controller Data Sheet
Figure 2. Two-Component Address Example
Serial Communications Support
The Am186CC microcontroller supports eight serial
interfaces. This includes four HDLC channels, a USB
peripheral controller, two UARTs, and a synchronous
serial interface.
Universal Serial Bus
The Am186CC microcontroller includes a highly
flexible integrated USB peripheral controller that lets
designers implement a variety of microcontroller-based
USB peripheral devices for telephony, audio, and other
high-end applications. This integrated USB peripheral
controller can provide a significant system-cost
reduction compared to other platforms that require a
separate USB controller.
The Am186CC microcontroller can be used in self-
powered USB peripherals that use the full-speed
signalling rate of 12 Mbit/s. The USB low-speed rate
(1.5 Mbit/s) is not supported. An integrated USB
transceiver is provided to minimize system device
count and cost, but an external transceiver can be used
instead, if necessary. The USB controller does not
support USB host or hub functions. However, the
Am186CC microcontroller can be used to implement
USB peripheral functions in a device that also contains
separate USB hub circuitry.
In addition, the Am186CC USB controller supports the
following:
nAn unlimited number of device descriptors
nA total of 6 endpoints: 1 control endpoint, 1 interrupt
endpoint, and 4 data endpoints that can be
config ured as c ontrol, interrup t, b ulk, or isochron ous.
The interrupt, bulk, and isochronous endpoints can
be configured for the IN or OUT direction.
nTwo data endpoints have 16-byte FIFOs; two data
endpoints have 64-byte FIFOs
nFully integrated differential driver, which supports
the USB interface directly
nSpecialized hardware, which supports adaptive
isochronous data streams and automatically
synchronizes with HDLC data streams
nGeneral-purpose DMA and SmartDMA channels
Table 5. Segment Register Selection Rules
Memory Reference Needed Segment Register Used Implicit Segment Selection Rule
Instructions Code (CS) Instructions (including immediate data)
Local Data Data (DS) All data references
Stack Stack (SS) All stack pushes and pops;
any memory references that use the BP register
External Data (Global) Extra (ES) All string instruction references that use the DI registe r as an inde x
1 2 A 4 0
0 0 0 2 2
1 2 A 6 2
1 2 A 4
0 0 2 2
Segment Base
Logical
Address
Shift
Left
4 Bits
Physical Address
To Memo ry
Offset
015
15
15
19
19
0
0
0
0
Am186™CC Communications Controller Data Sheet 31
Four HDLC Channels and Four TSAs
The Am186CC microcontroller provides four HDLC
channels that support the HDLC , SDLC, LAP-B, LAP-D,
PPP, and v.120 protocols. The HDLC channels can also
be used in transparent mode to suppor t v.110. Each
HDLC channel can connect to an external serial
interface directly (nonmultiplexed mode), or can pass
through a TSA (multiplex ed mode). The flexible interface
multiple xing arrangement allows each HDLC channel to
have its own external raw DCE or PCM highway
interface, share the GCI interface with up to two other
channe ls, sha re a co mmon PCM high way or other time
TDM bus with three or more ch anne ls, or wor k in some
combination.
Each HDLC channel’s independent TSA allows it to
extract a subset of data from a TDM bus. The entire
frame, or as little as 1 bit per frame, can be extracted.
Twelve-bit counters define the star t/stop bit times as
the number of bits after frame synchronization. The
time slot can be an arbitrary number of bits up to 4096
bits. Start bit and stop bit times identify the isolated
portion of the TDM frame. Support of less than eight
bits per time slot, or
bit slotting
, allows isolation of from
one to eight bits in a single time slot, providing a
convenient way to work with D-channel data. Each
TDM bus can have up to 5 12 8-bit ti me slo ts. Suppor t
of these features allows interoperation with PCM
highway, E1, IOM-2, T1, and other TDM buses.
The HDLC channels have features that make the
Am186CC m icrocontroller an attractive device for use
where general HDLC capability is required. These
features include CTS/R TR hardware handshaking and
auto-enable operation, collision detection for multidrop
applica tion s, transparenc y mode, address compar iso n
on receive, flag or mark idle operation, two dedicated
buffer descr iptor ring Smar tDMA channels per HDLC,
transmit and receive FIFOs, and full-duplex data
transfer. Each TSA channel can support a burst data
rate to/from the HDLC of up to 10 Mbit/s in both raw
DCE and PCM Highwa y modes, and up to 768 Kbit/s in
GCI mode. Total system data throughput is highly
dependent on the amount of per-packet and per-byte
CPU processing, the rate at which packets are being
sent, and other CPU activity.
When combined with the TSAs, the HDLC channels
can be used in a wide variety of applications such as
ISDN basic rate interface (BRI) and primary rate
interface (PRI) B and D channels, PCM highwa y, X.25,
F rame Relay, and other proprietary Wide Area Network
(WA N) co nnec ti ons.
General Circuit Interface
The General Circuit Interface (GCI) is an interface
specification developed jointly by Alcatel, Italtel, GPT,
and Siemens. This specification defines an industry-
standard serial bus for interconnecting
telecommunications integrated circuits. The standard
covers linecard, NT1, and terminal architectures for
ISDN applications. The Am186CC microcontroller
supports the terminal version of GCI.
The Am186CC GCI interface provides a glueless
connection between the Am186CC microcontroller and
GCI/IOM-2 based ISDN transceiver devices, such as
the AMD Am79C30 or Am79C32. The Am186CC
microcontroller GCI interface provides a 4-pin
connection to the transceiver device. The Am186CC
microcontroller also allows conversion of the GCI clock
and frame synchronization into a format usable by
PCM codecs, allowing PCM codecs to be used directly
with GCI/IOM-2 transceivers. Additional GCI features
include slave mode with pin reversal, Terminal Interchip
Communication (TIC) bus support for D channel
arbitration and co llision de tection, a nd sup port for one
Monitor and two Command/Indicate channels.
Eight SmartDMA™ Channels
The Am186CC microcontroller provides a total of 12
DMA channels. Eight of these channels are SmartDMA
channels, which provide a method for transmission and
reception of data across multiple memory buffers and a
sophisticated buffer-chaining mechanism. These
channels are always used in pairs: transmitter and
receiver. The transmit chann els can onl y transfer dat a
from memory to a peripheral; the receive channels can
only transfer data from a peripheral to memory.
Four of the channels (t wo pairs) are dedicated for use
with two of the on-board HDLC channels. The
remaining four SmartDMA
channels (two pairs) can
support either the third or fourth HDLC channel or USB
endpoints A, B, C, or D.
In addition to the eight SmartDMA channels, the
Am186CC microcontroller provides four general-
purpose DMA channels. For more information about
the four general-purpose DMA channels, refer to “Four
General-Purpose DMA Channels” on page 32.
Two Asynchronous Serial Ports
The Am186 CC microcontroller has two asynchronous
serial ports (a UART and a High-Speed UART) that
provide full-duplex, bidirectional data transfer at
speeds of up to 115.2 Kbit/s or up to 460 Kbit/s,
respectively. The High-Speed UART has 16-byte
transmit an d 32-byte receive FIFOs, special-ch aracter
matching , and automa tic baud -rate detect ion, w hich is
suitable for implementation of a Hayes-compatible
modem interface to a host PC . A lower speed UART is
also available that is typica lly u sed for a low baud-rat e
system configuration port or debug port. Each of these
UARTs c an der ive its ba ud rate from the system clock
or from a separate baud-rate generator clock input.
Both UARTs support 7-, 8-, or 9-bit data transfers;
32 Am186™CC Communications Controller Data Sheet
address bit generation and detection in 7- or 8-bit
frames; one or two stop bits; even, odd, or not parity;
break generation and detection; hardware flow control;
and DMA to and/or from the serial ports using the
general-purpose DMA channels.
Synchronous Serial Port
The Am186CC microcontroller includes one SSI, which
provides a half-duplex, bidirectional, communications
interface between the Am186CC microcontroller and
other system components. This interface is typically
used by the Am186CC microcontroller to monitor the
status of other system devices and/or to configure
these devices under software control. In a
communications application, these devices could be
system components such as audio codecs, line
interface units, and transceivers. The SSI supports
data transfer speeds of up to 25 Mbit/s with a 50-MHz
system clock.
The Am186CC SSI port operates as an interface
master, with the o ther a ttached devices ac ting as s lave
devices. Using this protocol, the Am186CC
microcontroller sends a command byte to the attached
device, and then follows that with e ither a read or write
of a byte of data.
The SSI port consists of three I/O pins: an enable
(SDEN), a clock (SCLK), and a bidirectional data pin
(SDATA). SDEN can be used dire ctly as an enable for
a single attached device. Whe n more than one device
requires control via the SSI, PIOs can be used to
provide enable pins for those devices.
The Am186CC S SI is, in gene ral, software co mpatible
with software written for the Am186EM SSI. (Additional
features have been added to the Am186CC SSI
implementation.) In addition, the Am186CC
microcontroller features the additional capability of
selecting the polarity of the SCLK and SDEN pins, as
well as the shift order of bits on th e SDATA pin ( least-
significant-bit first versus most-significant-bit first). The
Am186CC SSI por t also offers a programmable clock
divisor (dividing the clock from 2 to 256 in power of 2
increments), a bidirectional transmit/receive shift
register, and direct connection to AMD SLAC devices.
System Peripherals
Interrupt Controller
The Am186CC microcontroller features an interrupt
controller, which arranges the 36 maskable interrupt
requests by priority and presents them one at a time to
the CPU. In addition to interrupts managed by the
interrupt controller, the Am186CC microcontroller
supports eight nonmaskable interrupts—an external or
internal nonmaskable interrupt (NMI), a trace interrupt,
and software interrupts and exceptions.
The Am186CC interrupt controller supports 36
maskable interrupt sources through the use of 15
channels. Because of this, most channels support
multiple interrupt sources. These channels are
programmable to support the external interrupt pins and/
or various peripheral devices that can be configured to
gene rate int err u pts. T he 36 mask able in ter r upt s ourc es
includ e 19 int e rnal source s an d 17 external sourc es.
Four General-Purpose DMA Channels
The Am186CC microcontroller provides a total of 12
DMA channels. Four of the channels are general
purpose and can be used for data transfer between
memor y and I/O space s (i.e., memor y-to- I/O or I/O-to-
memory) or within the same space (i.e., memory-to-
memory or I/O-to-I/O). In addition, the Am186CC
microcontroller supports data transfer between
peripherals and memory or I/O. On-chip peripherals
that support general-purpose DMA are Timer 2, the
two asynchronous serial ports (UART and High-Speed
UART), and the USB controller. External peripherals
support DMA transfers through the external DMA
request pins. Each general-purpose channel can
accept synchronized DMA requests from one of four
sources: the DMA reques t pins (DRQ 1–DRQ0) , Timer
2, the UARTs, or t he USB contro ller. In ad dition to th e
four general-purpose channels, the Am186CC
microcontroller provides eight SmartDMA channels.
For more information about the eight SmartDMA
channels, refer to “Eight Smar tDMA™ Channels” on
page 31.
48 Programmable I/O Signals
The Am186CC microcontroller provides 48 user-
programmable input/output signals (PIOs). Each of
these signals shares a pin with at least one alternate
function. If an application does not need the alter nate
function, the associated PIO can be used by
programming the PIO registers.
If a pin is enabled to function as a PIO signal, the
alternate function is disabled and does not affect the
pin. A PIO signal can be configured to operate as an
input or output, with or without internal pullup or
pulldown resisto rs (pul lup or pul ldown d epends on the
pin configuration and is not user-configurable), or as an
open-drain output. Additionally, eight PIOs can be
configured as external interrupt sources.
Three Programmable Timers
There are three 16-bit programmable timers in the
Am186CC microcontroller. Timers 0 and 1 are highly
versat ile and are e ach connected to two exter nal pins
(each one has an input and an output). These two
timers can be used to count or time e xternal ev ents that
dri ve the time r input pins. Timers 0 an d 1 can also be
used to generate nonrepetitive or variable-duty-cycle
waveforms on the timer output pins.
Am186™CC Communications Controller Data Sheet 33
Time r 2 is not conn ect ed to an y external pins . It c an be
used by software to generate interrupts, or it can be
polled for real-time coding and time-dela y applications.
Timer 2 can also be used as a prescaler to Timer 0 and
Timer 1, or as a DMA request source.
The source clock for Timer 2 is one-fourth of the
system clock frequency. The source clock for Timers 0
and 1 can be configured to be one-fourth of the system
clock, or they can be dr i ven from the ir re sp ec tive timer
input pins. When driven from a timer input pin, the timer
is counting the “event” of an input transition.
The Am186CC microcon troller also provides a pulse width
demodulation (PWD) option so that a toggling input signal’s
Low state and H igh state durations can be measured.
Hardware Watchdog Timer
The Am186CC m icroc ontrolle r provides a fu ll-fe atured
watchdog timer, which includes the ability to generate
Non-Maskable Interrupts (NMIs), microcontroller
resets, and system resets when the timeout value is
reached. The timeout value is programmable and
ranges from 210 to 226 processor clocks.
The watchdog timer is used to regain control when a
system has failed due to a software error or to failure of
an external device to respond in the expected way.
Software errors can sometimes be resolved by
recapturing control of the execution sequence via a
watchdog-timer-generated NMI. When an external
device fails to resp ond, or res ponds i ncorrec tly, i t may
be necessary to reset the controller or the entire
system, including external devices. The Am186CC
watchdog timer provides the flexibility to suppor t both
NMI and reset generation.
Memory and Peripheral Interface
System Interfaces
The Am186CC bus interface controls all accesses to
the peripheral control block (PCB), memory-mapped
and I/O-mapped external peripherals, and memory
devices. Intern al peripherals are accessed by the bus
interface through the PCB.
The Am186CC bus interface features programmable
bus sizing; individually selectable chip selects for the
upper (UCS) memory space, lower (LCS) memory
space, all non-UCS, non-LCS and I/O memory spaces;
separate byte-write enables; and boot option from an 8-
or 16-bit device.
The integrated peripherals are controlled by 16-bit
read/write registers. The peripheral registers are
contained within an internal 1-Kbyte control block. At
reset, the base of the PCB is set to FC00h in I/O space.
The registers are physically located in the peripheral
devices they control, but they are addressed as a single
1-Kbyte block. For registers, refer t o the
Am186™CC/
CH/CU Microcontrollers Register Set Manual
(order
#21916).
Accesses to the PCB should be performed by direct
processor actions. The use of DMA to write or read
from the PCB results in unpredictable behavior, except
where explicit exception is made to support a
peripheral function, such as the High-Speed UART
transmit and receive data registers.
The 80C186 and 80C188 microcontrollers use a
multiplex ed address and data (AD) bus. The address is
present on the AD bus only dur ing the t1 clock phase.
The Am186CC microcontroller continues to provide the
multiplexed AD bus and, in addition, provide a
nonmultiplexed address (A) bus. The A bus provides an
address to the sys tem for the complete bus cy cle (t1–
t4). Dur ing refres h cycles, the AD bus is driven dur ing
the t1 phase and the values are unknown during the t2,
t3, and t4 phases. The value driven on the A bus is
undefined during a refresh cycle.
The nonmultiplexed address bus (A19–A0) is valid one-
half CLKOUT cycle in advance of the address on the
AD bus. When used with the modified UCS and LCS
outputs and the byte write en able sign als, the A19–A 0
bus provides a seamless interface to SRAM, DRAM,
and Flash/EPROM memory systems.
F or systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus on the Am186CC microcontroller during the
normal address portion of the bus cycle for accesses to
upper (UCS) and/or lower (LCS) address spaces. In
this mode, the affected bus is placed in a high-
impedanc e s tate during the addr es s po rtion of the bus
cycle. This feature is enabled through the DA bits in the
Upper Memory Chip Select (UMCS) and Lower
Memory Chip Select (LMCS) registers.
When address disable is in effect, the number of
signals that assert on the bus during all normal bus
cycles to the associated address space is reduced,
thus decreasing power consumption, reducing
processor switching noise, and preventing bus
contention with memory de vices and peripherals when
operating at high clock rates.
If the ADEN pin is asser ted during pr ocessor reset, the
value of the DA bits in the UMCS and LMCS registers is
ignored and the ad dress is driven on the AD bus for all
accesses, thus preserving the indust ry-standard 80C 18 6
and 80C188 microcontrollers’ multiplexed address bus
and providing suppor t for existing emulation tools. For
registers, refer to the
Am186™CC/CH/CU
Microcon trol ler s Reg ist er Se t Man ua l
(order #21 916 ).
Figure 3 on page 35 shows the affected signals during
a normal read or write operation. The address and data
are multiplexed onto the AD bus.
34 Am186™CC Communications Controller Data Sheet
Figure 4 on pa ge 36 shows a bus cy cle when add ress
bus disable is in effect, which causes the AD bus to
operate in a nonmultiplex ed data-only mode. The A bus
has the address during a read or write operation.
Bus Interface Unit
The bus interface unit controls all accesses to external
peripherals and memory devices. External accesses include
those to me mory devices, as well a s those to memor y-
mapped and I/O-mapped peripherals and the peripheral
control block. The Am186CC microcontro ller provides an
enhanced bus inter face unit with the following featu res:
nNonmultiplexed address bus
nSeparate byte write enables for high and low bytes
nOutput enable
The standard 80C186/80C188 multiplexed address
and data bus requires system interface logic and an e x-
ternal address latch. On the Am186CC microcontroller ,
byte write enables and a nonmultiplexed address bus
can reduce design costs by eliminating this external
logic.
Nonmultiplexed Address Bus
The nonmultiple xed address bus (A19–A0) is valid one-
half CLKOUT cycle in advance of the address on the
AD bus. When used in conjunction with the modified
UCS and LCS outputs and the byte write enable
signals, the A19–A0 b us provides a seamless interface
to external SRAM, and Flash memory/EPROM
systems.
Byte Write Enables
The Am186CC microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals
that act as byte write enables.
WHB is the logical OR of BHE and WR. WHB is Low
when both BHE and WR are Low. WLB is the logical
OR of A0 and W R. W LB is Low when A0 and WR are
both Low.
The byte write enables are driven with the
nonmultiplexed address bus as required for the write
timing requirements of common SRAMs.
Output Enable
The Am186CC microcontroller prov ides the RD (Read)
signal which acts as an output enable for memory or
peripheral devices. The RD signal is Low when a word
or byte is read by the Am186CC microcontroller.
DRAM Support
To supp ort DRA M, the Am 18 6C C m ic ro co nt r oller has a
fully integrated DRAM controller that provides a glueless
int erface to 25–70-n s Extende d Data Out (EDO) DR AM.
(EDO DRAM is sometimes called Hyper-Page Mode
DRAM.) Up to two banks of 4-Mbit (256 Kbit x 16 bit)
DRAM can be accessed. Page Mode DRAM, Fast Page
Mode DRAM, Asymmetrical DRAM, and 8-bit wide
DRAM are not supported. The Am186CC
microcontroller includes a glueless DRAM interface
providing z ero -wait stat e operation at up t o 50 M Hz wi th
40-ns DRAM. This allows designs requiring larger
amounts of memory to save system cost over SRAM
designs by taking advantage of low DRAM memory
costs.
The DRAM interface uses various chip select pins to
implement the RAS/CAS interface required by DRAMs.
The Am186CC DRAM controller drives the RAS/CAS
interface appropriately during both normal memory
accesses and during refresh. All signals required are
generated by the Am186CC microcontroller and no
external logic is required.
The DRAM mul tip lexed addres s pi ns are connecte d t o
the Am186CC microcontroller’s odd address pins,
starting with A1 on the Am186CC microcontroller
connecting to MA0 on the DRAM. The correct row and
column addresses are generated on these odd
address pins during a DRAM access.
The RAS pins are multiplexed with LCS and MCS3,
allowing a DRAM bank to be present in either high or
low memor y space. The MCS2 an d M CS1 funct ion as
the upper and lower CAS pins, respectively, and define
which b yte of data in a 16-bit DRAM is being accessed.
The Am186CC microcontroller supports the most
common DRAM refresh option, CAS-Before-RAS. All
refresh cy cles contain thre e wait states to suppor t th e
DRAMs at various frequencies. The DRAM controller
nev er performs a burst access. All accesses are single
accesses to DRAM. If the PCS chip selects are
decoded to be in the DRAM address range, PCS
accesses take precedence over the DRAM.
Chip Selects
The Am186CC microcontroller provides six chip select
outputs for use with memory devices and eight more
for use with peripherals in either memory or I/O space.
The six memor y chip selects can be used to address
three memory ranges. Each peripheral chip select
addresses a 256-byte block offset from a
programmable base address.
The Am186 CC microco ntroller c an be programm ed to
sense a ready signal for each of the peripheral or
memory chip select lines. A bit in each chip select
control register determines whether the external ready
signal is required or ignored.
The chip se lects can con trol th e number of wait st ates
inser ted in the bus cycle. Although most memor y and
peri pheral devices ca n be acce ssed with three or le ss
wait states, some slower devices cannot. This feature
allows devices to use wait states to slow down the bus.
Am186™CC Communications Controller Data Sheet 35
The chip se lect lines are active for all memory and I/O
cycles in their programmed areas, whether they are
generated by the CPU or by the integrated DMA unit.
General enhancements over the original 80C186
include bus mastering (th r ee- st ate ) s upp ort for all c hi p
selects and activation only when the associated
register is written, not when it is read.
Clock Control
The processor supports clock rates from 16 to 50 MHz
using an integrated crystal oscillator and PLL.
Commercial and industrial temperature ratings are
available. Separate crystal oscillator inputs are
provided for the USB and CPU. Fle xibility is provided to
run the entire device from a 12-, or 24-MHz crystal
when the USB is in use. The CPU can run in 1x, 2x, or
4x mode; USB can run in 2x or 4x mode.
Figure 3. Am186CC Controller Address Bus — Default Operation
CLKOUT
t1t2t3t4
AD15–AD0
(Read) Data
AD15–AD0
(Write)
LCS or UCS
Address
DataAddress
Address
Phase Data
Phase
A19–A0 Address
MCSx, PCSx
36 Am186™CC Communications Controller Data Sheet
Figure 4. Am186CC Controller—Address Bus Disable In Effect
CLKOUT
t1t2t3t4
AD15–AD0
(Write) Data
LCS or UCS
AD15–AD8
(Read)
AD7–AD0
(Read)
Address
Phase
Data
Data
Phase
Data
A19–A0 Address
Am186™CC Communications Controller Data Sheet 37
In-Circuit Emulator Support
Beca use pi ns ar e a n expensive reso ur ce, many pl ay a
dual role, and the programmer selects PIO operation or
an alter nate functio n. However, a pin c onfigured to be
a PIO may also be required for emulation support.
Therefore, it is important that before a design is
committed to hardware, a user should contact potential
emulator suppliers for a list of their emulator’s pin
requirements. The following PIO signals are
multiplexed with a lternate s ign als that may be u sed by
emulators: PIO8, PIO15, PIO33–PIO35.
The Am186CC microcontroller was designed to
minimize conflicts. In most cases, pin conflict is
avoi ded. For ex ample, if the ALE signal is requir ed for
multiplex bus support, then it would not be
programmed as PIO33. If the multiplex ed AD bus is not
used, then ALE can be programmed as a PIO pin. If the
multiplexed bus is not in use, then the emulator does
not require the ALE signal. However, an emulator is
likely to always use the de-multiplexed address,
regardless of how the AD bus is programmed.
APPLICATIONS
The Am186CC microcontroller, with its integrated
HDLC, USB, and other communications features,
provides a hig hly integrated, c ost-effective solut ion for
a wide range of telecommunications and networking
applications.
nISDN Modems and Terminal Adapters: Next-
generation ISDN equipment requires USB (or High-
Speed UART capability), in addition to three
channels of HDLC.
nLow-End Routers: ISDN to Ethernet-based per-
sonal routers, often used for connections in Small
Office/Home Office (SOHO) environments, require
three channels of HDLC, as well as the high perfor-
mance of a 16-bit controller.
nLinecard Applications: Typically, linecards used in
Central O ffices (COs) , PABX equip ment, and oth er
telephony app li ca tions requi re one or two cha nne ls
of HDLC. Linecard manufacturers are moving to
more lines per card for analog POT S as a means of
cost reduction. This, and digital linecards for sup-
port of ISDN, often require higher performance than
existing 8 -bit devices can offer. Th e Am186CC m i-
crocontroller is an ideal solution for these applica-
tions because it integrates much of the necessary
glue logic while providing higher performance.
nxDSL Applications: Today’s xDSL applications,
such as high-speed ADSL modems, require data
handling of 2 Mbit/s or greater and can take advan-
tage of the USB interface for easy connectivity to
the PC.
nDigital Corded Phones: Typical digital telephone
applications use up to three channels of HDLC and
may use USB for merged PC telephony applica-
tions.
nIndustrial Control: Embedded x86 processors
have long been used in the industrial control mar-
ket. These applications often require a robust, high-
performance processor solution with one or two
channels of HDLC.
nUSB Peripheral Devices: These devices will be-
come more common as the PC market embraces
the USB protocol. In addition to implementing com-
mun icati ons de vi ce cl ass s yste ms such as an ISDN
terminal adapter, the USB controller makes the
Am186CC microcontroller suitable for cer tain PC
desktop applicatio ns such as a USB camera inter-
face, ink-jet printers, and scanners.
nGeneral Communications Applications: The
Am186CC microcontroller will also find a home in
general embedded applications, because many de-
vices will in corpora te communicat ions capability in
the future. Many designs are adding HDLC capabil-
ity as a robust means of inter- and intra-system
communications. The Am186CC microcontroller is
especiall y attractive for 186 d esigns a dding HDLC,
USB, or both.
Block diagrams on the following pages show some
typical Am186C C m icr oc ontrol le r d esi gn s: Figure 5 on
page 38 shows an ISDN terminal adapter system
application, Figure 6 on page 38 shows an ISDN to
Ethernet low-end router application, and Figure 7 on
page 39 shows a 32-channel linecard application.
The ISDN terminal adapter features an S/T or
U interface and either a High-Speed UART or USB
connection for attaching the modem to the PC.
The ISDN-to-Ethernet low-end router features an S/T
or U interface, two POTS lines, and a 10-Mbit/s
connection to the PC.
The 32-channel linecard design demonstrates the
Am186CC microcontroller’s use in a linecard
application where 32 incoming POTS lines are
aggregated onto a single E1 connection.
38 Am186™CC Communications Controller Data Sheet
I
Figure 5. ISDN Terminal Adapter System Application
Figure 6. ISDN to Ethernet Low-End Router System Application
Am186™CC Communications Controller Data Sheet 39
Figure 7. 32-Channel Linecard System Application
40 Am186™CC Communications Controller Data Sheet
CLOCK GENERATION AND CONTROL
The Am186CC controller clocks include the general
system clock (CLKOUT), USB clock, transmitter/
receiver clocks fo r each HDLC cha nnel, and the bau d
rate generator clock for UAR T and High-Speed UART.
The SSI and the timers (Timers 0, 1, and 2) derive their
clocks from the system clock.
Features
The Am186CC controller clocks include the following
features and characteristics:
nTwo independent crystal-controlled oscillators that
use external fundamental mode crystals or
oscillators to generate the system input clock and
the USB input clock.
nTwo independent internal PLLs, one of which
generates a system cl ock (CLKO UT) that is 1x, 2x ,
or 4x the system input clock, and one that generates
the 48-M Hz clock required for the USB from either
a 48-, 24-, or 12-MHz input.
nSingle clock source operation possible by sharing
the clock source between the system and the USB.
nEach HDLC receives its clock inputs directly from
the external communication clock pins (TCLK _X
and RCLK_X ) in all mode s except in G CI mode. In
GCI mode the external GCI communication clocks
(TCLK_A and RCLK_A) are first conv erted to an in-
ternal clocking format (analogous to PCM Highwa y)
before presentation to the HDLC. The system clock
must be at least the same freque ncy as any HDLC
clock.
– HDLC DCE mode supports clocks up to 10 MHz.
– HDLC PCM mode supports clocks up to 10 MHz.
– HDLC GCI mode supports a 1.536-MHz clock
input. (System clock must be at least twice the
GCI clock.)
nSSI clo ck (SCLK ) i s der i ved from the sy s tem cl ock,
divided by 2, 4, 8, 16, 32, 64, 128, or 256.
nTimers 0 and 1 can be configured to be driven by
the timer input pins (TMRIN1, TMRIN0) or at one-
fourth of the system clock. Timer 2 is driven at one-
fourth of the system clock.
nU ART clock can be derived from the internal system
clock frequency or from the UART clock (UCLK)
input.
See Figure 8 on page 41 for a diagram of the basic
clock generation and Figure 9 on page 42 for
suggested clock frequencies and modes.
System Clock
The system PLL generates frequencies from 16 to
50 MHz. The reference for the system PLL can vary
from 8 to 40 MHz, depending on the PLL mode
selected and the desired system frequency (see
Figure 9 on page 42).
The system PLL modes ar e ch ose n by the state of the
{CLKSEL1} and {CLKSEL2} pins during reset. For
these pinstrap settings see Table 31, “Reset
Configuration Pins (Pinstraps),” on page A-10.
The system clock can be generated in one of two wa ys:
nUsing the interna l PLL running at 1x, 2x, or 4x the
reference clock. The reference clock can be
generated from an external crystal using the
integrated oscillator or an e xternal oscillator input.
nBypassing the internal PLL. The external reference
generated from either a crystal or an external
oscillator input is used to generate the system clock.
For more information about bypassing the internal
PLL, refer to “PLL Bypass Mode” on page 43.
USB Clock
The USB PLL provides the 48-MHz clock that is
required for USB full-speed operation. This clock is
divided down to provide a 12- MHz clo ck that suppor ts
the full-speed USB rate (12 Mbit/s). The low-speed rate
of 1.5 Mbit/s is not supported. The USB PLL modes are
chosen b y the state of the {USBSEL1} and {USBSEL2}
pins during reset. For these pinstrap settings, refer to
Table 31, “Reset Configuration Pins (Pinstraps),” on
page A-10.
The USB clock can be generated in one of two ways:
nUsing the system clock. In this mode, the system
PLL is restricted to 48-MHz operation only.
Note: When using the system clock for the USB clock
source, the designer must externally pull down the
USBX1 input.
nUsing its own internal 48-MHz PLL. This PLL can
run i n 2x or 4x mo de an d requi r es a 12- or 24- MHz
reference that can be generated by either the
integrated crystal-controlled oscillator or an
ex ternal oscillator input.
Note: The system clock must be a minimum of 24
MHz when us ing the USB peripheral con troller and its
internal 48-MHz PLL.
The USB specificat ion requires a frequency tolerance
of less than 2500 ppm, which must be met whether
using an external clock source, a crystal on USBX1–
USBX2, or clock sharing by system and USB. When
using a crystal, some frequency tolerance margin must
be allowed to account for the differences in external
loading capacitances, etc. The usual rule of thumb is to
specify a crystal with a frequency tolerance of one half
the required frequency tolerance.
Am186™CC Communications Controller Data Sheet 41
Clock Sharing by System and USB
The system and USB clocks can be generated from a
single sou rce in one of two ways:
nThe system can run at 48 MHz by using the system
clock for the USB clock.
Note: When using the system clock for the USB clock
source, the designer must externally pull down the
USBX1 input.
nThe system can be run at 24 MHz by sharing an
external clock reference (X1) with the USB
(USBX1). A 12-MHz source can be used with the
system PLL in 2x mode and the USB PLL in 4x
mode, or a 24-MHz source can be used with the
system in 1x mode and the USB in 2x mode.
Figure 8. System and USB Clock Generation
{CLKSEL2}–{CLKSEL1}
CLKOUT
PLL Bypass Mode
48-MHz
USB Clock
{USBSEL2}–{USBSEL1}
1x
2x
4x
2x
4x
X1 X2
Am186CC Controller
PLL
PLL
USBX1 USBX2
System Clock
42 Am186™CC Communications Controller Data Sheet
Figure 9. Suggested System Clock Frequencies, Clock Modes, and Crystal Frequencies
Crystal-Driven Clock Source
The internal oscillator circuit is designed to function
with an external parallel-resonant fundamental mode
crystal. The crystal frequency can vary from 8 to
40 MHz, depending on the PLL mode selected and de-
sired system frequency.
When sel ecti ng a crystal, th e load capac itanc e sho uld
always be specified (CL). This value can cause
variance in the oscillation frequency from the desired
specified value (resonance). The load capacitance and
the loading of the feedback network have the following
relationship:
where CS is the stray capacitance of the circuit.
Table 6 shows crystal parameter values. Figure 10
shows the system clocks using an external crystal and
the integrated oscillator . The specific values for C1 and
C2 must be determined by the designer and are
dependent on the c hara cteristics of the chose n crystal
and board design.
Figure 10. External Interface to Support Clocks—
Fundamental Mode Crystal
8-MHz to 25-MHz Xtal or Clock
4x Mode2x Mode1x Mode
32 MHz
System Operating Frequency
1The crystal oscillator is not guaranteed above 40 MHz.
16 MHz
20 MHz 30 MHz 40 MHz 50 MHz
0-MHz to 24-MHz Xtal or Clock
0 MHz 24 MHz
PLL B ypass Mode
8-MHz to 12.5-MHz Xtal or Clock
1x Mode
2x Mode
4x Mode
16-M H z to 40-MH z Xtal or C lo c k
1
PLL
Bypass
Mode
(C1 ⋅ C2)
CL = (C1 + C2)+ CS
Table 6. Crystal Parameters
Parameter Mi n.
Value Max.
Value Units
Frequency 8 40 MHz
ESR
8–24 MHz 20 90 ohms
24–50 MHz 20 60 ohms
Load Capacitance 10 — pF
C2
C1
Xtal
X1/USBX1
X2/USBX2
Am186™CC Communications Controller Data Sheet 43
Exter n al Clock Source
The internal oscillator also can be driven b y an e xternal
clock source. The external clock source should be
conne cted to the input of the inve r ting ampl ifier (X 1 or
USBX1) with the output (X2 or USBX2) left
unconnected. Figure 11 shows the system clocks
using an external clock source (oscillator bypass).
Note: X1, X2, U SBX1, and USBX2 are not 5-V toler-
ant and have a maximum input equal to V
CC
.
Figure 11. External Interface to Support Clocks—
External Clock Sourc e
Static Operation
The Am186CC controller is a fully static design and can
be placed in static mode by stopping the input clock.
PLL bypass mode must be used with an external clock
source. For PLL bypass mode, refer to the PLL Bypass
Mode discussion be low.
Note: It is the re spons ibil ity of the sy stem de sign er to
ensure that no short clock phases are generated when
starting or stopping the clock.
PLL Bypass Mode
The Am 186CC microcontroller provides a PLL Bypass
mode that allows the X1 input frequency to be
anywhere from 0 to 24 MHz. When the microcontroller
is in PLL Bypass mode, the CLKOUT frequency equals
the X1 inp ut frequency. This mode must be used with
an external clock source. For PLL Bypass mode
enabling, refer to Table 31, “Reset Configuration Pins
(Pinstraps),” on page A-10.
When changing frequency in PLL Bypass mode, the X1
input must not have any short or “runt” pulses. At
24 MHz, the nominal High/Low time is 21 ns. The
actual High times and Low times must not fall below 16
ns. These values allow a 60%/40% duty cycle at X1.
In the Am186CC microcontroller, the system clock
must be at the same or a greater frequency than the
HDLC clock and UCLK (if using UCLK). Therefore, if
reducing the system clock frequency, disable these
interfaces or run them at a lower frequency.
The USB PLL and USBX1 determine the USB clock.
USB requires the system clock to be 24 MHz or greater.
Therefore, disable the USB peripheral controller before
slowing the sys tem clock to less than 2 4 MHz. If USB
is not used, the USBX1 can be pulled down.
UART Baud Clock
The UARTs (low- and high-speed) have two possible
clock sources: the system clock or the UCLK input pin.
If UCLK is used f or the UART c lock, the system clock
must be at least the same frequency as UCLK. The
clock configurations are shown graphically in
Figure 12.
The baud clock is generated by dividing the clock
source by the value of baud rate divisor register. The
serial port logic can select its baud rate clock from
either an external pin (UCLK) or from the system clock.
The syste m or UCLK cl ock is sele cted indep endent of
any other settings.
The formula for determining the baud rate divisor
register value is:
BAUDDIV = (clock frequency/(16 • baud rate))
Note: UCLK canno t be clocked at a fr equency hig her
than the system cock frequency.
Figure 12. UART and High-Speed UART Clocks
External
Clock X1/USBX1
X2/USBX2
NC
Baud
Divisor
System Clock
UCLK
UART/High-Speed UART
Oversampling
Clock
Oversample
Baud Clock
Divide for
Autobaud Clock
Clock S ele ct (High-Speed UART Only)
44 Am186™CC Communications Controller Data Sheet
POWER SUPPLY OPERATION
CMOS dynamic power consumption is propor tional to
the square of the operating voltage multiplied by
capacitance and operating frequency. Static system
operation can reduce power consumption by enabling
the system designer to reduce operating frequency
when possible. However, operating voltage is always the
dominant factor in power consumption. By reducing the
operating voltage from 5 V to 3.3 V for any device, the
power consumed is reduced by 56%.
Reduction of system logic operating voltage dramatical-
ly reduces overall system power consumption. Addition-
al power savings can be realized as low-voltage ma ss
storage and peripheral devices become available.
Two basic strategies exist in designing systems
containing the Am186CC controller. The first strategy is
to design a homogenous system in which all logic
components operate at 3.3 V. This provides the lowest
overall power consumption. However, system
designers may need to include de vices for which 3.3-V
versions are not available.
In the second strategy, the syst em desig ner must then
design a mixed 5-V/3.3-V system. This compromise
enables the system designer to minimize the system
logic power consumption while still including the
functionality of the 5-V features. The choice of a mixed
voltage system design also involves balancing design
complexity with the need for the additional features.
Power Supply Connections
Connect all VCC pins together to the 3.3-V power
supply and all ground pins to a common system
ground.
Input/Output Circuitry
To accommodate current 5-V systems, the Am186CC
controller has 5-V tolerant I/O drivers. The drivers
produce TTL-compatible drive output (minimum 2.4-V
logic High) and receive TTL and CMOS levels (up to
VCC + 2.6 V). The following are some design issues
that should be considered with mixed 3.3-V/5-V
designs:
nDuring power-up, if the 3.3-V supply has a
significant delay in achieving stable operation
relative to 5-V supply, then the 5-V circuitry in the
system may start driving the processor’s inputs
above the maximum levels (VCC + 2.6 V). The
system design should ensure that the 5-V supply
does not exceed 2.6 V above the 3.3-V supply
during a power-on sequence.
nPreferably, all inputs are driven by sources that can
be three-stated during a system reset condition.
The system reset condition should persist until
stable VCC conditions are met. This should help
ensure that the maximum input levels are not
exceeded during power-up conditions.
nPreferably, all pullup resistors are tied to the 3.3-V
supply, which ensures that inputs requiring pullups
are not over stressed during power-up.
PIO Supply Current Limit
Each programmable I/O output is able to sink or source
a sust a in ed 1 6 -mA drive curr en t . Ho wever, only 40 m A
of sustained PIO current is allowed for each supply pin
(VCC), and only 60 mA is allowed for each ground pin
(VSS).
To calculate the PIO current for each supply or ground
pin, sum the applicable current (source or sink) of all
PIO pins on either side of the pin (to the adjacent
corresponding pins), and divide the sum by two. The
resulting value should not exceed 40 mA for VCC or
60 mA for VSS.
Exclude the following pins from this calculation: 72
(VSS_A), 82 (VSS_USB), 77 (VCC_A), and 79
(VCC_USB).
For example, to calculate the PIO current for pin 83
(VSS), total the sustained sinking current for all PIO
pins between pin 71 (VSS) and pin 100 (VSS), and
divide the sum by two.
Am186™CC Communications Controller Data Sheet 45
DRIVER CHARACTERISTICS—UNIVERSAL SERIAL BUS
Each USBD+ and USBD– pin connects through a
series resist or directly to the USB. The series resistor
value should be selected to achieve a total driver
impedance between 29 and 44 ohms, as required by
the USB Version 1.0 s pecif ication. A 36-W ±1 % ser ies
resistor is recommended for each pin.
Characteristics of these two pins are defined in the
USB Version 1.0 specification. Consult this
specification for details about overall USB system
design. (At the time of this writing, the current USB
specification and related information can be obtained
on the Web at www.usb.org.)
The Am186CC controller is guaranteed to meet all
USB specifications. Required analog transceivers are
integrated into the Am186CC controller.
ABSOLUTE MAXIMUM RATINGS1
Notes:
1. Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Parameter Symbol Minimum Maximum Unit
Temperature under bias: Commercial TC2
2. T
C
= case temperature.
0100°C
Industrial TA3
3. T
A
= ambient temperature.
–40 +85 °C
Stora ge temperature — –65 +150 °C
Voltag e on 5-V-toler ant pin s4 with respect to groun d
4. 5 V-tolerant pins are indicated in Table 35, “Pin List Summary,” on page A-12.
— –0.5 VCC + 2.6 V
Voltage on other pins with respect to ground — –0.5 VCC + 0.5 V
Sustained PIO current on any supply (VCC) pin5
5. See “PIO Supply Current Limit” on page 44.
—40—mA
Sustained PIO current on any ground (VSS) pin5—60—mA
OPERATING RANGES1
Notes:
1. Operating Ranges define those limits between which the functionality of the device is guaranteed.
Parameter Symbol Minimum Maximum Unit
Commercial TC2
2. T
C
= case temperature.
0100°C
Industrial TA3
3. T
A
= ambient temperature.
–40 + 85 °C
Supply voltage with respect to ground VCC 3.0 3.6 V
46 Am186™CC Communications Controller Data Sheet
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATIN G RA NGES1
Notes:
1. Current out of pin is stated as a negative value.
Symbol Parameter Preliminary Unit
Minimum Maximum
VOH Output High voltage (IOH = –2.4 mA) 2.4 — V
VOH Output High voltage (IOH = –0.1 mA)2
2. Characterized but not tested.
VCC - 0.2 — V
VOL Output Low voltage (IOL = 4.0 m A) — 0.45 V
VIH5 5-V tolerant Input High voltage 2.0 VCC + 2.6 V
VIH Input High volta ge, except 5-V tolerant 2.0 VCC+0.3 V
VIL Input Low voltage –0.3 0.8 V
ILI Input leakage current (0.1 V VOUT VCC)
(All pins except th ose with internal pullup/pulldown resistors) —±10mA
ILO Output leakage current3 (0.1 V VOUT VCC)
3. This parameter is for three-state outputs wher e V
OUT
is driven on the three-state output.
—±15mA
PCC Power cons umption — 1.2 W
CAPACITANCE
Symbol Parameter Preliminary Unit
Minimum Maximum
CIN Input capac ita nc e — 15 pF
CCLK Clock capacitanc e — 15 pF
COUT Output capacitance — 20 pF
CI/O I/O pin capacitance — 20 pF
Am186™CC Communications Controller Data Sheet 47
MAXIMUM LOAD DERATING
All maximum delay numbers should be increased by
0.035 ns for every pF of load (up to a maximum of 150
pF) over the maximum l oad spec ified in Table 35, “ Pi n
List Summary,” on page A-12.
POWER SUPPLY CURRENT
For the fol lowing typ ical sys tem spe cificat ion shown in
Figure 13, ICC has been measured at 6 mA per MHz of
system clock. The typical system is measured while the
system is executing code in a typical application with
nominal voltage and maximum case temperature.
Actual power supply current is dependent on system
design an d may be greater or less than th e typ ical ICC
fi gure presented here.
Typica l current in Figure 13 is given by:
ICC = 6 mA ¼ freq(MHz)
Please note that dynamic ICC measurements are de-
pendent upon chip activity, operating frequency, output
buffer logic, and capacitive/resistive loading of the out-
puts. For these ICC measurements, the devices were
set to the following modes:
nNo DC loads on the output buffers
nOutput capacitive load set to 30 pF
nAD bus set to data only
nPIOs are disabled
nTimer, serial port, refresh, and DMA are enabled
Tab l e 7 sh o ws th e v a lues that are used to ca lcul ate t he
typical power consumption value for the Am186CC
controller.
Figure 13. Typical Icc Versus Frequency
Table 7. Typical Power Consumption Calculation
MHz ¼ ICC ¼ Volts / 1000 = P Typical Power
in Watts
MHz Typical ICC Volts
25 6 3.3 0.495
40 6 3.3 0.792
50 6 3.3 0.99
Clock Frequency (MHz)
ICC (mA)
0
40
80
120
160
200
240
280
10 20 30 40 50
320
48 Am186™CC Communications Controller Data Sheet
THERMAL CHARACTERISTICS
PQFP Package
The Am186CC controller is specified for operation with
case temperature ranges from 0C to + 100 C for 3.3 V
± 0.3 V (commercial). Case temperature is measured
at the top center of the package as shown in Figure 14.
The v arious temperatures and thermal resistances can
be determined using the equations in Figure 15 with
information given in Table 8.
The total thermal resistance is qJA; qJA is the sum of
qJC, the internal thermal resistance of the assembly,
and qCA, the case to ambient thermal resistance.
The variable
P
is power in watts. Power supp ly cu rren t
(ICC) is in mA per MHz of clock frequency.
Figure 14. Thermal Resistance(C/Watt)
Figure 15. Thermal Characteristics Equations
qJA qCA
qJC
qJA = qJC + qCA
TC
Table 8. Thermal Chara cteri st ics (C/Watt)
Package/Board
Airflow
(Linear Feet
per Minute) qJC qCA qJA
PQFP/2-Layer 0 fpm 7 38 45
200 fpm 7 32 3 9
400 fpm 7 28 3 5
600 fpm 7 26 3 3
PQFP/4-Layer
to 6-La yer 0 fpm 5 18 23
200 fpm 5 16 2 1
400 fpm 5 14 1 9
600 fpm 5 12 1 7
qJA = qJC + qCA
P = ICC ¼ freq (MHz) ¼
V
CC
TJ = TC+ (P ¼ qJC)
TJ = TA+ (P ¼ qJA)
TC = TJ – (P ¼ qJC)
TC = TA + (P ¼ qCA)
TA = TJ – (P ¼ qJA)
TA = TC – (P ¼ qCA)
Am186™CC Communications Controller Data Sheet 49
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbreviations are used to ind icate the spec ific per iods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. Whe n no bus cycle is pe nding, an idle (t i) state
occurs.
In the switching parameter descriptions, the
multiplexed
address is referred to as the AD address
bus; th e
demultiplexed
address is referr ed to as the A
address bus. Figure 16 defines symbols used in the
switching waveform diagrams.
Table 9 on page 50 contains an alphabetical listing of
the switching parameter symbols, and Table 10 on
page 54 contains a numerical listing of the switching
parameter symbols.
Figure 16. Key to Switching Waveforms
Must be
Steady Will be
Steady
Will be
changing from H
to L or from H
to three-state
Will be changing
from L to H or
from L to three-
state
WAVEFORM INPUT OUTPUT
May change
from H to L or
from H to three-
state
May change
from L to H or
from L to three-
state
50 Am186™CC Communications Controller Data Sheet
Table 9. Alphabetical Key to Switching Parameter Symbols
Parameter
Symbol No. Description
tARYCH 49 ARDY resolution transition setup time
tARYCHL 51 ARDY inactive holding time
tARYHDSH 951ARDY High to DS High
tARYHDV 891ARDY assert to data valid
tARYLCL 52 ARDY setup time
tARYLDSH 961ARDY Low to DS High
tAVBL 87 A address valid to WHB, WLB Low
tAVCH 14 AD address valid to clock High
tAVLL 12 AD address valid to ALE Low
tAVRL 66 A address valid to RD Low
tAVWL 65 A address valid to WR Low
tAZRL 24 AD address float to RD active
tCH1CH2 45 CLKOUT rise time
tCHAV 68 CLKOUT High to A address valid
tCHCAS 404 Change in CAS delay
tCHCK 38 X1 High time
tCHCL 44 CLKOUT High time
tCHCSV 67 CLKOUT High to LCS/UCS valid
tCHCSX 18 MCS/PCS inactive delay
tCHCTV 22 Control active delay 2
tCHCV 64 Command lines valid delay (after float)
tCHCZ 63 Command lines float delay
tCHDX 8 Status hold time
tCHLH 9 ALE active delay
tCHLL 11 ALE inactive delay
tCHQ0SV 55 Queue status 0 output delay
tCHQ1SV 56 Queue status 1 output delay
tCHRAS 403 Change in RAS delay
tCHRFD 791CLKOUT High to RFSH valid
tCHSV 3 Status active delay
tCICO 69 X1 to CLKOUT skew
tCKHL 39 X1 fall time
tCKIN 36 X1 period
tCKLH 40 X1 rise time
tCL2CL1 46 CLKOUT fall time
tCLARX 50 ARDY active hold time
tCLAV 5 AD address and BHE valid delay
tCLAX 6 Address hold
tCLAZ 15 AD address float delay
tCLCH 43 CLKOUT Low time
tCLCK 37 X1 Low time
tCLCL 42 CLKOUT period
tCLCLX 801LCS inactive de lay
Am186™CC Communications Controller Data Sheet 51
tCLCSL 811LCS active delay
tCLCSV 16 MCS/PCS active delay
tCLDOX 30 D ata hold time
tCLDV 7 Data valid delay
tCLDX 2 Data in hold
tCLHAV 62 HLDA valid delay
tCLRF 821CLKOUT High to RFSH invalid
tCLRH 27 RD inactive delay
tCLRL 25 RD active delay
tCLSH 4 Status and BHE inactive delay
tCLSRY 48 SRDY transition hold time
tCLTMV 54 Timer output delay
tCOLV 402 Column address valid delay
tCSHARYL 881Chip select to ARDY Low
tCVCTV 20 Control active de lay 1
tCVCTX 31 Control inactive delay
tCVDEX 21 DEN/DS inactive delay
tCXCSX 17 MCS/PCS hold from command inactive
tDSHDIR 921DS High to data invalid—read
tDSHDIW 981DS High to data invalid—write
tDSHDX 931DS High to data bus turn-off time
tDSHLH 41 DS inactive to ALE inactive
tDSLDD 901DS Low to data driven
tDSLDV 911DS Low to data valid
tDVCL 1 Data in setup
tDVDSL 971Data valid to DS Low
tDXDL 19 DEN/DS inactive to DT/R Low
tHVCL 58 HOLD setup
tINVCH 53 Peripheral setup time
tLCRF 861LCS inactive to RFSH active delay
tLHAV 23 ALE High to address valid
tLHLL 10 ALE width
tLLAX 13 AD address hold from ALE inactive
tLRLL 841LCS precharge pulse widt h
tRESIN 57 RES setup time
tRFCY 851RFSH cycle time
tRHAV 29 RD inactive to AD address active
tRHDX 59 RD High to data hold on AD bus
tRHDZ 941RD High to data bus tur n-off time
tRHLH 28 RD inactive to ALE High
tRLRH 26 RD pulse width
tSRYCL 47 SRDY transition setup time
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol No. Description
52 Am186™CC Communications Controller Data Sheet
tWHDEX 35 WR inactive to DEN inactive
tWHDX 34 Data hold after WR
tWHLH 33 WR inactive to ALE High
tWLWH 32 WR pulse width
USB Timing (Clocks)
tUCHCK 3 USBX1 High time
tUCKHL 4 USBX1 fall time
tUCKIN 1 USBX1 period
tUCKLH 5 USBX1 rise time
tUCLCK 2 USBX1 Low time
USB Timing (Data/Jitter)
tF2Fall time
tJR1 3 Consecutive transition jitter
tJR2 4 Paired transition jitter
tR1Rise time
DCE
tTCLKH 2 DCE clock High
tTCLKHD 6 DC E clock hold
tTCLKL 3 DCE clock Low
tTCLKO 4 DCE clock to output delay
tTCLKPER 1 DC E clock pe riod
tTCLKR 7 DCE clock rise/fall
tTCLKSU 5 DCE cl ock setup
PCM (Slave)
tCLKP 1 PCM clock period
tDCD 8 Delay time from CLK High to TXD valid
tDCLT 13 Delay from CLK Low of last bit to TSC invalid
tDCT 11 Delay to TSC valid from CLK
tDFT 12 Delay to TSC valid from FSC
tDTW 17 Delay from last bit CLK Low to TXD weak drive
tDZF 5 Delay time to valid TXD from CLK
tDZF 6 Delay time to valid TXD from FSC
tHCD 10 Hold time from CLK Low to RXD invalid
tHCF 4 Hold time from CLK Low to FSC valid
tHFI 14 Hold time from CLK Low to FSC invalid
tSUDC 9 Setup time from RXD valid to CLK
tSUFC 7 Setup time for FSC High to CLK Low
tSYNSS 15 Time between successive synchronization pulses
tWH 2 PCM clock High
tWL 3 PCM clock Low
tWSYN 16 FSC width invalid
tDTZ 18 Delay from last bit CLK ( plus one) High to TXD disable
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol No. Description
Am186™CC Communications Controller Data Sheet 53
PCM (Master)
tDCFH 1 Delay time from CLK High to FSC High
tDCFL 2 Delay time from CLK High to FSC Low
GCI
tDHC 9 Data hold/clock
tDSC 7 Data delay/clock
tDSF 8 Data delay/FSC
tFD 5Frame delay/clock
tFH 4 Frame hold/clock
tHD 11 Data hold
tSD 10 Data setup
tSF 3 Frame setup
tWFH 6 Frame width High
tWH 1 P ulse width High
tWL 2 P ulse width Low
SSI
tCLEV 1 CLKOUT Low to SDEN valid
tCLSL 2 CLKOUT Low to SCLK Low
tDVSH 3 Data valid to SCLK High
tSHDX 4 SCLK High to data invalid
tSLDV 5 SCLK Low to data valid
Notes:
1. Specification defined but not in use at this time.
Table 9. Alphabetical Key to Switching Parameter Symbols (Continued)
Parameter
Symbol No. Description
54 Am186™CC Communications Controller Data Sheet
Table 10. Numerical Key to Switching Parameter Symbols
No. Parameter
Symbol Description
1t
DVCL Data in setup
2t
CLDX Data in hold
3t
CHSV Status active delay
4t
CLSH Status and BHE inactive delay
5t
CLAV AD address and BHE valid delay
6t
CLAX Address hold
7t
CLDV Data valid delay
8t
CHDX Status hold time
9t
CHLH ALE active delay
10 tLHLL ALE width
11 tCHLL ALE inacti ve delay
12 tAVLL AD address valid to ALE Low
13 tLLAX AD address hold from ALE inactive
14 tAVCH AD address valid to clock High
15 tCLAZ AD address float delay
16 tCLCSV MCS/PCS active delay
17 tCXCSX MCS/PCS hold from command inactive
18 tCHCSX MCS/PCS inactive delay
19 tDXDL DEN/DS inactive to DT/R Low
20 tCVCTV Control active delay 1
21 tCVDEX DEN/DS inactive delay
22 tCHCTV Control active delay 2
23 tLHAV ALE High to address valid
24 tAZRL AD address float to RD active
25 tCLRL RD active delay
26 tRLRH RD pulse width
27 tCLRH RD inactive delay
28 tRHLH RD inactive to ALE High
29 tRHAV RD inactive to AD address active
30 tCLDOX Data hold time
31 tCVCTX Control inactive delay
32 tWLWH WR puls e width
33 tWHLH WR inactive to ALE High
34 tWHDX Data hold after WR
35 tWHDEX WR inactive to DEN inactive
36 tCKIN X1 period
37 tCLCK X1 Low time
38 tCHCK X1 High time
39 tCKHL X1 fall time
40 tCKLH X1 rise time
41 tDSHLH DS inactive to ALE inactive
42 tCLCL CLKOUT period
43 tCLCH CLKOUT Low time
Am186™CC Communications Controller Data Sheet 55
44 tCHCL CLKOUT High time
45 tCH1CH2 CLKOUT rise time
46 tCL2CL1 CLKOUT fall time
47 tSRYCL SRDY transition setup time
48 tCLSRY SRDY transition hold time
49 tARYCH ARDY resolution transition setup time
50 tCLARX ARDY active hold time
51 tARYCHL ARDY inactive holding time
52 tARYLCL ARDY setup time
53 tINVCH Peripheral setup time
54 tINVCL DRQ setup time
54 tCLTMV Timer output delay
56 tCHQSV Q ueu e stat us output delay
57 tRESIN RES setup time
58 tHVCL HOLD setup
59 tRHDX RD High to data hold on AD bus
62 tCLHAV HLDA valid delay
63 tCHCZ Command lines float delay
64 tCHCV Command lines valid delay (after float)
65 tAVWL A address valid to WR Low
66 tAVRL A address valid to RD Low
67 tCHCSV CLKOUT High to LCS/UCS valid
68 tCHAV CLKOUT High to A address valid
69 tCICO X1 to CLKOUT skew
79 tCHRFD CLKOUT High to RFSH valid
801tCLCLX LCS inactive delay
811tCLCSL LCS active delay
821tCLRF CLKOUT High to RFSH invalid
841tLRLL LCS precharge pul se widt h
851tRFCY RFSH cycle time
861tLCRF LCS inactive to RFSH active delay
871tAVBL A address valid to WHB, WLB Low
881tCSHARYL Chip select to ARDY Low
891tARYHDV ARDY assert to data valid
901tDSLDD DS Low to data driven
911tDSLDV DS Low to data valid
921tDSHDIR DS High to data invalid—read
931tDSHDX DS High to data bus turn-off time
941tRHDZ RD High to data bus turn-off time
951tARYHDSH ARDY High to DS High
961tARYLDSH ARDY Low to DS High
971tDVDSL Data valid to DS Low
Table 10. Numerical Key to Switching Parameter Symbols (Continued)
No. Parameter
Symbol Description
56 Am186™CC Communications Controller Data Sheet
981tDSHDIW DS High to data invalid—write
402 tCOLV Column address valid delay
403 tCHRAS Change in RAS delay
404 tCHCAS Change in CAS delay
USB Timing (Clock s)
1t
UCKIN USBX1 period
2t
UCLCK USBX1 Low time
3t
UCHCK USBX1 High time
4t
UCKHL USBX1 fall time
5t
UCKLH USBX1 rise time
USB Timing (Data/J itter)
1t
RRise time
2t
FFall time
3t
JR1 Consecutive transition jitter
4t
JR2 Paired transition jitter
DCE
1t
TCLKPER DCE clock period
2t
TCLKH DCE clock High
3t
TCLKL DCE clock Low
4t
TCLKO DCE clock to output delay
5t
TCLKSU DCE clock setup
6t
TCLKHD DCE clo ck hold
7t
TCLKR DCE clock rise /fall
PCM (Slave)
1t
CLKP PCM clock period
2t
WH PCM clock High
3t
WL PCM clock Low
4t
HCF Hold time from CLK Low to FSC valid
5t
DZF Delay time to valid TXD from CLK
6t
DZF Delay time to valid TXD from FSC
7t
SUFC Setup time for FSC High to CLK Low
8t
DCD Delay time from CLK High to TXD valid
9t
SUDC Setup time from RXD valid to CLK
10 tHCD Hold time from CLK Low to RXD invalid
11 tDCT Delay to TSC valid from CLK
12 tDFT Delay to TSC valid from FSC
13 tDCLT Delay from CLK Low of last bit to TSC invalid
14 tHFI Hold time from CLK Low to FSC invalid
15 tSYNSS Time between successive synchronization pulses
16 tWSYN FSC width invalid
17 tDTW Delay from last bit CLK Low to TXD weak drive
18 tDTZ Delay from last bit CLK (plus one) High to TXD disable
Table 10. Numerical Key to Switching Parameter Symbols (Continued)
No. Parameter
Symbol Description
Am186™CC Communications Controller Data Sheet 57
PCM (Master)
1t
DCFH Delay time from CLK High to FSC High
2t
DCFL Delay time from CLK High to FSC Low
GCI
1t
WH Pulse width High
2t
WL Pulse width Low
3t
SF Frame setup
4t
FH Frame hold/clock
5t
FD Frame delay/clock
6t
WFH Fram e width High
7t
DSC Data delay/clock
8t
DSF Data delay/FSC
9t
DHC Data hold/clock
10 tSD Data setup
11 tHD Data hold
SSI
1t
CLEV CLKOUT Low to SDEN valid
2t
CLSL CLKOUT Low to SCLK Low
3t
DVSH Data valid to SCLK High
4t
SHDX SCLK High to data invalid
5t
SLDV SCLK Low to data valid
Notes:
1. Specification defined but not in use at this time.
Table 10. Numerical Key to Switching Parameter Symbols (Continued)
No. Parameter
Symbol Description
58 Am186™CC Communications Controller Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
In this section the following timings and timing
waveforms are shown:
nRead (page 58)
nWrite (page 61)
nSoftware halt (page 64)
nPeripheral (page 65)
nReset (page 66)
nExternal ready (page 68)
nBus hold ( page 69)
nSystem clocks (page 71)
nUSB clocks (page 72)
nGCI bus (page 73)
nPCM highway (slave) (page 74)
nPCM highway (master) (page 76)
nDCE interface (page 77)
nUSB (page 78)
nSSI (page 79)
nDRAM (page 80)
Table 11. Read Cycle Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
General Timing Requirements
1t
DVCL Data in setup 10 —5—5—ns
2t
CLDX Data in hold23—2—2—ns
General Timing Responses
3t
CHSV Status active delay 0 20 0 12 0 10 ns
4t
CLSH Status and BHE
inactive delay 020012010ns
5t
CLAV AD address and
BHE valid delay 020012010ns
6t
CLAX Address hold 0 — 0 — 0 — ns
8t
CHDX Status hold time 0 — 0 — 0 — ns
9t
CHLH ALE active delay — 20 — 12 — 10 ns
10 tLHLL ALE width tCLCL–10=30 — tCLCL–5=20 — tCLCL–5=15 — ns
11 tCHLL ALE inactiv e de lay — 20 — 12 — 10 ns
12 tAVLL AD address valid to
ALE Low30.5 • tCLCH — 0.5 • tCLCH —0.5 • t
CLCH —ns
13 tLLAX AD address hold
from ALE inactive3tCHCL —t
CHCL —t
CHCL —ns
14 tAVCH AD address valid to
clock High 0—0—0—ns
15 tCLAZ AD address floa t
delay tCLAX=0 20 tCLAX=0 12 tCLAX=0 10 ns
16 tCLCSV MCS/PCS active
delay 020012010ns
17 tCXCSX MCS/PCS hold from
command inactive tCLCH —t
CLCH —t
CLCH —ns
18 tCHCSX MCS/PCS inactive
delay 020012010ns
19 tDXDL DEN/DS inactiv e to
DT/R Low3, 4 –1 — –1 — –1 — ns
20 tCVCTV Control active
delay 1 020012010ns
Am186™CC Communications Controller Data Sheet 59
21 tCEVDX DEN/DS inactive
delay4020012010ns
22 tCHCTV Control active
delay 2 020012010ns
23 tLHAV ALE High to
addre ss valid 15 —7.5— 5 —ns
Read Cycle Timing Responses
24 tAZRL AD addres s float to
RD active 0—0—0—ns
25 tCLRL RD active delay 020010010ns
26 tRLRH RD pulse width 2tCLCL–15=65 — 2tCLCL–10=40 — 2tCLCL–10=30 — ns
27 tCLRH RD inactive delay020012010ns
28 tRHLH RD inactiv e to ALE
High3tCLCH–3 — tCLCH–2 — tCLCH–2 — ns
29 tRHAV RD inactive to AD
address ac tive 3tCLCL–10=30 — tCLCL–5=20 — tCLCL–5=15 — ns
59 tRHDX RD High to data
hold on AD Bus23—2—0—ns
66 tAVRL A address valid to
RD Low 1.5tCLCL–15=45 — 1.5tCLCL–10=
27.5 —1.5t
CLCL–10=20 — ns
67 tCHCSV CLKOUT High to
LCS/UCS valid 020010010ns
68 tCHAV CLKOUT High to A
addre ss valid 020010010ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. If either specification 2 or specification 59 is met with respect to data hold time, then the device functions correctly.
3. Testing is performed with equal loading on referenced pins.
4. The timing of this s ignal is the same for a read cycle, whether it is configured to be DEN or DS.
Table 11. Read Cycle Timing1 (Continued)
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
60 Am186™CC Communications Controller Data Sheet
Figure 17. Read Cycle Waveforms
T4 T1 T2 T3 T4
1
2
14
12
13
24 59 29
1010 28
2626 17
19
68
38
5
15
911
25 27
67
16 18
20 21
22 22
3 4
Addr. Data
CLKOUT
A19–A0
S61
AD15–AD0
ALE
RD
BHE
LCS, UCS
MCS3–MCS0,
DEN, DS
DT/R
S2–S0
6
23
4
5
tw
66
Notes:
1. S6 is not valid for the first fetch until the timing fo r parameter 3 (status active delay (t
CHSV
)) is met.
PCS7–PCS0
Am186™CC Communications Controller Data Sheet 61
Table 12. Write Cycle Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
General Timing Responses
3t
CHSV Status act ive delay 0 20 0 12 0 1 0 ns
4t
CLSH Status and BHE
inactive dela y 020012010ns
5t
CLAV AD address and
BHE va lid delay 020012010ns
6t
CLAX Addre ss ho ld 0 —0—0—ns
7t
CLDV Data valid delay 0 20 0 12 0 10 ns
8t
CHDX Status hold time 0 — 0 — 0 ns
9t
CHLH ALE active del ay — 20 — 12 — 10 ns
10 tLHLL ALE width tCLCL – 10 = 30 — tCLCL – 5 = 20 — tCLCL – 5 = 15 — ns
11 tCHLL ALE inactive delay — 20 — 12 — 10 ns
12 tAVLL AD address v alid
to ALE Low20.5 • tCLCH — 0.5 • tCLCH —0.5 • t
CLCH —ns
13 tLLAX AD add res s hold
from ALE inactive tCHCL —t
CHCL —t
CHCL —ns
14 tAVCH AD address v al id
to clock High 0—0—0—ns
16 tCLCSV MCS/PCS active
delay 020012010ns
17 tCXCSX MCS/PCS hold
from comman d
inactive
tCLCH —t
CLCH —t
CLCH —ns
18 tCHCSX MCS/PCS in active
delay 020012010ns
19 tDXDL DEN inactive to
DT/R2, 3 –1 — –1 — –1 — ns
20 tCVCTV Control activ e
delay 13,4 020012010ns
21 tCVDEX DS inactive
delay3,4 020012010ns
23 tLHAV ALE High to
address valid 15 — 7.5 — 5 — ns
62 Am186™CC Communications Controller Data Sheet
Wri te Cycle Timing Respo n se s
30 tCLDOX Data hold time 0 —0—0—ns
31 tCVCTX Control inacti ve
delay3,4 020012010ns
32 tWLWH WR pulse width 2tCLCL – 10 = 70 — 2tCLCL – 10 = 40 — 2tCLCL – 10 = 30 — ns
33 tWHLH WR inactive to ALE
High2tCLCH – 2 — tCLCH – 2 — tCLCH – 2 — ns
34 tWHDX Hold data after WR2tCLCL – 10 = 30 — tCLCL – 10 = 15 — tCLCL – 10 = 10 — ns
35 tWHDEX WR inactive to
DEN inactive2,3 tCLCH – 3 — tCLCH —t
CLCH —ns
65 tAVWL A address valid to
WR Low tCLCL + tCHCL –3 — tCLCL + tCHCL –
1.25 —t
CLCL + tCHCL –
1.25 —ns
67 tCHCSV CLKOUT High to
LCS/UCS valid 020010010ns
68 tCHAV CLKOUT High to A
address valid 020010010ns
87 tAVBL A address valid to
WHB, WLB Low tCHCL – 3 20 tCHCL – 1.25 12 tCHCL – 1.25 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. Testing is performed with equal loading on referenced pins.
3. The timing of this signal is different during a write cycle depending on whether it is configured to be DEN or DS.
4. This parameter applies to the DEN, DS, WR, WHB, and WLB signals.
Table 12. Write Cycle Timing1 (Continued)
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
Am186™CC Communications Controller Data Sheet 63
Figure 18. Write Cycle Waveforms
T4 T1 T2 T3 T4
14
87
12 13 34
10 33
32
35
17
19
68
38
5
7
30
911
20
31
20 31
67
16 18
31
34
Addr. Data
CLKOUT
A19–A0
S61
AD15—AD0
ALE
WR
WHB, WLB
BHE
LCS, UCS
MCS3–MCS0,
DEN
DT/R
S2–S0
23
6
tw
5
20
20
31
20 21
DS
65
4
PCS7–PCS0
Notes:
1. S6 is not valid for the first fetch until the timing fo r parameter 3 (status active delay (t
CHSV
)) is met.
64 Am186™CC Communications Controller Data Sheet
Figure 19. Software Halt Cycle Waveforms
Table 13. Software Halt Cycle Timing1
Parameter Preliminary Unit
25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
3t
CHSV Status active delay 0 20 0 12 0 10 ns
4t
CLSH Status inactive
delay 020012010ns
5t
CLAV AD address invalid
delay 020012010ns
9t
CHLH ALE active delay —20—12—10ns
10 tLHLL ALE width tCLCL – 10 = 30 — tCLCL – 5 = 20 — tCLCL – 5 = 15 — ns
11 tCHLL ALE inactive delay — 20 — 12 — 10 ns
19 tDXDL DEN inactive to
DT/R Low2–1 — –1 — –1 ns
22 tCHCTV Control active
delay 23020012010ns
68 tCHAV CLK OUT High to A
address invalid 020012010ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. Testing is performed with equal loading on referenced pins.
3. This parameter applies to the DEN/DS signal.
T4 T1 T2 TI TI
10
19
68
5
911
22
34
Invalid Addre ss
Invalid Addre ss
CLKOUT
A19–A0
S6, AD15–AD0
ALE
DEN, DS
DT/R
S2–S0
Am186™CC Communications Controller Data Sheet 65
Figure 20. Peripheral Timing Waveforms
Table 14. Peripheral Timing1, 2
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
53 tINVCH Peripheral setup time 10 —5— 5 — ns
54 tCLTMV Timer output delay — 25 — 15 — 12 ns
55 tCHQ0SV Queue status 0 output delay — 25 — 15 — 12 ns
56 tCHQ1SV Queue status 1 output delay — 25 — 15 — 12 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. PIO ou tputs cha nge anywhere from the be gin nin g o f T3 to the first half of T4 of the bus c yc le in w h ic h th e PIO d ata regi ster is
written.
53 54 55
CLKOUT
INT8–INT0, NMI, TMRINx
DRQ0, DRQ1
TMROUT
QS0
QS1
56
66 Am186™CC Communications Controller Data Sheet
Figure 21. Reset Waveforms
Table 15. Reset Timing1
Parameter Preliminary
Unit25 MHz 40 MH z 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
57 tRESIN RES setup time 10 —5— 5 —ns
61 tCLRO Reset delay — 18 — 15 — 12 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
61
RES
CLKOUT
RESOUT
Notes:
1. RES must be held Low for 1 ms during power-up to ensure proper device initialization.
2. Diagram is shown for the system PLL in its 2x mode of operation.
3. Diagram assumes that V
CC
is stable (i.e., 3.3 V ± 0.3 V) during the 1-ms RES active time.
57
Am186™CC Communications Controller Data Sheet 67
Figure 22. Signals Related to Reset (System PLL in 1x or 2x Mode)
Figure 23. Signals Related to Reset (System PLL in 4x Mode)
RES
CLKOUT
RESOUT
AD15–AD01
All Other
Outputs
All Pinstrap
Pins1, 2
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. For a list of all the pinstraps, refer to Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.
RES
CLKOUT
RESOUT
AD15–AD01
All Other
Outputs
All Pinstrap
Pins1, 2
Notes:
1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes.
2. For a list of all the pi nstraps, refer to Table 31, “Reset Configuration Pins (Pinstraps),” on page A-10.
68 Am186™CC Communications Controller Data Sheet
Figure 24. Synchronous Ready Waveforms
Table 16. External Ready Cycle Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commerc i al On ly)
No. Symbol Description Min Max Min Max Min Max
Ready Timing Requirements
47 tSRYCL SRDY transition setup time210 —5— 5 — ns
48 tCLSRY SRDY transition hold time23—2— 2 — ns
49 tARYCH ARDY resolution transition setup time310 — 5 — 5 — ns
50 tCLARX ARDY active hold time24—3— 3 — ns
51 tARYCHL ARDY inactive holding time 10 — 5 — 5 — ns
52 tARYLCL ARDY setup time215 — 5 — 5 — ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. This timing must be met to guarantee proper operation.
3. This timing must be met to guarantee recognition at the clock edge.
T1 T2 T3 Tw T4
47
48
Tw
T3
T2
Tw
Tw
T3
Tw
Tw
Tw
T4
T4
T4
CLKOUT
SRDY
Case 11
Case 21
Case 31
Case 42
Case 51T1 T2 T3 T4
Notes:
1. Normally not ready system.
2. Normally ready system.
Note 1
Note 2
Am186™CC Communications Controller Data Sheet 69
Figure 25. Asynchronous Ready Waveforms
Table 17. Bus Hold Timing1
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial On ly)
No. Symbol Description Min Max Min Max Min Max
5t
CLAV AD address valid delay 0 20 0 12 0 10 ns
15 tCLAZ AD address float delay 0 20 0 12 0 10 ns
18 tCHCSX MCSx/PCSx inactive delay 0 20 0 12 0 10 ns
58 tHVCL HOLD setup2
2. This timing must be met to guarantee recognition at the next clock.
10 —5— 5 — ns
62 tCLHAV HLDA va li d delay 0 20 0 12 0 10 ns
63 tCHCZ Command lines float delay — 20 — 12 — 10 ns
64 tCHCV Command lines valid delay (after float) — 25 — 12 — 10 ns
49
51
50
50
CLKOUT
ARDY1
ARDY2
49
(Normally Not-Ready System)
(Normally Ready System)
52
Notes:
1. In a normally not ready system, wait states are added after T3 until t
ARYCH
and t
CLARX
are met.
2. In a normally ready system, a wait state is added if t
ARYCH
and t
ARYCHL
during T2 or t
ARYLCL
and t
CLARX
during
T3 are met.
T1
Tw
T3
T2
T1
Case 11
Case 21
Case 31
Case 42
Case 51
T2 T3 Tw T4
Tw
Tw
T3
Tw
Tw
Tw
T4
T4
T4
T2 T3 T4
70 Am186™CC Communications Controller Data Sheet
Figure 26. Entering Bus Hold Waveforms
Figure 27. Exiting Bus Hold Waveforms
T4 Ti Ti
58
62
15
63
Ti Ti Ti
CLKOUT
HOLD
HLDA
AD15–AD0, DEN
Case 1
Case 2
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0, W HB,
WLB, UCS, LCS, ALE
MCS3–MCS0, PCS7–PCS0
18
Ti Ti T4 T1
58
62
5
64
Ti Ti Ti T1
CLKOUT
HOLD
HLDA
AD15–AD0, DEN
MCS3–MCS0),
Case 1
Case 2
A19–A0, S6, RD, WR,
BHE, DT/R, S2–S0 , WHB,
WLB, UCS, LCS, ALE
PCS7–PCS0)
Am186™CC Communications Controller Data Sheet 71
Table 18. System Clocks Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
CLKIN Requirements for 4x PLL Mode
36 tCKIN X1 period2Not Supported 100 125 80 125 ns
37 tCLCK X1 Lo w ti me (1 .5 V ) 45 —35—ns
38 tCHCK X1 High time (1.5 V) 45 — 35 — ns
39 tCKHL X1 fall time
(3.5 to 1.0 V) —5—5ns
40 tCKLH X1 rise time
(1.0 to 3.5 V) —5—5ns
CLKIN Requirements for 2x PLL Mode
36 tCKIN X1 period280 125 50 125 40 125 ns
37 tCLCK X1 Lo w ti me (1 .5 V ) 35 — 20 — 15 — ns
38 tCHCK X1 High time (1.5 V) 35 — 20 — 15 — ns
39 tCKHL X1 fall time
(3.5 to 1.0 V) —5—5—5ns
40 tCKLH X1 rise time
(1.0 to 3.5 V) —5—5—5ns
CLKIN Requirements for 1x PLL Mode
36 tCKIN X1 period240 60 25 60 Not Supported ns
37 tCLCK X1 Lo w ti me (1 .5 V ) 15 — 7.5 — ns
38 tCHCK X1 High time (1.5 V) 15 — 7.5 — ns
39 tCKHL X1 fall time
(3.5 to 1.0 V) —5—5 ns
40 tCKLH X1 rise time
(1.0 to 3.5 V) —5—5 ns
CLKOUT Timing3
42 tCLCL CLKOUT period 40 — 25 — 20 — ns
43 tCLCH CLKOUT Low time
(CL = 50 pF) 0.5tCLCL–2 =18 — 0.5tCLCL–1.25
=11.25 —0.5t
CLCL–1 = 9 — ns
44 tCHCL CLKOUT High time
(CL = 50 pF) 0.5tCLCL–2 =18 — 0.5tCLCL–1.25
=11.25 —0.5t
CLCL–1 = 9 — ns
45 tCH1CH2 CLKOUT rise time
(1.0 to 3.5 V) —3—3—3ns
46 tCL2CL1 CLKOUT fall time
(3.5 to 1.0 V) —3—3—3ns
69 tCICO X1 to CLK OUT s ke w — 10 — 10 — 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. Testing is performed with equal loading on referenced pins.
3. The PLL requires a maximum of 1 ms to achieve lock after all other operating conditions (V
CC
) are stable, which is normally
achieved by holding RES active for at least 1 ms.
72 Am186™CC Communications Controller Data Sheet
Figure 28. S yst em Clock Timing Waveforms—Active Mode (PLL 1x Mode)
Figure 29. USB Clock Timing Waveforms
36 37
40
42 44
45
69
38
43
46
X2
X1
CLKOUT
39
Table 19. USB Clocks Timing1
Parameter Preliminary
Unit
48 MHz
No. Symbol Description Min Max
CLKIN Requirements for 4x PLL Mode
1t
UCKIN USBX1 period 80 85 ns
2t
UCLCK USBX1 Low time (1.5 V) 35 —ns
3t
UCHCK USBX1 High time (1.5 V) 35 — ns
4t
UCKHL USBX1 fall time (3.5 to 1.0 V) — 5 ns
5t
UCKLH USBX1 rise time (1.0 to 3.5 V) — 5 ns
CLKIN Requirements for 2x PLL Mode
1t
UCKIN USBX1 period 40 42 ns
2t
UCLCK USBX1 Low time (1.5 V) 15 — ns
3t
UCHCK USBX1 High time (1.5 V) 15 — ns
4t
UCKHL USBX1 fall time (3.5 to 1.0 V) — 5 ns
5t
UCKLH USBX1 rise time (1.0 to 3.5 V) — 5 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unle ss otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
123
USBX2
USBX1 45
Am186™CC Communications Controller Data Sheet 73
Figure 30. GCI Bus Waveforms
Table 20. GCI Bus Timing1
Parameter Preliminary Unit
No. Symbol Description Min Max
1t
WH Pulse width High 240 —ns
2t
WL Pulse width Low 240 — ns
3t
SF Frame setup 70 — ns
4t
FH Frame hold/clock 20 — ns
5t
FD Frame delay/clock 0 — ns
6t
WFH Frame width High 130 — ns
7t
DSC Data delay/clock — 1002ns
8t
DSF Data delay/FSC — 1002ns
9t
DHC Data hold/clock 702—ns
10 tSD Data setup tWH + 20 — ns
11 tHD Data hold 50 — n s
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. C
L
= 150 pF.
2
5
1
7
3 4
6
GCI_DCL_A
GCI_FSC_A
GCI_DD_A
GCI_DU_A
8
10 11
9
74 Am186™CC Communications Controller Data Sheet
Table 21. PCM Highway Timing (Timing Slave)1, 2
Parameter Preliminary Unit
No. Symbol Description Min Max
1t
CLKP PCM clock period 200 —ns
2t
WH PCM c lock High 80 — ns
3t
WL PCM clock Low 80 — ns
4t
HCF Hold time from CLK Low to FSC valid 0 — ns
5t
DZF Delay time to valid TXD from CLK 1 25 ns
6t
DZF Delay time to valid TXD from FSC 1 25 ns
7t
SUFC Setup time for FSC High to CLK Low 35 — ns
8t
DCD Delay time from CLK High to TXD valid 1 25 ns
9t
SUDC Setup time from RXD va lid to CLK 35 — ns
10 tHCD Hold time from CLK Low to RXD invalid 5 — ns
11 tDCT Delay to TSC valid from CLK 1 25 ns
12 tDFT Delay to TSC valid from FSC 1 25 ns
13 tDCLT Delay from CLK Low of last bit to TSC invalid 1 25 ns
14 tHFI Hold time from CLK Low to FSC invalid 0 — ns
15 tSYNSS Time between successive synchronization pulses 16 — CLK
16 tWSYN FSC width invalid 8 — CLK
17 tDTW3Delay from last bit CLK Low to TXD weak drive 1 25 ns
18 tDTZ Delay from last bit CLK (plus 1) High to TXD disable 1 25 ns
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. TXD becomes valid after the CLK rising edge or FSC enable, whichever is later.
3. During the second half of the last bit transmittal, TXD is driven weak so that other devices can safely drive during this time.
Am186™CC Communications Controller Data Sheet 75
Figure 31. PCM Highway Waveforms (Timing Slave)
4
PCM_CLK_x
PCM_FSC_x
PCM_TXD_x
789
PCM_RXD_x
PCM_TSC_x
23
1
10
11 12
15 16
17
12 34n
13
5 14
618
n+1
Notes:
Note that the PCM_TXD_x outputs three-state. In the signal description and pin list summary tables, PCM_TXD_x is listed as
O-LS-OD (totem pole output/programmable to hold last state of pin/open drain output) because of the following design characteristic.
On the las t bit to be transm itted in PCM highwa y mode, PCM_TXD_ x will be driven normally during the first 1/2 bit tim e. During
the last 1/2 bit time of the last bit of the transmission, PCM_TXD_x control will be in the hold-last-state condition (LS). In this
condition, the output is driven, but at a much weaker strength. This permits another device (external to the microcontroller) to
start driving dur ing this time witho ut bus contention problems. After this 1/2 bit time of hold-last-state condition, the PCM_TXD_x
pin will be fully three-stated.
In some applications, several PCM highway devices may have their PCM_TXD pins tied together. The time slot assigners
should be programmed so that only one device is active at any time.
The PCM_TSC_x signal permits external bus drivers, possibly to go external to the board. Each PCM_TSC_x signal is open-
drain so that multiple PCM_TSC_x pins can be connected together. For example, two Am186CC microcontrollers could be con-
nected on the same PCM highway and (with proper configuration of the time slot assigners) could occupy different time slots.
An extern al bus dri ver wo uld nee d to be acti ve for bo th Am186 CC time slots. The open dra in on the PCM_TS C_x pins permits
them to be wired together to achieve this.
76 Am186™CC Communications Controller Data Sheet
Figure 32. PCM Highway Waveforms (Timing Master)
Table 22. PCM Highway Timing (Timing Master)1
Parameter Preliminary Unit
No. Symbol Description Min Max
1t
DCFH Delay time from CLK High to FSC High 0 30 ns
2t
DCFL Delay time from CLK High to FSC Low 0 30 ns
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted . All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
PCM_CLK_x
PCM_FSC_x
12
Am186™CC Communications Controller Data Sheet 77
Figure 33. DCE Transmit Waveforms
Figure 34. DCE Receive Waveforms
Table 23. DC E Interface Timing1, 2
Parameter Preliminary Unit
No. Symbol Description Min Max
1t
TCLKPER DCE clock period 95 —ns
2t
TCLKH DCE clock High 40 — ns
3t
TCLKL D CE clock Low 40 — ns
4t
TCLKO DCE clock to output delay 1 20 ns
5t
TCLKSU DCE clock set up 15 — ns
6t
TCLKHD DCE clock hold 5 — ns
7t
TCLKR DCE clock rise/fall — 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. Timings are shown with TCLK and RCLK in the default mode without the optional clock inversion.
DCE_CTS_x
3
12
4 4
5
DCE_TCLK_x
DCE_TXD_x
7 7
6
1 2 3
5 5
4 4
DCE_RCLK_x
DCE_RXD_x
DCE_RTR_x
7 7
6
78 Am186™CC Communications Controller Data Sheet
Figure 35. USB Data Signal Rise and Fall Times
Figure 36. USB Receiver Jitter Tolerance
Table 24. USB Timing1, 2
Parameter Preliminary Unit
48 MHz
No. Symbol Description Min Max
1t
RRise time (Cl = 50 pF) 4 20 ns
2t
FFall time (Cl = 50 pF) 4 2 0 ns
3t
JR1 Consecutive transition jitter (measured at crossover point) –18.5 18.5 ns
4t
JR2 Paired transition jitter (measured at crossover point) –9 9 ns
Notes:
1. All timing parameters are measured at V
CC
/2 with 50-pF loadi ng on CL KOUT unless otherwise noted. All output test conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
2. Parame ters 3 (t
JR1
) and 4 (t
JR2
) show ji tter for the re ceiver, not the transm itter . Se e the USB V ersio n 1.0 spe cificati on for more
details.
Rise Time Fall Time
10%
90%
10%
Differential
Data Lines (D+/D–)
1 2
CLK
D+/D–
Consecutive Transition
Paired Transition
3 4
Am186™CC Communications Controller Data Sheet 79
Figure 37. Synchronous Serial Interface Waveforms
Table 25. SSI Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commercial Only)
No. Symbol Description Min Max Min Max Min Max
1t
CLEV CLKOUT Low to SDEN valid 0 20 0 12 0 10 ns
2t
CLSL CLKOUT Low to SCLK Low 0 20 0 15 0 12 ns
3t
DVSH Data valid to SCLK High 10 —5— 5 — ns
4t
SHDX SCLK High to data invalid 3 — 2 — 2 — ns
5t
SLDV SCLK Low to data valid — 20 — 12 — 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
1
223
4
5
CLKOUT
SDEN
SCLK
SDATA (RX)
SDATA (TX)
Notes:
1. SDEN is configured to be active High.
2. SCLK is configured to be CLKOUT/2.
3. Waveforms are shown for “normal” clock mode (i.e., transmit on negative edge of SCLK and receive on positive edge
of SCLK).
80 Am186™CC Communications Controller Data Sheet
Figure 38. DRAM Read Cycle without Wait-States Waveform
Table 26. DRAM Timing1
Parameter Preliminary
Unit25 MHz 40 MHz 50 MHz
(Commerc i al On ly)
No. Symbol Description Min Max Min Max Min Max
1t
DVCL Data in setup 10 —5— 5 — ns
2t
CLDX Data in hold 3 — 2 — 2 — n s
5t
CLAV AD address valid delay 0 20 0 12 0 10 ns
7t
CLDV Data valid delay 0 20 0 12 0 10 ns
15 tCLAZ AD address float delay 0 20 0 12 0 10 ns
20 tCVCTV Control active delay 1 0 20 0 12 0 10 ns
25 tCLRL RD active delay 0 20 0 12 0 10 ns
27 tCLRH RD inactive delay 0 20 0 12 0 10 ns
30 tCLDOX Data hold time 0 — 0 — 0 — ns
31 tCVCTX Control in active delay 0 20 0 12 0 10 ns
68 tCHAV CLKOUT High to A address valid 0 20 0 12 0 10 ns
402 tCOLV Column address valid delay 0 20 0 12 0 10 ns
403 tCHRAS Change in RAS delay 3 20 3 12 3 10 ns
404 tCHCAS Change in CAS delay 3 20 3 12 3 10 ns
Notes:
1. All timing parameters are measured at V
CC
/2 wit h 50-pF loading on CLKOUT unless otherwise note d. All output tes t conditions
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
T4 T1 T2 T3 T4
1
2
515
68 402
403 403
404 404
25 27
Data
Row
Addr.
CLKOUT
AD15–A0
A17, A15, A13, A11 ,
RAS0, RAS1
CAS0, CAS1
RD
Column
A9, A7, A5, A3, A1
Am186™CC Communications Controller Data Sheet 81
Figure 39. DRAM Read Cycle with Wait-States Waveform
Figure 40. DRAM Write Cycle without Wait-States Waveform
T4 T1 T2 TW T3 T4
1
2
515
68 402
403 403
404 404
25 27
DATA
Row
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, RAS1
RD
Column
A9, A7, A5, A3, A1
T4 T1 T2 T3 T4
5 7 30
68 402
403 403
404 404
20 31
Row
Addr.
CLKOUT
AD15–AD0
RAS0, RAS1
CAS0, CAS1
WR
Column
Data
A17, A15, A13, A11, A9,
A7, A5, A3, A1
82 Am186™CC Communications Controller Data Sheet
Figure 41. DRAM Write Cycle with Wait-States Waveform
Figure 42. DRAM Refresh Cycle Waveform
30
T4 T1 T2 TW T3 T4
5 7
68 402
403 403
404 404
20 31
Data
Row
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, CAS1
WR
Column
A9, A7, A5, A3, A1
T4 T1 T2 TW1 TW2 TW3 T3 T4
515
68 402
403403
404 404
25 27
Addr.
CLKOUT
AD15–AD0
A17, A15, A13, A11,
RAS0, RAS1
CAS0, CAS1
RD
403403
Column (Invalid)Row (Invalid)
A9, A7, A5, A3, A1
Am186™CC Communications Controller Data Sheet A-1
APPENDIX A—PIN TABLES
This appendix contains pin tables for the Am186CC
controller. Sev eral different tables are included with the
following characteristics:
■Power-on reset pin defaults including pin numbers
and multiplexed functions—Table 27 on page A-2.
■Multiplexed signal trade-offs—Table 28 on
page A-5.
■Programmable I/O pins ordered by PIO pin number
and multiple xed signal name, respectively, including
pin number s, multiplexed funct ions, and pin confi g-
urations following system reset—Table 29 on
page A-8 and Table 30 on page A-9.
■Pinstraps and pinstrap options—Table 31 on
page A-10.
■Pin and si gnal summar y showing signal name an d
alternate function, pin number, I/O type, maximum
load values, power-on reset default function, reset
state, POR default operation, hold state, and volt-
age column—Table 35 on page A-12.
For pin t ables showing pins sor t ed by pin number an d
signal name, respectively, see Table 1, “PQFP Pin
Assignments—Sorted by Pin Number” on page 10 and
Table 2, “PQFP Pin Assignments—Sorted by Signal
Name” on page 11.
For signal descriptions, see Table 4, “Signal
Descriptions” on page 14.
In all tables the brackets, [ ], indicate alternate,
multiplexed functions, and braces, { }, indicate reset
configuration pins (pinstraps). The line over a pin name
indicates an active Low. The word pin refers to the
physical wire; the word signal refers to the electrical
signal that flows through it.
A-2 Am186™CC Communications Controller Data Sheet
Table 27. Power-On Reset (POR) Pin Defaults
POR Default Pin
Number Multiplexed
Signal Multiplexed
Signal Multiplexed
Signal PIO Pinstrap
Bus Interface U nit
A0 30 —————
A1 31—————
A2 32—————
A3 36—————
A4 37—————
A5 42—————
A6 43—————
A7 44—————
A8 45—————
A9 49—————
A10 50—————
A11 64—————
A12 65—————
A13 69—————
A14 70—————
A15 84—————
A16 85—————
A17 88—————
A18 89—————
A19 90—————
AD0 28—————
AD1 34—————
AD2 38—————
AD3 46—————
AD4 51—————
AD5 66—————
AD6 86—————
AD7 92—————
AD8 29—————
AD9 35—————
AD1039—————
AD1147—————
AD1252—————
AD1367—————
AD1487—————
AD1593—————
ALE 19 — — — PIO33 —
ARDY 14 — — — PIO8 —
BHE 20 — — — PIO34 {ADEN}
BSIZE8 94—————
DEN 18 DS ——PIO30—
DRQ1105—————
DT/R 17 — — — PIO29 —
HLDA98—————
HOLD99—————
RD 97—————
S0 57 — — — — {USBXCVR}
S1 56—————
S2 55—————
Am186™CC Communications Controller Data Sheet A-3
S6 54 —————
SRDY 15 — — — PIO35 —
WHB 95—————
WLB 96—————
WR 16 — — — PIO15 —
Chip Selects —
LCS 131 RAS0 ————
MCS1 127 CAS1 ————
MCS2 128 CAS0 ————
PCS0 5 — — — PIO13 {USBSEL1}
PCS1 6 — — — PIO14 {USBSEL2}
PCS2 7—————
PCS3 8—————
UCS 132 — — — — {ONCE}
Reset/Clocks
CLKOUT60—————
RES 114—————
RESOUT58—————
USBX1 75 — — — — —
USBX2 76 — — — — —
X1 73—————
X2 74—————
Interrupts
INT0 107 — — — — —
INT1 109 — — — — —
INT2 110 — — — — —
INT3 111 — — — — —
INT4 112 — — — — —
INT5 113 — — — — —
NMI 115—————
Synchronous Communications Interfaces
Channel A (DCE)
DCE_RXD_A 118 GCI_DD_A PCM_RXD_A — — —
DCE_TXD_A 119 GCI_DU_A PCM_TXD_A — — —
DCE_RCLK_A 117 GCI_DCL_A PCM_CLK_A — — —
DCE_TCLK_A 116 GCI_FSC_A PCM_FSC_A — — —
High-Speed UART/HDLC Channel D Handshaking
TXD_HU26—————
Debug Support
QS0 62—————
QS1 63—————
Universal Serial Bus
USBD+ 81 UDPLS — — — —
USBD- 80 UDMNS — — — —
PIOs
PIO0 144 TMRIN1 — — —
PIO1 143 TMROUT1 — — —
PIO2 10 PCS5 —— —
PIO3 9 PCS4 —— {CLKSEL2}
PIO4 126 MCS0 —— {UCSX8}
Table 27. Power-On Reset (POR) Pin Defaults (Continued)
POR Default Pin
Number Multiplexed
Signal Multiplexed
Signal Multiplexed
Signal PIO Pinstrap
A-4 Am186™CC Communications Controller Data Sheet
PIO5 129 MCS3 RAS1 — —
PIO6 147 INT8 PWD — —
PIO7 146 INT7 — — —
PIO9 124 DRQ0 — — —
PIO10 2 SDEN — — —
PIO11 3 SCLK — — —
PIO12 4 SDATA — — —
PIO16 25 RXD_HU — — —
PIO17 123 DCE_CTS_A PCM_TSC_A — —
PIO18 122 DCE_RTR_A —— —
PIO19 145 INT6 — — —
PIO20 159 TXD_U DCE_TXD_D PCM_TXD_D —
PIO21 22 UCLK USBSOF USBSCI —
PIO22 150 DCE_RCLK_C PCM_CLK_C — —
PIO23 149 DCE_TCLK_C PCM_FSC_C — —
PIO24 157 CTS_U DCE_TCLK_D PCM_FSC_D —
PIO25 156 RTR_U DCE_RCLK_D PCM_CLK_D —
PIO26 158 RXD_U DCE_RXD_D PCM_RXD_D —
PIO27 142 TMRIN0 — — —
PIO28 141 TMROUT0 — — —
PIO31 13 PCS7 —— —
PIO32 11 PCS6 —— —
PIO36 138 DCE_RXD_B PCM_RXD_B — —
PIO37 139 DCE_TXD_B PCM_TXD_B — —
PIO38 137 DCE_CTS_B PCM_TSC_B — —
PIO39 136 DCE_RTR_B —— —
PIO40 135 DCE_RCLK_B PCM_CLK_B — —
PIO41 134 DCE_TCLK_B PCM_FSC_B — —
PIO42 153 DCE_RXD_C PCM_RXD_C — —
PIO43 154 DCE_TXD_C PCM_TXD_C — —
PIO44 152 DCE_CTS_C PCM_TSC_C — —
PIO45 151 DCE_RTR_C —— —
PIO46 24 CTS_HU DCE_CTS_D PCM_TSC_D —
PIO47 23 RTR_HU DCE_RTR_D — —
Reserved1
RSVD_104 104 UXVRCV — — — —
RSVD_103 103 UXVOE ————
RSVD_102 102 UTXDMNS — — — —
RSVD_101 101 UTXDPLS — — — —
Notes:
1. For default operation and reset states, refer to Table 35, “Pin List Summary,” on page A-12.
Table 27. Power-On Reset (POR) Pin Defaults (Continued)
POR Default Pin
Number Multiplexed
Signal Multiplexed
Signal Multiplexed
Signal PIO Pinstrap
Am186™CC Communications Controller Data Sheet A-5
Table 28. Multiplexed Signal Trade-offs
DESIRED FUNCTION LOST FUNCTION
Interface Name Pin Interface Name Interface Name Interface Name Interface Name
Memory
SRAM LCS 131 DRAM RAS0 ——————
MCS1 127 CAS1 ——————
MCS2 128 CAS0 ——————
MCS3 129 RAS1 ——————
DRAM CAS0 128 SRAM MCS2 ——————
CAS1 127 MCS1 ——————
RAS0 131 LCS ——————
RAS1 129 MCS3 ——————
Synchronous Communications Interfaces
DCE
Channel
A
DCE_RXD_A 118 PCM
Channel
A
PCM_RXD_A — — GCI
Channel
A
GCI_DD_A PIO —
DCE_TXD_A 119 PCM_TXD_A — — GCI_DU_A —
DCE_RCLK_A 117 PCM_CLK_A — — GCI_DCL_A —
DCE_TCLK_A 116 PCM_FSC_A — — GCI_FSC_A —
DCE_CTS_A 123 PCM_TSC_A —— —PIO17
DCE_RTR_A 122 ——— —PIO18
DCE
Channel
B
DCE_RXD_B 138 PCM
Channel
B
PCM_RXD_B — — — — PIO PIO36
DCE_TXD_B 139 PCM_TXD_B — — — — PIO37
DCE_RCLK_B 135 PCM_CLK_B — — — — PIO40
DCE_TCLK_B 134 PCM_FSC_B — — — — PIO41
DCE_CTS_B 137 PCM_TSC_B — — — — PIO38
DCE_RTR_B 136 — — — — — PIO39
DCE
Channel
C
DCE_RXD_C 153 PCM
Channel
C
PCM_RXD_C — — GCI to
PCM
Con-
version
—PIO
PIO42
DCE_TXD_C 154 PCM_TXD_C — — —PIO43
DCE_RCLK_C 150 PCM_CLK_C — — PCM_CLK_C PIO22
DCE_TCLK_C 149 PCM_FSC_C — — PCM_FSC_C PIO23
DCE_CTS_C 152 PCM_TSC_C —— —PIO44
DCE_RTR_C 151 ——— —PIO45
DCE
Channel
D
DCE_RXD_D 158 PCM
Channel
D
PCM_RXD_D Low-
Speed
UART
RXD_U High-
Speed
UART
(Flow
Control)
PIO PIO26
DCE_TXD_D 159 PCM_TXD_D TXD_U PIO20
DCE_RCLK_D 156 PCM_CLK_D RTR_U PIO25
DCE_TCLK_D 157 PCM_FSC_D CTS_U PIO24
DCE_CTS_D 24 PCM_TSC_D —CTS_HU PIO46
DCE_RTR_D 23 ——
RTR_HU PIO47
PCM
Channel
A
PCM_RXD_A 118 DCE
Channel
A
DCE_RXD_A — — GCI
Channel
A
GCI_DD_A PIO —
PCM_TXD_A 119 DCE_TXD_A — — GCI_DU_A —
PCM_CLK_A 117 DCE_RCLK_A — — GCI_DCL_A —
PCM_FSC_A 116 DCE_TCLK_A — — GCI_FSC_A —
PCM_TSC_A 123 DCE_CTS_A —— —PIO17
PCM
Channel
B
PCM_RXD_B 138 DCE
Channel
B
DCE_RXD_B — — — — PIO PIO36
PCM_TXD_B 139 DCE_TXD_B — — — — PIO37
PCM_CLK_B 135 DCE_RCLK_B — — — — PIO40
PCM_FSC_B 134 DCE_TCLK_B — — — — PIO41
PCM_TSC_B 137 DCE_CTS_B — — — — PIO38
A-6 Am186™CC Communications Controller Data Sheet
PCM
Channel
C
PCM_RXD_C 153 DCE
Channel
C
DCE_RXD_C ——
GCI to
PCM
Con-
version
— PIO PIO42
PCM_TXD_C 154 DCE_TXD_C — — — PIO43
PCM_CLK_C 150 DCE_RCLK_C — — PCM_CLK_C PIO22
PCM_FSC_C 149 DCE_TCLK_C — — PCM_FSC_C PIO23
PCM_TSC_C 152 DCE_CTS_C —— — PIO44
PCM
Channel
D
PCM_RXD_D 158 DCE
Channel
D
DCE_RXD_D Low-
Speed
UART
RXD_U High-
Speed
UART
— PIO PIO26
PCM_TXD_D 159 DCE_TXD_D TXD_U — PIO20
PCM_CLK_D 156 DCE_RCLK_D RTR_U —PIO25
PCM_FSC_D 157 DCE_TCLK_D CTS_U —PIO24
PCM_TSC_D 24 DCE_CTS_D — CTS_HU PIO46
Low-
Speed
UART
RXD_U 158 DCE
Channel
D
DCE_RXD_D PCM
Channel
D
PCM_RXD_D —— PIO PIO26
TXD_U 159 DCE_TXD_D PCM_TXD_D ——PIO20
RTR_U 156 DCE_RCLK_D PCM_CLK_D ——PIO25
CTS_U 157 DCE_TCLK_D PCM_FSC_D ——PIO24
High-
Speed
UART
RXD_HU 25 DCE
Channel
D
—PCM
Channel
D
——— PIO PIO16
TXD_HU 26 ——
———
RTR_HU 23 DCE_RTR_D ———PIO47
CTS_HU 24 DCE_CTS_D PCM_TSC_D ——PIO46
GCI
Channel
A
GCI_DD_A 118 DCE
Channel
A
DCE_RXD_A PCM
Channel
A
PCM_RXD_A ——PIO—
GCI_DU_A 119 DCE_TXD_A PCM_TXD_A ———
GCI_DCL_A 117 DCE_RCLK_A PCM_CLK_A ———
GCI_FSC_A 116 DCE_TCLK_A PCM_FSC_A ———
GCI to
PCM
Con-
version
PCM_CLK_C 150 DCE
Channel
C
DCE_RCLK_C PCM
Channel
C
PCM_CLK_C —— PIO PIO22
PCM_FSC_C 149 DCE_TCLK_C PCM_FSC_C ——PIO23
Miscellaneous
Bus
Interface DEN 18 Bus
Interface DS ——————
DS 18 DEN ——————
Clocks UCLK 22 Clocks USBSOF Clocks USBSCI — — PIO PIO21
USBSOF 22 UCLK USBSCI — — PIO21
USBSCI 22 UCLK USBSOF — — PIO21
PIOs
PIO0 144 TMRIN1 — —
PIO1 143 TMROUT1 — —
PIO2 10 PCS5 — —
PIO3 9 PCS4 — —
PIO4 126 MCS0 — —
PIO5 129 MCS3 RAS1 —
PIO6 147 INT8 PWD —
PIO7 146 INT7 — —
PIO8 14 ARDY — —
PIO9 124 DRQ0 — —
PIO10 2 SDEN — —
PIO11 3 SCLK — —
PIO12 4 SDATA — —
Table 28. Multiplexed Signal Trade-offs (Continued)
DESIRED FUNCTION LOST FUNCTION
Interface Name Pin Interface Name Interface Name Interface Name Interface Name
Am186™CC Communications Controller Data Sheet A-7
PIO13 5 PCS0 — —
PIO14 6 PCS1 — —
PIO15 16 WR — —
PIO16 25 RXD_HU — —
PIO17 123 DCE_CTS_A PCM_TSC_A —
PIO18 122 DCE_RTR_A — —
PIO19 145 INT6 — —
PIO20 159 TXD_U DCE_TXD_D PCM_TXD_D
PIO21 22 UCLK USBSOF USBSCI
PIO22 150 DCE_RCLK_C PCM_CLK_C —
PIO23 149 DCE_TCLK_C PCM_FSC_C —
PIO24 157 CTS_U DCE_TCLK_D PCM_FSC_D
PIO25 156 RTR_U DCE_RCLK_D PCM_CLK_D
PIO26 158 RXD_U DCE_RXD_D PCM_RXD_D
PIO27 142 TMRIN0 — —
PIO28 141 TMROUT0 — —
PIO29 17 DT/R — —
PIO30 18 DEN DS —
PIO31 13 PCS7 — —
PIO32 11 PCS6 — —
PIO33 19 ALE — —
PIO34 20 BHE — —
PIO35 15 SRDY — —
PIO36 138 DCE _RXD_B PCM_RXD_B —
PIO37 139 DCE_TXD_B PCM_TXD_B —
PIO38 137 DCE_CTS_B PCM_TSC_B —
PIO39 136 DCE_RTR_B — —
PIO40 135 DCE_RCLK_B PCM_ CLK_B —
PIO41 134 DCE_TCLK_B PCM_FSC_B —
PIO42 153 DCE_RXD_C PCM_RXD_C —
PIO43 154 DCE_TXD_C PCM_TXD_C —
PIO44 152 DCE_CTS_C PCM_TSC_C —
PIO45 151 DCE_RTR_C — —
PIO46 24 CTS_HU DCE_CTS_D PCM_TSC_D
PIO47 23 RTR_HU DCE_RTR_D —
Table 28. Multiplexed Signal Trade-offs (Continued)
DESIRED FUNCTION LOST FUNCTION
Interface Name Pin Interface Name Interface Name Interface Name Interface Name
A-8 Am186™CC Communications Controller Data Sheet
Table 29. PIOs Sorted by PIO Number
PIO No. Pin No. Multiplexed Signal Multiplexed Signa l Multiplexed Signal Pin Configura tion Following
System Reset1
PIO0 144 TMRIN1 — — Input with pullup
PIO1 143 TMROUT1 — — Input with pulldown
PIO2 10 PCS5 — — Input with pullup
PIO3 9 PCS4 — — Input with pullup
PIO4 126 MCS0 — — Input with pullup
PIO5 129 MCS3 RAS1 — Input with pullup
PIO6 147 INT8 PWD — Input with pullup
PIO7 146 INT7 — — Input with pullup
PIO8 14 ARDY — — Alternate operation2
PIO9 124 DRQ0 — — Input with pulldown
PIO10 2 SDEN — — Input with pulldown
PIO11 3 SCLK — — Input with pullup
PIO12 4 SDATA — — Input with pullup
PIO13 5 PCS0 — — Alternate operation2
PIO14 6 PCS1 — — Alternate operation2
PIO15 16 WR — — Alternate operation2
PIO16 25 RXD_HU — — Input with pullup
PIO17 123 DCE_CTS_A PCM_TSC_A — Input with pullup
PIO18 122 DCE_RTR_A — — Input with pullup
PIO19 145 INT6 — — Input with pullup
PIO20 159 TXD_U DCE_TXD_D PCM_TXD_D Input with pullup
PIO21 22 UCLK USBSOF USBSCI Input with pullup
PIO22 150 DCE_RCLK_C PCM_CLK_C — Input with pulldown
PIO23 149 DCE_TCLK_C PCM_FSC_C — Input with pulldown
PIO24 157 CTS_U DCE_TCLK_D PCM_FSC_D Input with pullup
PIO25 156 RTR_U DCE_RCLK_D PCM_CLK_D Input with pullup
PIO26 158 RXD_U DCE_RXD_D PCM_RXD_D Input with pullup
PIO27 142 TMRIN0 — — Input with pullup
PIO28 141 TMROUT0 — — Input with pulldown
PIO29 17 DT/R — — Alternate operation2
PIO30 18 DEN DS — Alternate operation2
PIO31 13 PCS7 — — Input with pullup
PIO32 11 PCS6 — — Input with pullup
PIO33 19 ALE — — Alternate operation3
PIO34 20 BHE — — Alternate operation2
PIO35 15 SRDY — — Alternate operation2
PIO36 138 DCE_RXD_B PCM_RXD_B — Input with pullup
PIO37 139 DCE_TXD_B PCM_TXD_B — Input with pullup
PIO38 137 DCE_CTS_B PCM_TSC_B — Input with pullup
PIO39 136 DCE_RTR_B — — Input with pullup
PIO40 135 DCE_RCLK_B PCM_CLK_B — Input with pullup
PIO41 134 DCE_TCLK_B PCM_FSC_B — Input with pullup
PIO42 153 DCE_RXD_C PCM_RXD_C — Input with pulldown
PIO43 154 DCE_TXD_C PCM_TXD_C — Input with pulldown
PIO44 152 DCE_CTS_C PCM_TSC_C — Input with pullup
PIO45 151 DCE_RTR_C — — Input with pullup
PIO46 24 CTS_HU DCE_CTS_D PCM_TSC_D Input with pullup
PIO47 23 RTR_HU DCE_RTR_D — Input with pullup
Notes:
1. System reset is defined as a power-on reset (i.e., the
RES
input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When used as a PIO, input with pullup option available.
3. When us ed as a PIO, input with a pu lldown option av ailab le.
Am186™CC Communications Controller Data Sheet A-9
Table 30. PIOs Sorted by Signal Name
Signal PIO No. Pin No. Multiplexed Signal Multiplexed Signal Pin Configura tion Follow ing
System Reset1
ALE PIO33 19 — — Alternate operation2
ARDY PIO8 14 — — Alternate operation3
BHE PIO34 20 — — Alternate operation3
CTS_HU PIO46 24 DCE_CTS_D PCM_TSC_D Input with pullup
CTS_U PIO24 157 DCE_TCLK_D PCM_FSC_D Input with pullup
DCE_CTS_A PIO17 123 PCM_TSC_A — Input with pullup
DCE_CTS_B PIO38 137 PCM_TSC_B — Input with pullup
DCE_CTS_C PIO44 152 PCM_TSC_C — Input with pullup
DCE_RCLK_B PIO40 135 PCM_CLK_B — Input with pullup
DCE_RCLK_C PIO22 150 PCM_CLK_C — Input with pulldown
DCE_RTR_A PIO18 122 — — Input with pullup
DCE_RTR_B PIO39 136 — — Input with pullup
DCE_RTR_C PIO45 151 — — Input with pullup
DCE_RXD_B PIO36 138 PCM_RXD_B — Input with pullup
DCE_RXD_C PIO42 153 PCM_RXD_C — Input with pulldown
DCE_TCLK_B PIO41 134 PCM_FSC_B — Input with pullup
DCE_TCLK_C PIO23 149 PCM_FSC_C — Input with pulldown
DCE_TXD_B PIO37 139 PCM_TXD_B — Input with pullup
DCE_TXD_C PIO43 154 PCM_TXD_C — Input with pulldown
DEN PIO30 18 DS — Alternate operation3
DRQ0 PIO9 124 — — Input with pulldown
DT/R PIO29 17 — — Alternate operation3
INT6 PIO19 145 — — Input with pullup
INT7 PIO7 146 — — Input with pullup
INT8 PIO6 147 PWD — Input with pullup
MCS0 PIO4 126 — — Input with pullup
MCS3 PIO5 129 RAS1 — Input with pullup
PCS0 PIO13 5 — — Alternate operation3
PCS1 PIO14 6 — — Alternate operation3
PCS4 PIO3 9 — — Input with pullup
PCS5 PIO2 10 — — Input with pullup
PCS6 PIO32 11 — — Input with pullup
PCS7 PIO31 13 — — Input with pullup
RTR_HU PIO47 23 DCE_RTR_D — Input with pullup
RTR_U PIO25 156 DCE_RCLK_D PCM_CLK_D Input with pullup
RXD_HU PIO16 25 — — Input with pullup
RXD_U PIO26 158 DCE_RXD_D PCM_RXD_D Input with pullup
SCLK PIO11 3 — — Input with pullup
SDATA PIO12 4 — — Input with pullup
SDEN PIO10 2 — — Input with pulldown
SRDY PIO35 15 — — Alternate operation3
TMRIN0 PIO27 142 — — Input with pullup
TMRIN1 PIO0 144 Input with pullup
TMROUT0 PIO28 141 — — Input with pulldown
TMROUT1 PIO1 143 — — Input with pulldown
TXD_U PIO20 159 DCE_TXD_D PCM_TXD_D Input with pullup
UCLK PIO21 22 USBSOF USBSCI Input with pullup
WR PIO15 16 — — Alternate operation3
Notes:
1. System reset is defined as a power-on reset (i.e., the RES input pin transitioning from its Low to High state) or a reset due to
a watchdog timer timeout.
2. When us ed as a PIO, input with a pu lldown option av ailab le.
3. When us ed as a PIO, input with a pu llup o ption available.
A-10 Am186™CC Communications Controller Data Sheet
Table 31. Reset Configuration Pins (Pinstraps)1
Signal Name Multiplexed
Signal(s) Description
{ADEN}BHE
PIO34 Address Enable: If {ADEN} is held High or left floating during power-on reset, the
address portion of the AD bus (AD15–AD0) is enabled or disabled during LCS, UCS, or
othe r mem ory bus cy cl es ba se d o n how the soft w are configures the D A b i t sett i ng . In
this case, the memory address is accessed on the A19–A0 pins. There is a weak
internal pullup resistor on { ADEN} so no external pullup is required. This mode of
operation reduces power consumption.
If {ADEN} is held Low on power-on reset, the AD bus drives both addresses and data,
regardless of how software configures the DA bit setting.
{CLKSEL1}
{CLKSEL2}
HLDA
[PCS4]
PIO3
CPU PLL Mode Select 1 determines the PLL mode for the system clock source.
CPU PLL Mode Select 2 is sampled on the rising edge o f reset and determines the PLL
mode fo r the sy s t em cl ock source. T his pin has an i nte rnal pu ll up re si sto r tha t is ac ti ve
only during reset. There are four CPU PLL modes that are selected by the values of
{CLKSEL1} and {CLKSEL2} as shown in Table 32. (For details on clocks see “Clock
Generation and Control” on page 40.)
{ONCE} UCS ONCE Mode Request asserted Low places the Am186CC microco ntroller into ON CE
mode. O therwise , the controller ope rates normally. In ONCE mode, all pins are three-
stated and remain in that state until a s ubsequent reset occurs. To guarantee that the
controller does not inadvertently enter ONCE mod e , {ONCE} has a weak internal pullup
resistor that is active only during a reset. A reset ending ONCE mode s hould be as long
as a power-on reset for the PLL to stabiliz e.
{UCSX8}[MCS0]
PIO4 Upper Memory Chip Select, 8 -Bit Bus asserted Lo w con fig ures the up per c hip s elect
regi on for an 8-bit b us siz e. This pi n has a pullup re sistor that is active only during reset,
so no external pullup is required to set the bus to 16-bit mode.
{USBSEL2}
{USBSEL1}
PCS1
PIO14
PCS0
PIO13
USB Clock Mode Selects 1–2 select the USB PLL operating mode. The pins have
internal pullups that are active only during reset. The USB PLL can operate in one of
three modes. With a crystal and the internal USB oscillator or an external oscillator , the
USB PLL can output 4x or 2x the input frequency. The USB PLL can al so be disabled
and the USB peripheral controller can receive its clock from the CPU PLL, which is the
default mode. The pins are encoded as shown in Table 33. (For details on clocks see
“Clock Generation and Control” on page 40.)
{USBXCVR}S0 U SB External Transceiver Enable asserted Low disabl es the internal USB transceiver
and enables the pins needed to hook up an ex ternal transceiver . This pin has a pul lup
resistor that is active only during reset, so no external pullup is required as long as the user
ensures that this input is not driven Lo w during a pow e r-on rese t.
Notes:
1. A pinstrap is used to enable or disable features based on the state of the pin during an external reset. The pinstrap must be
held in its desired state for at least 4.5 clock cycles after the deassertion of RES. The pinstraps are sampled in an external
reset only (when RES is asserted), not during an internal watchdog timer-generated reset.
Table 32. CPU PLL Modes
{CLKSEL1} {CLKSEL2} CPU PLL Mode
1 1 2X, CPU PLL enabled (default)
1 0 4X, CPU PLL enabled
0 1 1X, CPU PLL enabled
0 0 PLL Bypass
Table 33. USB PLL Modes
{USBSEL1} {USBSEL2} USB PLL Mode
1 1 Use system clock (after CPU PLL mode
select), USB PLL disabled (default)
1 0 4x, USB PLL enabled
0 1 2x, USB PLL enabled
00Reserved
Am186™CC Communications Controller Data Sheet A-11
Pin List Table Column Definitions
The following paragraphs describes the individual
columns of information in Table 35, “Pin List Summary,”
on page A- 12. The pin s are grouped alphabeti cally by
function.
Note: All maximum delay numbers should be in-
creased by 0.035 ns for every pF of load (up to a max-
imum of 150 pF) over the maximum load specified in
Table 35 on page A-12.
Column #1—Signal Name, [Alternate Function],
{Pinstrap}
This column denotes the primary and alternate
functions of the pins. Most of the pins that have
alternate functions are configured for these functions
via firmware modifying values in the Peripheral Control
Block. Refer to the
Am186™CC/CH/CU
Microcontrollers Register Set Manual
, order #21916,
for full documentation of this process.
Brackets, [ ], are used to indicate the alternate,
multiplexed function of a pin (i.e., not power-on reset
default).
Braces, { }, are used to indicate the functionality of a pin
only during a processor reset. These signals are called
pinstraps. To select the desired configuration, the
pinstraps are terminated internally with pullup resistors
or externally with pulldown resistors. Their state is
sampled during a processor reset and latched on the
rising edge of reset. The signals must be held in the
desired state for 4.5 system clock cycles after the
deassertion of reset. Based on the pinstrap’s state at
the time they are latched, certain features of the
Am186CC controller are enabled or disabled. All
external termination should be implemented with 10-
kohm resistors on these signals.
The pinstraps are listed in Table 31, “Reset
Configuration Pins (Pinstraps),” on page A-10.
Column #2—Pin No.
The pin number column identifies the pin number of the
individual I/O signal on the pac kage.
Column #3—T ype
Definitio ns of the abbreviations in the Type column are
shown in Table 34.
Column #4—Max Load (pF)
The Max Load column designates the capacitive load
at which the I/O timing for that pin is guaranteed.
Column #5—POR Default Function
The POR Default Function column shows the status of
these pins after a power-on reset. In some cases the
pin is the function outlined in the “Signal Name” column
of the table. The signal name is listed in the POR
Default Function column if the signal is the default
function and not a PIO after a processor reset. In other
cas es the pin is a PIO configured as an input.
Column #6—Reset State
The Reset State column indicates the termination
present on the signal at reset (pul lup or pull down) and
indicates whether the signal is a three-stated output or
a Schmitt trigger input. Refer to Table 34 for
abbreviations used in this column.
Column #7—POR Default Operation
The POR Default Operation column describes the type
of input and/or output that is default pin operation.
Refer to Table 34 for abbreviations used in this column.
Column #8—Hold State
The Hold State column shows the state of the pin in
hold sta te. Refer to Table 34 for abbreviations u sed in
this column.
Column #9—5 V
A "5 V" in the 5-V column indicates 5-V tolerant inputs.
These inputs are not damaged and do not dra w excess
power when driven with levels up to VCC + 2.6 volts.
These pins only drive t o VCC.
Table 34. Pin List Table Definitions
Type Definition
[ ] Pin alternate function
{ } Pinstrap pin
B Bidirectional
HHigh
LS Programmable to hold last state of pin
O Totem pole output
OD Open drain output
OD-O Open drain output or totem pole output
PD Internal pulldown resistor
PU Internal pullup re sistor
STI Schmitt trigger Input
STI-OD Schmitt trigger input or open drain output
TS Three-state output
A-12 Am186™CC Communications Controller Data Sheet
Table 35. Pin List Summary
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
Bus Interface U nit
A0 30 O 70 A0 TS-PD O TS-PD 5 V
A1 31 O 70 A1 TS-PD O TS-PD 5 V
A2 32 O 70 A2 TS-PD O TS-PD 5 V
A3 36 O 70 A3 TS-PD O TS-PD 5 V
A4 37 O 70 A4 TS-PD O TS-PD 5 V
A5 42 O 70 A5 TS-PD O TS-PD 5 V
A6 43 O 70 A6 TS-PD O TS-PD 5 V
A7 44 O 70 A7 TS-PD O TS-PD 5 V
A8 45 O 70 A8 TS-PD O TS-PD 5 V
A9 49 O 70 A9 TS-PD O TS-PD 5 V
A10 50 O 70 A10 TS-PD O TS-PD 5 V
A11 64 O 70 A11 TS-PD O TS-PD 5 V
A12 65 O 70 A12 TS-PD O TS-PD 5 V
A13 69 O 70 A13 TS-PD O TS-PD 5 V
A14 70 O 70 A14 TS-PD O TS-PD 5 V
A15 84 O 70 A15 TS-PD O TS-PD 5 V
A16 85 O 70 A16 TS-PD O TS-PD 5 V
A17 88 O 70 A17 TS-PD O TS-PD 5 V
A18 89 O 70 A18 TS-PD O TS-PD 5 V
A19 90 O 70 A19 TS-PD O TS-PD 5 V
AD0 28 B 70 AD0 TS-PD B TS 5 V
AD1 34 B 70 AD1 TS-PD B TS 5 V
AD2 38 B 70 AD2 TS-PD B TS 5 V
AD3 46 B 70 AD3 TS-PD B TS 5 V
AD4 51 B 70 AD4 TS-PD B TS 5 V
AD5 66 B 70 AD5 TS-PD B TS 5 V
AD6 86 B 70 AD6 TS-PD B TS 5 V
AD7 92 B 70 AD7 TS-PD B TS 5 V
AD8 29 B 70 AD8 TS-PD B TS 5 V
AD9 35 B 70 AD9 TS-PD B TS 5 V
AD10 39 B 70 AD10 TS-PD B TS 5 V
AD11 47 B 70 AD11 TS-PD B TS 5 V
AD12 52 B 70 AD12 TS-PD B TS 5 V
AD13 67 B 70 AD13 TS-PD B TS 5 V
AD14 87 B 70 AD14 TS-PD B TS 5 V
AD15 93 B 70 AD15 TS-PD B TS 5 V
ALE
[PIO33] 19 O
STI-PD [STI] [O] 50 ALE TS-PD O TS-PD 5 V
ARDY
[PIO8] 14 STI-PU
STI-PU [STI] [O] 50 ARDY STI-PU STI-PU STI 5 V
Am186™CC Communications Controller Data Sheet A-13
BHE
[PIO34]
{ADEN}20 O
STI-PU [STI] [O]
STI 50 BHE STI-PU O TS-PU 5 V
BSIZE8 94 O 50 BSIZE8 TS-PU O ——
DEN
[DS]
[PIO30] 18 O
O
STI-PU [STI] [O] 50 DEN TS-PU O TS-PU 5 V
[DRQ0]
PIO9 124 STI-PD
STI-PD [STI] [O] 50 PIO9 STI-PD STI-PD [STI] [O] — 5 V
DRQ1 105 STI-PD — DRQ1 STI-PD STI-PD — 5 V
DT/R
[PIO29] 17 O
STI-PU [STI] [O] 50 DT/R TS-PU O TS-PU 5 V
HLDA
{CLKSEL1} 98 O
STI 50 HLDA STI-PU O H 5 V
HOLD 99 STI — HOLD STI-PD STI H 5 V
RD 97 O 70 RD TS-PU O TS-PU 5 V
S0
{USBXCVR}57 O
STI 50 S0 STI-PU O TS 5 V
S1 56 O 50 S1 TS-PU O TS 5 V
S2 55 O 50 S2 TS-PU O TS 5 V
S6 54 O 50 S6 TS-PD O TS 5 V
SRDY
[PIO35] 15 STI-PU
STI-PU [STI] [O] 50 SRDY STI-PU STI-PU — 5 V
WHB 95 O 70 WHB TS-PU O TS-PU 5 V
WLB 96 O 70 WLB TS-PU O TS-PU 5 V
WR
[PIO15] 16 O
STI-PU [STI] [O]
STI 50 WR STI-PU O TS-PU 5 V
Chip Selects
LCS
[RAS0]131 O
O50 LCS TS-PU O TS-PU 5 V
[MCS0]
PIO4
{UCSX8}126 O
STI-PU [STI] [O]
STI 50 PIO4 STI -PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
MCS1
[CAS1]127 O
O50 MCS1 TS-PU O TS-PU 5 V
MCS2
[CAS0]128 O
O50 MCS2 TS-PU O TS-PU 5 V
[MCS3]
[RAS1]
PIO5 129 O
O
STI-PU [STI] [O] 50 PIO5 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
PCS0
[PIO13]
{USBSEL1} 5O
STI-PU [STI] [O]
STI 50 PCS0 STI-PU O TS-PU 5 V
PCS1
[PIO14]
{USBSEL2} 6O
STI-PU [STI] [O]
STI 50 PCS1 STI-PU O TS-PU 5 V
PCS2 7 O 50 PCS2 TS-PU O TS-PU 5 V
Table 35. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
A-14 Am186™CC Communications Controller Data Sheet
PCS3 8 O 50 PCS3 TS-PU O TS-PU 5 V
[PCS4]
PIO3
{CLKSEL2} 9O
STI-PU [STI] [O]
STI 50 PIO3 STI -PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
[PCS5]
PIO2 10 O
STI-PU [STI] [O] 50 PIO2 STI-PU O TS-PU 5 V
[PCS6]
PIO32 11 O
STI-PU [STI] [O] 50 PIO32 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
[PCS7]
PIO31 13 O
STI-PU [STI] [O] 50 PIO31 STI-PU S T I - P U [ S T I ] [ O ] TS-PU 5 V
UCS
{ONCE}132 O
STI 50 UCS STI-PU O TS-PU 5 V
Reset/Clocks
CLKOUT 60 O 70 CLKOUT —O ——
RES 114 ST — RES STI STI — 5 V
RESOUT 58 O 50 RESOUT H O — 5 V
[UCLK]
[USBSOF]
[USBSCI]
PIO21
22
STI
O
STI
STI-PU [STI] [O]
50 PIO21 STI-PU STI-PU [STI] [O] — 5 V
USBX1 75 STI — USBX1 — STI — —
USBX2 76 O — USBX2 — O — —
X1 73 STI — X1 — STI — —
X2 74 O — X2 — O — —
Programmable T im ers
[TMRIN0]
PIO27 142 STI-PU
STI-PU [STI] [O] 50 PIO27 STI-PU STI-PU [STI] [O] — 5 V
[TMRIN1]
PIO0 144 STI-PU
STI-PU [STI] [O] 50 PIO0 STI-PU STI-PU [STI] [O] — 5 V
[TMROUT0]
PIO28 141 O
STI-PD [STI] [O] 50 PIO28 STI-PD STI-PD [STI] [O] TS 5 V
[TMROUT1]
PIO1 143 O
STI-PD [STI] [O] 50 PIO1 STI-PD STI-PD [STI] [O] TS 5 V
Interrupts
INT0 107 STI — INT0 STI-PU STI — 5 V
INT1 109 STI — INT1 STI-PU STI — 5 V
INT2 110 STI — INT2 STI-PU STI — 5 V
INT3 111 STI — INT3 STI-PU STI — 5 V
INT4 112 STI — INT4 STI-PU STI — 5 V
INT5 113 STI — INT5 STI-PU STI — 5 V
[INT6]
PIO19 145 STI
STI-PU [STI] [O] 50 PIO19 STI-PU STI-PU [STI] [O] — 5 V
[INT7]
PIO7 146 STI
STI-PU [STI] [O] 50 PIO7 STI-PU STI-PU [STI] [O] — 5 V
Table 35. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
Am186™CC Communications Controller Data Sheet A-15
[INT8]
[PWD]
PIO6 147 STI
STI
STI-PU [STI] [O] 50 PIO6 STI-PU STI-PU [STI] [O] —5 V
NMI 115 STI — NMI STI-PU STI — 5 V
Synchronous Communications Interfaces
Channel A
DCE_RXD_A
[GCI_DD_A]
[PCM_RXD_A] 118 STI
B-OD
STI 50 DCE_RXD_A STI-PU STI — 5 V
DCE_TXD_A
[GCI_DU_A]
[PCM_TXD_A] 119 O-OD
B-OD
O-LS-OD 50 DCE_TXD_A TS-PU OD-O — 5 V
DCE_RCLK_A
[GCI_DCL_A]
[PCM_CLK_A] 117 STI
STI
STI — DCE_RCLK_A STI-PU STI — 5 V
DCE_TCLK_A
[GCI_FSC_A]
[PCM_FSC_A] 116 STI
STI
STI — DCE_TCLK_A STI-PU STI — 5 V
[DCE_CTS_A]
[PCM_TSC_A]
PIO17 123 STI
OD
STI-PU [STI] [O] 50 PIO17 STI-PU STI-PU [STI] [O] — 5 V
[DCE_RTR_A]
PIO18 122 O
STI-PU [STI] [O] 30 PIO18 STI-PU STI-PU [S TI ] [ O ] — 5 V
Channel B
[DCE_RXD_B]
[PCM_RXD_B]
PIO36 138 STI
STI
STI-PU [STI] [O] 50 PIO36 STI-PU STI-PU [STI] [O] — 5 V
[DCE_TXD_B]
[PCM_TXD_B]
PIO37 139 OD-O
O-LS-OD
STI-PU [STI] [O] 50 PIO37 STI-PU STI-PU [STI] [O] — 5 V
[DCE_RCLK_B]
[PCM_CLK_B]
PIO40 135 STI
STI
STI-PU [STI] [O] 50 PIO40 STI-PU STI-PU [STI] [O] — 5 V
[DCE_TCLK_B]
[PCM_FSC_B]
PIO41 134 STI
STI
STI-PU [STI] [O] 50 PIO41 STI-PU STI-PU [STI] [O] — 5 V
[DCE_CTS_B]
[PCM_TSC_B]
PIO38 137 STI
OD
STI-PU [STI] [O] 50 PIO38 STI-PU STI-PU [STI] [O] — 5 V
[DCE_RTR_B]
PIO39 136 O
STI-PU [STI] [O] 30 PIO39 STI-PU STI-PU [STI] [O] — 5 V
Channel C
[DCE_RXD_C]
[PCM_RXD_C]
PIO42 153 STI
STI
STI-PD [STI] [O] 50 PIO42 STI-PD STI-PD [STI] [O] — 5 V
[DCE_TXD_C]
[PCM_TXD_C]
PIO43 154 OD-O
O-LS-OD
STI-PD [STI] [O] 50 PIO43 STI-PD STI-PD [STI] [O] — 5 V
Table 35. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
A-16 Am186™CC Communications Controller Data Sheet
[DCE_RCLK_C]
[PCM_CLK_C]
PIO22 150 STI
STI-O
STI-PD [STI] [O] 50 PIO22 STI-PD STI-PD [STI] [O] —5 V
[DCE_TCLK_C]
[PCM_FSC_C]
PIO23 149 STI
STI-O
STI-PD [STI] [O] 50 PIO23 STI-PD STI-PD [STI] [O] — 5 V
[DCE_CTS_C]
[PCM_TSC_C]
PIO44 152 STI
OD
STI-PU [STI] [O] 50 PIO44 STI-PU STI-PU [STI] [O] — 5 V
[DCE_RTR_C]
PIO45 151 O
STI-PU [STI] [O] 30 PIO45 STI-PU STI-PU [STI] [O] — 5 V
Low-Speed UART/Synchronous Communications Channel D
[RXD_U] (UART)
[DCE_RXD_D]
[PCM_RXD_D]
PIO26
158
STI
STI
STI
STI-PU [STI] [O]
50 PIO26 STI-PU STI-PU [STI] [O] — 5 V
[TXD_U] (UART)
[DCE_TXD_D]
[PCM_TXD_D]
PIO20
159
O
OD-O
O-LS-OD
STI-PU [STI] [O]
50 PIO20 STI-PU STI-PU [STI] [O] — 5 V
[CTS_U] (UART)
[DCE_TCLK_D]
[PCM_FSC_D]
PIO24
157
STI
STI
STI
STI-PU [STI] [O]
50 PIO24 STI-PU STI-PU [STI] [O] — 5 V
[RTR_U] (UART)
[DCE_RCLK_D]
[PCM_CLK_D]
PIO25
156
O
STI
STI
STI-PU [STI] [O]
30 PIO25 STI-PU STI-PU [STI] [O] — 5 V
High-Speed UART
[RXD_HU]
PIO16 25 STI
STI-PU [STI] [O] 50 PIO16 STI-PU STI-PU [STI] [O] — 5 V
TXD_HU 26 O 30 TXD_HU TS-PU O — 5 V
[CTS_HU]
[DCE_CTS_D]
[PCM_TSC_D]
PIO46
24
STI
STI
OD
STI-PU [STI] [O]
50 PIO46 STI-PU STI-PU [STI] [O] — 5 V
[RTR_HU]
[DCE_RTR_D]
PIO47 23 O
O
STI-PU [STI] [O] 30 PIO47 STI-PU STI-PU [STI] [O] — 5 V
Debug Support
QS0 62 O 30 QS0 TS-PD O — 5 V
QS1 63 O 30 QS1 TS-PD O — 5 V
Universal Serial Bus
USBD+
[UDPLS] 81 B
STI — USBD+ TS B — —
USBD-
[UDMNS] 80 B
STI — USBD- TS B — —
Table 35. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
Am186™CC Communications Controller Data Sheet A-17
Synchronous Serial Interface
[SCLK]
PIO11 3O
STI-PU [STI] [O] 50 PIO11 STI-PU STI-PU [STI] [O] —5 V
[SDATA]
PIO12 4O
STI-PU [STI] [O] 50 PIO12 STI-PU STI-PU [STI] [O] — 5 V
[SDEN]
PIO10 2O
STI-PD [STI] [O] 50 PIO10 STI-PD STI-PD [STI] [O] — 5 V
Reserved Pins
RSVD_104
[UXVRCV] 104 —
STI — — STI-PU — — —
RSVD_103
[UXVOE]103 —
O50 — TS-PU — — —
RSVD_102
[UTXDMNS] 102 —
O50 — PU — — —
RSVD_101
[UTXDPLS] 101 —
O50 — PU — — —
Power and Ground
VCC 12 — — — — — — —
VCC 27 — — — — — — —
VCC 40 — — — — — — —
VCC 48 — — — — — — —
VCC 59 — — — — — — —
VCC 68 — — — — — — —
VCC 78 — — — — — — —
VCC 91 — — — — — — —
VCC 106 — — — — — — —
VCC 120 — — — — — — —
VCC 125 — — — — — — —
VCC 133 — — — — — — —
VCC 148 — — — — — — —
VCC 160 — — — — — — —
VCC_A77———————
VCC_USB 79 — — — — — — —
VSS 1————— ——
VSS 21 — — — — — — —
VSS 33 — — — — — — —
VSS 41 — — — — — — —
VSS 53 — — — — — — —
VSS 61 — — — — — — —
VSS 71 — — — — — — —
VSS 83 — — — — — — —
VSS 100 — — — — — — —
VSS 108 — — — — — — —
VSS 121 — — — — — — —
Table 35. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
A-18 Am186™CC Communications Controller Data Sheet
VSS 130 ——— — — ——
VSS 140 — — — — — — —
VSS 155 — — — — — — —
VSS_A72———————
VSS_USB 82 — — — — — — —
Table 35. Pin List Summary (Continued)
Signal Name
[Alternate
Function]
{Pinstrap}
Pin
No. Type Max
Load
(pF)
POR
Default
Function
Reset
State
POR
Default
Operation
Hold
State 5 V
Am186™CC Communications Controller Data Sheet B-1
APPENDIX B—PHYSICAL DIMENSIONS: PQR160, PLASTIC QUAD FLAT PACK (PQFP)
25.35
REF
27.90
28.1031.00
31.40
Pin 120
Pin 80
0.65 BASIC
3.20
3.60
0.25
Min
Pin 40
Pin 1 I.D.
25.35
REF
Pin 160
27.90
28.10
31.00
31.40
3.95
MAX
SEATING PLANE
16-038-PQR-1
PQR160
12-22-95 lv
B-2 Am186™CC Communications Controller Data Sheet
Am186™CC Communications Controller Data Sheet C-1
APPENDIX C—CUSTOMER SUPPORT
Related AMD Products—E86™ Family Devices
Device Description
80C186/80C188 16-bit microcontroller
80L186/80L188 Low-voltage, 16-bit microcontroller
Am186™EM/Am188™EM High-performance, 16-bit embedded microcontroller
Am186EMLV/Am188EMLV High-performance, 16-bit embedded microcontroller
Am186ES/Am188ES High-performance, 16-bit embedded microcontroller
Am186ESLV/Am188ESLV High-performance, 16-bit embedded microcontroller
Am186ED High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller
with 8- or 16-bit external data bus
Am186EDLV High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded
microcontroller with 8- or 16-bit external data bus
Am186ER/Am188ER High-performance, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of in-
ternal RAM
Am186CC High-performance, 16-bit embedded communications controller
Am186CH High-performance, 16-bit embedded HDLC microcontroller
Am186CU High-performance, 16-bit embedded USB microcontroller
Élan™SC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
ÉlanSC310 High-performance, single-chip, 32-bit embedded PC/AT microcontroller
ÉlanSC400 Single-chip, low-power, PC/AT-compatible microcontroller
ÉlanSC410 Single-chip, PC/AT-compatible microcontroller
ÉlanSC520 High-performance, 32-bit embedded microcontroller
Am386®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Am386®SX High-performance, 32-bit embedded microprocessor with 16-bit external data bus
Am486®DX High-performance, 32-bit embedded microprocessor with 32-bit external data bus
Am5x86® High-performance, 32-bit embedded microprocessor with 32-bit external data bus
AMD-K6™E High-performance, 32-bit embedded microprocessor with 64-bit external data bus
AMD-K6™-2E High-performance, 32-bit embedded microprocessor with 64-bit external data bus and
3DNow!™ technology
Notes:
1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit
external data bus and 80C188-compatible (except where noted otherwise); LV = low voltage
Am386
®
SX/DX
Microprocessors
Am486
®
DX
Microprocessor
E86™ Family of Embedded Microprocessors and Microcontrollers
Am186 E S and
Am188™EM
Am188EMLV Microcontrollers
Am188ER
— Microprocessors
— 16- and 32-bit microcontrollers
— 16-bit microcontrollers
AMD-K6™E
Microprocessor
AMD-K6™-2E
Microprocessor
Am5x86®
Microprocessor
Am186CC
Communications
Controller
Am186™CU USB
Microcontroller
Am186CH HDLC
Microcontroller
80C186 and 80C188
Microcontrollers
Am188ES
Microcontrollers
Am186EM and
Microcontrollers
80L186 and 80L188
Microcontrollers
Am186EMLV &
Microcontrollers
Am186ESLV &
Am188ESLV
Am186ER and
Microcontrollers
Am186ED
Am186EDLV
Microcontroller
Microcontroller
Élan™SC310
Microcontroller
ÉlanSC300
Microcontroller
ÉlanSC410
Microcontroller
ÉlanSC400
Microcontroller
ÉlanSC520
Microcontroller
C-2 Am186™CC Communications Controller Data Sheet
Related Documents
The following documents provide additional
inf ormation regarding th e Am186CC microcontroller.
■
Am186™CC/CH/CU Microcontrollers User’s Manual
,
order #21 914
■
Am186™CC/CH/CU Microcontrollers Register Set
Manual
, order #21916
■
Am186™ and Am188™ Family Instruction Set
Manual
, order #21267
■
Interfacing an Am186™CC Communications
Controller to an AMD SLAC™ Device Using the
Enhanced SSI Application Note
, order #21921
Other information of interest includes:
■
E86™ Family Products and Development Tools CD,
order #21058
Am186CC/CH/CU Microcontroller
Customer De velopment Platform
The Am186CC/CH/CU customer development
platfor m (CDP) is provided as a test and developmen t
platform for the Am186CC/CH/CU microcontrollers.
The Am186CC/CH/ CU CDP ships with the Am186CC
microcontroller. Because this device supports a
superset of the features of the Am186CH HDLC and
the Am1 86CU USB micr ocontro llers, the developmen t
platform can be used to evaluate the Am186CH and
the Am186CU devices.
The CDP is divided into two major sections: a main
board and a development module. The main board
serves as the primary platform for silicon evaluation
and software development. The board provides
connectors for accessing the major communications
peripherals, switches to easily configure the
microcontroller, logic analyzer, and debug headers.
The develo pme nt mo dul e, which att ac hes to the top of
the main board, provides ready-to-run hardware for
three of the most common communications
requirements:
■A 10 Mbit/s Ethernet connection
■An ISDN connection (with both an S/T and a
U interface)
■Two POTS interfaces
The CDP provides a good star ting point for hardware
designers, and software development can begin
immediately without the normal delay that occurs while
waiting for prototypes.
The CDP also comes with AMD’s CodeKit software
that provides customers with pre-written driver
software for the major communications peripherals
associated with a typical Am186Cx design. Included
are drivers for the HDLC channels, USB peripheral
controller (for the Am186CU USB microcontroller),
UARTs, PCnet-ISA II (AMD’s single-chip Ethernet
solution), and several other common peripherals. The
CodeKit software comes complete with instructions,
royalty-free distribution rights, and software in both
binary and source code formats.
Third-Party Development Support Products
The FusionE86 Program of Partnerships for
Application Solutions provides the customer with an
array of products designed to meet critical time-to-
market needs. Products and solutions available from
the AMD FusionE86 partners include protocol stacks,
emulators, hardware and software debuggers, board-
lev el products, and software dev elopment tools, among
others.
In addition, mature de v elopment tools and applications
for the x8 6 pl atfo rm are wi del y available in the general
marketplace.
Customer Service
The AMD customer service network includes U.S.
offices, international offices, and a customer training
center. Expert technical assistance is available from
the AMD wo rldwide staff of fi eld appli cation e ngineers
and factory suppor t staff to answer E86 and Co mm86
family hardware and software development questions.
Note: The support telephone numbers listed below
are subject to change. For current telephone numbers,
refer to www.amd.com/support/literature.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides
e-mail suppor t as well as a toll-free number for direct
access to our corporate applications hotline.
The AMD World Wide Web home page provides the
latest product information, including technical
information and data on upcoming product releases. In
addition, EPD CodeKit software on the Web site
provides tested source code example applications.
Additional contact information is listed on the back of
this datasheet. For technical suppor t questions on all
E86 and Comm86 products, send e-mail to
epd.support@amd.com.
Corporate Applications Hotline
(800) 222-9323 Toll-free for U.S. and Canada
44-(0) 1276-803-299 U.K. and Europe hotline
Am186™CC Communications Controller Data Sheet C-3
World Wide Web Home Page
To access the AMD home page go to: www.amd.com.
Then follow the Embedded Processors link for
information about E86 and Comm86 products .
Questions, requests, and input concerning AMD’s
WWW pages can be sent via e-mail to
webmaster@amd.com.
Documentation and Literature
Fr ee inform ation such as data books, user’s manuals,
data sheets, application notes, the
E86™ Family
Products and Development Tools CD
, order #21058,
and other literature is available with a simple phone
call. Internationally, contact your local AMD sales office
for product literature. Additional contact information is
listed on the back of this data sheet.
Literature Ordering
(800) 222-9323 Toll-free for U.S. and Canada
C-4 Am186™CC Communications Controller Data Sheet
Am186™CC Communications Controller Data Sheet Index-1
INDEX
A
A19–A0 signals, 14
absolute maximum ratings, 45
AD15–AD0 signals, 14
address and data bus, 14, 17
address bus
address bus disable in effect, 36
default operation, 35
description, 14, 17
ALE signal, 14
Am186CC controller
archit ectural overview, 28
block diagram, 28
DC characteristics over commercial and industrial
operating ranges, 46
detailed description, 28
distinctive characteristics, 1
general description, 1
I/O circuitry, 44
logic diagram by default pin function, 7
logic diagram by interface, 6
ordering information, 2
pin assignment tables, 10
pin tables (Appendix A), A-1
PQFP package, B-1
related AMD E86 family devices, C-1
signal description table, 14
static operation, 43
applications, 37
32-channel linecard system, 39
ISDN terminal adapter system, 38
ISDN to ethernet low-end router system, 38
archit ectural overview, 28
ARDY signal, 14
asynchronous communications
asynchronous ready waveforms, 69
asynchronous serial ports (description), 31
baud clock, 43
High-Speed UART clocks, 43
High-Speed UART signal descriptions, 23
UART signal descriptions, 22
B
BHE signal, 15
block diagram, 28
BSIZE8 signal, 15
busaddress bus description, 14, 17
bus hold timing, 69
bus status pins, 17
entering bus hold waveforms, 70
ex iting bus hold waveforms, 70
bus i n terfa ce
signal li st, 14
C
capacit ance, 46
chip selects
description, 34
ranges and DRAM configuration, 14, 20
signal des cription s, 19
CLKOUT signal, 17
clock
CLKOUT signal description, 17
clock generation and control, 40
clock sharing by system and USB, 41
crystal parameters, 42
crystal selection, 42
crystal-driven clock source, 42
external clock source, 43
external interface to support clocks, 42–43
features, 40
High-Speed UART clocks, 43
PLL bypass mode, 43
suggested system clock frequencies, clock modes
and crystal frequencies, 42
system and USB clock generation, 41
system clock, 40
system interfaces and clock control, 33
UART baud clock, 43
USB clock, 40
USB clock timing waveforms, 72
USB clocks timing, 72
CPU
Am186 embedded CPU, 29
CPU PLL modes, A-10
Index-2 Am186™CC Communications Controller Data Sheet
crystal
crystal-driven clock source, 42
parameters, 4 2
selecting a crystal, 42
suggested crystal frequencies, 42
customer support
documentation and literature, C-3
hotline and web, C-2
literature ordering, C-3
ordering the Am186CC controller, 2
third-party development support products, C-2
web home page, C-3
D
DC characteristics over commercial and industrial
operating ranges, 46
USB, 46
DCE (data communications equipment)
DCE interface timing, 77
DCE receive waveforms, 77
DCE transmit waveforms, 77
signal descriptions, 23
DCE_RCLK_A signal, 23
DCE_RCLK_D signa l, 25
DCE_RXD_A signal, 23
DCE_RXD_D signal, 24
DCE_TCLK_A signal, 24
DCE_TXD_A si gna l, 2 3
debug
debug support signals, 19
DEN signal, 15
DMA (direct memory access)
DMA request signals, 15
general-purpose DMA channels, 32
SmartDMA channels, 31
documenta tio n, C-3
DRAM
chip selects and DRAM configuration, 14
description, 34
read cycle with wait-states waveform, 81
read cycle without wait-states waveform, 80
refresh cycle waveform, 82
signal descriptions, 20
ti ming, 80
write cycle with wait-states waveform, 82
write cycle without wait-states wa veform, 81
driver characteristics - universal serial bus, 45
DRQ1 signal, 15
DT/R signal, 15
E
emulation
in-circuit emulator support, 37
evaluation platform, C-2
G
GCI (general circuit interface)
bus timing, 73
bus waveforms, 73
description, 31
signal des cription s, 26
H
HDLC (high-level data link control)
channel s, 31
signal des cr i pti on s, 2 3
High-Speed UART
signal des cription s, 23
HLDA signal, 16
HOLD signal, 16
hotline and world wide web support, C-2
I
I/OI/O circuitry, 44
I/O space, 29
programmable I/O (PIO), 32
INT5–INT0 signals, 21
interrupts
interrupt controller, 32
signal des cription s, 21
L
LCS signal, 19
logic diagram by default pin function, 7
logic diagram by interface, 6
M
MCS1 signal, 19
MCS2 signal, 19
memory
memory organization, 29
segment register selection rules, 30
memory and peripheral interface, 33
multiplexed functions
signal trade-offs, A-5
Am186™CC Communications Controller Data Sheet Index-3
N
NMI signal, 2 1
O
operating ranges, 45
ordering information, 2
P
package
PQFP physical dimensions, B-1
PCM (pulse - code modulation ) highway
signal descriptions, 25
timing (timing master), 76
timing (timing slave), 74
waveforms (timing master), 76
waveforms (timing slave), 75
PCS0 signal, 20
PCS1 signal, 20
PCS2 signal, 20
PCS3 signal, 20
peripherals
memory and peripheral interface, 33
peripheral timing, 65
peripheral timing waveforms, 65
system interfaces, 32
pins
pin and signal tables, 9
pin assignments sorted by pin number, 10
pin assignments sorted by signal name, 11
pin connection diagram, 8
pin defaults, A-2
pin list summary, A-12
pin tables (Appendix A), A-1
pinstraps
pinstraps table, A-10
PIO supply current limit, 44
PIO47–PIO0 signals, 22
PIOs (programmable I/Os)
description, 32
signal descriptions, 22
sorted b y pin number, A-8
sorted b y signal name, A-9
PLL (phase-locked loop)
modes, A-10
PLL b ypass (CPU), A-10
PLL bypass mode, 43
system PLL, 40
USB PLL, 40
PLL bypass mode, 43
POR (power-on reset)
pin defaults, A-2
power
power consumption calculation, 47
power supply operation, 44
supply connections, 44
supply current, 47
typical ICC versus frequency, 47
PQFP package
physical dimensions, B-1
Q
QS1–Q S0 si gna l, 19
R
RD signal, 16
read cycle timing, 58
read cycle waveforms, 60
RES signal, 18
reset
definition of types, 13
power-on reset pin def aults table, A-2
signals related to reset, 67
timing, 66
waveforms, 66
reset configuration pins
See pinstraps, A-10
RESOUT signal, 18
RSVD_101 pin , 18
RSVD_102 pin , 18
RSVD_103 pin , 18
RSVD_104 pin , 18
S
S0 signal, 17
S1 signal, 17
S2 signal, 17
S6 signal, 16
serial communications
asynchronous serial ports, 31
description, 30
GCI, 31
HDLC, 31
SmartDMA, 31
synchron ous ser i al port, 32
TSAs, 31
USB, 30
Index-4 Am186™CC Communications Controller Data Sheet
signals
multiplexed signal trade-offs table, A-5
pin and signal tables, 9
pin assignments sorted by signal name, 11
signal descriptions, 14
signals related to reset, 67
SmartDMA
chann els , 3 1
softw are halt cycle t iming, 64
software halt cycle waveforms, 64
SRDY signal, 16
static operation, 43
switching characteristics and waveforms
key to switching waveforms, 49
numerical key to switching parameter symbols, 54
over commercial/industrial operating ranges, 58
parameter sy mb ols , 5 0
synchronous serial interface (SSI)
signal descriptions, 23
synchronous ready waveforms, 68
synchronous serial port, 32
ti ming, 79
waveforms, 79
system
system clock timing waveforms, 72
system clocks timing, 71
T
thermal characteristics, 48
equations, 48
thermal resistance, 48
timers
programmable timers, 32
signal descriptions, 22
timing
asynchronous ready waveforms, 69
bus hold, 69
DCE interface, 77
DRAM, 80
external ready cycle, 68
GCI, 73
PCM highway, 74–76
peripheral timing, 65
read cycle timing, 58
reset, 66
software halt cycle, 64
SSI, 79
synchronous ready waveforms, 68
system clocks, 71
USB, 78
USB clocks, 72
write cycle timing, 61
TSAs (time slot assigners)
description, 31
TXD_HU signal, 23
U
UART, 23
asynchronous ready waveforms, 69
asynchronous serial ports (description), 31
baud clock, 43
High-Speed UART clocks, 43
High-Speed UART signal descriptions, 23
UART signal descriptions, 22
UCS signal, 20
universal serial bus
driver characteristics, 45
USB
clock, 40
clock timing waveforms, 72
clocks timing, 72
data signal rise and fall times, 78
description, 30
external transceiver signals, 26
PLL mode s, A -10
receiver jitter tolerance, 78
signal des cr i pti on s, 2 6
system and USB clock generation, 41
timing, 78
USBD– signa l, 26
USBD+ signal, 26
USBX1 signal, 18
USBX2 signal, 18
UTXDMNS signal, 27
UTXDPLS signal, 27
UXVOE signal, 27
UXVRCV signal, 27
W
watchdog timer
description, 33
RES and watchdog timer reset, 18
WHB signal, 17
WLB signal, 17
WR signal, 17
write cycle timing, 61
write cycle waveforms, 63
www
home page, C-3
support, C-2
Am186™CC Communications Controller Data Sheet
Trademarks
È
2000 Advanced Micro Devic es, Inc. All rights reser ved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am5x86, Am386, and Am486 are registered trademarks, and AMD-K6, 3DNow!, Am186, Am188, CodeKit, Comm86, E86, Élan, PCnet, SLAC,
and SmartDMA are trademarks of Advanced Micro Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, I nc. ("AMD") products. AMD makes no representations
or warranties with respect to the accur acy or completeness of the contents of this publication and reserves the right to make changes to speci-
fications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any in-
tellectual property rights is granted by this pub lication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of
merchantability, fitness for a particular purpos e, or infringement of any intellectual property r ight.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
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situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontin ue o r make
changes to its products at any time without notice.
© 2000 Advanced Micro Devices, Inc.
All rights reserved.
