FARRIS SEMICONDUCTOR CD4029BMS December 1992 CMOS Presettable Up/Down Counter Features e High-Voltage Type (20V Rating) Medium Speed Operation: 8MHz (Typ.) at CL = S0pF and VDD - VSS = 10V Multi-Package Parallel Clocking for Synchronous High Speed Output Response or Ripple Clocking for Slow Clock Input Rise and Fall Times Preset Enable and Individual Jam Inputs Provided Binary or Decade Up/Down Counting BCD Outputs In Decade Mode 100% Tested for Maximum Quiescent Current at 20V 5V, 10V and 15V Parametric Ratings * Standardized Symmetrical Output Characteristics Maximum Input Current of 1A at 18V Over Full Pack- age-Temperature Range; 100nA at 18V and +25C Noise Margin (Over Full Package Temperature Range): + 1V at VDD = 5V 2Vat VOD = 10V - 2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Stan- dards No. 13B, Standard Specifications for Descrip- tlon of B Series CMOS Devices Applications * Programmable Binary and Decade Counting/Fre- quency Synthesizers-BCD Output Analog to Digital and Digital to Analog Conversion * Up/Down Binary Counting * Difference Counting * Magnitude and Sign Generation Up/Down Decade Counting Description CD4029BMS consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both count- ing modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 anda CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRE-SET ENABLE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN made pro- vided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel- clocking or a ripple-clocking arrangement as shown in Figure 17. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. The CD4029BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X Frit Seal DIP HiF Ceramic Flatpack H6W Pinout CD4029BMS TOP VIEW PRESETENABLE[1] ~ fie] VOD os [2 Hg] CLock vam 4 [3] a] a3 samt [4] 3] JAM 3 CARRY IN [5] Ha] JAM 2 ai [e fi] a2 CARRY oot [7 fio] UP/DOWN vss [9] BINARYDECADE Functional Diagram JAM INPUTS PRESET ENABLE] 735g f VOD came | slodols ENABLE) 5 6 at __> BINARY/ 1102 DECADE 9 _ Q3 BUFFERED UP/DOWN 10 p> | OUTPUTS 2% CLOCK 15 7 , i 13, our vss CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. ' File Number 3304 Copyright Harris Corporation 1992 7-798Specifications CD4029BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) ............... -0.5V to+20V Thermal Resistance ................ Gia 8. (Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package... .. BOC/AW 20C/W Input Voltage Range, All Inputs ............. -0.5V to VDD +0.5V Flatpack Package .............6.- 70CW 20C/w DC Input Current, Any One tnput...................0..06- +10mA Maximum Package Power Dissipation (PD) at +125C Operating Temperature Range..............5. -55G to +125C For TA = -55C to +100C (Package Type D, F,K) ...... 500mwW Package Types D, F, K, H For TA = +100C to +125C (Package Type D, F,K)...... Derate Storage Temperature Range (TSTG)........... -65C to +150C Linearity at 12MW/C to 200mW Lead Temperature (During Soldering) ................. +265C _ Device Dissipation per Output Transistor ............... 100mw At Distance 1/16 + 1/32 Inch (1.59mm + 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types) 10s Maximum Junction Temperature 2.0... eee +175C TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A LIMITS PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS] TEMPERATURE MIN | MAX |UNITS Supply Current iDD VDD = 20V, VIN = VDD or GND 1 +25C - 10 pA 2 +125C - 1000 | pA VOD = 18V, VIN = VDD or GND 3 -55C - 10 pA Input Leakage Current HL VIN=VODorGND- |VDD = 20 1 +25C -100 - nA 2 +125C -1000 - nA VDD = 18V 3 55C -100 - nA Input Leakage Current WH VIN=VDDorGND [VDD = 20 1 +25C. : 100 nA 2 +125C : 1000 nA VDD = 18V 3 55C - 100 nA Output Voltage VOL15 [VDD = 15V, No Load 1,2,3 +25C, +125C, -55C : 50 mV Output Voltage VOH15 ]|VDD = 15V, No Load (Note 3) 1,2,3 +25C, +125C, -55C] 14.95 - Vv Output Current (Sink) IOLS [VDD = 5V, VOUT = 0.4V 1 +25C 0.53 - mA Output Current (Sink) IOL10 |VDD = 10V, VOUT = 0.5V i +25C 1.4 - mA Output Current (Sink) 1OL15 [VDD = 15V, VOUT = 1.5V j +25C 3.5 - mA Output Current (Source)f IOH5A [VDD = 5V, VOUT = 4.6V 1 +25C - 0.53 | mA Output Current (Source)}| IOH5B [VDD = 5V, VOUT = 2.5V 1 +25C - -18 | mA Output Current (Source)}| IOH10 [VDD = 10V, VOUT = 9.5V 1 +25C - -1.4 [ mA Output Current (Source)]| !OH15 |VDD = 15V, VOUT = 13.5V 1 +25C - 3.5 mA N Threshold Voltage VNTH [VDD = 10V, ISS = -10nA 1 +25C 2.8 | 0.7 Vv P Threshold Voltage VPTH_ [VSS = OV, IDD = 10nA 1 +25C 0.7 2.8 v Functional F VDD = 2.8V, VIN = VDD or GND 7 +25C VOH>|VOL<| V VDD = 20V, VIN = VDD or GND 7 425C vbD/2 | VOD/2 VDD = 18V, VIN = VDD or GND 8A +125C VDD = 3V, VIN = VDD or GND 8B -55C Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1,2,3 +25C, +125C, -55C]- 1.5 Vv (Note 2) Input Voltage High VIH_ {VDD = 5V, VOH > 4.5V, VOL < 0.5V 1,2,3 425C, +125C, -55C] 3.5 - v (Note 2) Input Voltage Low VIL [VDD = 15V, VOH > 13.5v, 1,2,3 +25C, +125C, -55C]- 4 Vv (Note 2) VOL < 1.5V Input Voltage High VIH VDD = 15V, VOH > 13.5vV, 1,2,3 +25C, +125C, -55C] 11 - v (Note 2) VOL < 1.5V NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VOD. Limit implemented. 2. Go/No Go test with limits applied to inputs. is 0.050V max. 7-799 o 9 aSpecifications CD4029BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A LIMITS PARAMETER SYMBOL | CONDITIONS (NOTE 1, 2) SUBGROUPS | TEMPERATURE| MIN MAX | UNITS Propagation Delay TPHL1 | VDD = 5V, VIN = VDD or GND 9 +25C - 500 ns Clock To Q Output TPLHt 10, 11 +125C, 55C | - 675 | ns Propagation Delay TPHL2 | VDD = 5V, VIN = VDD or GND 9 +25C - 560 ns Clock To Garry Out TPLH2 10, 11 125C, 55C | - 756 ns Propagation Delay TPHL3 | VDD = 5V, VIN = VDD or GND 9 +25C . 470 ns Preset Enable To Q TPLH3 10, 11 +125C, -55C . 635 ns Propagation Delay TPHL4 | VOD = 5V, VIN = VDD or GND 9 +25C - 640 ns Guest Enable To Carry- | TPLH4 10, 14 4+125C, 55C | - 864 ns Propagation Delay TPHLS | VOD = 5V, VIN = VDD or GND 9 +25C . 340 ns Can, a TPLHS 10, 14 +125C, 55C | - 459 ns Transition Time TTHL | VDD = 5V, VIN = VDD or GND 9 +25C : 200 ns Q Output TTLH 40, 11 +125C, 55C | - 270 | ns Maximum Clock Input FCL | VDD =5V, VIN = VDD or GND 9 +25C 2 - MHz Frequency 10,11 425C, 55C | 1.48 | - | MHz NOTES: 1. VDD = 5V, CL = 50pF, Ri = 200K 2. -55C and +125C limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE! MIN MAX | UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND 1,2 -65C, +25C : 5 pA +125C - 150 HA VDD = 10V, VIN = VDD or GND 1,2 -55C, +25C - 10 pA 4125C : 300 HA VDD = 15V, VIN = VDD or GND 1,2 -55C, +25C : 10 pA +125C - 600 HA Output Voltage VOL | VDD = 5V, No Load 1,2 425C, +125C, - 50 mV 55C Output Voltage VOL VDD = 10V, No Load 1,2 +25C, +125C, : 50 mV -55C Output Voltage VOH VDD = 5V, No Load 1,2 425C, +125C, | 4.95 - Vv -55C Output Voltage VOH VDD = 10V, No Load 1,2 +256C, +125C, 9.95 - v -55C. Output Current (Sink) 10L5 | VDD = 5V, VOUT = 0.4V 1,2 +125C 0.36 - mA -55C 0.64 - mA Output Current (Sink) 1OL10 | VDD = 10V, VOUT = 0.5V 1,2 +125C. 0.9 - mA -55C 1.6 - mA Output Current (Sink) JOL15 | VDD = 15V, VOUT = 1.5V 1,2 +125C 2.4 - mA -55C 4.2 - mA Output Current (Source) lOH5A_ | VOD = 5V, VOUT = 4.6V 1,2 +125C. - 0.36 mA -55C - -0.64 mA 7-800Specifications CD4029BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE| MIN MAX | UNITS Output Current (Source) 1OH5B | VDD = 5V, VOUT = 2.5V 1,2 +125C - -1.15 mA -65C : -2.0 mA Output Current (Source) JOH10 [| VDD = 10V, VOUT = 9.5V 1,2 +125C - 0.9 mA -55C - -2.6 mA Output Current (Source) 1OH15 [VDD =15V, VOUT = 13.5V 1,2 +125C - -2.4 mA -55C - 4.2 mA Input Voltage Low VIL VDD = 10V, VOH > SV, VOL < 1V 1,2 +25C, +125C, - 3 Vv -55C Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1,2 +25C, +125C, 7 - Vv -55C Propagation Delay TPHL1 | VDD = 10V 1,2,3 +25C : 240 ns Q Output TPLHI [Vp = 15V 1,2,3 425C : 180 | ns Propagation Delay TPHL2 | VDD = 10V 1,2,3 425C - 260 ns Carry Output TPLH2 [yop = 15V 1,2,3 +25C : 190 | ns Propagation Delay TPHL3 | VDD = 10V 1,2,3 +25C - 200 ns Presat Enable To Q TPLH3 VDD = 15V 1,2,3 425C . 160 ns Propagation Delay TPHL4 | VOD =10V 1,2,3 +25C - 290 ns pu et Enabla To Gamy- | TPLH4 Finp = tev 12,3 425C - 210 | ns Propagation Delay TPHL5 | VDD = 10V 1,2,3 +25C - 140 ns Carty InTo Carry Out | TPLHS Wop a yev 12,3 +25C : 100 | ns Transition Time TTHL [VOD =10V 1,2,3 +25C - 100 ns TTLH [yop = 15v 12,3 +25C ; 80 ns Maximum Clock Input FCL VDD = 10V 1,2,3 +25C 4 - MHz Frequency VDD = 15V 1,2,3 425C 5.5 : MHz 2 Minimum Data Setup Ts |vop-=6v 1,2,3 425C , 340 ns o No 4 VDD = 10V 12,3 +25C : 140 | ns VDD = 15V 1,2,3 +25C - 100 ns Clock Rise And Fall Time} TRCL | VDD =5V 1,2,3 +25C : 15 ys Note 5 TFCL [yop = 10v 12,3 425C : 15 us VDD = 15V 1,2,3 +26C - 15 ps Minimum Clock Pulse Tw VDD = 5V 1,2,3 +25C - 180 ns Width VOD = 10V 1,2,3 +25C - 90 ns VOD = 15V 1,2,3 +25C - 60 ns Minimum Carry In Setup TS VDD = 5V 1,2,3 +25C - 200 ns Noe 6 VDD = 10V 1,2,3 +25C . 70 ns VDD = 15V 1,2,3 +25C - 60 ns Minimum Carry Input TH VDD = 5V 1,2,3 +25C : 50 ns Now .~ VDD = 10V 1,2,3 +25C - 30 ns VDD = 15V 1,2,3 +25C - 25 ns Minimum Preset Enable TREM |VOD=5V 1,2,3 425C - 200 ns Nomoval Time VDD = 10V 12,3 +25C ; 110 | ns VDD = 15V 1,2,3 +25C - 80 ns 7-801Specifications CD4029BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE| MIN MAX UNITS Minimum Preset Enable TW VOD = 5V 1,2,3 425C - 130 ns Pulse Width VDD = 10V 1,2,3 +25C. - 70 ns VDD = 15V 1,2,3 +25C - 50 ns Input Capacitance CIN | Any Input 1,2 +25C - 7.8 pF NOTES: : 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on Initial design release and upon design changes which would affect these characteristics. 3. CL = SOpF, RL = 200K, Input TR, TF < 20ns. . From Up/Down, Binary/Decode, Carry in, or Preset Enable Control Inputs to Clock Edge. 5. If more than one unit is cascaded in the parallel clocked application, t CL should be made s the sum of the fixed propagation delay at 15pF and the transition time of the carry output driving stage for the estimated capacitive load. This measurement was made with a de- coupling capacitor (>1pF) between VDD and VSS. 6. From Carry in to Clock Edge. > TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS UMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE} MIN MAX | UNITS Supply Current DD VDD = 20V, VIN = VDD or GND 1,4 +25C - 25 pA N Threshold Voitage VNTH | VDD = 10V, ISS = -10pA 1,4 425C. 2.8 0.2 v N Threshold Voltage AVTN [VDD = 10V, ISS = -10pA 1,4 425C - +1 Vv Delta P Threshold Voltage VTP VSS = OV, IDD = 10pA 1,4 +25C. 0.2 2.8 v P Threshold Voltage AVTP [VSS =OV, IDD = 10HA 1,4 +25C - +1 Vv Delta Functional F VDD = 18V, VIN VDD or GND 1 +25C VOH > | VOL < v VOD = 3V, VIN = VOD or GND vob/2 | vbD/2 Propagation Delay Time TPHL | VDD=5V 1,2,3,4 +25C - 1.35 x ns TPLH +25C Limit NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns 3. See Tabla 2 for +25C limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 toD t 1.0pA Output Current (Sink) 1OL5 + 20% x Pre-Test Reading Output Current (Source) lOH5SA + 20% x Pre-Test Reading 7-802Specifications CD4029BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Bum-in) 100% 5004 1,7,9 IDD, [OLS, IOHSA Interim Test 1 (Post Burn-in) 100% 5004 1,7,9 IDD, 1OL5, IOH5A Interim Test 2 (Post Burn-in) 100% 5004 1,7,9 DD, IOLS, IOH5A PDA (Note 1) 100% 5004 1,7, 9, Deltas interim Test 3 (Post Burn-in) 100% 5004 1,7,9 {DD, IOL5, IOH5A PDA (Note 1) 100% 5004 1,7, 9, Deltas Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group 8 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11 Subgroup B-6 Sample 5005 1,7,9 Group D Sample 5005 1, 2,3, BA, 8B, 9 Subgroups 1,23 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MiL-STD-883 TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE4RRAD POST-IRRAD PRE-RRAD POST-IRRAD Group E Subgroup 2 5005 1,7,9 Table 4 1,9 Table 4 TABLE 8. SURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND voD 9V + -0.5V S0kHz 25kHz StaticBurn-Ini | 2,6,7,11,14 ]1,3-5, 8-10, 12, 16 Note 1 13, 15 Static Burn-in2 2, 6, 7, 11, 14 8 1,3-5,9, 10, 12, Note 1 13, 15, 16 Dynamic Bum- - 1,3-5, 8, 12,13 9, 10, 16 2,6, 7, 11, 14 15 - In Note 1 Irradiation 2, 6, 7, 11, 14 8 1,3- 5,9, 10, 12, Note 2 13, 15, 16 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K + 5%, VDD = 18V + 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K + 5%; Group E, Subgroup 2, sample size is 4 dica/wafer, 0 failures, VDD = 10V + 0.5V 7-803 o o o 4CD4029BMS L aHNSt ic 31 ad TT @1eD 1,U0g = X N|/oO;oTx] tt x] 7 uoNISUBIL 49019 SOd ye J9JUNOD BoURApY 0 (31avN3 49079) UONISUBLL 49019 SOd (1D) NI AWD ye eoueapy 16]UN0D ON 1 Nfo;orx] +t fey NL wet ON 0 (ad) uj wer L equug yeseld ofepriyot.x x junog uMog 0 (ain) junoo dn t NMOO/dN ofoyxirfof N junoy epeseq 0 (ara) qunog Areuig t og0/NIG t}ofolo|x x NOLLOV GAR LNdNt o| ofr | ad] al | 19079 21907 IOULNOD a1av. NOLLONNA 37@V1 HLNYL vO 0 Logic Diagram SSA MYHOMLIN NOLLDSLOWd SOWD AG G3L93L0ud SUV SLNdNI TIV, aaa WI0TD NMOGdN Z18VN3 9079 * NIAWYYD * J18VN3 43aS3ud * 30V930 /AMVNIG 7-804CD4029BMS Typical Performance Characteristics AMBIENT T= a 8 & 8 OUTPUT LOW (SINK) CURRENT (I0L) (mA) 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERSTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (Ta) = 425C GATE-TO-SOURCE VOLTAGE (VGS) = 5V a ' a o e & & OUTPUT HIGH (SOURCE) CURRENT (OH) (mA) ay a FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS ! q t q AMBIENT TEMPERATURE (T,) = 425C w 8 SUPPLY VOLTAGE (VDD) = 5V & 7 any 15V 8 \ TRANSITION TIME (tTHL, tTLH) (na) g g 0 20 40 6o 8 8680)s+100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE OUTPUT LOW (SINK) CURRENT (IOL} (mA) 3 PROPAGATION DELAY TIME (tPHL, tPLH) (ns) wn 8 ~ a 3 a ~ on n a BV 5 10 16 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 15 -10 s 9 AMBIENT TEMPERATURE (Ta) = 425C GATE-TO-SOURCE VOLTAGE (VGS) = -6V an a a wn 3 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT (T,) = 8 SUPPLY VOLTAGE (VDD) = 5V 8 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (Q OUTPUT) 7-805 2 S aCD4029BMS Typical Performance Characteristics (continued) ' E 7 AMBIENT TEMPERATURE (Tq) = 425C ? 300 |. SUPPLY VOLTAGE (VDD) = 5V ee z eseenemy po w -_ = > 200 > Z a z 10 wo 15 = 3 x a 5 20 rr) 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CARRY OUTPUT) 105 8 4 s 2 = 10s 2 4 3 2 F 10 9 g 4 G4 3 107g ww Ci = SOpF wane OL <15pF 2 a= 2 6 2 46 2 107 108 104 CLOCKFREQUENCY (fCL) (kHz) FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY 10 2 468 2 486 4 46s 10 Timing Diagrams CLOCK (CL) CABRY IN __ (CL ENABLE) UP/DOWN BINARY/ DECADE PRESET ENABLE J J2 J3 J4 Qi Q2 Q3 Q4 CARRY OUT COUNT (5 56/7/98: 9 '10:19:12:19'14:15'9'6:7!6:5:4!3/2!1:0:0: 15 The CD4029BMS CLOCK and UP/DOWN inputs are used directly in most applications. In applications where CLOCK UP and CLOCK DOWN inputs are provided, conversion to the CD4029BMS CLOCK and UP/DOWN inputs can easily be realized by use of the circuit in Figure 11. CD4029BMS changes count on positive transitions of CLOCK UP or CLOCK DOWN inputs. For the gate configu- ration in Figure 12, when counting up the CLOCK DOWN input must be maintained high and conversely when count- ing down the CLOCK UP input must be maintained high. CLOCK UP"; 1004011 QUAD 2 INPUT NAND GATE FIGURE 11. CONVERSION OF CLOCK UP, CLOCK DOWN INPUT SIGNALS TO CLOCK AND UP/DOWN INPUT SIGNALSCD4029BMS Timing Diagrams (Continued) clock (CL) LUAU UL CARRY IN ___ (CL ENABLE) UP/DOWN BINARY/ DECADE PRESET ENABLE J1 J2 J3 J4 Q1 Q2 Q3 a4 CARRY OUT COUNT O01: 25S 4ESLSI7 SVB T GIS Mi Si 2ipiaioisisi7 FIGURE 12. TIMING DIAGRAM-DECADE MODE PARALLEL CLOCKING UP/DOWN > > PRESET ENABLE Lidl bid aoe UPD PE J1 J2 J3 J4 UPD PE J1 U2 3 Js UP/D PE J1 J2 J3 J * a to a co Ga to o cy cpsozs = 00 a cpsoza = GO. a cpsoz9 = CO P 3 BD CL Qt G2 Q3 O64 B/D CL Qt a2 a3 a4 B/D CL 1 @2 G3 a4 a Jedd $id) Jedd CLOCK > . BINARY/ y . DECADE *CARRY OUT LINES AT THE 2ND, 3AD, ETC, STAGES MAY HAVE A NEG- ATIVE-GOING GLITCH PULSE RESULTING FROM DIFFERENTIAL DELAYS OF DIFFERENT CD4029BMS ICS. THESE NEGATIVE GOING GLITCHES DO NOT AFFECT PROPER CD4029BMS OPERATION. HOW- EVER, IF THE CARAY OUT SIGNALS ARE USED TO TRIGGER OTHER EDGE-SENSITIVE LOGIC DEVICES, SUCH AS FF'S OR COUNTERS, THE CARRY OUT SIGNALS SHOULD BE GATED WITH THE CLOCK SIGNAL USING A 24NPUT OR GATE SUCH AS CD4071BMS. FIGURE 13. CASCADING COUNTER PACKAGES 7-807CD4029BMS Timing Diagrams (Continued) RIPPLE CLOCKING UP/DOWN > > PRESET 5 > ENABLE UP/D PE J1 J2 J3 u4 UP/D PE J1 J2 J3 ua UP/D PE Jt J2 J3 J rie cD4029 [ore) re cD4029 cs ce cD4029 cS p BO CL Qi a2 a3 a B/D CL Q1 G2 03 a4 BD CL Qt 2 03 a4 clock 1/4 CD40718 1/4 6040718 BINARY/ > > DECADE RIPPLE CLOCKING MODE: THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK INPUT TO THE FARST COUNTING STAGE MUST BE HIGH. FOR CASCADING COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT MODE, THE OR GATES ARE NOT REQUIRED BETWEEN STAGES, AND CO IS CON- NECTED DIRECTLY TO THE CL INPUT OF THE NEXT STAGE WITH Cl GROUNDED, FIGURE 13. CASCADING COUNTER PACKAGES (Continued) Chip Dimensions and Pad Layout Pe &4-92 {2.134-2 3361 i : 7 AWA san LS ll 7 i o ae 10.102-0 250) 108-3 I 12.667- 2.8701 Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10 inch) METALLIZATION: Thickness: 11kA ~ 14kA, AL. PASSIVATION: 10.4kA- 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-808