Tiny 16-/14-/12-Bit I2C nanoDAC+, with
±2 LSB INL (16-Bit) and 2 ppm/°C Reference
Data Sheet
AD5693R/AD5692R/AD5691R/AD5693
Rev. D Document Feedback
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Technical Support www.analog.com
FEATURES
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): ±2 LSB maximum at 16 bits
AD5693R/AD5692R/AD5691R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5693
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): ±0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05 % of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
1.8 V VLOGIC compatible
Wide operating temperature range: −40°C to +105°C
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
Optical modules
GENERAL DESCRIPTION
The AD5693R/AD5692R/AD5691R/AD5693, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage output DACs. The devices, except the AD5693,
include an enabled by default internal 2.5 V reference, offering
2 ppm/°C drift. The output span can be programmed to be 0 V to
VREF or 0 V to 2 × VREF. All devices operate from a single 2.7 V to
5.5 V supply and are guaranteed monotonic by design. The
devices are available in a 2.00 mm × 2.00 mm, 8-lead LFCSP or
a 10-lead MSOP.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The AD5693R/AD5692R/
AD5691R/AD5693 contain a power-down mode that reduces the
current consumption of the device to 2 µA (maximum) at 5 V and
provides software selectable output loads.
The AD5693R/AD5692R/AD5691R/AD5693 use an I2C
interface. Some device options also include an asynchronous
RESET pin and a VLOGIC pin, allowing 1.8 V compatibility.
FUNCTIONAL BLOCK DIAGRAM
AD5693R/
AD5692R/
AD5691R
V
REF
GND
LDAC
REF
V
DD
V
LOGIC
POWER-DOWN
CONTROL LOGIC
DAC
REGISTER
POWER-ON
RESET 2.5V
REF
OUTPUT
BUFFER
16-/14-/12-BIT
DAC
INPUT
CONTROL LOGIC
V
OUT
SCL
SDA
RESET
A0
RESISTOR
NETWORK
12077-001
Figure 1. MSOP
12077-002
AD5693R/
AD5692R/
AD5691R/
AD5693
V
REF
GND
REF
V
DD
LDAC OR V
LOGIC
OR RESET
1
POWER-DOWN
CONTROL LOGIC
DAC
REGISTER
POWER-ON
RESET 2.5V REF
2
OUTPUT
BUFFER
16-/14-/12-BIT
DAC
INPUT
CONTROL LOGIC
V
OUT
SCLSDA A0
RESISTOR
NETWORK
1
NOT ALL PINS AVAILABLE IN ALL 8-LEAD LFCSP MODELS.
2
NOT AVAILABLE IN THE AD5693.
Figure 2. LFCSP
Table 1. Related Devices
Interface
Reference
12-Bit
SPI
Internal
AD5681R
External
I2C Internal AD5693R AD5692R AD5691R
External AD5693
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL): ±2 LSB maximum
(AD5693R/AD5693, 16-bit).
2. Low drift, 2.5 V on-chip reference: 2 ppm/°C typical and
5 ppm/°C maximum temperature coefficient.
3. 2 mm × 2 mm, 8-lead LFCSP and 10-lead MSOP.
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Applicat ions ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 5
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Digital-to-Analog Converter .................................................... 19
Transfer Function ....................................................................... 19
DAC Architecture ....................................................................... 19
Serial Interface ................................................................................ 20
I2C Serial Data Interface ............................................................ 20
I2C Address .................................................................................. 20
Write Operation.......................................................................... 20
Read Operation........................................................................... 22
Load DAC (Hardware LDAC Pin) ........................................... 23
Hardware RESET ........................................................................ 23
Thermal Hysteresis .................................................................... 23
Power-Up Sequence ................................................................... 23
Recommended Regulator .......................................................... 24
Layout Guidelines....................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
2/2017—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changes to Specifications Section .................................................. 3
Changes to VLOGIC Parameter, Table 2 ............................................ 4
Changes to AC Characteristics Section and Timing
Characteristics Section ..................................................................... 5
Changes to Table 5 ............................................................................ 7
Changes to RESET Pin Description, Table 7................................. 8
Changes to RESET Pin Description, Table 10 ............................ 11
Changes to Figure 49 ...................................................................... 22
5/2016—Rev. B to Rev. C
Changed VLOGIC = 1.8 V to 5.5 V to VLOGIC = 1.8 V − 10% to 5 V +
10% .................................................................................. Throughout
Changes to Features Section............................................................ 1
Changes to VLOGIC Parameter, Table 2 ............................................ 4
Changes to Table 7 ............................................................................ 8
Changes to Table 9 .......................................................................... 10
Changes to Terminology Section.................................................. 18
11/2014—Rev. A to Rev. B
Changes to Figure 2 .......................................................................... 1
Changes to Table 8 ............................................................................ 9
Change to Figure 7 ......................................................................... 10
Added Table 9; Renumbered Sequentially .................................. 10
Added Figure 8; Renumbered Sequentially, and Table 10 ......... 11
Added Recommended Regulator Section ................................... 24
Changes to Ordering Guide .......................................................... 26
5/2014—Rev. 0 to Rev. A
Added AD5693 ................................................................... Universal
Changes to Features, General Description, Figure 2, Table 1,
and Product Highlights .................................................................... 1
Added AD5693 Parameter, Table 1 and AD5693 Parameter,
Table 1 ................................................................................................. 3
Changes to Endnote 1, Specifications Section, Table 1 ................ 4
Change to Total Harmonic Distortion, AC Characteristics,
Table 3 and Endnote 2, Table 3 ........................................................ 5
Changes to Endnote 7, Timing Characteristics, Table 4 .............. 5
Change to Pin 9, Description, Table 7 ............................................ 8
Changes to Figure 6 and Table 8 ...................................................... 9
Change to Figure 11 ....................................................................... 10
Change to Figure 18 ....................................................................... 11
Change to the External Reference Section .................................. 17
Change to Figure 46 ....................................................................... 19
Change to Figure 48 ....................................................................... 20
Change to Figure 50 ....................................................................... 21
Changes to Ordering Guide .......................................................... 23
2/2014—Revision 0: Initial Version
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 3 of 26
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V to VDD − 0.2 V, VLOGIC = 1.62 V to 5.5 V, −40°C < TA < +105°C,
unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
1
AD5693R
Resolution 16 Bits
Relative Accuracy (INL)
A Grade ±8 LSB
B Grade
±2
LSB
Gain = 2
±3 LSB Gain = 1
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5692R
Resolution 14 Bits
Relative Accuracy ±4 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5691R
Resolution 12 Bits
Relative Accuracy
A Grade ±2 LSB
B Grade ±1 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5693
Resolution 16 Bits
Relative Accuracy (INL) ±2 LSB Gain = 2
±3 LSB Gain = 1
Differential Nonlinearity
±1
LSB
Guaranteed monotonic by design
Zero Code Error 1.25 mV All 0s loaded to DAC register
Offset Error ±1.5 mV
Full-Scale Error ±0.075 % of FSR All 1s loaded to DAC register
Gain Error ±0.05 % of FSR
Total Unadjusted Error ±0.16 % of FSR Internal reference, gain = 1
±0.14 % of FSR Internal reference, gain = 2
±0.075 % of FSR External reference, gain = 1
±0.06 % of FSR External reference, gain = 2
Zero Code Error Drift ±1 µV/°C
Offset Error Drift ±1 µV/°C
Gain Temperature Coefficient ±1 ppm/°C
DC Power Supply Rejection Ratio 0.2 mV/V DAC code = midscale, VDD = 5 V ±10%
OUTPUT CHARACTERISTICS
Output Voltage Range
0
V
REF
V
Gain = 0
0 2 × VREF V Gain = 1
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
Resistive Load 1 kΩ CL = 0 µF
Load Regulation 10 µV/mA VDD = 5 V, DAC code = midscale, −30 mA ≤ IOUT ≤ +30 mA
10 µV/mA VDD = 3 V, DAC code = midscale, −20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current 20 50 mA
Load Impedance at Rails2 20 Ω
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 4 of 26
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE OUTPUT
Output Voltage 2.4975 2.5025 V
At ambient temperature
Voltage Reference TC3 See the Terminology section
A Grade 5 20 ppm/°C
B Grade
2
5
ppm/°C
Output Impedance 0.05 Ω
Output Voltage Noise 16.5 µV p-p 0.1 Hz to 10 Hz
Output Voltage Noise Density 240 nV/√Hz At ambient temperature, f = 10 kHz, CL = 10 nF
Capacitive Load Stability 5 µF RL = 2 kΩ
Load Regulation Sourcing 50 µV/mA At ambient temperature, VDD ≥ 3 V
Load Regulation Sinking 30 µV/mA At ambient temperature
Output Current Load Capability ±5 mA VDD ≥ 3 V
Line Regulation 80 µV/V At ambient temperature
Thermal Hysteresis 125 ppm First cycle
25 ppm Additional cycles
REFERENCE INPUT
Reference Current 35 µA VREF = VDD = VLOGIC = 5.5 V, gain = 1
57 µA VREF = VDD = VLOGIC = 5.5 V, gain = 2
Reference Input Range
4
V
DD
V
Reference Input Impedance 120 kΩ Gain = 1
60 kΩ Gain = 2
LOGIC INPUTS
IIN, Input Current
±1
µA Per pin
±3 µA SDA and SCL pins
VINL, Input Low Voltage4 0.3 × VDD V
V
INH
, Input High Voltage
4
0.7 × V
DD
V
CIN, Pin Capacitance 2 pF
LOGIC OUTPUTS (SDA)
4
Output Low Voltage, VOL 0.4 V ISINK = 200 μA
Output High Voltage, VOH VDD − 0.4 V ISOURCE = 200 μA
Pin Capacitance 4 pF
POWER REQUIREMENTS
VLOGIC 5 1.62 5.5 V
ILOGIC5 0.25 3 µA VIH = VLOGIC or VIL = GND
VDD 2.7 5.5 V Gain = 1
VREF + 1.5 5.5 V Gain = 2
I
DD 6
V
IH
= V
DD
, V
IL
= GND
Normal Mode7 350 500 µA Internal reference enabled
110 180 µA Internal reference disabled
Power-Down Modes8 2 µA
1 Linearity calculated using a reduced code range: AD5693R/AD5693 (Code 512 to Code 65,535); AD5692R (Code 128 to Code 16,384); AD5691R (Code 32 to Code 4096).
Output unloaded.
2 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output
devices; for example, when sinking 1 mA, the minimum output voltage with 20 Ω, 1 mA generates 20 mV. See Figure 36 for more details.
3 Voltage reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
4 Substitute VLOGIC for VDD if the device includes a VLOGIC pin.
5 The VLOGIC pin is not available on all models.
6 If the VLOGIC pin is not available, IDD = IDD + ILOGIC.
7 Interface inactive. DAC active. DAC output unloaded.
8 DAC powered down.
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 5 of 26
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V to VDD − 0.2 V, VLOGIC = 1.62 V to 5.5 V, −40°C < TA < +105°C,
typical at 25°C, unless otherwise noted.
Table 3.
Parameter Typ Max Unit Conditions/Comments
Output Voltage Settling Time1, 2 5 7 µs Gain = 1
Slew Rate 0.7 V/µs
Digital-to-Analog Glitch Impulse1 0.1 nV-s ±1 LSB change around major carry, gain = 2
Digital Feedthrough1 0.1 nV-s
Total Harmonic Distortion1 −80 dB At ambient temperature, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
Output Noise Spectral Density1 300 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 6 µV p-p 0.1 Hz to 10 Hz; internal reference
SNR 90 dB At ambient temperature, bandwidth (BW) = 20 kHz, VDD =5 V, fOUT = 1 kHz
SFDR 83 dB At ambient temperature, BW = 20 kHz, VDD =5 V, fOUT = 1 kHz
SINAD 80 dB At ambient temperature, BW = 20 kHz, VDD =5 V, fOUT = 1 kHz
1 See the Terminology section.
2 For the AD5693R/AD5693, to ±2 LSB. For the AD5692R, to ±1 LSB. For the AD5691R, to ±0.5 LSB
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VLOGIC = 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise noted.
Table 4.
Parameter1 Min Typ Max Unit Description
fSCL2 400 kHz Serial clock frequency
t1 0.6 µs SCL high time, tHIGH
t2 1.3 µs SCL low time, tLOW
t3 100 ns Data setup time, tSU; DAT
t
43
0
0.9
µs
Data hold time, t
HD; DAT
t5 0.6 µs Setup time for a repeated start condition, tSU; STA
t6 0.6 µs Hold time (repeated) start condition, tHD; STA
t7 1.3 µs Bus free time between a stop and a start condition, tBUF
t8 0.6 µs Setup time for a stop condition, tSU; STO
t9 20 300 ns Rise time of SDA signal, tr
t104 20 × (VDD/5.5 V) 300 ns Fall time of SDA signal, tf
t11 20 300 ns Rise time of SCL signal, tr
t124 20 × (VDD/5.5 V) 300 ns Fall time of SCL signal, tf
tSP5 0 50 ns Pulse width of suppressed spike (not shown in Figure 3)
t13 400 ns LDAC falling edge to SCL falling edge
t
14
400
ns
LDAC
pulse width (synchronous mode)
t15 20 ns LDAC pulse width (asynchronous mode)
t16 75 ns RESET pulse width
tREF_POWER_UP6 600 µs Reference power-up (not shown in Figure 3)
tSHUTDOWN7 6 µs Exit shutdown (not shown in Figure 3)
1 Maximum bus capacitance is limited to 400 pF. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the device.
3 The master should add at least 300 ns for the SDA signal (with respect to the VOH (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
4 Substitute VLOGIC for VDD on devices that include a VLOGIC pin.
5 Not applicable for standard mode.
6 Expect the same timing when powering up the device after VDD is equal to 2.7 V.
7 Time to exit power-down to normal mode of AD5693R/AD5692R/AD5691R/AD5693 operation.
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 6 of 26
Timing Diagrams
t
12
t
2
t
1
t
11
t
5
t
6
t
3
t
4
t
7
t
8
t
9
t
10
SDA
START
OR
REPEAT START
CONDITION
REPEAT START
CONDITION
STOP
CONDITION
SCL
12077-003
Figure 3. I2C Serial Interface Timing Diagram
t
13
t
15
t
16
t
14
SDA
LDAC
SYNCHRONOUS
DAC UPDATE
ASYNCHRONOUS
DAC UPDATE
STOP
CONDITION
ACK
SCL
12077-004
RESET
Figure 4. I2C RESET and LDAC Timing
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 7 of 26
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +7 V
VLOGIC to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
VREF to GND −0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
Digital Input Voltage to GND1 −0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
Operating Temperature Range
Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 135°C
Power Dissipation (TJ max − TA)/θJA
1 Substitute VDD with VLOGIC on devices that include a VLOGIC pin.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 6. Thermal Resistance1
Package Type θJA θJC Unit
8-Lead LFCSP 90 25 °C/W
10-Lead MSOP
135
N/A
°C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 8 of 26
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
VLOGIC 2
RESET 3
LDAC 4
GND 5
VOUT
10
VREF
9
SDA
8
SCL
7
A0
6
AD5693R/
AD5691R
TOP VIEW
(No t t o Scale)
12077-005
Figure 5. AD5693R/AD5691R Pin Configuration, 10-Lead MSOP
Table 7. AD5693R/AD5691R Pin Function Descriptions, 10-Lead MSOP
Pin No. Mnemonic Description
1 VDD Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
2 VLOGIC Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple the supply to GND.
3
RESET
Hardware Reset Pin. The
RESET
input is low level sensitive. When
RESET
is low, the device is reset and external
pins are ignored. The input and DAC registers are loaded with zero code value and control register loaded with
default values. Tie this pin to VLOGIC if not used. If this pin is forced low at power-up, the power-on reset (POR)
circuit does not initialize the device correctly until this pin is released.
4 LDAC Load DAC. Transfers the content of the input register to the DAC register. It can be operated in two modes,
asynchronously and synchronously, as shown in Figure 4. This pin can be tied permanently low, and the DAC
updates when new data is written to the input register.
5 GND Ground Reference.
6 A0 Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.
7 SCL Serial Clock Line.
8 SDA Serial Data Input/Output.
9 VREF Reference Input/Output. In the AD5693R/AD5691R, this is a reference output pin by default. It is recommended
to use a 10 nF decoupling capacitor for the internal reference.
10 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 9 of 26
3GND
4A0
1V
DD
2LDAC
6SDA
5SCL
8 V
OUT
7 V
REF
AD5693R/
AD5692R/
AD5691R/
AD5693
TOP VI EW
(No t t o Scale)
NOTES
1. CO NNE CT THE E X P OSED P AD TO GND.
12077-006
Figure 6. AD5693R/AD5692R/AD5691R/AD5693 Pin Configuration, 8-Lead LFCSP, LDAC Option
Table 8. AD5693R/AD5692R/AD5691R/AD5693 Pin Function Descriptions, 8-Lead LFCSP, LDAC Option
Pin No. Mnemonic Description
1
V
DD
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
2 LDAC Load DAC. Transfers the content of the input register to the DAC register. It can be operated in two modes,
asynchronously and synchronously, as shown in Figure 4. This pin can be tied permanently low and the DAC
updates when new data is written to the input register.
3 GND Ground Reference.
4
A0
Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.
5 SCL Serial Clock Line.
6 SDA Serial Data Input/Output.
7 VREF Reference Input/Output. In the AD5693R/AD5692R/AD5691R, this is a reference output pin by default. In the AD5693,
this pin is a reference input only. It is recommended to use a 10 nF decoupling capacitor for the internal reference.
8 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
EPAD Exposed Pad. Connect the exposed pad to GND.
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 10 of 26
3GND
4A0
1V
DD
2V
LOGIC
6SDA
5SCL
8 V
OUT
7 V
REF
AD5693R-1
AD5691R-1
TOP VI EW
(No t t o Scale)
NOTES
1. CO NNE CT THE E X P OSED P AD TO GND.
12077-007
Figure 7. AD5693R-1/AD5691R-1 Pin Configuration, 8-Lead LFCSP, VLOGIC Option
Table 9. AD5693R-1/AD5691R-1 Pin Function Descriptions, 8-Lead LFCSP, VLOGIC Option
Pin No. Mnemonic Description
1 VDD Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
2 VLOGIC Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple the supply to GND.
3 GND Ground Reference.
4 A0 Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.
5 SCL Serial Clock Line.
6 SDA Serial Data Input/Output.
7 VREF Reference Input/Output. In the AD5693R-1/AD5691R-1, this is a reference output pin by default. It is
recommended to use a 10 nF decoupling capacitor for the internal reference.
8 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
EPAD Exposed Pad. Connect the exposed pad to GND.
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 11 of 26
3GND
4A0
1VDD
2RESET
6SDA
5SCL
8 VOUT
7 VREF
AD5693R-2
TOP VIEW
(No t t o Scale)
NOTES
1. CO NNE CT THE E X P OSED P AD TO GND.
12077-107
Figure 8. AD5693R-2 Pin Configuration, 8-Lead LFCSP, RESET Option
Table 10. AD5693R-2 Pin Function Descriptions, 8-Lead LFCSP, RESET Option
Pin No. Mnemonic Description
1
V
DD
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
2 RESET Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external pins
are ignored. The input and DAC registers are loaded with zero code value and the control register is loaded with
default values. Tie this pin to VDD if not used. If this pin is forced low at power-up, the power-on reset (POR) circuit
does not initialize the device correctly until this pin is released.
3 GND Ground Reference.
4 A0 Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.
5 SCL Serial Clock Line.
6 SDA Serial Data Input/Output.
7 VREF Reference Input/Output. In the AD5693R-2, this is a reference output pin by default. It is recommended to use a
10 nF decoupling capacitor for the internal reference.
8 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
EPAD Exposed Pad. Connect the exposed pad to GND.
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 12 of 26
TYPICAL PERFORMANCE CHARACTERISTICS
2
1
0
–1
–2 0
INL (LSB)
CODE 50000 60000 6553540000300002000010000
12077-009
V
DD
= 5V
T
A
= 25° C
V
REF
= 2.5V
Figure 9. AD5693R/AD5693 INL
2
1
0
–1
–2 0
INL (LSB)
CODE 100008000600040002000 12000 14000 16383
12077-010
VDD = 5V
TA = 25° C
VREF = 2.5V
Figure 10. AD5692R INL
2.0
1.0
0
–1.0
1.5
0.5
–0.5
–1.5
–2.0 0500 1000 1500 2000 2500 3000 3500 4000
INL (LSB)
CODE
12077-011
V
DD
= 5V
T
A
= 25° C
V
REF
= 2.5V
Figure 11. AD5691R INL
2
1
0
–1
–2
DNL ( LSB)
CODE
12077-012
050000 60000 65535
4000030000
20000
10000
V
DD
= 5V
T
A
= 25° C
V
REF
= 2.5V
Figure 12. AD5693R/AD5693 DNL
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
DNL ( LSB)
CODE
12077-013
0100008000600040002000 12000 14000 16383
V
DD
= 5V
T
A
= 25° C
V
REF
= 2.5V
Figure 13. AD5692R DNL
1.0
0.6
0
–0.6
0.8
0.2
–0.4
0.4
–0.2
–0.8
–1.0 0500 1000 1500 2000 2500 3000 3500 4000
DNL ( LSB)
CODE
12077-014
V
DD
= 5V
T
A
= 25° C
V
REF
= 2.5V
Figure 14. AD5691R DNL
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 13 of 26
1.2
–0.2
0
0.2
0.4
0.6
0.8
1.0
–40 –20 020 40 60 80 105
INL AND DNL ERROR (L S B)
TEMPERATURE (°C)
U1_DNL_INT_REF
U3_DNL_INT_REF
U2_DNL_EXT_REF
U1_INL_INT_REF
U3_INL_INT_REF
U2_INL_EXT_REF
U2_DNL_INT_REF
U1_DNL_EXT_REF
U3_DNL_EXT_REF
U2_INL_INT_REF
U1_INL_EXT_REF
U3_INL_EXT_REF
12077-015
V
DD
= 5V
V
REF
= 2.5V
Figure 15. INL and DNL Error vs. Temperature (AD5693R/AD5693)
1.4
1.2
–0.2
0
0.2
0.4
0.6
0.8
1.0
2.70 3.30 3.75 4.25 4.75 5.25
INL AND DNL ERROR (L S B)
V
DD
(V)
U1_DNL_INT_REF
U3_DNL_INT_REF
U2_DNL_EXT_REF
U1_INL_INT_REF
U3_INL_INT_REF
U2_INL_EXT_REF
U2_DNL_INT_REF
U1_DNL_EXT_REF
U3_DNL_EXT_REF
U2_INL_INT_REF
U1_INL_EXT_REF
U3_INL_EXT_REF
12077-016
T
A
= 25° C
Figure 16. INL and DNL Error vs. VDD
0.06
–0.04
–0.02
0
0.02
0.04
–40 040 80
TUE ( % FSR)
TEMPERATURE (°C)
U1_EXT_REF
U2_EXT_REF
U3_EXT_REF
U1_INT_REF
U2_INT_REF
U3_INT_REF
V
DD
= 5V
GAI N = 1
V
REF
= 2.5V
12077-017
Figure 17. TUE vs. Temperature
1.4
1.2
–0.2
0
0.2
0.4
0.6
0.8
1.0
2345
INL AND DNL ERROR (L S B)
V
REF
(V)
U1_DNL
U3_DNL
U2_INL
U2_DNL
U1_INL
U3_INL
V
DD
= 5V
T
A
= 25° C
12077-018
Figure 18. INL and DNL Error vs. VREF (AD5693R/AD5693)
12077-019
0
0
010000
2500
50000 12000
3000
60000 16383
4095
65535
8000
2000
40000
6000
1500
30000
4000
1000
20000
2000
500
10000
0.02
–0.04
–0.03
–0.02
–0.01
0
0.01
TUE ( % FSR)
CODE
(AD5692R)
(AD5691R)
(AD5693R/AD5693)
Figure 19. TUE vs. Code
0.04
–0.02
–0.01
0
0.01
0.02
0.03
2.70 3.30 3.75 4.25 4.75 5.25
TUE ( % FSR)
V
DD
(V)
U1_INT_REF
U2_INT_REF
U3_INT_REF
U1_EXT_REF
U2_EXT_REF
U3_EXT_REF
T
A
= 25° C
GAIN = 1
V
REF
= 2.5V
12077-020
Figure 20. TUE vs. VDD
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 14 of 26
0.03
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
–40 040 80
ERROR (% FSR)
TEMPERATURE (°C)
U1_INT_REF
U2_INT_REF
U3_INT_REF
U1_EXT_REF
U2_EXT_REF
U3_EXT_REF
V
DD
= 5V
GAI N = 1
V
REF
= 2.5V
12077-021
Figure 21. Gain Error and Full-Scale Error vs. Temperature
350
0
50
100
150
200
250
300
ERROR (µV)
TEMPERATURE (°C) 105
80604020
0–20–40
U1_INT_REF
U2_INT_REF
U3_INT_REF
U1_EXT_REF
U2_EXT_REF
U3_EXT_REF
VDD = 5V
GAI N = 1
VREF = 2.5V
12077-022
Figure 22. Zero Code Error and Offset Error vs. Temperature
V
REF
(V)
TEMPERATURE (°C)6010
–40
2.495
2.497
2.499
2.501
2.503
2.505 U1
U2
U3
12077-023
V
DD
= 5V
Figure 23. Internal Reference Voltage vs. Temperature (Grade B)
2.70 3.30 3.75 4.25 4.75 5.25 5.50
ERROR (% FSR)
V
DD
(V)
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
U1_INT_REF
U2_INT_REF
U3_INT_REF
U1_EXT_REF
U2_EXT_REF
U3_EXT_REF
T
A
= 25° C
GAIN = 1
V
REF
= 2.5V
12077-024
Figure 24. Gain Error and Full-Scale Error vs. VDD
2.70 3.30 3.75 4.25 4.75 5.25 5.50
ERROR (µV)
V
DD
(V)
0
500
400
300
200
100
U1_INT_REF
U2_INT_REF
U3_INT_REF
U1_EXT_REF
U2_EXT_REF
U3_EXT_REF
12077-025
T
A
= 25° C
GAIN = 1
V
REF
= 2.5V
Figure 25. Zero Code Error and Offset Error vs. VDD
NUMBER OF HI TS
V
REF
(V)
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.50001
2.50004
2.50007
2.50010
2.50013
2.50016
2.50019
2.50022
2.50025
2.50028
2.50031
2.50034
2.50037
2.50040
2.50043
2.50046
2.50049
2.50052
2.50055
2.50058
2.50061
2.50064
2.50067
2.50070
2.50073
2.50076
2.50079
2.50082
2.50085
2.50088
2.50091
2.50094
2.50097
2.50100
V
DD
= 5V
T
A
= 25° C
GAI N = 1
12077-026
Figure 26. Reference Output Spread
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 15 of 26
2.5 5.54.53.5
V
REF
(V)
V
DD
(V)
2.49980
2.49985
2.49990
2.49995
2.50000
2.50005
2.50010
2.50015
D11
D12
D13
12077-027
T
A
= 25°C
Figure 27. Internal Reference Voltage vs. VDD
CH1 10µV M1.00s A CH1 2.00µV
1
T
12077-028
T
A
= 25°C
V
DD
= 5V
Figure 28. Internal Reference Noise, 0.1 Hz to 10 Hz
CH1 10µV M1.00s A CH1 2.00µV
1
T
12077-029
T
A
= 25°C
V
DD
= 5V
Figure 29. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference On
–0.005 –0.003 –0.001 0.001 0.003 0.005
VREF (V)
LOAD CURRENT (A)
2.5003
2.5004
2.5005
2.5006
2.5007
2.5008
2.5009 5.5V
5.0V
3.0V
2.7V
12077-030
TA = 25°C
Figure 30. Internal Reference Voltage vs. Load Current
10 100 1k 10k 100k 1M
INTERNAL REFERENCE NSD (nV/√Hz)
FREQUENCY (Hz)
0
200
400
600
800
1000
1200
1400
1600
1800 V
DD
= 5V
T
A
= 25°C
12077-031
Figure 31. Internal Reference Noise Spectral Density vs. Frequency
CH1 10µV M1.00s A CH1 2.00µV
1
T
12077-032
T
A
= 25°C
V
DD
= 5V
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 16 of 26
10 100 1k 10k 100k 1M
NSD (nV/√Hz)
FRE Q UE NCY ( Hz )
0
200
400
600
800
1000
1200 V
DD
= 5V
T
A
= 25° C
GAI N = 1
FULL-SCALE
MIDSCALE
ZEROSCALE
12077-033
Figure 33. Noise Spectral Density vs. Frequency, Gain = 1
–50 050
VOUT (V)
LOAD CURRENT ( mA)
–1
0
6
5
4
3
2
1
VDD = 5V
TA = 25° C
GAI N = 1
0x4000
0xC000
0x0000
0x8000
0xFFFF
12077-034
Figure 34. Source and Sink Capability, Gain = 1
500
450
400
350
300
250
200
150
100
50
0–40 –20 020 40 60 80 105
I
DD
(µA)
TEMPERATURE (°C)
ZS _I NT_REF _GAIN = 1
FS _EX T_REF _GAIN = 2
FS _I NT_REF _GAIN = 2
ZS _I NT_REF _GAIN = 2
FS _I NT_REF _GAIN = 1
FS _EX T_REF _GAIN = 1
12077-035
V
DD
= 5V
Figure 35. IDD vs. Temperature
1.4
1.0
0.6
0.2
–0.2
–0.6
–1.0
–1.4 00.01 0.02 0.03
ΔVOUT (V)
LOAD CURRENT ( A)
SINKING, VDD = 3V
SOURCING, VDD = 5V
SINKING, VDD = 5V
SOURCING, VDD = 3V
12077-036
TA = 25° C
Figure 36. Headroom/Footroom vs. Load Current
–50 050
V
OUT
(V)
LOAD CURRENT ( mA)
–2
–1
0
7
6
5
4
3
2
1
V
DD
= 5V
T
A
= 25° C
GAI N = 2
0x4000
0xC000
0x0000
0x8000
0xFFFF
12077-037
Figure 37. Source and Sink Capability, Gain = 2
0 7654321
V
OUT
(V)
TIME (µs)
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
GAI N = 2
GAI N = 1 V
DD
= 5V
T
A
= 25° C
REF ERE NCE = 2.5V
CODE = 0x7FFF TO 0x8000
12077-038
Figure 38. Digital-to-Analog Glitch Impulse
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 17 of 26
00.01 0.02
VOUT (V)
TIME (ms)
0
0.5
1.0
1.5
2.0
2.5
VDD = 5V
TA = 25° C
GAI N = 1
RL = 2kΩ
INTERNAL RE FERENCE = 2.5V
0nF
0.2nF
1nF
4.7nF
10nF
12077-039
Figure 39. Capacitive Load vs. Settling Time, Gain = 1
010 20515
TOTAL HARMONIC DISTORTION (dBV)
FRE Q UE NCY ( kHz )
–180
–130
–80
–30
20 V
DD
= 5V
T
A
= 25° C
INTERNAL RE FERENCE = 2.5V
12077-040
Figure 40. Total Harmonic Distortion at 1 kHz
0 4 8
2 63 71 5
V
DD
(V)
V
OUT
(V)
TIME (ms)
–1
6
5
4
3
2
1
0
–0.01
0.06
0.05
0.04
0.03
0.02
0.01
0
V
DD
V
OUT
12077-041
Figure 41. Power-On Reset to 0 V
00.01 0.02
VOUT (V)
TIME (ms)
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VDD = 5V
TA = 25° C
GAI N = 2
RL = 2kΩ
INTERNAL RE FERENCE = 2.5V
0nF
0.2nF
1nF
4.7nF
10nF
12077-042
Figure 42. Capacitive Load vs. Settling Time, Gain = 2
1k 10k 100k 10M1M
BANDWIDTH (dB)
FRE Q UE NCY ( Hz )
–80
–10
–20
–30
–40
–50
–60
–70
0
VDD = 5V
TA = 25° C
VOUT = MI DS CALE
EXT E RNAL REF E RE NCE = 2.5V, ±0.1V p - p
GAI N = 2
GAI N = 1
12077-043
Figure 43. Multiplying Bandwidth, External Reference = 2.5 V, ±0.1 V p-p,
10 kHz to 10 MHz
–5 0 5 15
SYNC
10
V
OUT
(V)
TIME (µs)
0
2
1
3
12077-044
MI DS CALE, GAIN = 2
MI DS CALE, GAIN = 1
V
DD
= 5V
T
A
= 25° C
Figure 44. Exiting Power-Down to Midscale
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 18 of 26
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. For typical INL vs. code plots, see Figure 9, Figure 10,
and Figure 11.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design. For
typical DNL vs. code plots, see Figure 12, Figure 13, and Figure 14.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
is 0 V. The zero code error is always positive in the AD5693R/
AD5692R/AD5691R/AD5693 because the output of the DAC
cannot go below 0 V due to a combination of the offset errors in
the DAC and the output amplifier. Zero code error is expressed
in m V. For plots of zero code error, see in Figure 22 and Figure 25.
Full-Scale Error
Full-scale error is a measurement of the output error when
full-scale code (0xFFFF) is loaded to the DAC register. Ideally,
the output is VREF − 1 LSB or |2 × VREF| − 1 LSB. Full-scale error is
expressed in percent of full-scale range. For plots of full-scale error
vs. temperature, see Figure 21 and Figure 24.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Zero Code Error Drift
Zero code error drift is a measurement of the change in zero
code error with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in gain
error with changes in temperature. It is expressed in ppm of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5693R with
Code 512 loaded in the DAC register (Code 256 for the AD5692R
and Code 128 for the AD5693R/AD5693). It can be negative or
positive.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by ±10%.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000)
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Noise Spectral Density
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC to
midscale and measuring noise at the output. It is measured in
nV/√Hz. For plots of noise spectral density, see Figure 29,
Figure 32, and Figure 33. The noise spectral density for the
reference is shown in Figure 28 and Figure 31.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of these finite bandwidths. A
sine wave on the reference (with full-scale code loaded to the DAC)
appears on the output. The multiplying bandwidth is the frequency
at which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and THD is a measurement of the harmonics
present on the DAC output. It is measured in dB.
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given tempera-
ture range expressed in ppm/°C as follows:
6
10×
×
−
=TempRangeV
VV
TC
REFnom
REFminREFmax
where:
VREFmax is the maximum reference output measured over the
total temperature range.
VREFmin is the minimum reference output measured over the total
temperature range.
VREFnom is the nominal reference output voltage, 2.5 V.
TempRange is the specified temperature range, −40°C to +105°C.
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 19 of 26
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5693R/AD5692R/AD5691R/AD5693 are single 16-bit,
14-bit, and 12-bit, serial input, voltage output DACs with a 2.5 V
internal reference. The devices operate from supply voltages of 2.7 V
to 5.5 V. Data is written to the AD5693R/AD5692R/AD5691R/
AD5693 in a 24-bit word format via an I2C serial interface.
The AD5693R/AD5692R/AD5691R/AD5693 incorporate a
power-on reset circuit that ensures that the DAC output powers up
to zero scale. The devices also have a software power-down mode
that reduces the current consumption to 2 µA maximum.
TRANSFER FUNCTION
The internal reference is on by default. The input coding to the
DAC is straight binary. The ideal output voltage is given by the
following equations:
For the AD5693R/AD5693,
VOUT(D) = Gain × VREF ×
536,65
D
For the AD5692R,
VOUT(D) = Gain × VREF ×
384,16
D
For the AD5691R,
VOUT(D) = Gain × VREF ×
4096
D
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
Gain is the gain of the output amplifier and it is set to ×1 by
default. The gain can also be set to ×2 using the gain bit in the
control register.
DAC ARCHITECTURE
The AD5693R/AD5692R/AD5691R/AD5693 implement a
segmented string DAC architecture with an internal output buffer.
Figure 45 shows the internal block diagram.
INPUT
REGISTER DAC
REGISTER
2.5V
REF
RESISTOR
STRING
REF (+)
REF ( –)
GND
VOUT
VREF
12077-045
Figure 45. DAC Channel Architecture Block Diagram
The simplified segmented resistor string DAC structure is
shown in Figure 46. The code loaded to the DAC register
determines the switch on the string that is connected to the
output buffer.
Because each resistance in the string has same value, R, the
string DAC is guaranteed monotonic.
R
R
R
R
RTO OUTPUT
BUFFER
12077-046
V
REF
Figure 46. Simplified Resistor String Structure
Internal Reference
The AD5693R/AD5692R/AD5691R on-chip reference is on at
power-up but can be disabled via a write to the control register.
The AD5693R/AD5692R/AD5691R each have a 2.5 V, 2 ppm/°C
reference, giving a full-scale output of 2.5 V or 5 V, depending
on the state of the gain bit.
The internal reference is available at the VREF pin. It is internally
buffered and capable of driving external loads of up to 5 mA.
External Reference
The VREF pin is an input pin in the AD5693. The VREF pin can also
be configured as an input pin on the AD5693R/AD5692R/
AD5691R, allowing the use of an external reference if the
application requires it.
In the AD5693R/AD5692R/AD5691R, the default condition of
the on-chip reference is on at power-up. Before connecting an
external reference to the pin, disable the internal reference by
writing to the REF bit (Bit DB12) in the control register.
Output Buffer
The output buffer is designed as an input/output rail-to-rail
buffer, which gives a maximum output voltage range of up to
VDD. The gain bit sets the segmented string DAC gain to ×1 or
×2, as shown in Table 14.
The output buffer voltage is determined by VREF, the gain bit,
and the offset and gain errors.
The output buffer can drive a 10 nF capacitance with a 2 kΩ
resistor in parallel, as shown in Figure 39 and Figure 42. If
a higher capacitance load is required, use the snubber method
or a shunt resistor to isolate the load from the output amplifier.
The slew rate is 0.7 V/µs with a ¼ to ¾ scale settling time of 5 µs.
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 20 of 26
SERIAL INTERFACE
The AD5693R/AD5692R/AD5691R/AD5693 have 2-wire, I2C-
compatible serial interfaces. These devices can be connected to
an I2C bus as a slave device, under the control of a master
device. See Figure 3 for a timing diagram of a typical write
sequence.
The AD5693R/AD5692R/AD5691R/AD5693 support standard
(100 kHz) and fast (400 kHz) data transfer modes. Support is
not provided for 10-bit addressing and general call addressing.
I2C SERIAL DATA INTERFACE
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the 9th clock pulse (this is
called the acknowledge (ACK) bit). At this stage, all other
devices on the bus remain idle while the selected device
waits for data to be written to, or read from, its shift
register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, and then high during the 10th
clock pulse to establish a stop condition.
I2C ADDRESS
The AD5693R/AD5692R/AD5691R/AD5693 have a 7-bit slave
address. The five MSBs are 10011. The second last bit set by the
state of the A0 address pin and the LSB is 0. The ability to make
hardwired changes to A0 lets the user have two of these devices
on one bus, as outlined in Table 11. Additionally, the pin can be
updated before starting the transmission, allowing multiple
devices in the same bus by connecting the pin to a GPIO or a
multiplexer.
Table 11. Device Address Selection
A0 Pin Connection A0 I2C Address
GND 0 1001100
VLOGIC (VDD on LFCSP Package) 1 1001110
WRITE OPERATION
When writing to the AD5693R/AD5692R/AD5691R/AD5693,
the user must begin with a start condition followed by an address
byte (R/W = 0), after which the DAC acknowledges that it is pre-
pared to receive data by pulling SDA low, as shown in Figure 47.
The AD5693R/AD5692R/AD5691R/AD5693 require a
command byte that controls various DAC functions (see Table 12)
and two bytes of data for the DAC. All these data bytes are
acknowledged by the AD5693R/AD5692R/AD5691R/AD5693. A
stop condition follows. The write sequence is shown in Figure 47.
SCL
SDA
START BY
MASTER FRAM E 1
SLAVE ADDRESS
FRAM E 3
DATA HIG H BY TE FRAM E 4
DATA LOW BYTE
FRAM E 2
COM M AND BY TE
ACK B Y
AD5693R/AD5692R/AD5691R/AD5693
ACK B Y
AD5693R/AD5692R/AD5691R/AD5693 ACK BY
AD5693R/AD5692R/AD5691R/AD5693 STOP BY
MASTER
ACK B Y
AD5693R/AD5692R/AD5691R/AD5693
SCL
(CONTINUED)
SDA
(CONTINUED)
1
1 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A0
1 1 R/W
9 91
1 9 91
12077-047
Figure 47. I2C Write Operation
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 21 of 26
Table 12. Command Table1
Command Byte Data High Byte Data Low Byte
Operation
DB7 DB6 DB5 DB4 [DB3:DB0] [DB7:DB3] [DB2:DB0] [DB7:DB4] DB3 DB2 DB1 DB0
0
0
0
0
XXXX
XXXXX
XXX
XXXX
X
X
X
NOP: do nothing.
0 0 0 1 XXXX DB15:DB11 DB10:DB8 DB7:DB4 DB32 DB22 DB12, 3 DB02, 3 Write input register.
0 0 1 0 XXXX XXXXX XXX XXXX X X X X Update DAC register (LDAC
software).
0 0 1 1 XXXX DB15:DB11 DB10:DB8 DB7:DB4 DB32 DB22 DB12, 3 DB02, 3 Write DAC and input
registers.
0 1 0 0 XXXX DB15:DB11 000 0000 0 0 0 0 Write control register.
1 X is don’t care.
2 This bit is a don’t care for the AD5691R.
3 This bit is a don’t care for the AD5692R.
Write Input Register
The input register allows the preloading of a new value for the
DAC register. The transfer from the input register to the DAC
register can be triggered by hardware, the LDAC pin, or by
software using Command 2.
If new data is loaded into the DAC register, the DAC register
automatically overwrites the input register.
Update DAC Register
This command transfers the contents of the input register to the
DAC register and, consequently, the VOUT pin is updated. The
data contained in the serial write is ignored.
This operation is equivalent to a software LDAC.
Write DAC Register
This command updates the DAC output on completion of the
write operation. The input register is refreshed automatically
with the DAC register value.
Write Control Register
The control register is used to set the power-down and gain
functions. It is also used to enable/disable the internal reference
and perform a software reset. See Table 13 for the control
register functionality.
Table 13. Control Register Bits
D15 D14 D13 D12 D11
Reset
PD1
PD0
REF
Gain
Gain Bit
The gain bit selects the gain of the output amplifier. Table 14
shows how the output voltage range corresponds to the state of
the gain bit.
Table 14. Gain Bit
Gain Output Voltage Range
0 0 V to VREF (default)
1
0 V to 2 × V
REF
REF Bit
In the AD5693R/AD5692R/AD5691R only, the on-chip reference
is on at power-up by default. This reference can be turned on or
off by setting a software programmable bit, DB12, in the control
register. Table 15 shows how the state of the bit corresponds to
the mode of operation.
To reduce the power consumption, it is recommended to disable
the internal reference if the device is placed in power-down mode.
Table 15. Reference Bit
REF Reference Function
0 Reference enabled (default)
1 Reference disabled
PD0 and PD1 Bits
The AD5693R/AD5692R/AD5691R/AD5693 contain two
separate modes of operation that are accessed by writing to the
control register.
In normal mode, the output buffer is directly connected to the
VOUT pin.
In power-down mode, the output buffer is internally disabled
and the VOUT pin output impedance can be selected to a well
known value, as shown in Table 16.
Table 16. Operation Modes
Operating Mode
PD1
PD0
Normal Mode 0 0
Power-Down Modes
1 kΩ Output Impedance 0 1
100 kΩ Output Impedance 1 0
Three-State Output Impedance 1 1
In power-down mode, the device disables the output buffer but
does not disable the internal reference. To achieve maximum
power savings, it is recommended to disable the internal reference.
Disabling both the internal reference and the output buffer
results in the supply current falling to 2 μA at 5 V.
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 22 of 26
The output stage is shown in Figure 48.
RESISTOR
NETWORK
V
OUT
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
12077-048
Figure 48. Output Stage During Power-Down
The output amplifier is shut down when the power-down mode
is activated. However, unless the internal reference is powered
down (using Bit DB12 in the control register), the bias
generator, reference, and resistor string remain on. The supply
current falls to 2 μA at 5 V. The contents of the DAC register are
unaffected when in power-down mode, and the DAC register can
continue to be updated. The time that is required to exit power-
down is typically 4 µs for VDD = 5 V, or 600 µs if the reference is
disabled.
Reset Bit
The AD5693R/AD5692R/AD5691R/AD5693 control register
contains a software reset bit that resets the DAC to zero-scale and
resets the input, DAC, and control registers to their default values.
A software reset is initiated by setting the RESET bit in the
control register to 1. When the software reset has completed,
the reset bit is cleared to 0 automatically.
READ OPERATION
When reading the input register back from the AD5693R/
AD5692R/AD5691R/AD5693 DACs, the user begins with an
address byte (R/W = 1), after which the DAC acknowledges that
it is prepared to receive data by pulling SDA low. Two bytes of
data containing the contents of the input register are then read
from the DAC, as shown in Figure 49. A NACK condition from
the master followed by a STOP condition completes the read
sequence.
SCL
SDA
START BY
MASTER FRAM E 1
SLAVE ADDRESS
FRAM E 3
DATA HIG H BY TE
FRAM E 2
COM M AND BY TE
ACK B Y
AD5693R/AD5692R/AD5691R/AD5693
NACK BY
MASTER STOP BY
MASTER
ACK B Y MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
1
1 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A01 1 R/W
9 91
1 9
12077-049
Figure 49. I2C Read Operation
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 23 of 26
LOAD DAC (HARDWARE LDAC PIN)
The AD5693R/AD5692R/AD5691R/AD5693 DAC has a double
buffered interface consisting of an input register and a DAC
register. The LDAC pin transfers data from the input register to
the DAC register, and the output is updated.
Synchronous DAC Update
If the LDAC pin is held low while the input register is written,
the DAC register, input register, and output are updated on the
last SCL falling edge before the ACK bit, as shown in Figure 4.
Asynchronous DAC Update
LDAC is held high while data is transmitted to the device. The
DAC output is updated by taking LDAC low after the stop
condition has been generated. The output DAC is updated on
the falling edge of the LDAC pin. If LDAC is pulsed while the
device is accessed, the pulse is ignored.
HARDWARE RESET
RESET is an active low signal that resets the DAC output to zero-
scale and sets the input, DAC, and control registers to their
default values. It is necessary to keep RESET low for 75 ns to
complete the operation. When the RESET signal is returned high,
the output remains at zero scale until a new value is programmed.
While the RESET pin is low, the AD5693R/AD5692R/AD5691R/
AD5693 ignore any new command. If the RESET pin is held
low at power-up, the internal reference is not initialized
correctly until the RESET pin is released.
THERMAL HYSTERESIS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
The thermal hysteresis data is shown in Figure 50. It is measured by
sweeping the temperature from ambient to −40°C, then to +105°C,
and finally returning to ambient. The VREF delta is measured
between the two ambient measurements; the result is shown in
solid lines in Figure 50. The same temperature sweep and
measurements were immediately repeated; the results are
shown in dashed lines in Figure 50.
6
4
5
3
2
1
0
–100 6020–20–60 400–40–80
NUMBER O F HITS
DISTORTION (ppm)
FIRST TEMPERATURE SWEEP
SUBSEQUENT SWEEPS
12077-051
Figure 50. Thermal Hysteresis
POWER-UP SEQUENCE
Because diodes limit the voltage compliance at the digital pins
and analog pins, it is important to power GND first before
applying any voltage to VDD, VOUT, and VLOGIC. Otherwise, the
diode is forward-biased such that VDD is powered uninten-
tionally. The ideal power-up sequence is GND, VDD, VLOGIC,
VREF, followed by the digital inputs.
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 24 of 26
RECOMMENDED REGULATOR
The AD5693R/AD5692R/AD5691R/AD5693 use a 5 V (VDD)
supply as well as a digital logic supply (VLOGIC).
The analog and digital supplies required for the AD5693R/
AD5692R/AD5691R/AD5693 can be generated using Analog
Devices, Inc., low dropout (LDO) regulators such as the ADP7118
and the ADP162, respectively, for analog and digital supplies.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Design the printed circuit board (PCB) on
which the ADCs are mounted such that the AD5693R/AD5692R/
AD5691R/AD5693 lie on the analog plane.
Ensure that the AD5693R/AD5692R/AD5691R/AD5693 have
ample supply bypassing of 10 µF, in parallel with a 0.1 µF capacitor
on each supply that is located as near the package as possible
(ideally, right up against the device). The 10 µF capacitors are
of the tantalum bead type. Ensure that the 0.1 µF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
In systems where many devices are on one board, it is often
useful to provide some heat sinking capability to allow
the power to dissipate easily.
The LFCSP package of the AD5693R/AD5692R/AD5691R/
AD5693 has an exposed pad beneath the device. Connect this
pad to the GND supply of the device. For optimum performance,
use special consideration when designing the motherboard and
mounting the package. For enhanced thermal, electrical, and
board level performance, solder the exposed pad on the bottom
of the package to the corresponding thermal land pad on the
PCB. Design thermal vias into the PCB land pad area to further
improve heat dissipation.
The GND plane on the device can be increased (as shown in
Figure 51) to provide a natural heat sinking effect.
AD5693R/
AD5692R/
AD5691R/
AD5693
GND
PLANE
BOARD
12077-052
Figure 51. Pad Connection to Board
Data Sheet AD5693R/AD5692R/AD5691R/AD5693
Rev. D | Page 25 of 26
OUTLINE DIMENSIONS
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PI N 1 INDEX
AREA
SEATING
PLANE
0.60
0.55
0.50
1.10
1.00
0.90
0.20 RE F
0.15 RE F
0.05 M AX
0.02 NOM
0.50 BS C
EXPOSED
PAD
PI N 1
INDICATOR
(R 0. 15)
FOR PROP E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONF IGURATION AND
FUNCTIO N DE S CRIPT IONS
SECTION OF THIS DATA SHEET.
01-14-2013-C
2.10
2.00 S Q
1.90
Figure 52. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD]
2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead
(CP-8-10)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 53. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
AD5693R/AD5692R/AD5691R/AD5693 Data Sheet
Rev. D | Page 26 of 26
ORDERING GUIDE
Model1 Resolution (Bits) Pinout Temperature Range Performance
Package
Description
Package
Option Branding
AD5693RACPZ-RL7 16 LDAC −40°C to +105°C A Grade 8-Lead LFCSP_UD CP-8-10 AB
AD5693RACPZ-1RL7 16 VLOGIC −40°C to +105°C A Grade 8-Lead LFCSP_UD CP-8-10 AC
AD5693RARMZ 16 −40°C to +105°C A Grade 10-Lead MSOP RM-10 DJU
AD5693RARMZ-RL7 16 −40°C to +105°C A Grade 10-Lead MSOP RM-10 DJU
AD5693RBCPZ-2RL7 16 RESET −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 AD
AD5693RBRMZ 16 −40°C to +105°C B Grade 10-Lead MSOP RM-10 DJV
AD5693RBRMZ-RL7 16 −40°C to +105°C B Grade 10-Lead MSOP RM-10 DJV
AD5693BCPZ-RL7 16 LDAC −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 AA
AD5692RACPZ-RL7 14 LDAC −40°C to +105°C A Grade 8-Lead LFCSP_UD CP-8-10 4M
AD5691RACPZ-1RL7 12 VLOGIC −40°C to +105°C A Grade 8-Lead LFCSP_UD CP-8-10 5W
AD5691RBCPZ-RL7 12 LDAC −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 6M
AD5691RBRMZ 12 −40°C to +105°C B Grade 10-Lead MSOP RM-10 DK2
AD5691RBRMZ-RL7 12 −40°C to +105°C B Grade 10-Lead MSOP RM-10 DK2
EVAL-AD5693RSDZ Evaluation Board
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12077-0-2/17(D)