M28W160CB90N6 - STMicroelectronics

1/49February 2003

M28W160CT

M28W160CB

16 Mbit (1Mb x16, Boot Block)

3V S upply Flash Mem ory

0CFEAT URE S SUMMARY

■SUPPLY VOLTAGE

–V

DD = 2.7V to 3.6V Core Power Supply

–V

DDQ= 1.65V to 3.6V for Input/Output

–V

PP = 12V for fast Program (optional)

■ACCESS TIME: 70, 85, 90,100ns

■PRO GRAMMIN G TIME:

– 10µs typic al

– D ou ble Word P rogrammin g Option

■COMMON FLASH INTERFACE

– 64 bit Sec urity Code

■MEMORY BLOCKS

– Parameter Bl o cks (Top or Bottom locati o n )

– M ain B locks

■BLOCK LOCKING

– A ll blocks locked at Power Up

– A ny combi nation of blocks can be locked

–WP

for Block Lock-Down

■SECURITY

– 64 bit user Programmable OTP cells

– 64 bit uni que dev ice identifier

– One Parameter Block Permanently Lockab le

■AUTOMATIC STAND-BY MODE

■PROG RAM and E RASE SUSPEND

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code, M28W160CT: 88CEh

– B ot tom Device Code, M28W 160CB : 88CFh

Figure 1. Packages

FBGA

TSOP48 (N)

12 x 20mm

TFBGA46 (ZB)

6.39 x 6.37mm

M28W160CT, M28W160CB
2/49
TABLE OF CONT ENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table  1. Signal Names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP  Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA Connect ions (Top view through pack age). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 8
Figure 6. Security Block and Protection Regi ster Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 9
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
D ata Input/Output (DQ0-DQ 15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 9
Out put Enabl e (G).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
W rite Enable (W).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (WP).  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 9
VDD Supply Volt age. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . .  . 9
VDDQ Supply Vo ltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VPP Program Supply Voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS Ground.  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R ead.. .  . . . . . . . . . . . .  . . .  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . .  . . . . . . . . . . . . . . . . . . .  . . . . . . 1 0
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Standby .  . . . . . . . . . . . . . . . . . .  . . . . . . . . .  . . . .  . . . . . . . . . . . .  . . .  . . . . . . . . . . . . . . . . . . . . . . . 10
Autom at ic Standby. . . . . .  . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . . 10
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
R ead Electroni c Signature Com ma nd. . . . . . . . . . . . . . . .  . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Bus Ope rations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COMMAND INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
R ead Memory Array Com man d. . .  . . . . . . . . . . . . . . . . .  . . . . . .  . . . . . . . .  . . . . . .  . . . . . .  . . . . . .11
R ead Status Register Comma nd. . . . . . . . . . . . . . . . . . .  . . .  . . . .  . . . . . .  . . . . . . . .  . . . . . . . . . . .11
R ead Electroni c Signature Com ma nd. . . . . . . . . . . . . . . .  . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 11
R ead CFI Query Command. . . .  . . . . . .  . . . . . . . . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . . . . . 11
Block Erase  Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1 1
D ouble Word Program  Command .  . . . .  . . . . . . . .  . . . . . . . . . . .  . . .  . . . .  . . . . . .  . . . . . . . .  . . . . . 12
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Program /Era se Suspend Com m and . . . .  . . . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . . . .  . . . . 12
Program/Erase Resume Com mand  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection Register Program Command  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Lock-Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M28W160CT, M28W160CB
Table 3. Commands  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table  4. Read El ec tronic Signature. . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . . . . . . .  . . . . . . . . . . . 14
Table  5. Read Block Lock Signature . . . .  . . . . . . .  . . . . . . . .  . . . . . . . . . . . . . . . .  . . .  . . . . . . . . . .15
Table  6. Read Prot ect ion Register and Lock Register  . . . .  . . . .  . . . . . . . . . .  . . . .  . . . . . .  . . . . . . 15
Table  7. Pr ogram , Erase Times  and Prog ram/Er ase Endu rance Cycles  . . . .  . . . . . . . . . .  . . . . . . 15
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
R eading  a Block’s Lock Status . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . . . . . . . .  . . .  . . . . . . . . . . 16
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 1 6
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locking Operations During Erase Suspend  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1 7
Table 9. Protecti on Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STATUS REGIST ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Erase S uspend S tatus (Bit 6) . . . . . . . .  . . .  . . . . . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . . 1 8
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Status (Bit 4 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program  Susp end Status (Bit 2) . .  . . . .  . . . . . . . .  . . . . . . . . . . .  . . .  . . . .  . . . . . .  . . . . . . . .  . . . . . 18
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1 9
Reserve d (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 19
Table 10. Status Re gister Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Absolute Maximum Ratin gs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
Table  12. Operating and AC Measuremen t Conditions. . . . .  . . . .  . . . . . . .  . . . . . . . . . . . .  . . . . . . 21
Figure 7. AC Measurement I/O  Wave form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. AC Meas urement Load  Circuit. . . . . . . . . . . . .  . . . . . .  . . . . . . . . . .  . . . .  . . . . . .  . . . . . . 21
Table  13. Capacitance.  . . .  . . . . . . . . . .  . . .  . . . . . . . . . .  . . .  . . . . . . . . . . . . . . . .  . . .  . . . . . . . . . . 2 1
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 9. Read Mode AC Waveforms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table  15. Read AC Characteristics . . . . . . . . . . . . . . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . . 23
Figure 10. Write AC Wavef orms, Write Enable Controlled . . . . . . . . . . . .  . . . . . .  . . .  . . . .  . . . . . . 24
Table  16. Write AC Characteristics, Write Enable Controlled . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . . 25
Figure 11. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 17 . Write AC Characteristics, Chip Enable Controlled  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 12. Pow er-Up  and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18 . Power-Up a nd Reset AC Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M28W160CT, M28W160CB
4/49
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Out lin e  . . . . . . . . 29
Table 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data  . 29
Figure 14. TFBGA4 6 6.39x 6.37mm - 8x6 ball array, 0.75m m  pitch, Bottom View Package Outlin e30
Table  20. TFBG A 46 6 .39x6.37m m  - 8x6 ball array, 0.75mm pitch, Pack age Mecha nical Data . . . 30
Figure 15. TFBGA46 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 31
Figure 16. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package). . . . 31
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 21. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 22 . Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table  23. Top Boot Block Ad dresse s, M28W160CT . . . . .  . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 24 . Bottom Boot Blo ck Addresses, M28W160CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX B. COMMON FLASH INT ERFACE (CF I)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 25. Query Structu re Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table  26. CFI Query Identification String  .  . . . . . .  . . . . . . . . . . . .  . . . . . .  . . . . . .  . . .  . . . .  . . . . . .34
Table 27. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 28. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table  29. Pr i mary Algorithm -Spe cific Extende d Query Table . . . . . . . . . . . . .  . . . . . . . . . .  . . . . . . 37
Table  30. Security Code Area . . . .  . . . . . . . . . . . . . . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . . 38
APPENDIX C. F LOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. Program Flowchart and Pseudo Code . . . . . . . . . . . .  . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . . 39
Figure 18. Double Wor d Program Flowchart and Pseudo Code . . . . .  . . . . . . .  . . . . . . . . . . . . .  . . 40
Figure 19. Program Suspend & Resume Flowch art and Pseudo Code  . . . . . . . . .  . . . . . . . .  . . . . 41
Figure 20. Erase Flowchart and Pseudo Code . . .  . . . . . . . .  . . . .  . . . . . .  . . .  . . . .  . . . . . .  . . . . . . 42
Figure 21. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . .  . . . . . .  . . . . . .  . . . . . . 43
Figure 22. Locking Operations Flowc hart and Pseudo Code  . . . . .  . . . . . . . . . . . .  . . . . . . .  . . . . . 44
Figure 23. Protection Register Program Flowchart and Pseudo Code . . . .  . . . . . .  . . . . . . . .  . . . . 45
APPENDIX D. CO MMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 46
Table 31 . Write State Machine Current/Next, sheet 1 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 32 . Write State Machine Current/Next, sheet 2 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33 . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

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M28W160CT, M28W160CB

SUMMARY DESCRIPTION

The M28W160C is a 16 Mbit (1 Mbit x 16) non-vol-

atile Flash memory that can be erased elect rically

at the block level and programmed in-system on a

Word-by-Word basis. These operations can be

performed using a single low voltage (2.7 t o 3.6V)

supply. VDDQ allows to drive the I/O pin down to

1.65V. An o ptional 12V VPP power supply is pro-

vided to speed up customer programm ing.

The device features an asymmetrical blocked ar-

chitecture. The M28W160C has an array of 39

blocks: 8 Parameter Blocks of 4 KWord and 31

Main Blocks of 32 KWord. M28W160CT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W160CB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 5, Block Ad-

dresses.

The M28W160C features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protect ion. They can be locked and

locked-down individually preventing any acciden-

tal programmi ng or erasure. There is an addit ional

hardware protection against program and erase.

When VPP ≤ VPPLK all bloc ks are protected agains t

program or eras e. A ll blo cks are l ock ed a t power-

up.

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each blo ck can be

programmed and erased over 100,000 cycles.

The device includ es a 128 b it Prot ection Register

and a Security Block t o increase the protection of

a system design. The Pro tect ion Register is divid-

ed into two 64 bit segments, the first one contains

a unique device number written by ST, while the

second one is on e-time-programmable by the us-

er. The user programmable se gment can be per-

manently protected. The Security Block,

parameter bloc k 0 , can be p ermanently protected

by the user. Figure 6, shows the Security Block

and Protection Register Mem ory Map.

Program and Erase command s a re written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for pr ogram and erase operati ons.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

The memory is offered in TSOP48 (10 X 20mm)

and TFBGA46 (6.39 x 6.37mm, 0.75mm pitch)

packages and is supplied with all the bits erased

(set to ’1’).

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A19 Address Inputs

DQ0-DQ15 Data Input/Output

EChip Enable

GOutput Enable

WWrite Enable

RP Reset

WP Write Protect

VDD Core Power Supply

VDDQ Power Supply for

Input/Output

VPP Optional Supp ly Voltage for

Fast Program & Erase

VSS Ground

NC Not Connected Internally

AI03811

A0-A19

DQ0-DQ15

VDD

M28W160CT

M28W160CB

VSS

VDDQ VPP

M28W160CT, M28W160CB

6/49

Figu re 3. TSOP C onnecti on s

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15

VDD

DQ4

DQ5

DQ7

VPP

AI03812

M28W160CT

M28W160CB

24 25

DQ8

A19

A18

DQ1

DQ11

A12

A13

A16

A11

VDDQ

A15

A14 VSS

VSS

7/49

M28W160CT, M28W160CB

Figure 4. TFBGA Connections ( Top vi ew throug h package)

AI03804

87654321

A7VPP

A8A11

A13

A0EDQ8DQ5DQ14A16

VSS

DQ0DQ9DQ3DQ6

DQ15

VDDQ

DQ1DQ10VDD

DQ7VSS

DQ2

A5A17WA10

A14

A1A3A6A9A12A15

RP A18

DQ4

DQ13 G

DQ12

DQ11

WP A19

M28W160CT, M28W160CB

8/49

Figure 5. Block Addresses

Note: Also see A ppendix A, T ables 23 and 24 for a f ul l l isting o f the Block A ddress es.

Figure 6. Securi ty Block an d Protection Register Memory Map

AI04311

4 KWords

FFFFF

FF000

32 KWords

0FFFF

08000

32 KWords

07FFF

00000

M28W160CT

Top Boot Block Addresses

4 KWords

F8FFF

F8000

32 KWords

F0000

F7FFF

Total of 8

4 KWord Blocks

Total of 31

32 KWord Blocks

4 KWords

FFFFF

F8000 32 KWords

32 KWords

00FFF

00000

M28W160CB

Bottom Boot Block Addresses

4 KWords

F7FFF

0FFFF 32 KWords

F0000

08000

Total of 31

32 KWord Blocks

Total of 8

4 KWord Blocks

07FFF

07000

AI03523

Parameter Block # 0

User Programmable OTP

Unique device number

Protection Register Lock 2 1 0

88h

85h

84h

81h

80h

SECURITY BLOCK

PROTECTION REGISTER

9/49

M28W160CT, M28W160CB

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 1,Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A19). The Address Inputs

select the cell s in the memory arra y to access dur-

ing Bus Read operations. During Bus Writ e opera-

tions they control the commands sent to the

Comman d Interface of the internal stat e ma chine.

Data Input/Output (DQ 0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the dat a to be programm ed durin g a W rite B us

operation.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at VILand Reset is at VIH the device is in active

mode. When Chi p E nable is at V IH the memory is

deselected, the outputs are high impedance and

the power consumption i s reduced to the stand-by

level.

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

Write Enable (W). Th e Wri te Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are l atched

on the rising edge of Chip Ena ble, E, or Write En-

able, W, whichever occurs first.

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

each block. When Wri te Protect is at VIL, t he Lock-

Down is en abled and the protection status of the

block cannot be changed. When Write Protect is at

VIH, the Lock-Down is disabled and the block can

be locked or unlocked. (refer to Table 6, Read Pro-

tection Register and Protection Register Lock).

Reset (R P). The Reset input provides a hard-

ware reset of the memory. When Reset is at VIL,

the memory is in reset mode: the outputs are high

impedance and the current consumption is mini-

mized. After Reset all blocks are in the Locked

state. When Res et is at VIH, the device is in normal

operation. Exiting reset mode the device enters

read array mode, but a negative transition of Chip

Enable or a change of the address is requi re d to

ensure valid data outputs.

VDD Supply Voltage . VDD provides the power

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

VDDQ Su pp ly V o lta ge . VDDQ provides the

power supp ly to the I/O pins and ena bles all Ou t-

puts to be powered independently from VDD. VDDQ

can be tied to V DD or can use a separate supply.

VPP Program Supply Voltage. VPP is both a

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin. The Supply Voltage VDD and the

Program Supply Voltage VPP can be applied in

any order.

If V PP is kept in a low voltage range (0V to 3.6V)

VPP is seen as a control input. In this case a volt-

age lower than VPPLK gives an absolut e protection

against program or erase, while VPP > VPP1 en-

ables these functions (see Table 1 4, DC Charac-

teristics for the relevant values). VPP is only

sampled at the beginni ng of a program or erase; a

change in its valu e af ter the operation has started

does not have any effect and program or erase op-

erations conti nue.

If VPP is in the range 11.4V to 12.6V it acts as a

power supply pin. In this condition VPP must be

stable until the Program/Erase algorithm is com-

pleted (see Table 16 and 17).

VSS Ground. VSS is the referenc e f or a ll voltage

measurements.

Note: Each device in a system should have

VDD,

VDDQ and V PP decoupled wi th a 0.1 µF ca-

pacitor close to the pin. S ee Figu re 8, AC M ea-

surement Load Circuit. The PCB trace widths

should be sufficient to carry the required VPP

program and erase currents.

M28W160CT, M28W160CB

10/49

BUS OPERATIONS

There are si x standard bus operati ons that control

the device. These are Bus Read, Bus Wri te, Out-

put Disable, St andby, A utom at ic Standby and Re-

set. See Table 2, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chi p Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Int erface. Both Chip Enable and Output En-

able mu st be at VIL in o rder t o perform a read op-

eration. The Chip Enable in put should be us ed to

enable t he de vice . Out put Enable s houl d be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 9, Read Mode AC Waveforms, and Table

15, Read AC Characteristics, for details of when

the output becomes valid.

Read mode is the default state of the device when

exiting Reset or after power-up.

Write. Bus Write operations write Commands to

the memory or lat ch Input Data to be programmed.

A write operation is initiated when Chip Enable

and Write Enable are at V IL with Output Enable at

VIH. Commands, Input Data and Addresses are

latched on t he rising edge of Write Enable or Chip

Enable, whichever occurs f irst.

See Figures 10 and 11, Write AC Wavef orms, and

Tables 16 and 17, Write AC Characteristics, for

details of th e timing requiremen ts.

Outp ut Disable. The data outputs are high im-

pedance when the Output Enable is at VIH.

Standby. Standby disables most of the internal

circuitry allowing a substant ial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable is at VIH and the device is in

read mode. The power consumption i s reduced to

the stand-b y level and the o utputs are se t to high

impedance, independently from the Output Enable

or Write Enabl e inpu ts. If Chip Enable switches to

VIH du ring a program or erase operation, the de-

vice enters Standby mode when finished.

Automatic Stand by. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inact iv-

ity even i f Chip Enable is Low, VIL, and the supply

current is reduced to IDD1. The data Inputs/Out-

puts will sti ll output data if a bus Read operation is

in progress.

Reset. During Reset mode when Output Enable

is Low, VIL, the memory is deselect ed and the out-

puts are high impedance. The memory is in Reset

mode when Reset is at V IL. The power c onsump-

tion i s reduced to the Standby level, independently

from t he Chip Enable, Output Enable or Writ e En-

able inputs. If Reset is pu lled to VSS during a Pro-

gram or Erase, this operation is aborted and the

memory content is no longer va lid.

Table 2. Bus Operati ons

No te: X = VIL or VIH, VPPH = 12V ± 5%.

Operation E G W RP WP VPP DQ0-DQ15

Bus Read VIL VIL VIH VIH X Don’t Care Data Output

Bus Write VIL VIH VIL VIH XVDD or VPPH Data Input

Output Disable VIL VIH VIH VIH X Don’t Care Hi-Z

Standby VIH XX

IH X Don’t Care Hi-Z

Reset X X X VIL X Don’t Care Hi-Z

11/49
M28W160CT, M28W160CB
COMMAND INTERFACE
All Bus  Write operations t o the  memory are in ter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/ Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controll er provides a S tatus Regi ster
whose output may be read at any time during, to
monitor the progress  of the operation, or t he Pro-
gram/Erase states. See Appendix 21, Table 31,
Write State Machin e Current /Ne xt, for a summary
of the Command Interface.
The Command Interface is reset to Read mode
when power is fi rst  applied, when exi ting from Re-
set or whenever VDD is lower than VLKO. Com-
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 3, Com mands,
in co njunction with the text descriptions below.
Read Memory Array Comman d 
The Read command returns the memory to its
Read mode. One Bus Writ e cycle is  required to i s-
sue the Read Memory Array command and return
the memory to Read m ode. Subsequ ent read op-
erations will r ead the addressed loc ation and out-
put the data. When a device Reset occurs, the
memory defaults to Read mode. 
Read Status Register Command 
The Status  Register indicates when a program  or
erase operation is complete and the success or
failure of the  operat ion i tself. Issue a Read S tatus
Register command to read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Register at any address, until another
command is issued. See Table 10, Status Register
Bits, for details on the definitions of the bits.
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will  auto matically output the con-
tent of the Status Register. 
Read Electronic Signature Command 
The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read El ectronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down S tatus, or the Protec-
tion and Lock Register. See Tables 4, 5 and 6 for
the valid address. 
Read CFI Query Comman d 
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or appli-
cations to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com-
mand. Once the command is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See Appendix B,
Common Flash Interface, Tables 25, 26, 27, 28,
29 and 30 for details on the information con tained
in the  Common Flash Interface memory area.
Block Erase Command 
The B lock Erase com mand  can be  used  to  erase
a block. It s ets all  the bit s wi thin the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the dat a in the block will not be changed and
the Status Register will output the error.
Two Bus Write cycles are required to issue the
command. 
■The first bus cycle sets up the Erase command. 
■The second  latches the block address in the 
internal state machine and sta rts the Program/
Erase Controller.
If the second bus cycle is not Writ e Erase Confirm
(D0h), Status  Regist er  bit s b4 and b 5 are set  and
the command aborts.
Erase aborts if Reset turns to VIL.  As data i nt egr ity
cannot be guarant eed when the Erase operation is
aborted, the block must be erased again. 
During Erase operations the memory will accept
the Rea d Status Re gister com mand  and the P ro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table  7 , Program, Eras e Times and Pro-
gram/Erase Endurance Cy cl es.
See Appendi x C, Figure 20 , Erase Flowchart  and
Pseudo Code, f or a sugges ted f lowchart fo r using
the Erase command.
Progra m Command  
The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program Command. 
■The first bus cycle  sets up the P rogram  
comman d. 
■The second latches the Address and the Data to 
be written and starts the Program/Erase 
Controller. 
During Program operations the memory will ac-
cept the Read Status Register comm and and the
Program/Erase Suspend command. Typical Pro-
gram t imes  are given  in Tab le 7, P rogram, E rase
Times and Progra m/Er ase Endura nce Cycles.
Programming  aborts  if Reset goe s to  VIL. As data
integrity cannot be guaranteed when the program
operation is aborted, the block containing the

M28W160CT, M28W160CB

12/49

memory location must be erased and repro-

grammed.

See Appendix C, Figure 17, Program Flowchart

and Pseudo Code, for the flowcha rt for using the

Program com man d.

Double Word Prog r am Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. P rogram m ing s hould not b e at t emp t-

ed when VPP is not at VPPH. The command can be

executed if VPP is below VPPH but the result is not

guaranteed.

Three bus write cycles are n eces sary to issue the

Double Wor d Program command.

■The first bus cycle sets up the Double Word

Program Command.

■The second bus cycle latches the Address and

the Data of the first word to be wri tten.

■The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controlle r.

Read operations output the Status Register con-

tent after the prog ramming has s tarted. Program-

ming a borts if Res et goes to VIL. As data in teg rity

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogramm ed.

See Appendix C, Figure 18, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Clear Status Regi st er Command

The Clear S tatus Reg ister com m and can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the S tatus Register do not aut omati cal-

ly return to ‘0’ when a new Program or Erase c om-

mand is issued. The error bits in the Status

new Program or Erase command .

Program/ Erase Suspend Command

The Progr am/Eras e Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue t he Program/ Erase

command and pause the Progra m/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Block Lock, Block Lock-Down or

Protection Program commands will also be ac-

cepted. T he block being erased may be pr otected

by issuing the Block Protect, Block Lock or Protec-

tion Program commands. When the Program/

Erase Resume command is issued the operation

will complete. Only the blocks not being erased

may be read or programm ed correc tly.

During a Program/Erase Suspend, the dev ice can

be placed in a pseudo-standby mode by taking

Chip Enable to VIH. Program/Erase is aborted if

Reset turns to V IL.

See Appendi x C , F igure 19, Program Suspend &

Resume Flowcha rt and Pseudo Code, and Figure

21, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend com man d.

Progra m/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/E ras e Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

See Appendi x C , Figure 19, Program Suspend &

Resume Flowcha rt and Pseudo Code, and Figure

21, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Resume command.

P rotectio n R egister Pr ogram C om m and

The Protection Register Program command is

used to Program the 64 bit user One-Time-Pro-

grammabl e (OTP) se gment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits t o ‘0’.

Two write cycles are required to issue the Pro tec-

tion Register Program command.

■The first bus cycle sets up the Protec tion

■The second latches the Address and the Data to

be written to t he P rotection Register and starts

the Program/Erase Controlle r.

Read operations output the Status Register con-

tent after the programm ing has started.

The segment can be protect ed by programming bit

1 of t he Pro tection Lock Register. Bit 1 of t he Pro-

tection Loc k Register prote cts bi t 2 of t he Pro tec-

tion Lock Register. Programming bit 2 of the

Protection Loc k Register will result in a permanent

protection of the S ecurity Block (see Fi gure 6, Se-

curity Block and Protection Register Memory

Map). Attempting to program a previously protect -

ed Protection Register will result in a Status Reg-

ister error. The protection of the Protection

ible.

13/49

M28W160CT, M28W160CB

The Protection Register Program cannot be sus-

pended. See Appendix C, Figure 23, Protection

for the flowchart fo r using the P rote ction Register

Program com man d.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

■The first bus cycle sets up the Blo ck Lock

comman d.

■The secon d Bus Write cycle latche s th e blo ck

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 9 shows the protection status after issuing

a Block Lock command.

The B lock Loc k bits are volatile, onc e s et t hey re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to t he section, Block Loc king, for

a detail ed explanat i on.

Block Unlock Command

The Blocks Unlock command is u se d to u nlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Blocks Unlock comman d.

■The first bus cycle sets up the B lo ck Unlock

comman d.

■The secon d Bus Write cycle latche s th e blo ck

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 9 show s the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,

or have its protection stat us changed when WP is

low, VIL. When WP is high, VIH, the Lock-Down

function is disabl ed and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

Two Bus Write cycles are required to issue the

Block Lock-Down comman d.

■The first bus cycle sets up the Blo ck Lock

comman d.

■The secon d Bus Write cycle latche s th e blo ck

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blo cks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table. 9 shows t he protection status

after issuing a Block Lock-Down command. Refer

to the sect ion, Block Locking, for a detailed expla-

nation.

M28W160CT, M28W160CB

14/49

Table 3. Commands

No te: 1. X = Don’t Care.

2. The si gnature addres ses are li st ed in Tabl es 4, 5 and 6 .

3. Addr 1 and Addr 2 must be consecutive Address es d i ffering on l y f or A0.

Table 4. Read Electronic Sign atur e

Note: RP = VIH.

Commands No. of

Cycles

Bus Write Operations

1st Cycle 2nd Cycle 3nd Cycle

Bus

Op. Addr Data Bus

Op. Addr Data

Read Memory Array 1+ Write X FFh Read Read

Addr Data

Read Status Register 1+ Write X 70h Read XStat us

Read Electronic Sign ature 1+ Write X 90h Read Signature

Addr (2) Signature

Read CFI Query 1+ Write X 98h Read CFI Addr Query

Erase 2 Write X 20h Write Block

Addr D0h

Program 2 Write X 40h or

10h Writ e Addr Dat a Inp ut

Double Word Program(3) 3 Wr ite X 30h Write Addr 1 Data Input Write Addr 2 Data

Input

Clear St atus Register 1 Write X 50h

Program/Erase Suspend 1 Write X B0h

Program/E rase Resume 1 Write X D0h

Block Lock 2 Write X 60h Writ e Block

Address 01h

Block Unlock 2 Write X 60h Write Block

Address D0h

Block Lock- Down 2 Write X 60h Write Bloc k

Address 2Fh

Protection Register

Program 2 Write X C0h Write Address Data Input

Code Device E G W A0 A1 A2-A7 A8-A19 DQ0-DQ7 DQ8-DQ15

Manufacture.

Code VIL VIL VIH VIL VIL 0 Don’t Care 20h 00h

Device Code M28W160CT VIL VIL VIH VIH VIL 0 Don’t Care CEh 88h

M28W160CB VIL VIL VIH VIH VIL 0 Don’t Care CFh 88h

15/49

M28W160CT, M28W160CB

Table 5. Read Block Lock Signature

Note: 1. A Lock ed-Down Block can be locked "DQ0 = 1" or unlo ck ed "DQ0 = 0" ; s ee Block Lo cking section.

Table 6. Read Protection Register and Lock Register

Table 7. Progra m , Erase Times and Pro gra m /Erase Endura nce Cycl es

Block Status E G W A0 A1 A2-A7 A8-A11 A12-A19 DQ0 DQ1 DQ2-DQ15

Locked Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address 1 0 00h

Unlocked Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address 0 0 00h

Locked-Down

Block VIL VIL VIH VIL VIH 0 Don’t Care Block Address X (1) 1 00h

Word E G W A0-A7 A8-A19 DQ0 DQ1 DQ2 DQ3-DQ7 DQ8-DQ15

Lock VIL VIL VIH 80h Don’t Care 0 OTP Prot.

data Security

prot. data 00h 00h

Unique ID 0 VIL VIL VIH 81h Don’t Care ID data ID data ID data ID data ID data

Unique ID 1 VIL VIL VIH 82h Don’t Care ID data ID data ID data ID data ID data

Unique ID 2 VIL VIL VIH 83h Don’t Care ID data ID data ID data ID data ID data

Unique ID 3 VIL VIL VIH 84h Don’t Care ID data ID data ID data ID data ID data

OTP 0 VIL VIL VIH 85h Don’t Care OTP data OTP data OTP data OTP data OTP data

OTP 1 VIL VIL VIH 86h Don’t Care OTP data OTP data OTP data OTP data OTP data

OTP 2 VIL VIL VIH 87h Don’t Care OTP data OTP data OTP data OTP data OTP data

OTP 3 VIL VIL VIH 88h Don’t Care OTP data OTP data OTP data OTP data OTP data

Parameter Test Conditions M28W160C Unit

Min Typ Max

Word Program VPP = VDD 10 200 µs

Double Word Program VPP = 12V ±5% 10 200 µs

Main Block Program VPP = 12V ±5% 0.16 5 s

VPP = VDD 0.32 5 s

Parameter Block Program VPP = 12V ±5% 0.02 4 s

VPP = VDD 0.04 4 s

Main Block Erase VPP = 12V ±5% 110 s

PP = VDD 110 s

Parameter Block Erase VPP = 12V ±5% 0.8 10 s

VPP = VDD 0.8 10 s

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

M28W160CT, M28W160CB

16/49

BLOCK LOCKING

The M28W160C features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

■Lock/ Unlock - th is first leve l allows software-

only control of block locking.

■Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■VPP ≤ VPPLK - the third level offers a complete

hardware protection against program and erase

on all blocks.

The lock status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 9, de-

fines all of the possible protection states (WP,

DQ1, DQ0 ), an d Appendix C, Figure 22, shows a

flowchart for the loc king operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 5,

will output the lock status of that block. The lock

status is represented by DQ0 and DQ1. DQ0 indi-

cates the Block Lock/Unlock status and is set by

the Lock command and cleared by the Unlock

command. I t is also autom atica lly set when enter-

ing Lock-Down. DQ1 indicates the Loc k-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

The following sections explain t he operati on of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any progr am or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock com mand.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks re tu rn to the Locked sta te after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are

protected from p rogram a nd erase operations (as

for Locked blocks) but their lock statu s cannot be

changed using software commands alone. A

Locked or Unlocked block can be Locked-Down by

issuing the Lock-Down command. Locked-Down

blocks revert to the Locked sta te when the device

is reset or powered-down.

The Lock-Do wn function is depen dent on the WP

input pin. When WP=0 (VIL), the blocks in the

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

WP=1 (VIH) the Lock-Down function is disabled

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be relocked

(1,1,1) and unlocked (1,1,0) as desired while WP

remains high. When WP is lo w , blocks that were

previously Locked-Down return to the Lock -Down

state (0,1,x) regardless of any changes made

while WP was high. Device reset or power-down

resets all bl oc ks , including those in Lock-Down, to

the Locked state.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation i s in progress .

To change block locking during an erase opera-

tion, first write t he Erase Suspend comm and, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the protection status will be changed. After

completing any des ired lock, read, or program op-

erations, resume the erase operation with the

Erase Resume command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed im mediately, but when the erase

is resumed, the erase operation will complete.

Locking ope ra tions c annot be performed du ring a

program suspend. Refer to Appendix D, Com-

mand Interface and Program/Erase Controller

State, for detailed information on which com-

mands are valid during erase suspend.

17/49

M28W160CT, M28W160CB

Table 8. Block Lock Status

Table 9. Protection Status

Note: 1. The p rotect i on status is defined by th e write protec t pi n and by DQ1 (‘1’ f or a locked-down block) and DQ0 (‘1’ for a lo cked bl ock)

as read in the Read Elec tr oni c Signat ure com m and with A1 = VIH and A0 = V IL.

2. All blocks are l ocked at power-up, so the default configuration i s 001 or 101 accor di ng to WP status.

3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.

Item Address Data

Block Lock Configuration

xx002

LOCK

Block is Unlocked DQ0=0

Block is Locke d DQ0=1

Block is Locked-Down DQ1=1

Current

Protection Status(1)

(WP, DQ1, DQ0)

Next Protection Status(1)

(WP, DQ1, DQ0)

Current State Program/Erase

Allowed

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

After

WP trans ition

1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0

1,0,1(2) no 1,0,1 1,0,0 1,1,1 0,0,1

1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1

1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1

0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0

0,0,1(2) no 0,0,1 0,0,0 0,1,1 1,0,1

0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)

M28W160CT, M28W160CB

18/49

STATUS REGIST E R

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits c onvey inf ormation and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the cont ents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signal s, and can be read until Chi p Enable

or Output Enable returns to VIH. Either Chip En-

able or Output Enable must be toggled to update

the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are s um marized in

Table 10, Status Register Bits. Refer to Table 10

in co njunction with the following text descriptions.

Program/Erase Controll er Status ( Bit 7). The Pro-

gr a m/Erase Controller Status bit indicates whether

the Program/ Erase Controller is activ e or inact i ve.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued unt i l the Program/Eras e Controller

pauses. After the Program/E rase Cont roller paus-

es the bit is High .

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled t o find the

end of the operation. Other bits i n the Status Reg-

ister should not be tested until the Program /Erase

Controller completes the operation and the bit is

High.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V PP

Status and Block Lock Status bits should be tested

for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status b it indicates that an Erase o perati on

has been suspended or is going to be suspended.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and t he memo ry is waiting for a P ro-

gram/Erase Resume command.

The Er ase Suspend St atus should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 i s set within 30µs of the Program /Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering t he Suspend mode.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Pro gram/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased corr ectly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Prog ram/Erase Con-

troller inactive).

Once s et High, the Erase Status bit can only be re-

set Low by a Clear Status Register c ommand or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the by te and still failed to ver-

ify that it has programm ed correctly. The Program

Status bit should be read once t he Program/Erase

Controller Status bit is High (Prog ram/Erase Con-

troller inactive).

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set Hi gh it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

VPP Status (Bit 3). The VPP Status bit can be

used to identify an invalid voltage on the VPP pin

during Program and Erase operations. The VPP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if VPP becomes invali d during an operation.

When the VPP Status bit is Low (set to ‘0’), the volt-

age on the VPP pin was sampled at a valid voltage;

when the VPP Status bit is High (set to ‘1’), the VPP

pin has a voltage that is below the VPP Lockout

Voltage, VPPLK, the memory is protect ed and Pro-

gram and Erase operations cannot be perform ed.

Once set High, the VPP Status bit can only be reset

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Suspen d Status (Bit 2). The Program

Suspend St atus bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a P rogram/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

19/49

M28W160CT, M28W160CB

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the me mory may still complete t he

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Stat us bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identi fy if a Pro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a lock ed block .

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register c om-

mand or a hardware reset. If set High it shoul d be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

Table 10. Status Register Bits

Note: Logic level ’1’ is High, ’0’ is Low.

Bit Name Logic Level Definition

7 P/E.C. Status ’1’ Ready

’0’ Busy

6 Erase Suspend Status ’1’ Suspended

’0’ In progress or Completed

5 Erase Status ’1’ Erase Error

’0’ Erase Success

4 Program Status ’1’ Program Error

’0’ Program Succ ess

3VPP Status ’1’ VPP Invalid, Abort

’0’ VPP OK

2 Program Suspend Status ’1’ Suspended

’0’ In Progress or Completed

1 Block Protection Status ’1’ Program/Erase on protected Block, Abort

’0’ No operation to protected blocks

0 Reserved

M28W160CT, M28W160CB

20/49

MAX I MUM R A TI N G

Stressing the device ab ove t he rating listed in t he

Absolute Maxi mum Ratings table m ay cause per-

manent damage to the device. These are stress

ratings only and operation of the device at t hes e or

any other con ditions ab ove those i ndicated i n the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 11. Absolute Maximum Ratings

Not e: 1. Depends on range.

Symbol Parameter Value Unit

Min Max

TAAmbient Operating Temperature (1) – 40 85 °C

TBIAS Temperature Under Bias – 40 125 °C

TSTG S torage Te mperat ure – 55 155 °C

VIO Input or Output Voltage – 0.6 VDDQ+0.6 V

VDD, VDDQ Supply Voltage – 0.6 4.1 V

VPP Program Voltage – 0.6 13 V

21/49

M28W160CT, M28W160CB

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 12,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circu it match the measurement conditions

when relying on th e quoted parameters.

Table 12. Operating and AC Measurem en t Conditions

Figure 7. AC Measurement I/O Wavefo rm Figure 8. AC Measurem ent Load Circuit

Table 13. Capacitance

No te : Sampled only, not 100% te sted.

M28W160CT, M28W160CB

Parameter 70 85 90 100 Units

Min Max Min Max Min Max Min Max

VDD Supply Voltage 2.7 3.6 2.7 3.6 2.7 3.6 2.7 3.6 V

VDDQ Supply Voltage (VDDQ ≤

VDD)2.7 3.6 2.7 3.6 2.7 3.6 1.65 3.6 V

Ambient Operati ng Tem peratur e – 40 85 – 40 85 – 40 85 – 40 85 °C

Load Capacitance (CL)50 50 50 50 pF

Input Rise and Fall Times 5 5 5 5 ns

Input Pulse Voltages 0 to VDDQ 0 to VDDQ 0 to VDDQ 0 to VDDQ V

Input and Output Timing Ref.

Voltages VDDQ/2 VDDQ/2 VDDQ/2 VDDQ/2 V

AI00610

VDDQ

VDDQ/2

AI00609C

VDDQ

CL includes JIG capacitance

25kΩ

DEVICE

UNDER

TEST

0.1µF

VDD

0.1µF

VDDQ

25kΩ

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

OUT Output Capacitance VOUT = 0V 12 pF

M28W160CT, M28W160CB

22/49

Table 14. DC Characteristics

Symbol Parameter Test Condition Min Typ Max Unit

ILI Input Leakage Current 0V≤ VIN ≤ VDDQ ±1 µA

ILO Output Leakage Current 0V≤ VOUT ≤VDDQ ±10 µA

IDD Supply Current (Read) E = VSS, G = VIH, f = 5MHz 10 20 mA

IDD1 Supply Current (Stand-by or

Automatic Stand-by) E = VDDQ ± 0.2V,

RP = VDDQ ± 0.2V 15 50 µA

IDD2 Supply Current

(Reset) RP = VSS ± 0.2V 15 50 µA

IDD3 Supply Current (Program)

Program in progress

VPP = 12V ± 5% 10 20 mA

Program in progress

VPP = VDD 10 20 mA

IDD4 Supply Current (Erase)

Erase in progress

VPP = 12V ± 5% 520mA

Erase in progress

VPP = VDD 520mA

DD5 Supply Current

(Program/Erase Suspend) E = VDDQ ± 0.2V,

Erase suspended 50 µA

IPP Program Current

(Read or Stand-by) VPP > VDD 400 µA

IPP1 Program Current

(Read or Stand-by) VPP ≤ VDD 5µA

PP2 Program Current (Reset) RP = VSS ± 0.2V 5µA

PP3 Program Current (Program)

Program in progress

VPP = 12V ± 5% 10 mA

Program in progress

VPP = VDD 5µA

PP4 Program Current (Erase)

Erase in progress

VPP = 12V ± 5% 10 mA

Erase in progress

VPP = VDD 5µA

IL Input Low Voltage –0.5 0.4 V

VDDQ ≥ 2.7V –0.5 0.8 V

VIH Input High Voltage VDDQ –0.4 VDDQ +0.4 V

VDDQ ≥ 2.7V 0.7 VDDQ VDDQ +0.4 V

VOL Output Low Voltage IOL = 100µA, VDD = VDD min,

VDDQ = VDDQ min 0.1 V

VOH Output High Voltage IOH = –100µA, VDD = VDD min,

VDDQ = VDDQ min VDDQ –0.1 V

VPP1 Program Voltage (Program or

Erase operations) 1.65 3.6 V

VPPH Program Voltage

(Program or Erase

operations) 11.4 12.6 V

VPPLK Program Voltage

(Program and Erase lock-out) 1V

LKO VDD Supply Voltage (Program

and Erase lock-out) 2V

23/49

M28W160CT, M28W160CB

Figure 9. Read Mode AC Waveforms

Table 15. Read AC Characteristics

Not e: 1. Sampled only, not 100% tested.

2. G may be delayed by up to tELQV - tGLQV after the fallin g edge of E without in creasi ng tELQV.

Symbol Alt Parameter M28W160C Unit

70 85 90 100

tAVAV tRC Address Valid to Next Address Valid Min 70 85 90 100 ns

tAVQV tACC Address Valid to Output Valid Max 70 85 90 100 ns

tAXQX (1) tOH Address Transition to Output Transition Min 0 0 0 0 ns

tEHQX (1) tOH Chip Enable High to Output Transition Min 0 0 0 0 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z Max 20 20 25 30 ns

tELQV (2) tCE Chip Enable Low to Output Valid Max 70 85 90 100 ns

tELQX (1) tLZ Chip Enable Low to Output Transition Min 0 0 0 0 ns

tGHQX (1) tOH Output Enable High to Output Transition Min 0 0 0 0 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z Max 20 20 25 30 ns

tGLQV (2) tOE Output Enable Low to Output Valid Max 20 20 30 35 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition Min 0 0 0 0 ns

DQ0-DQ15

AI03813b

VALID

A0-A19

tAXQX

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

ADDR. VALID

CHIP ENABLE OUTPUTS

ENABLED DATA VALID STANDBY

tGHQX

tGHQZ

tEHQX

tEHQZ

M28W160CT, M28W160CB

24/49

Figure 10. Write AC Waveforms, Wr ite Enable Controlled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A19

tAVAV

tQVVPL

tAVWH tWHAX

PROGRAM OR ERASE

tELWL tWHEH

tWHDXtDVWH

tWLWH

tWHWL

tVPHWH

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tELQV

AI03814b

tWPHWH

tWHGL

tQVWPL

tWHEL

25/49

M28W160CT, M28W160CB

Table 16. Write AC Characteristics, Write Enable Controlle d

Not e: 1. Sampled only, not 100% tested.

2. Appli cable if VPP is se en as a logic i nput (V PP < 3. 6V).

Symbol Alt Parameter M28W160C Unit

70 85 90 100

tAVAV tWC Write Cycle Time Min 70 85 90 100 ns

tAVWH tAS Address Valid to Write Enable High Min 45 45 50 50 ns

tDVWH tDS Data Valid to Write Enable High Min 45 45 50 50 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 0 ns

tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns

tQVVPL (1,2) Output Valid to VPP Low Min 0 0 0 0 ns

tQVWPL Output Valid to Write Protect Low Min 0 0 0 0 ns

tVPHWH (1) tVPS VPP High to Write Enable High Min 200 200 200 200 ns

tWHAX tAH Write Enable High to Address Transition Min 0 0 0 0 ns

tWHDX tDH Write Enable High to Data Transition Min 0 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 0 ns

tWHEL Write Enable High to Chip Enable Low Min 25 25 30 30 ns

tWHGL Write Enable High to Output Enable Low Min 20 20 30 30 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 25 25 30 30 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 45 50 50 ns

tWPHWH Write Protect High to Write Enable High Min 45 45 50 50 ns

M28W160CT, M28W160CB

26/49

Figure 11. Write AC Waveforms, Chip Enable Controlled

DQ0-DQ15 COMMAND CMD or DATA STATUS REGISTER

VPP

VALIDA0-A19

tAVAV

tQVVPL

tAVEH tEHAX

PROGRAM OR ERASE

tWLEL tEHWH

tEHDX

tDVEH

tELEH

tEHEL

tVPHEH

POWER-UP AND

SET-UP COMMAND CONFIRM COMMAND

OR DATA INPUT STATUS REGISTER

READ

1st POLLING

tELQV

AI03815b

tWPHEH

tEHGL

tQVWPL

27/49

M28W160CT, M28W160CB

Table 17. W rite AC Characteristics, Chip Enable Controlled

Not e: 1. Sampled only, not 100% tested.

2. Appli cable if VPP is se en as a logic i nput (V PP < 3. 6V).

Symbol Alt Parameter M28W160C Unit

70 85 90 100

tAVAV tWC Write Cycle Time Min 70 85 90 100 ns

tAVEH tAS Address Valid to Chip Enable High Min 45 45 50 50 ns

tDVEH tDS Data Valid to Chip Enable High Min 45 45 50 50 ns

tEHAX tAH Chip Enable High to Address

Transition Min 0 0 0 0 ns

tEHDX tDH Chip Enable High to Data Transition Min 0 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 25 30 30 ns

tEHGL Chip Enable High to Output Enable

Low Min 25 25 30 30 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 50 50 ns

tELQV Chip Enable Low to Output Valid Min 70 85 90 100 ns

tQVVPL (1,2) Output Valid to VPP Low Min 0 0 0 0 ns

tQVWPL Data Valid to Write Protect Low Min 0 0 0 0 ns

tVPHEH (1) tVPS VPP High to Chip Enable High Min 200 200 200 200 ns

tWLEL tCS Write Enable Low to Chip Enable Low Min 0 0 0 0 ns

tWPHEH Write Protect High to Chip Enable High Min 45 45 50 50 ns

M28W160CT, M28W160CB

28/49

Figure 12. Power-Up and Reset AC Waveforms

Table 18. Po wer-Up and Reset AC Characteristics

No te : 1. The device Reset is po ssibl e but not gu aranteed if tPLPH < 10 0ns.

2. Sampled only, not 100% tested.

3. It is im portant to assert R P in order to al l ow prop er CPU init i al i zation during power up or reset .

Symbol Parameter Test Condition M28W160C Unit

70 85 90 100

tPHWL

tPHEL

tPHGL

Reset High to Write Enable Low, Chip

Enable Low, Output Enable Low

During

Program

and Erase Min 50 50 50 50 µs

others Min 30 30 30 30 ns

tPLPH(1,2) Reset Low to Reset High Min 100 100 100 100 ns

tVDHPH(3) Supply Voltages High to Reset High Min 50 50 50 50 µs

AI03537b

tPHWL

tPHEL

tPHGL

E, G

VDD, VDDQ

tVDHPH

tPHWL

tPHEL

tPHGL

tPLPH

Power-Up Reset

29/49

M28W160CT, M28W160CB

PACKAGE MECHANICAL

Figure 13. TSOP 48 - 48 lead Plastic Thin Small Outli ne, 12 x 20mm, Package Outline

Not e: Drawing is not to scale.

Table 19. TSOP48 - 48 lead Plastic Thin Small Ou tline, 12 x 20mm, Packag e Mech anical Data

Not e: Drawing is not to scale

Symbol mm inches

Typ Min Max Typ Min Max

A 1.20 0.0472

A1 0.05 0.15 0.0020 0.0059

A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106

C 0.10 0.21 0.0039 0.0083

D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 11.90 12.10 0.4685 0.4764

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0279

α0° 5° 0° 5°

N48 48

CP 0.10 0.0039

TSOP-a

1 N

N/2

DIE

LA1 α

M28W160CT, M28W160CB

30/49

Figure 14. TFBGA4 6 6. 39x6 .37 m m - 8x6 ball array, 0.75mm pitch, Bottom View Packa ge Ou tline

Drawing is not to scale.

Table 20. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data

E1E

bA2

BGA-Z13

ddd

BALL "A1"

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.200 0.0079

A2 1.000 0.0394

b 0.400 0.350 0.450 0.0157 0.0138 0.0177

D 6.390 6.290 6.490 0.2516 0.2476 0.2555

D1 5.250 – – 0.2067 – –

ddd 0.100 0.0039

E 6.370 6.270 6.470 0.2508 0.2469 0.2547

e 0.750 – – 0.0295 – –

E1 3.750 – – 0.1476 – –

FD 0.570 – – 0.0224 – –

FE 1.310 – – 0.0516 – –

SD 0.375 – – 0.0148 – –

SE 0.375 – – 0.0148 – –

31/49

M28W160CT, M28W160CB

Figure 15. TFBGA4 6 Daisy Chain - Pa ckag e Connections (Top view thro ug h package)

Figure 16. TFBGA46 Daisy Chain - PCB Connections pro posal (Top view through package)

AI03298

87654321

AI3299

87654321

START

POINT

END

POINT

M28W160CT, M28W160CB

32/49

PART NUMBERING

Table 21. Ordering Information Scheme

Table 22. Daisy Chain Orderi ng Sch eme

Note:Devices are shipped from the factor y with the memory content bits erased to ’1’. For a list of available

options (Speed, Pac kage, etc.) or for further inf ormation on any aspect of this device, please contact

the ST Sales Office nearest to you.

Example: M28W160CT 90 N 6 T

Device Type

M28

Operating Voltage

W = VDD = 2.7V to 3.6V; VDDQ = 1.65V to 3.6V

Device Function

160C = 16 Mbit (1 Mb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

85 = 85 ns

90 = 90 ns

100 = 100 ns

Package

N = TSOP48: 12 x 20 mm

ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

T = Tape & Reel 24mm Packing

S = Tape & Reel 16mm Packing

Example: M28W160C -ZB T

Device Type

M28W160C

Daisy Chain

-ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Option

T = Tape & Reel Packing

33/49

M28W160CT, M28W160CB

APPENDIX A. BLOCK ADDRESS TABLES

Table 23. Top Boot Block Addresses,

M28W160CT Table 24. Bottom Bo ot Block Addresses,

M28W160CB

#Size

(KWord) Address Range

0 4 FF000-FFFFF

1 4 FE000-FEFFF

2 4 FD000-FDFFF

3 4 FC000-FCFFF

4 4 FB000-FBFFF

5 4 FA000-FAFFF

6 4 F9000-F9FFF

7 4 F8000-F8FFF

8 32 F0000-F7FFF

99 32 E8000-EFFFF

10 32 E0000-E7FFF

11 32 D8000-DFFFF

12 32 D0000-D7FFF

13 32 C8000-CFFFF

14 32 C0000-C7FFF

15 32 B8000-BFFFF

16 32 B0000-B7FFF

17 32 A8000-AFFFF

18 32 A0000-A7FFF

19 32 98000-9FFFF

20 32 90000-97FFF

21 32 88000-8FFFF

22 32 80000-87FFF

23 32 78000-7FFFF

24 32 70000-77FFF

25 32 68000-6FFFF

26 32 60000-67FFF

27 32 58000-5FFFF

28 32 50000-57FFF

29 32 48000-4FFFF

30 32 40000-47FFF

31 32 38000-3FFFF

32 32 30000-37FFF

33 32 28000-2FFFF

34 32 20000-27FFF

35 32 18000-1FFFF

36 32 10000-17FFF

37 32 08000-0FFFF

38 32 00000-07FFF

#Size

(KWord) Address Range

38 32 F8000-FFFFF

37 32 F0000-F7FFF

36 32 E8000-EFFFF

35 32 E0000-E7FFF

34 32 D8000-DFFFF

33 32 D0000-D7FFF

32 32 C8000-CFFFF

31 32 C0000-C7FFF

30 32 B8000-BFFFF

29 32 B0000-B7FFF

28 32 A8000-AFFFF

27 32 A0000-A7FFF

26 32 98000-9FFFF

25 32 90000-97FFF

24 32 88000-8FFFF

23 32 80000-87FFF

22 32 78000-7FFFF

21 32 70000-77FFF

20 32 68000-6FFFF

19 32 60000-67FFF

18 32 58000-5FFFF

17 32 50000-57FFF

16 32 48000-4FFFF

15 32 40000-47FFF

14 32 38000-3FFFF

13 32 30000-37FFF

12 32 28000-2FFFF

11 32 20000-27FFF

10 32 18000-1FFFF

9 32 10000-17FFF

8 32 08000-0FFFF

7 4 07000-07FFF

6 4 06000-06FFF

5 4 05000-05FFF

4 4 04000-04FFF

3 4 03000-03FFF

2 4 02000-02FFF

1 4 01000-01FFF

0 4 00000-00FFF

M28W160CT, M28W160CB

34/49

APPENDIX B. COMMON FL ASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system sof tware t o query the de vic e to determine

various electrical and timing parameters, density

information and functions supported by t he mem-

ory. The system can interface easily with the de-

vice, enabling the s oftware to upgrad e itse lf when

necessary.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

structure is read from the m em ory. Tables 25 , 26,

27, 28, 29 and 30 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 30, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impos sible to change t he secu rity num -

ber after it has been written by ST. Issue a Read

command to return to Read mode.

Table 25. Query Structure Overview

Note: Query data are always presented on the lowest order data outputs.

Table 26. CFI Query Identification String

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ 8-DQ15 are ‘0’.

Offset Sub-section Name Description

00h Reserved Reserved for algorithm-specific information

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

P Primary Algorithm-specific Extended Query table Additional information specific to the Primary

Algorithm (optional)

A Alternate Algorithm-specific Extended Query table Additional information specific to the Alternate

Algorithm (optional)

Offset Data Description Value

00h 0020h Manufacturer Code ST

01h 88CEh

88CFh Device Code Top

Bottom

02h-0Fh reserved Reserved

10h 0051h "Q"

11h 0052h Query Unique ASCII String "QRY" "R"

12h 0059h "Y"

13h 0003h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm Intel

compatible

14h 0000h

15h 0035h Address for Primary Algorithm extended Query table (see Table 28) P = 35h

16h 0000h

17h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor -

specified algorithm supported (0000h means none exists) NA

18h 0000h

19h 0000h Address for Alternate Algorithm extended Query table

(0000h means none exists) NA

1Ah 0000h

35/49

M28W160CT, M28W160CB

Table 27. CFI Query System In terface Information

Offset Data Description Value

1Bh 0027h VDD Logic Supply Minimum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 2.7V

1Ch 0036h VDD Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 3.6V

1Dh 00B4h VPP [Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 11.4V

1Eh 00C6h VPP [Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV 12.6V

1Fh 0004h Typical time-out per single word program = 2n µs 16µs

20h 0004h Typical time-out for Double Word Program = 2n µs 16µs

21h 000Ah Typical time-out per individual block erase = 2n ms 1s

22h 0000h Typical time-out for full chip erase = 2n ms NA

23h 0005h Maximum time-out for word program = 2n times typical 512µs

24h 0005h Maximum time-out for Double Word Program = 2n times typical 512µs

25h 0003h Maximum time-out per individual block erase = 2n times typical 8s

26h 0000h Maximum time-out for chip erase = 2n times typical NA

M28W160CT, M28W160CB

36/49

Table 28. Device Geometry Definition

Offset W or d

Mode Data Description Value

27h 0015h Device Size = 2n in number of bytes 2 MByte

28h

29h 0001h

0000h Flash Device Interface Code description x16

Async.

2Ah

2Bh 0002h

0000h Maximum number of bytes in multi-byte program or page = 2n 4

2Ch 0002h Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size. 2

M28W160CT

2Dh

2Eh 001Eh

0000h Region 1 Information

Number of identical-size erase block = 001Eh+1 31

2Fh

30h 0000h

0001h Region 1 Information

Block size in Region 1 = 0100h * 256 byte 64 KByte

31h

32h 0007h

0000h Region 2 Information

Number of identical-size erase block = 0007h+1 8

33h

34h 0020h

0000h Region 2 Information

Block size in Region 2 = 0020h * 256 byte 8 KByte

M28W160CB

2Dh

2Eh 0007h

0000h Region 1 Information

Number of identical-size erase block = 0007h+1 8

2Fh

30h 0020h

0000h Region 1 Information

Block size in Region 1 = 0020h * 256 byte 8 KByte

31h

32h 001Eh

0000h Region 2 Information

Number of identical-size erase block = 001Eh+1 31

33h

34h 0000h

0001h Region 2 Information

Block size in Region 2 = 0100h * 256 byte 64 KByte

37/49

M28W160CT, M28W160CB

Table 29. Primary Algorithm- Speci fic Extended Qu ery Ta ble

No te : 1. See T able 26, of fset 15 for P pointer defin i tion.

Offset

P = 35h (1) Data Description Value

(P+0)h = 35h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

(P+1)h = 36h 0052h "R"

(P+2)h = 37h 0049h "I"

(P+3)h = 38h 0031h Major version number, ASCII "1"

(P+4)h = 39h 0030h Minor version number, ASCII "0"

(P+5)h = 3Ah 0066h Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0 Chip Erase supported (1 = Yes, 0 = No)

bit 1 Suspend Erase supported (1 = Yes, 0 = No)

bit 2 Suspend Program supported (1 = Yes, 0 = No)

bit 3 Legacy Lock/Unlock supported (1 = Yes, 0 = No)

bit 4 Queued Erase supported (1 = Yes, 0 = No)

bit 5 Instant individual block locking supported (1 = Yes, 0 = No)

bit 6 Protection bits supported (1 = Yes, 0 = No)

bit 7 Page mode read supported (1 = Yes, 0 = No)

bit 8 Synchronous read supported (1 = Yes, 0 = No)

bit 31 to 9 Reserved; undefined bits are ‘0’

Yes

(P+6)h = 3Bh 0000h

(P+7)h = 3Ch 0000h

(P+8)h = 3Dh 0000h

(P+9)h = 3Eh 0001h Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’ Yes

(P+A)h = 3Fh 0003h Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes

(P+B)h = 40h 0000h

(P+C)h = 41h 0030h VDD Logic Supply Optimum Program/Erase voltage (highest performance)

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

(P+D)h = 42h 00C0h VPP Supply Optimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

12V

(P+E)h = 43h 0001h Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available 01

(P+F)h = 44h 0080h Protection Field 1: Protection Description

This field describes user-available. One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection register Lock byte, the section’s first byte.

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7 Lock/bytes JEDEC-plane physical low address

bit 8 to 15 Lock/bytes JEDEC-plane physical high address

bit 16 to 23 "n " such that 2n = factory pre-programmed bytes

bit 24 to 31 "n " such that 2n = user programmable bytes

80h

(P+10)h = 45h 0000h 00h

(P+11)h = 46h 0003h 8 Byte

(P+12)h = 47h 0003h 8 Byte

(P+13)h = 48h Reserved

M28W160CT, M28W160CB

38/49

Table 30. Security Code Area

Offset Data Description

80h 00XX Protection Register Lock

81h XXXX

64 bits: unique device number

82h XXXX

83h XXXX

84h XXXX

85h XXXX

64 bits: User Programmable OTP

86h XXXX

87h XXXX

88h XXXX

39/49

M28W160CT, M28W160CB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figu re 17 . Program Fl owchar t an d Pseud o C od e

No te : 1. Stat us chec k of b1 ( Prote ct ed Blo ck ), b3 (VPP Inv al i d) an d b4 (Program Error) can be mad e after each program operati on or after

a sequence.

2. If an er ror is found, the St atus Re gi ster must be cleared before fu rther P rogram/ E rase Controll e r operat ions.

Write 40h or 10h

AI03538b

Start

Write Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

/*or writeToFlash (any_address, 0x10) ; */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

M28W160CT, M28W160CB

40/49

Figu re 18. Double Word Prog ra m Fl owc ha rt a nd Pseudo Co de

No te : 1. Stat us chec k of b1 ( Prote ct ed Blo ck ), b3 (VPP Inv al i d) an d b4 (Program Error) can be mad e after each program operati on or after

a sequence.

2. If an er ror is found, the St atus Re gi ster must be cleared before fu rther P rogram/ E rase operati ons.

3. Address 1 an d Ad dress 2 must be co nsecuti ve a ddresse s di f fering only for bi t A0.

Write 30h

AI03539b

Start

Write Address 1

& Data 1 (3)

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

Write Address 2

& Data 2 (3)

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

41/49

M28W160CT, M28W160CB

Figure 19. Program Suspend & Resume Flowchart and Pseudo Code

Write 70h

AI03540b

Read Status

YES

b7 = 1

YES

b2 = 1

Program Continues

Write D0h

Read data from

another address

Start

Write B0h

Program Complete

Write FFh

Read Data

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

}

Write FFh

M28W160CT, M28W160CB

42/49

Figure 20. Erase Flowcha rt and Pseudo Code

Note: If an error is found, the Status Regi st er must be cl eared before fu rther Program/Erase o perations.

Write 20h

AI03541b

Start

Write Block

Address & D0h

Read Status

YES

b7 = 1

YES

b3 = 0

YES

b4, b5 = 1

VPP Invalid

Error (1)

Command

Sequence Error (1)

b5 = 0 Erase Error (1)

End

YES

b1 = 0 Erase to Protected

Block Error (1)

YES

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

} while (status_register.b7== 0) ;

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

error_handler ( ) ;

}

43/49

M28W160CT, M28W160CB

Figure 21. Erase Suspend & Resume Flow chart and Pseud o Code

Write 70h

AI03542b

Read Status

YES

b7 = 1

YES

b6 = 1

Erase Continues

Write D0h

Read data from

another block

Program/Protection Program

Block Protect/Unprotect/Lock

Start

Write B0h

Erase Complete

Write FFh

Read Data

Write FFh

erase_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

M28W160CT, M28W160CB

44/49

Figu re 22 . Lo cki ng Operations Fl ow c hart and Pse ud o C ode

Write

01h, D0h or 2Fh

AI04364

Read Block

Lock States

YES

Locking

change

confirmed?

Start

Write 60h locking_operation_command (address, lock_operation) {

writeToFlash (any_address, 0x60) ; /*configuration setup*/

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

/*Check the locking state (see Read Block Signature table )*/

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

}

Write FFh

Write 90h

End

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

45/49

M28W160CT, M28W160CB

Figure 23. Protection Register Program Flowchart and Pseudo Code

No te : 1. Stat us chec k of b1 ( Prote ct ed Blo ck ), b3 (VPP Inv al i d) an d b4 (Program Error) can be mad e after each program operati on or after

a sequence.

2. If an er ror is found, the St atus Re gi ster must be cleared before fu rther P rogram/ E rase Controll e r operat ions.

Write C0h

AI04381

Start

Write Address

& Data

Read Status

YES

b7 = 1

YES

b3 = 0

b4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0xC0) ;

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

} while (status_register.b7== 0) ;

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

YES

End

YES

b1 = 0 Program to Protected

Block Error (1, 2)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

if (status_register.b4==1) /*program error */

error_handler ( ) ;

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

}

M28W160CT, M28W160CB

46/49

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 31. Write State Machine Current/Next, sheet 1 of 2.

Note: Cm d = Command, Elect .S g. = Elec tr oni c Signature, Ers = Er ase, Prog. = P rogram, Pr ot = Protection, Sus = S uspend.

Curre nt

State SR

bit 7

Data

When

Read

Command Input (and Next State)

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read Array “1” A rray Read Array Prog.Setup Ers. Se tup Read Array Read Sts. Read Array

Read

Status “1” Status Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Read

Elect.Sg. “1” Electronic

Signature Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Read CFI

Query “1” CFI Read Arra y Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Lo ck Setup “1” S tatus Lock Command Error Lock

(complete) Lock Cmd

Error Lock

(complete) Lock Command Error

Lock Cm d

Error “1” Status Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Lock

(complete) “1” Status Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Prot. Prog.

Setup “1 ” Status Protec t i on Regis ter Pro gram

Prot. Prog.

(continue) “0” S ta tus Protectio n Regis ter Progr am continue

Prot. Prog.

(complete) “1” Status Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Prog. Setup “1” Status Program

Program

(continue) “0” S ta tus P rogram (continue ) Prog. Sus

Re ad S ts Program (continu e)

Prog. Sus

Status “1” Status Prog. Sus

Read Arra y P rogram Suspend t o

Re ad A rray Program

(continue) P rog. Su s

Rea d Array Program

(continue) Prog. S u s

Read Sts Pro g. S u s

Read Array

Prog. Sus

Read Array “1” Array Prog. Sus

Read Arra y P rogram Suspend t o

Re ad A rray Program

(continue) P rog. Su s

Rea d Array Program

(continue) Prog. S u s

Read Sts Pro g. S u s

Read Array

Prog. Sus

Read

Elect.Sg. “1” Electronic

Signature Prog. Sus

Read Arra y P rogram Suspend t o

Re ad A rray Program

(continue) P rog. Su s

Rea d Array Program

(continue) Prog. S u s

Read Sts Pro g. S u s

Read Array

Prog. Sus

Read CFI “1” CFI Prog. Sus

Read Arra y P rogram Suspend t o

Re ad A rray Program

(continue) P rog. Su s

Rea d Array Program

(continue) Prog. S u s

Read Sts Pro g. S u s

Read Array

Program

(complete) “1” Status Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Erase

Setup “1” Status Erase Command Error Erase

(continue) Erase

CmdError Erase

(continue) Erase Command Error

Erase

Cmd.Error “1” Status Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

Erase

(continue) “0” S ta tus Eras e (continue) Erase Sus

Re ad S ts E rase (con tinue)

Eras e Sus

Rea d Sts “1” Status E rase S u s

Read Arra y Program

Setup Erase Sus

Read Array Erase

(continue) E rase Sus

Rea d Array Erase

(continue) Eras e Sus

Read Sts Er ase S us

Read Array

Eras e Sus

Read Array “1” Array Erase Su s

Read Arra y Program

Setup Erase Sus

Read Array Erase

(continue) E rase Sus

Rea d Array Erase

(continue) Eras e Sus

Read Sts Er ase S us

Read Array

Eras e Sus

Read

Elect.Sg. “1” Electronic

Signature Erase Sus

Read Arra y Program

Setup Erase Sus

Read Array Erase

(continue) E rase Sus

Rea d Array Erase

(continue) Eras e Sus

Read Sts Er ase S us

Read Array

Eras e Sus

Read CFI “1” CFI Erase S u s

Read Arra y Program

Setup Erase Sus

Read Array Erase

(continue) E rase Sus

Rea d Array Erase

(continue) Eras e Sus

Read Sts Er ase S us

Read Array

Erase

(complete) “1” Status Read Array Program

Setup Erase

Setup Rea d Array Read

Status Read Array

47/49

M28W160CT, M28W160CB

Table 32. Write State Machine Current/Next, sheet 2 of 2.

Note: Cm d = Command, Elect .S g. = Elec tr oni c Signature, Prog. = Program, Prot = P rot ection.

Current State

Command Input (and Next State)

Read Elect.Sg .

(90h)

Read CFI

Q u ery

(98h)

Lock S etup

(60h) Prot . Pr og .

Setup (C0h) Lock Confirm

(01h) Lock Down

Confirm (2Fh )

Unlock

Confirm

(D0h)

Read Arra y Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog.

Setup Read Arra y

Read Sta tus Re ad E l ect.Sg. R ead CFI Query Lock Set up Prot. Prog.

Setup Read Arra y

Read Ele ct .Sg. Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog.

Setup Read Arra y

Read CFI Query Read Elect .Sg. Read CFI Query Lock Setup Prot. Prog.

Setup Read Arra y

Lock Setup Lock Com m a nd Error Lock (compl et e)

Loc k Cmd Error Read Elect.Sg. Read CFI Query Lock Setup Prot. Prog.

Setup Read Arra y

Lock (c omplete) Re ad E l ect.Sg. R ead CFI Query Lock Set up Prot. Prog.

Setup Read Arra y

Prot. Prog.

Setup Prot ection Register Progr am

Prot. Prog.

(continue) Protection Register Program (continue)

Prot. Prog.

(complete) Read E l ect.Sg. Read CFI Query Lock Setup Prot. Prog.

Setup Read Arra y

Prog. Setup Program

Program

(continue) Program (continue)

Prog. Sus p end

Read Status Pr og. Suspend

Re ad E l ect.Sg. Prog. Suspend

Read CFI Query P rogram Su spend Read Array Program

(continue)

Pr og. Suspen d

Read Array Prog. Suspend

Re ad E l ect.Sg. Prog. Suspend

Read CFI Query P rogram Su spend Read Array Program

(continue)

Pr og. Suspen d

Read Elect.Sg. Prog. Suspend

Re ad E l ect.Sg. Prog. Suspend

Read CFI Query P rogram Su spend Read Array Program

(continue)

Pr og. Suspen d

Read CFI Pr og. Suspend

Re ad E l ect.Sg. Prog. Suspend

Read CFI Query P rogram Su spend Read Array Program

(continue)

Program

(complete) Read Elect.Sg. Read CFIQuery Lock Setup Prot. Prog.

Setup Read Arra y

Erase Setup Erase Command Error Erase

(continue)

Erase

Cmd.Error Read Elect.Sg. R ead CFI Query Lock Set up Prot. Prog.

Setup Read Arra y

Eras e (continue) Erase (continue)

Erase Suspend

Read Status Erase Suspend

Re ad E l ect.Sg. Erase Suspend

Read CFI Query Lo ck Setup Erase Suspend Read Array Erase

(continue)

Erase Suspend

Read Array Erase Suspend

Re ad E l ect.Sg. Erase Suspend

Read CFI Query Lo ck Setup Erase Suspend Read Array Erase

(continue)

Erase Suspend

Read Elect.Sg. Erase Suspend

Re ad E l ect.Sg. Erase Suspend

Read CFI Query Lo ck Setup Erase Suspend Read Array Erase

(continue)

Erase Suspend

Read CFI Query Erase Suspend

Re ad E l ect.Sg. Erase Suspend

Read CFI Query Lo ck Setup Erase Suspend Read Array Erase

(continue)

Eras e

(complete) Read E l ect.Sg. Read CFI Query Lock Setup Prot. Prog.

Setup Read Arra y

M28W160CT, M28W160CB

48/49

RE VISION HISTORY

Table 33. D ocum ent Revision History

Date Version Revision Details

January 2001 -01 First Issue

3/06/01 -02 Document type: from Preliminary Data to Data Sheet

70ns Speed Class added

24-Apr-2001 -03 Completely rewritten and restructured, 85ns speed class added.

29-May-2001 -04 Corrections made to CFI data.

31-May-2001 -05 Corrections to TFBGA46 package dimensions.

02-Jul-2001 -06 Corrections to Table 3. Commands (Lock, Unlock, Lock-Down)

31-Oct-2001 -07 VDDQ Maximum changed to 3.3V

Commands Table, Read CFI Query Address on 1st cycle changed to ‘X’ (Table 3)

tWHEL description clarified (Table 16)

16-May-2002 -08 VDDQ Maximum changed to 3.6V, TFBGA package dimensions added to description.

19-Feb-2003 8.1

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 08 equals 8.0). Revision History moved to end of document.

Data Retention parameter added to Table 7, Program, Erase Times and Program/

Erase Endurance Cycles. S option added to Table 21, Ordering Information Scheme,

and T option specified.

49/49

M28W160CT, M28W160CB

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