SLVS449A − DECEMBER 2002 − REVISED MAY 2003
FEATURES
DFully Integrated VCC and VPP Switching for
Single-Slot or Dual-Slot PC Card Interface
DP2C 3-Lead Serial Interface Compatible With
CardBus Controller
DMeets PC Card Standard
DRESET for System Initialization of PC Cards
D12-V Supplies Can Be Disabled Except During
12-V Flash Programming
DShort-Circuit and Thermal Protection
D24-Pin HTSSOP (PWP), 30-Pin SSOP (DB),
and 32-Pin TSSOP (DAP) Packages
DCompatible With 3.3-V, 5-V, and 12-V PC
Cards
DLow rDS(on) (95-mΩ, 5-V VCC Switch; 85-mΩ
3.3-V VCC Switch)
DSingle-Slot Switch: TPS2210A
Dual-Slot Switch: TPS2204A and TPS2206A
DBreak-Before-Make Switching
APPLICATIONS
DNotebook and Desktop Computers
DSet-Top Boxes
DPersonal Digital Assistants(PDAs)
DDigital Cameras
DBar Code Scanners
DESCRIPTION
The TPS2204A and TPS2206A PC CardBus
power-interface switches provide an integrated
power-management solution for two PC Card sockets.
The TPS2210A is a single-slot option for this family of
devices. These devices allow the controlled distribution of
3.3 V, 5 V, and 12 V to each card slot. The current-limiting
and thermal-protection features eliminate the need for
fuses. Current-limit reporting helps the user isolate a
system fault. The switch rDS(on) and current-limit values
are set for the peak and average current requirements
stated i n the PC Card specification, and are optimized for
cost.
The TPS2206A is pin and/or functionally compatible with
the TPS2206, TPS2216, TPS2216A, TPS2226,
TPS2226A, and TPS2228 with a few exceptions, as
shown in the Available Options table.
AVAILABLE OPTIONS OF THE TPS2206A PIN COMPATABLE SWITCHES
PART NUMBER
INDEPENDENT
PIN VARIATION
INPUT
PART NUMBER
INDEPENDENT
VPP SWITCHING RESET RESET SHDN MODE STBY
INPUT
VOLTAGES
TPS2206 No Yes Yes No No No 3.3 V, 5 V, 12 V
TPS2206A No Yes No Yes No No 3.3 V, 5 V, 12 V
TPS2216 Yes/No(1) Yes Yes No Yes Yes 3.3 V, 5 V, 12 V
TPS2216A Yes/No(1) Yes Yes No Yes Yes 3.3 V, 5 V, 12 V
TPS2226 Yes Yes No Yes No No 3.3 V, 5 V, 12 V
TPS2226A Yes Yes No Yes No No 3.3 V, 5 V, 12 V
TPS2228 Yes Yes No Yes No No 1.8 V, 3.3 V, 5 V
(1) Selected by MODE pin.
! "#$ ! %#&'" ($) (#"!
" !%$""! %$ *$ $! $+! !#$! !(( ,-)
(#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
P2C is a trademark of Texas Instruments.
PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002 − 2003, Texas Instruments Incorporated
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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2
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION PACKAGED DEVICES
TAPLASTIC SMALL OUTLINE
(DB) POWERPAD PLASTIC SMALL
OUTLINE (DAP−32) POWERPAD PLASTIC SMALL
OUTLINE (PWP−24)
−40°C to 85°C TPS2206ADB TPS2206ADAP TPS2204APWP
TPS2210APWP
(1) The DB, PWP, and DAP packages are available taped and reeled. Add R suffix to device type (e.g., TPS2206ADBR) for taped and reeled.
PACKAGE DISSIPATION RATINGS
PACKAGE(1) TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
DB (30) 821.46 mW 10.95 mW/°C328.58 mW 164.29 mW
DAP (32) 3191.4 mW 42.55 mW/°C1276.5 mW 638.29 mW
PWP (24) 2491.6 mW 33.22 mW/°C996.67 mW 498.33 mW
(1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).
ABSOLUTE MAXIMUM RATINGS
over o p e r ating free-air temperature range unless otherwise noted(1)
UNITS
VI(3.3V)−0.3 V to 5.5 V
Input voltage range for card power VI(5V) −0.3 V to 5.5 V
Input voltage range for card power
VI(12V) −0.3 V to 14 V
Logic input/output voltage −0.3 V to 6 V
Output voltage
VO(xVCC) −0.3 V to 6 V
Output voltage
VO(xVPP) −0.3 V to 14 V
Continuous total power dissipation See Dissipation Rating Table
Output current
IO(xVCC) Internally Limited
Output current
IO(xVPP) Internally Limited
Operating virtual junction temperature range, TJ−40°C to 100 °C
Storage temperature range, TSTG −55°C to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) 260 °C
OC sink current 10 mA
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PowerPAD is a trademark of Texas Instruments.
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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3
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Input voltage, VI(3.3V) is required for all circuit operations. 5 V and
VI(3.3V)(1) 3 3.6
Input voltage, VI(3.3V) is required for all circuit operations. 5 V and
12 V are only required for their respective functions.
VI(5V) 3 5.5 V
12 V are only required for their respective functions.
VI(12V) 7 13.5
V
Output current, IO
IO(xVCC) at TJ = 100°C 1 A
Output current, I
OIO(xVPP) at TJ = 100°C 100 mA
Clock frequency, f(clock) 2.5 MHz
Data 200
Pulse duration, tw
Latch 250
ns
Pulse duration, t
wClock 100
ns
Reset 100
Data-to-clock hold time, th (see Figure 2) 100 ns
Data-to-clock setup time, tsu (see Figure 2) 100 ns
Latch delay time, td(latch) (see Figure 2) 100 ns
Clock delay time, td(clock) (see Figure 2) 250 ns
Operating virtual junction temperature, TJ (maximum to be calculated at worst case PD at 85°C ambient) −40 100 °C
(1) It is understood that for VI(3.3V)< 3 V, voltages within the absolute maximum ratings applied to pin 5 V or pin 12 V will not damage the IC.
ELECTRICAL CHARACTERISTICS
TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted)
POWER SWITCH
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
3.3V to xVCC(2)
IO = 750 mA each 85 110
3.3V to xVCC(2)
IO = 750 mA each, TJ = 100°C110 140
mΩ
Static drain-
5V to xVCC(2)
IO = 500 mA each 95 130
m
Ω
rDS(on)
Static drain-
source on-state
5V to xVCC(2)
IO = 500 mA each, TJ = 100°C 120 160
r
DS(on)
source on-state
resistance
3.3V or 5V to xVPP(2)
IO = 50 mA each 0.8 1
resistance
3.3V or 5V to xVPP(2)
IO = 50 mA each, TJ = 100°C 1 1.3
Ω
12V to xVPP(2)
IO = 50 mA each 2 2.5 Ω
12V to xVPP(2)
IO = 50 mA each, TJ = 100°C 2.5 3.4
Output discharge
Discharge at xVCC IO(disc) = 1 mA 0.5 0.7 1
kΩ
Output discharge
resistance Discharge at xVPP IO(disc) = 1 mA 0.2 0.4 0.5
k
Ω
Limit (steady-state value),
output powered into a short
IOS(xVCC) 1 1.4 2 A
IOS
Short-circuit output current
output powered into a short
circuit IOS(xVPP) 120 200 300 mA
I
OS
Short-circuit output current
Limit (steady-state value),
output powered into a short
IOS(xVCC) 1 1.4 2 A
output powered into a short
circuit, TJ = 100°CIOS(xVPP) 120 200 300 mA
Thermal shutdown
(2)
Thermal trip point, TJRising temperature 135
°C
Thermal shutdown
temperature(2) Hysteresis, TJ10 °
C
Current-limit response time (3)(4)
5V to xVCC = 5 V, with 100-m Ω short to GND 10
s
Current-limit response time (3)(4)
5V to xVPP = 5 V, with 100-mΩ short to GND 3µ
s
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
(2) TPS2204A and TPS2206A: two switches on. TPS2210A: one switch on.
(3) Specified by design; not tested in production.
(4) From application of short to 110% of final current limit.
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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4
ELECTRICAL CHARACTERISTICS Continued
TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Normal
II(3.3V)
VO(xVCC) = VO(xVPP) = 3.3 V and
140 200
Normal
operation
II(5V) VO(xVCC) = VO(xVPP) = 3.3 V and
also for RESET = 0 V
8 12
II
Input current,
operation
II(12V)
also for RESET = 0 V
100 180
A
I
I
Input current,
quiescent
Shutdown
II(3.3V) 0.3 2 µ
A
quiescent
Shutdown
mode
II(5V) V
O
(xVCC) = V
O
(xVPP) = Hi-Z 0.1 2
mode
II(12V)
VO(xVCC) = VO(xVPP) = Hi-Z
0.3 2
VO(xVCC) = 5 V,
10
Ilkg
Leakage current,
Shutdown mode
VO(xVCC) = 5 V,
VI(5V) = VI(12V) = 0 V TJ = 100°C 50
A
I
lkg
Leakage current,
output of f state
Shutdown mode
VO(xVPP) = 12 V,
10 µ
A
output of f state
VO(xVPP) = 12 V,
VI(5V) = VI(12V) = 0 V TJ = 100°C 50
LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
II(RESET)(1)
RESET = 5.5 V −1 1
I
I(RESET)
(1)
RESET = 0 V −30 −20 −10
II(SHDN)(1)
SHDN = 5.5 V −1 1
I
I
Input current, logic
I
I(SHDN)
(1)
SHDN = 0 V −50 −3 µA
II
Input current, logic
II(LATCH)(1)
LATCH = 5.5 V 50
µA
I
I(LATCH)
(1)
LATCH = 0 V −1 1
II(CLOCK, DATA) 0 V to 5.5 V −1 1
VIH High-level input voltage, logic 2 V
VIL Low-level input voltage, logic 0.8 V
VO(sat) Output saturation voltage at OC IO = 2 mA 0.14 0.4 V
Ilkg Leakage current at OC VO(/OC) = 5.5 V 0 1 µA
(1) LATCH has low current pulldown. RESET and SHDN have low-current pullup.
UVLO AND POR (POWER-ON RESET)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI(3.3V) Input voltage at 3.3V pin, UVLO 3.3-V level below which all switches are Hi-Z 2.4 2.7 2.9 V
Vhys(3.3V) UVLO hysteresis voltage at VA (1) 100 mV
VI(5V) Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z 2.3 2.5 2.9 V
Vhys(5V) UVLO hysteresis voltage at 5 V(1) 100 mV
tdf Delay time for falling response, UVLO(1) Delay from voltage hit (step from 3 V to 2.3 V)
to Hi-Z control (90% VG to GND) 4µs
VI(POR) Input voltage, power-on reset(1) 3.3-V voltage below which POR is asserted
causing a RESET internally with all line
switches open and all discharge switches
closed.
1.7 V
(1) Specified by design; not tested in production.
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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5
SWITCHING CHARACTERISTICS
VCC = 5 V, T A = 25°C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V (not applicable for TPS2223A) all outputs unloaded (unless otherwise noted)
PARAMETER(1) LOAD CONDITION TEST CONDITIONS(2) MIN TYP MAX UNIT
(3)
CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF,
VO(xVCC) = 5 V 0.9
tr
Output rise times(3)
CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF,
IO(xVCC) = 0 A, IO(xVPP) = 0 A VO(xVPP) = 12 V 0.26
ms
t
r
Output rise times(3)
CL(xVCC)= 150 µF, CL(xVPP)= 10 µF,
VO(xVCC) = 5 V 1.1
ms
CL(xVCC)= 150 µF, CL(xVPP)= 10 µF,
IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA VO(xVPP) = 12 V 0.6
(3)
CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF,
VO(xVCC) = 5 V,
Discharge switches ON 0.5
tfOutput fall times
(3)
CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF,
IO(xVCC) = 0 A, IO(xVPP) = 0 A VO(xVPP) = 12 V,
Discharge switches ON 0.2 ms
f
CL(xVCC)= 150 µF, CL(xVPP)= 10 µF,
VO(xVCC) = 5 V 2.35
CL(xVCC)= 150 µF, CL(xVPP)= 10 µF,
IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA VO(xVPP) = 12 V 3.9
Latch↑ to xVPP (12 V)
tpdon 2
Latch↑ to xVPP (12 V)
tpdoff 0.62
Latch↑ to xVPP (5 V)
tpdon 0.77
Latch
↑
to xVPP (5 V)
tpdoff 0.51
CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF,
Latch↑ to xVPP (3.3 V)
tpdon 0.75
ms
CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF,
IO(xVCC) = 0 A, IO(xVPP) = 0 A
Latch
↑
to xVPP (3.3 V)
tpdoff 0.52
ms
IO(xVCC) = 0 A, IO(xVPP) = 0 A
Latch↑ to xVCC (5 V)
tpdon 0.3
Latch
↑
to xVCC (5 V)
tpdoff 2.5
Latch↑ to xVCC (3.3V)
tpdon 0.3
tpd
Propagation delay
(3)
Latch
↑
to xVCC (3.3V)
tpdoff 2.8
t
pd
Propagation delay
times(3)
Latch↑ to xVPP (12 V)
tpdon 2.2
times
Latch↑ to xVPP (12 V)
tpdoff 0.8
Latch↑ to xVPP (5 V)
tpdon 0.8
Latch
↑
to xVPP (5 V)
tpdoff 0.6
CL(xVCC)= 150 µF, CL(xVPP)= 10 µF,
Latch↑ to xVPP (3.3 V)
tpdon 0.8
ms
CL(xVCC)= 150 µF, CL(xVPP)= 10 µF,
IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA
Latch
↑
to xVPP (3.3 V)
tpdoff 0.6
ms
IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA
Latch↑ to xVCC (5 V)
tpdon 0.6
Latch
↑
to xVCC (5 V)
tpdoff 2.5
Latch↑ to xVCC (3.3V)
tpdon 0.5
Latch
↑
to xVCC (3.3V)
tpdoff 2.6
(1) Refer to Parameter Measurement Information in Figure 1.
(2) No card inserted, assumes a 0.1-µF output capacitor (see Figure 1).
(3) Specified by design; not tested in production.
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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6
PIN ASSIGNMENTS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC − No internal connection
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TPS2206A
DB PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
AVCC
GND
NC
RESET
3.3V
5V
NC
NC
NC
NC
SHDN
12V
BVPP
BVCC
BVCC
BVCC
NC
OC
3.3V
3.3V
1
5V
5V
NC
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
AVCC
GND
RESET
NC
3.3V
5V
NC
NC
NC
NC
NC
SHDN
12V
BVPP
BVCC
BVCC
BVCC
OC
NC
3.3V
3.3V
TPS2206A
DAP PACKAGE
(TOP VIEW)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TPS2210A
PWP PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
GND
RESET
NC
NC
NC
SHDN
12V
NC
NC
NC
NC
OC
NC
3.3V
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
TPS2204A
PWP PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
GND
RESET
5V
NC
NC
SHDN
12V
BVPP
BVCC
BVCC
NC
OC
3.3V
3.3V
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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7
TERMINAL FUNCTIONS
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME TPS2204A TPS2206A TPS2210A
I/O
DESCRIPTION
NAME
PWP DB DAP PWP
3.3V 13, 1 4 15, 16, 17 16, 17, 18 13 I 3.3-V input for card power and chip power
5V 1, 2, 24 1, 2, 30 1, 2, 32 1, 2 I5-V VCC input for card power
12V 7, 20 7, 24 8, 25 7, 20 I12-V VPP input for card power (xVPP). The two 12-V pins must be
externally connected.
AVCC 9, 10 9, 10, 11 10, 11, 12 9, 10 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card.
AVPP 8 8 9 8 O Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
to card.
BVCC 17, 18 20, 21, 22 21, 22, 23 −− O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance.
BVPP 19 23 24 −− O Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance.
CLOCK 4 4 5 4 I Logic-level clock for serial data word
DATA 3 3 4 3 I Logic-level serial data word
GND 11 12 13 11 Ground
LATCH 5 5 6 5 I Logic-level latch for serial data word, internal pulldown
NC 6, 16, 22,
23 13, 19,
26−29 3, 7, 15,
19, 27−31
6, 14,
16 − 19,
22−24 No internal connection
OC 15 18 20 15 O Open-drain overcurrent reporting output that goes low when an
overcurrent condition exists.
An external pullup is required.
SHDN 21 25 26 21 I Hi-Z (open) all switches. Identical function to serial D8. Asynchronous
active-low command, internal pullup
RESET 12 14 14 12 I Logic-level RESET input active low. Do not connect if terminal 6 is
used.
TYPICAL PC CARD POWER−DISTRIBUTION APPLICATION
TPS2206A
3
12 V
5 V
3.3 V
Power Supply
Supervisor
PCMCIA
Controller
12 V
5 V
3.3 V
RESET
SHDN
Serial
Interface
OC
AVPP
AVCC
AVCC
AVCC
BVPP
BVCC
BVCC
BVCC
VPP1
VPP2
VCC
VCC
VPP1
VPP2
VCC
VCC
PC
Card A
PC
Card b
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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8
PARAMETER MEASUREMENT INFORMATION
50%
LATCH VDD
GND
10%
90%
tpd(on)
GND
VO(xVPP)
Propagation Delay (xVPP)
50%
LATCH VDD
GND
10%
90%
tpd(on)
GND
VO(xVCC)
Propagation Delay (xVCC)
10%
90%
tr
GND
VO(xVPP)
Rise/Fall Time (xVPP)
tf
10%
90%
tr
GND
VO(xVCC)
Rise/Fall Time (xVCC)
tf
50% VDD
GND
10%
90%
ton
GND
VO(xVCC)
Turnon/off Time (xVCC)
xVPP
VOLTAGE WAVEFORMS
LOAD CIRCUIT (xVPP)
IO(xVPP)
xVCC
50%
LATCH VDD
GND
10%
90%
ton
GND
VO(xVPP)
Turnon/off Time (xVPP)
IO(xVCC)
tpd(off)
tpd(off)
toff toff
LOAD CIRCUIT (xVCC)
VI(12V/5V/3.3V) VI(5V/3.3V)
VI(12V/5V/3.3V) VI(5V/3.3V)
VI(12V/5V/3.3V) VI(5V/3.3V)
LATCH
Figure 1. Test Circuits and Voltage Waveforms
D8 D7 D6 D5 D4 D3 D2 D1 D0DATA
LATCH
CLOCK
NOTE:Data is clocked in on the positive edge of the clock. The latch should occur before the next positive leading edge of the clock. For definition
of D0to D8, see the control logic table.
Figure 2. Serial-Interface Timing for TPS2206A
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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9
TABLE OF GRAPHS
FIGURE
Short-circuit response, short applied to powered-on 5-V xVCC-switch output vs Time 3
Short-circuit response, short applied to powered-on 12-V xVPP-switch output vs Time 4
OC response with ramped overcurrent-limit load on 5-V xVCC-switch output vs Time 5
OC response with ramped overcurrent-limit load on 12-V xVPP-switch output vs Time 6
Turnon propagation delay time, xVCC (CL = 150 µF) vs Junction temperature 7
Turnoff propagation delay time, xVCC (CL = 150 µF) vs Junction temperature 8
Turnon propagation delay time, xVPP (CL = 10 µF) vs Junction temperature 9
Turnoff propagation delay time, xVPP (CL = 10 µF) vs Junction temperature 10
Turnon propagation delay time, xVCC (T J = 25°C) vs Load capacitance 11
Turnoff propagation delay time, xVCC (TJ = 25°C) vs Load capacitance 12
Turnon propagation delay time, xVPP (TJ = 25°C) vs Load capacitance 13
Turnoff propagation delay time, xVPP (TJ = 25°C) vs Load capacitance 14
Rise time, xVCC (CL = 150 µF) vs Junction temperature 15
Fall time, xVCC (CL = 150 µF) vs Junction temperature 16
Rise time, xVPP (CL = 10 µF) vs Junction temperature 17
Fall time, xVPP (CL = 10 µF) vs Junction temperature 18
Rise time, xVCC (TJ = 25°C) vs Load capacitance 19
Fall time, xVCC (TJ = 25°C) vs Load capacitance 20
Rise time, xVPP (TJ = 25°C) vs Load capacitance 21
Fall time, xVPP (TJ = 25°C) vs Load capacitance 22
Figure 3
SHORT-CIRCUIT RESPONSE,
SHORT APPLIED TO POWERED-ON 5-V
xVCC-SWITCH OUTPUT
vs
TIME
100 200 300 400 500
t − Time − µs
0
VO(/OC)
5 V/div
IO(VCC)
5 A/div
VIN(5V)
2 V/div
Figure 4
SHORT-CIRCUIT RESPONSE,
SHORT APPLIED TO POWERED-ON 12-V
xVPP-SWITCH OUTPUT
vs
TIME
12345
t − Time − ms
0
VO(/OC)
2 V/div
IO(xVPP)
2 A/div
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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10
Figure 5
OC RESPONSE WITH RAMPED
OVERCURRENT-LIMIT LOAD ON 5-V
xVCC-SWITCH OUTPUT
vs
TIME
10 20 30 40 50
t − Time − ms
0
VO(/OC)
5 V/div
IO(xVCC)
1 A/div
Figure 6
OC RESPONSE WITH RAMPED
OVERCURRENT-LIMIT LOAD ON 12-V
xVPP-SWITCH OUTPUT
vs
TIME
246810
t − Time − ms
0
VO(/OC)
5 V/div
IO(xVPP)
100 mA/div
Figure 7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
−50 −20 10 40 70 100
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
− Turnon Propagation Delay Time, xVCC − ms
TURNON PROPAGATION DELAY TIME, xVCC
vs
JUNCTION TEMPERATURE
tpd(on)
TJ − Junction Temperature − °C
Figure 8
2.25
2.3
2.35
2.4
2.45
2.5
2.55
2.6
−50 −20 10 40 70 100
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
TURNOFF PROPAGATION DELAY TIME, xVCC
vs
JUNCTION TEMPERATURE
tpd(off)
TJ − Junction Temperature − °C
− Turnoff Propagation Delay Time, xVCC − ms
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11
Figure 9
0
0.5
1
1.5
2
2.5
3
−50 −20 10 40 70 100
TURNON PROPAGATION DELAY TIME, xVPP
vs
JUNCTION TEMPERATURE
tpd(on)
TJ − Junction Temperature − °C
xVPP = 12 V
IO = 0.05 A
CL = 10 µF
− Turnon Propagation Delay Time, xVPP − m s
Figure 10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
−50 −20 10 40 70 100
− Turnoff Propagation Delay Time, xVCC − ms
TURNOFF PROPAGATION DELAY TIME, xVPP
vs
JUNCTION TEMPERATURE
tpd(off)
TJ − Junction Temperature − °C
xVCC = 12 V
IO = 0.05 A
CL = 10 µF
Figure 11
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.1 1 10 100 1000
− Turnon Propagation Delay Time, xVCC − ms
TURNON PROPAGATION DELAY TIME, xVCC
vs
LOAD CAPACITANCE
tpd(on)
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
Figure 12
2.25
2.3
2.35
2.4
2.45
2.5
2.55
0.1 1 10 100 1000
TURNOFF PROPAGATION DELAY TIME, xVCC
vs
LOAD CAPACITANCE
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
tpd(off) − Turnoff Propagation Delay Time, xVCC − ms
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Figure 13
1.95
2
2.05
2.1
2.15
2.2
2.25
0.1 1 10
− Turnon Propagation Delay Time, xVPP − m s
TURNON PROPAGATION DELAY TIME, xVPP
vs
LOAD CAPACITANCE
tpd(on)
xVPP = 1 2 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
Figure 14
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1 1 10
− Turnoff Propagation Delay Time, xVPP − m s
TURNOFF PROPAGATION DELAY TIME, xVPP
vs
LOAD CAPACITANCE
tpd(off)
xVPP = 12 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
Figure 15
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.22
−50 −20 10 40 70 100
RISE TIME, xVCC
vs
JUNCTION TEMPERATURE
− Rise Time, xVCC − ms
tr
TJ − Junction Temperature − °C
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
Figure 16
2.34
2.35
2.36
2.37
2.38
2.39
2.4
2.41
−50 −20 10 40 70 100
− Fall Time xVCC − ms
tf
FALL TIME, xVCC
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
xVCC = 5 V
IO = 0.75 A
CL = 150 µF
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Figure 17
0.575
0.58
0.585
0.59
0.595
0.6
0.605
−50 −20 10 40 70 100
RISE TIME, xVPP
vs
JUNCTION TEMPERATURE
− Rise T ime xVPP − ms
tr
TJ − Junction Temperature − °C
xVPP = 12 V
IO = 0.05 A
CL = 10 µF
Figure 18
3.85
3.9
3.95
4
4.05
4.1
4.15
−50 −20 10 40 70 100
FALL TIME, xVPP
vs
JUNCTION TEMPERATURE
− Fall T ime, xVPP − m s
tf
TJ − Junction Temperature − °C
xVPP = 12 V
IO = 0.05 A
CL = 10 µF
Figure 19
0
0.2
0.4
0.6
0.8
1
1.2
0.1 1 10 100 1000
RISE TIME, xVCC
vs
LOAD CAPACITANCE
− Rise Time, xVCC − ms
tr
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
Figure 20
0
0.5
1
1.5
2
2.5
0.1 1 10 100 1000
− Fall Time xVCC − ms
tf
FALL TIME, xVCC
vs
LOAD CAPACITANCE
xVCC = 5 V
IO = 0.75 A
TJ = 25°C
CL − Load Capacitance − µF
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Figure 21
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.1 1 10
RISE TIME, xVPP
vs
LOAD CAPACITANCE
− Rise T ime, xVPP − ms
tr
xVPP = 1 2 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
Figure 22
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0.1 1 10
− Fall T ime, xVPP − m s
tf
FALL TIME, xVPP
vs
LOAD CAPACITANCE
xVPP = 12 V
IO = 0.05 A
TJ = 25°C
CL − Load Capacitance − µF
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Input current, xVCC = 3.3 V 23
I
I
Input current, xVCC = 5 V vs Junction temperature 24
II
Input current, xVPP = 12 V
vs Junction temperature
25
Static drain-source on-state resistance, 3.3 V to xVCC switch 26
r
DS(on)
Static drain-source on-state resistance, 5 V to xVCC switch vs Junction temperature 27
rDS(on)
Static drain-source on-state resistance, 12 V to xVPP switch
vs Junction temperature
28
xVCC switch voltage drop, 3.3-V input 29
V
O
xVCC switch voltage drop, 5-V input vs Load current 30
VO
xVPP switch voltage drop, 12-V input
vs Load current
31
Short-circuit current limit, 3.3 V to xVCC 32
I
OS
Short-circuit current limit, 5 V to xVCC vs Junction temperature 33
IOS
Short-circuit current limit, 12 V to xVPP
vs Junction temperature
34
Figure 23
0
20
40
60
80
100
120
140
160
180
−50 −20 10 40 70 100
INPUT CURRENT, xVCC = 3.3 V
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
II− Input Current, xVCC = 3.3 V − Aµ
Figure 24
0
2
4
6
8
10
12
14
−50 −20 10 40 70 100
INPUT CURRENT, xVCC = 5 V
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
II− Input Current, xVCC = 5 V − Aµ
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Figure 25
0
20
40
60
80
100
120
−50 −20 10 40 70 100
INPUT CURRENT, xVPP = 12 V
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
II− Input Current, xVPP = 12 V − Aµ
Figure 26
0
0.02
0.04
0.06
0.08
0.1
0.12
−50 −20 10 40 70 10
0
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
3.3 V TO xVCC SWITCH
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
Ω
rDS(on) − Static Drain-Source On-State Resistance,
3.3 V to xVCC Switch −
Figure 27
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
−50 −20 10 40 70 100
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
5 V TO xVCC SWITCH
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
Ω
rDS(on) − Static Drain-Source On-State Resistance,
5 V to xVCC Switch −
Figure 28
0
0.5
1
1.5
2
2.5
3
−50 −20 10 40 70 10
0
STATIC DRAIN-SOURCE ON-STATE RESISTANCE,
12 V TO xVPP SWITCH
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
Ω
rDS(on) − Static Drain-Source On-State Resistance,
12 V to xVPP Switch −
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Figure 29
0
0.02
0.04
0.06
0.08
0.1
0.12
0 0.2 0.4 0.6 0.8 1
TJ = −40°C
TJ = 85°C
TJ = 100°C
xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT
vs
LOAD CURRENT
IL − Load Current − A
− xVCC Switch Voltage Drop, 3.3-V Input − VVO
TJ = 25°C
TJ = 0°C
Figure 30
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.2 0.4 0.6 0.8 1
xVCC SWITCH VOLTAGE DROP, 5-V INPUT
vs
LOAD CURRENT
IL − Load Current − A
− xVCC Switch Voltage Drop, 5-V Input − VVO
TJ = −40°C
TJ = 85°C
TJ = 100°C
TJ = 25°C
TJ = 0°C
Figure 31
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.01 0.02 0.03 0.04 0.05
xVPP SWITCH VOLTAGE DROP, 12-V INPUT
vs
LOAD CURRENT
IL − Load Current − A
− xVPP Switch Voltage Drop, 12-V Input − VVO
TJ = −40°C
TJ = 85°C
TJ = 100°C
TJ = 25°C
TJ = 0°C
Figure 32
1.355
1.36
1.365
1.37
1.375
1.38
1.385
1.39
1.395
−50 −20 10 40 70 100
SHORT-CIRCUIT CURRENT LIMIT, 3.3 V T O xVCC
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
IOS− Short-Circuit Current Limit, 3.3 V to xVCC − A
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Figure 33
1.385
1.39
1.395
1.4
1.405
1.41
1.415
1.42
1.425
1.43
1.435
−50 −20 10 40 70 100
SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
IOS− Short-Circuit Current Limit, 5 V to xVCC − A
Figure 34
0.19
0.192
0.194
0.196
0.198
0.2
0.202
0.204
0.206
0.208
−50 −20 10 40 70 100
xVPP = 12 V
SHORT-CIRCUIT CURRENT LIMIT, 12 V T O xVPP
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
IOS− Short-Circuit Current Limit, 12 V to xVPP − A
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19
APPLICATION INFORMATION
OVERVIEW
PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly
took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, and hard-disk versions were
soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for
a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card
International Association) was established, comprising members from leading computer, software, PC Card, and
semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from
different vendors would be transparently compatible.
PC CARD POWER SPECIFICATION
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth
by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68
terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple
VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified
as separate signals, but are normally tied together in the host to form a single node to minimize voltage losses. Card primary
power is supplied through the VCC terminals; flash-memory programming and erase voltage are supplied through the Vpp
terminals.
DESIGNING FOR VOLTAGE REGULATION
The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In a typical PC
power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV). Also, a voltage drop
from the power supply to the PC Card results from resistive losses, VPCB, in the PCB traces and the PCMCIA connector.
A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the
allowable voltage drop, VDS, for the device would be the PCMCIA voltage regulation less the power supply regulation and
less the PCB and connector resistive drops:
VDS +VO(reg)–VPS(reg)–VPCB
Typically, this would leave 100 mV for the allowable voltage drop across the TPS2204A, TPS2206A, or TPS2210A. The
voltage drop is the output current multiplied by the switch resistance of the device. Therefore, the maximum output current,
IO max, that can be delivered to the PC Card in regulation is the allowable voltage drop across the device, divided by the
output-switch resistance.
IOmax +VDS
rDS(on)
The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Card specification
within regulation over the operating temperature range. The xVPP outputs have been designed to deliver 100 mA
continuously.
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
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20
OVERCURRENT AND OVERTEMPERATURE PROTECTION
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against
short-circuited cards that could lead to power-supply or PCB trace damage. Even extremely robust systems could undergo
rapid battery discharge into a damaged PC Card, resulting in the rather sudden and unacceptable loss of system power.
The reliability of fused systems is poor, in comparison, as blown fuses require troubleshooting and repair, usually by the
manufacturer.
The TPS2204A, TPS2206A, and TPS2210A take a two-pronged approach to overcurrent protection. Overcurrent
protection is designed to activate if an output is shorted or when an overcurrent condition is present when switches are
powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike sense resistors
or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced.
Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output
current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from 1 A to 2.2
A, typically around 1.6 A; the xVPP outputs limit from 100 mA to 250 mA, typically around 200 mA.
Second, when an overcurrent condition is detected, the device asserts an active low OC signal that can be monitored by
the microprocessor or controller to initiate diagnostics and/or send the user a warning message. If an overcurrent condition
persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down
all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis.
Thermal limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings.
During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush current into a large
load capacitance, faulty card, or connector.
12-V SUPPLY NOT REQUIRED
Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which requires that
power be present at all times. The TPS2204A, TPS2206A, and TPS2210A offer considerable power savings by using an
internal charge pump to generate the required higher gate drive voltages from the 3.3-V input. Therefore, the external 12-V
supply can be disabled except when needed by the PC Card in the slot, thereby extending battery lifetime. A special feature
in the 12-V circuitry actually helps to reduce the supply current demanded from the 3.3-V input. When 12 V is supplied and
requested at the Vpp output, a voltage selection circuit draws the charge-pump drive current for the 12-V FETs from the
12-V input. This selection is automatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper
operation of this feature, a minimum 3.3-V input capacitance of 4.7 µF is recommended, and a minimum 12-V input ramp-up
rate of 12 V/50 ms (240 V/s) is required. Additional power savings are realized during a software shutdown in which
quiescent current drops to a maximum of 1 µA.
BACKWARD COMPATIBILITY
The TPS2206A is backward compatible with the TPS2206 product, with the following considerations. An active low /SHDN
is added to provide fast shutdown capability. Also, the TPS2206A does not have the active−high RESET input, which is left
as no connect.
3.3–V input is required for device operation of TPS2206A.
VOLTAGE-TRANSITIONING REQUIREMENT
PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and
increase logic speeds. The TPS2204A, TPS2206A, and TPS2210A meet all combinations of power delivery as currently
defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card
with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on
3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V
circuitry is not subjected to any residual 5-V charge and functions as a power RESET. PC Card specification requires that
VCC be discharged within 100 ms. PC Card resistance cannot be relied on to provide a discharge path for voltages stored
on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The devices
include discharge transistors on all xVCC and xVPP outputs to meet the specification requirement.
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SHUTDOWN MODE
In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and
xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 µA or less to
conserve battery power.
POWER-SUPPLY CONSIDERATIONS
These switches have multiple pins for each 3.3-V (except for the TPS2210A) and 5-V power input and for the switched
xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel,
the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended
that all input and output power pins be paralleled for optimum operation.
To increase the noise immunity of the TPS2204A, TPS2206A, and TPS2210A, the power-supply inputs should be
bypassed with at least a 4.7-µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It
is strongly recommended that the switched outputs be bypassed with a 0.1-µF (or larger) ceramic capacitor; doing so
improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB
traces between the devices and the load. High switching currents can produce large negative voltage transients, which
forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below −0.3 V.
RESET INPUT
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at
the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground. A low-impedance
output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host
and PC Cards) to be powered up concurrently. The active low RESET input closes internal ground switches S1, S4, S7,
and S11 with all other switches left open. The devices remain in the low-impedance output state until the signal is
deasserted and new data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET
is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an
internal 150-kΩ pullup resistor.
CALCULATING JUNCTION TEMPERATURE
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is
dependent on both r DS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 26 through 28,
using an initial temperature estimate about 30°C above ambient. Then calculate the power dissipation for each switch,
using the formula:
PD+rDS(on) I2
Next, sum the power dissipation of all switches and calculate the junction temperature:
TJ+ǒȍPD RqJAǓ)TA,R
qJA +108°CńW
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few
degrees of each other, recalculate using the calculated temperature as the initial estimate.
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LOGIC INPUTS AND OUTPUTS
The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the
clock (see Figure 2). The 9-bit (D0−D8) serial data word is loaded during the positive edge of the latch signal. The latch
signal should occur before the next positive edge of the clock.
The shutdown bit of the data word places all VCC and Vpp outputs in a high-impedance state and reduces chip quiescent
current to 1 µA to conserve battery power.
The serial interface is designed to be compatible with serial-interface PCMCIA controllers and current PCMCIA and Japan
Electronic Industry Development Association (JEIDA) standards.
An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the VCC and VPP
outputs as previously discussed.
CS
CS
S1
S4
CS
S7
CS
S11
Control Logic
SHDN
RESET
DATA
CLOCK
LATCH
OC
GND
UVLO
POR
Current Limit
Thermal Limit
S2
S5
S3
S6
S8
S9
S10
S12
S13
S14
Discharge
Element
3.3 V
3.3 V
5 V
5 V
5 V
12 V
12 V
AVCC
AVCC
BVCC
BVCC
AVPP
BVPP
BVCC
AVCC
See Note B
see Note A
See Note B
See Note A
See Note A
See Note A
NOTES:A. Current sense
B. The two 12-V pins must be externally connected.
Figure 35. Internal Switching Matrix, TPS2204A and TPS2206A
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23
CS
S1
CS
S7
Control Logic
SHDN
RESET
DATA
CLOCK
LATCH
OC
GND
UVLO
POR
Current Limit
Thermal Limit
S2
S3
S4
S5
S6
3.3 V
5 V
5 V
12 V
AVCC
AVCC
AVPP
See Note D
See Note C
See Note C
NOTES:C. Current sense
D. The two 12-V pins must be externally connected.
12 V
See Note D
Figure 36. Internal Switching Matrix, TPS2210A
CONTROL LOGIC
AVPP BVPP
CONTROL SIGNALS OUTPUT CONTROL SIGNALS OUTPUT
D8 (SHDN) D0 D1 VAVPP D8 SHDN) D4 D5 VBVPP
1 0 0 0 V 1 0 0 0 V
1 0 1 AVCC(1) 1 0 1 BVCC(2)
1 1 0 12 V 1 1 0 12 V
1 1 1 Hi–Z 1 1 1 Hi–Z
0 X X Hi–Z 0 X X Hi–Z
(1) Output depends on AVCC (2) Output depends on BVCC
AVCC BVCC
CONTROL SIGNALS OUTPUT CONTROL SIGNALS OUTPUT
D8 SHDN) D3 D2 VAVCC D8 SHDN) D6 D7 VBVCC
1 0 0 0 V 1 0 0 0 V
1 0 1 3.3 V 1 0 1 3.3 V
1 1 0 5 V 1 1 0 5 V
1 1 1 0 V 1 1 1 0 V
0 X X Hi–Z 0 X X Hi–Z
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24
USING THE DEVICES WITH 11-BIT SERIAL DATA INTERFACE CONTROLLERS
Even though the control logic table only shows a 9-bit interface, it can be used with most 11-bit serial data interface
controllers. With the use of the latch input, the TPS2204A, TPS2206A, and TPS2210A only latch the last 9 bits from the
serial stream. This means that for an 11-bit serial stream, bits 9 and 10 are ignored. 11-bit serial interface controllers use
bits 9 and 10 for independent voltage selection of 3.3 V and 5 V between xVCC and xVPP.
ESD PROTECTIONS (see FIGURE 37)
All TPS2206A inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be exposed
to potentially higher discharges from the external environment through the PC Card connector . Bypassing the outputs with
0.1-µF capacitors protects the devices from discharges up to 10 kV.
TPS2206A VCC
BVPP
BVCC
BVCC
AVPP
AVCC
AVCC
LATCH
CLOCK
DATA
OC
RESET
VCC
0.1 µF
0.1 µFVpp1
Vpp2
PC Card
Connector A
VCC
VCC
0.1 µF
0.1 µFVpp1
Vpp2
PC Card
Connector B
DATA
CLOCK
LATCH
GPI/O
Controller
From PCI or
System RST
12 V
3.3 V
5 V
12 V
3.3 V
5 V
12 V
3.3 V
3.3 V
5 V
0.1 µF
0.1 µF
0.1 µF
4.7 µF
4.7 µF
4.7 µF
5 V
AVCC
BVCC
SHDN From PCI or
System Shutdown
NOTE A: Maximum recommended output capacitance for xVCC is 220 µF including card capacitance, and for xVPP is 10 µF, without OC
glitch when switches are powered on.
see Note A
see Note A
see Note A
see Note A
Figure 37. Detailed Interconnections and Capacitor Recommendations
SLVS449A − DECEMBER 2002 − REVISED MAY 2003
www.ti.com
25
12-V FLASH MEMORY SUPPLY
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device
is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider
operating input-voltage range, and higher output currents. As shown in Figure 36, the only external components required
are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop
compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount
components. An enable input is provided to shut the converter down and reduce the supply current to 3 µA when 12 V is
not needed.
The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET power
switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize
the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one
small capacitor. A 1.22-V reference, pin 2 of TPS6734, is brought out for external use. For additional information, see the
TPS6734 data sheet (SLVS127).
NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high.
TPS2206A
BVPP
BVCC
BVCC
BVCC
AVPP
AVCC
AVCC
AVCC
LATCH
CLOCK
DATA
OC
RESET
3.3 V
5 V
12 V
3.3 V
5 V
12 V
3.3 V
3.3 V
5 V
5 V
SHDN
0.1 µF
0.1 µF1 µF
0.1 µF4.7 µF
EN
REF
SS
COMP
TPS6734
VCC
FB
OUT
GND
1
2
3
4
L1
18 µH
8
7
6
5
R1
10 kΩ
Enable
(see Note A)
C1
33 µF
20 V
C2
0.01 µF
12 V
D1
33 µF, 20 V
C4
0.001 µF
3.3 V or 5 V
+
C1+
Figure 38. TPS2206A With TPS6734 12-V, 120-mA Supply
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2204APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS2204APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS2206ADAP ACTIVE HTSSOP DAP 32 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
TPS2206ADAPG4 ACTIVE HTSSOP DAP 32 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples
TPS2206ADB ACTIVE SSOP DB 30 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2206ADBG4 ACTIVE SSOP DB 30 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS2206ADBR ACTIVE SSOP DB 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2206ADBRG4 ACTIVE SSOP DB 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS2210APWP ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS2210APWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS2210APWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS2210APWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2206ADBR SSOP DB 30 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
TPS2210APWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2206ADBR SSOP DB 30 2000 367.0 367.0 38.0
TPS2210APWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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