PD - 97061C IRFB4110PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability HEXFET(R) Power MOSFET VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited) 100V 3.7m: 4.5m: 180A c 120A D D G S G D TO-220AB S G D S Gate Drain Source Absolute Maximum Ratings Max. Units ID @ TC = 25C Symbol Continuous Drain Current, VGS @ 10V (Silicon Limited) 180c A ID @ TC = 100C Continuous Drain Current, VGS @ 10V (Silicon Limited) 130c ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 120 IDM Pulsed Drain Current d 670 PD @TC = 25C Parameter Maximum Power Dissipation 370 W Linear Derating Factor 2.5 VGS Gate-to-Source Voltage 20 W/C V dv/dt TJ Peak Diode Recovery f 5.3 Operating Junction and -55 to + 175 TSTG Storage Temperature Range V/ns C 300 Soldering Temperature, for 10 seconds (1.6mm from case) 10lbxin (1.1Nxm) Mounting torque, 6-32 or M3 screw Avalanche Characteristics EAS (Thermally limited) Single Pulse Avalanche Energy e IAR Avalanche Currentd EAR Repetitive Avalanche Energy g 190 mJ See Fig. 14, 15, 22a, 22b A mJ Thermal Resistance Typ. Max. RJC Symbol Junction-to-Case k Parameter --- 0.402 RCS Case-to-Sink, Flat Greased Surface 0.50 --- RJA Junction-to-Ambient j --- 62 www.irf.com Units C/W 1 http://store.iiic.cc/ 04/07/08 IRFB4110PbF Static @ TJ = 25C (unless otherwise specified) Symbol Parameter V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Typ. Max. Units 100 --- --- --- 0.108 --- --- 3.7 4.5 2.0 --- 4.0 --- --- 20 --- --- 250 --- --- 100 --- --- -100 Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAd m VGS = 10V, ID = 75A g V VDS = VGS, ID = 250A A VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V Dynamic @ TJ = 25C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Qg Qgs Qgd Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge 160 --- --- --- --- 150 35 43 --- 210 --- --- RG td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance --- 1.3 25 67 78 88 9620 670 250 820 950 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)i --- --- Effective Output Capacitance (Time Related)h S nC Conditions VDS = 50V, ID = 75A ID = 75A VDS = 50V VGS = 10V g ns pF VDD = 65V ID = 75A RG = 2.6 VGS = 10V g VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 80V j VGS = 0V, VDS = 0V to 80V h Diode Characteristics Symbol IS Parameter Min. Typ. Max. Units Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode)di Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM --- --- 170c --- --- 670 A Conditions MOSFET symbol showing the integral reverse D G S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 75A, VGS = 0V g VR = 85V, --- 50 75 ns TJ = 25C T = 125C I --- 60 90 J F = 75A di/dt = 100A/s g --- 94 140 nC TJ = 25C TJ = 125C --- 140 210 --- 3.5 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.033mH RG = 25, IAS = 108A, VGS =10V. Part not recommended for use above this value. ISD 75A, di/dt 630A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ approximately 90C. 2 www.irf.com http://store.iiic.cc/ IRFB4110PbF 1000 1000 BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP 100 ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V BOTTOM 100 4.5V 60s PULSE WIDTH 60s PULSE WIDTH Tj = 25C Tj = 175C 10 10 0.1 1 10 100 0.1 V DS, Drain-to-Source Voltage (V) 10 100 Fig 2. Typical Output Characteristics 1000 3.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 100 T J = 25C 10 T J = 175C 1 VDS = 25V 60s PULSE WIDTH 0.1 ID = 75A VGS = 10V 2.5 2.0 1.5 1.0 0.5 1 2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 100000 12.0 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd VGS, Gate-to-Source Voltage (V) ID= 75A Coss = Cds + Cgd C, Capacitance (pF) 4.5V Ciss 10000 Coss 1000 Crss 100 10.0 VDS= 80V VDS= 50V 8.0 6.0 4.0 2.0 0.0 1 10 100 0 VDS, Drain-to-Source Voltage (V) 50 100 150 200 QG, Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage www.irf.com 3 http://store.iiic.cc/ IRFB4110PbF 10000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 T J = 175C 100 T J = 25C 10 1 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100sec 100 10msec Tc = 25C Tj = 175C Single Pulse VGS = 0V 1 0.1 0.0 0.5 1.0 1.5 0 2.0 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 180 Limited By Package ID, Drain Current (A) 140 120 100 80 60 40 20 0 25 50 75 100 125 150 10 100 1000 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 160 1 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) 175 125 Id = 5mA 120 115 110 105 100 95 90 -60 -40 -20 0 20 40 60 80 100120140160180 TC , Case Temperature (C) T J , Temperature ( C ) Fig 10. Drain-to-Source Breakdown Voltage Fig 9. Maximum Drain Current vs. Case Temperature 5.0 EAS , Single Pulse Avalanche Energy (mJ) 800 4.5 4.0 3.5 3.0 Energy (J) 1msec DC 10 2.5 2.0 1.5 1.0 0.5 ID 17A 27A BOTTOM 108A 700 TOP 600 500 400 300 200 100 0.0 0 0 20 40 60 80 100 120 25 75 100 125 150 175 Starting TJ , Junction Temperature (C) VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 50 Fig 12. Maximum Avalanche Energy vs. DrainCurrent 4 www.irf.com http://store.iiic.cc/ IRFB4110PbF Thermal Response ( Z thJC ) 1 D = 0.50 0.1 0.20 0.10 0.05 0.02 0.01 0.01 J R1 R1 J 1 R2 R2 R3 R3 C 2 1 3 2 3 C i= i/R i C i= i/Ri 0.001 SINGLE PULSE ( THERMAL RESPONSE ) 0.0001 1E-006 C Ri (C/W) 0.09876251 0.2066697 0.09510464 i (sec) 0.000111 0.001743 0.012269 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) Avalanche Current (A) 100 0.01 0.05 10 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 250 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 108A 200 150 100 50 0 25 50 75 100 125 150 PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav 175 Starting TJ , Junction Temperature (C) Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 http://store.iiic.cc/ IRFB4110PbF 25 IF = 30A V R = 85V 3.5 20 TJ = 25C TJ = 125C 3.0 2.5 IRR (A) VGS(th) , Gate threshold Voltage (V) 4.0 ID = 250A 2.0 ID = 1.0mA 15 10 ID = 1.0A 1.5 5 1.0 0 0.5 -75 -50 -25 0 0 25 50 75 100 125 150 175 200 200 600 800 1000 Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage vs. Temperature 25 560 IF = 45A V R = 85V 20 TJ = 25C TJ = 125C 15 QRR (A) IRR (A) 400 diF /dt (A/s) T J , Temperature ( C ) 10 480 IF = 30A V R = 85V 400 TJ = 25C TJ = 125C 320 240 5 160 0 80 0 200 400 600 800 1000 0 200 diF /dt (A/s) 400 600 800 1000 diF /dt (A/s) Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt QRR (A) 560 480 IF = 45A V R = 85V 400 TJ = 25C TJ = 125C 320 240 160 80 0 200 400 600 800 1000 diF /dt (A/s) 6 Fig. 20 - Typical Stored Charge vs. dif/dt http://store.iiic.cc/ www.irf.com IRFB4110PbF D.U.T Driver Gate Drive - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + D= Period P.W. + VDD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG + V - DD IAS VGS 20V tp A 0.01 I AS Fig 21a. Unclamped Inductive Test Circuit LD Fig 21b. Unclamped Inductive Waveforms VDS VDS 90% + VDD - 10% D.U.T VGS VGS Pulse Width < 1s Duty Factor < 0.1% td(on) Fig 22a. Switching Time Test Circuit tr td(off) tf Fig 22b. Switching Time Waveforms Id Vds Vgs L VCC DUT 0 Vgs(th) 1K Qgs1 Qgs2 Fig 23a. Gate Charge Test Circuit Qgd Qgodr Fig 23b. Gate Charge Waveform www.irf.com http://store.iiic.cc/ 7 IRFB4110PbF TO-220AB Package Outline (Dimensions are shown in millimeters (inches)) TO-220AB Part Marking Information (;$03/( 7+,6,6$1,5) /27&2'( $66(0%/('21:: ,17+($66(0%/</,1(& Note: "P" in assembly line position indicates "Lead-Free" ,17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$57180%(5 '$7(&2'( <($5 :((. /,1(& TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. 8 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 04/08 www.irf.com http://store.iiic.cc/