RT9041E
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Pin Configurations
Ordering Information
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
(TOP VIEW)
WDFN-8L 2x2
500mA, Low Voltage, LDO Regulator with External B ias Supply
General Description
The RT9041E is a low voltage, low dropout linear regulator
with an external bias supply input. The bias supply drives
the gate of the internal N-MOSFET pass transistor, making
these devices ideal for applications that require low voltage
outputs from low voltage inputs. The RT9041E provides
fixed output voltage from 1V to 2V with 0.1V increments.
Adjustable output voltage is available for the RT9041E by
using external resistors. Other features include current
limit and thermal shutdown to protect regulator from fault
conditions.
The RT9041E is available in a WDFN-8L 2x2 package.
Features
±±
±±
±2% Output Voltage Accura cy
No Minimum Load Current Required
1V to 5.5V Input Supply Voltage
3V to 5.5V Input Bias Supply Voltage
PGOOD Open-Drain Output
Supports Fixed/Adjustable Output Voltage
Low Supply Current
5μμ
μμ
μA (max) Shutdown Supply Current
RoHS Compliant and Halogen Free
Applications
Set Top Box
Notebook Computers
VID Power Supplies
PDAs
Cell Phones
Low Dropout Regulators with External Bias Supply
VOUT
GND
ADJ
VIN
NC
VDD
EN
PGOOD
7
6
5
1
2
3
4
8
GND
9
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
Package Type
QW : WDFN-8L 2x2
Lead Plating System
G : Green (Halogen Free and Pb Free)
RT9041E-
Output Voltage
10 : 1.0V/Adj
11 : 1.1V/Adj
:
19 : 1.9V/Adj
20 : 2.0V/Adj
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Function Pin Description
Pin No. Pin Name Pin Function
1 VOUT Output Voltage.
2 ADJ
Output Voltage Adjust Pin. Set the output voltage by the internal feedback
resistors when ADJ is ground. If external feedback resistors is used,
VOUT = VREF x (R1 + R2)/R2.
3 PGOOD Power Good Open Drain Output.
4, 9 (Exposed pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
5 EN Chip Enable (Active-High).
6 VDD Supply Voltage of Control Circuitry.
7 NC No Internal Connection.
8 VIN Supply Input Voltage.
Function Block Diagram
OCP
Error
Amplifier
UVLO
EN
GND
VIN
PGOOD
VOUT
VDD
+
-
+
-
0.8V
0.7V
OTP
Driver
VIN
Mode ADJ
Typical Application Circuit
8
5
6
3
2
1
VDD
GND
EN
VIN VOUT
ADJ
RT9041E
10µF
COUT
10µF
Chip Enable
1V to 5.5V
R2
R1
PGOOD
CIN
3.3V to 5.5V
R3
100k
CVDD
0.1µF
4, Exposed pad (9)
VDD
VOUT
VIN
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Absolute Maximum Ratings (Note 1)
Bias Supply Input Voltage, VDD ---------------------------------------------------------------------------------------- 6V
Supply Input Voltage, VIN ------------------------------------------------------------------------------------------------ 6V
Other Input/Output Pins ------------------------------------------------------------------------------------------------- 6V
Power Dissipation, PD @ TA = 25°C
WDFN-8L 2x2 -------------------------------------------------------------------------------------------------------------- 0.833VW
Package Thermal Resistance (Note 2)
WDFN-8L 2x2, θJA -------------------------------------------------------------------------------------------------------- 120°C/W
WDFN-8L 2x2, θJC ------------------------------------------------------------------------------------------------------- 8.2°C/W
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM -------------------------------------------------------------------------------------------------------------------------- 2kV
MM ---------------------------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
Bias Supply Input Voltage, VDD ---------------------------------------------------------------------------------------- 3V to 5.5V
Supply Input Voltage, VIN ------------------------------------------------------------------------------------------------ 1V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit
Input
Adjustable Output Voltage Range VOUT 0.8 -- 2.5 V
Bias Input Under Voltage Lockout VUVLO -- 2.7 -- V
VIN Shutdown Current ISHDN 1V < VIN < 5.5V, VIN = VOUT + 0.6V -- 1 5 μA
Quiescent Current IQ 3V < VDD < 5.5V -- 160 250 μA
VDD Shutdown Current ISHDN 3V < VDD < 5.5V -- 1 5 μA
Regul ator Characteristi cs
Line Regulation ΔVOU T / ΔVIN IOUT = 10mA, 1.5V < VIN < 5.5V,
VIN = VOUT + 0.6V −0.15 -- 0.15 %/V
Load Regulation ΔVOU T / ΔIIN VIN = VOUT + 0.6V,
ILOAD = 1mA to 300mA -- 0.2 1 %
Fixed Output Voltage Accuracy ΔVOU T Short ADJ to GND, IOUT = 10mA −2 -- 2 %
Reference Voltage VREF I
OUT = 10mA 0.784 0.8 0.816 V
IOUT = 300mA, VDD − VOU T ≥ 2.1V -- 200 300
Dropout Voltage VDROP IOUT = 500mA, VDD − VOU T ≥ 2.1V -- 300 500 mV
Current Limit ILIM R
LOAD = 0 550 700 1400 mA
Thermal-Shutdown TSD 3V < VDD < 5.5V -- 160 -- °C
Thermal-Shutdown Hysteresis ΔTSD -- 20 -- °C
(VIN = 1.8V, ILOAD = 1mA, COUT = 10μF, T A = 25°C unless otherwise specified)
To be continued
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Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC
51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
Parameter Symbol Test Conditions Min Typ Max Unit
ADJ
ADJ Pin Threshold -- 0.2 -- V
PGOOD Comparator
Comparator Threshold % of regulated output voltage -- 88 -- %
Comparator Hysteresis VHYST (Note 5) -- 10 -- mV
Log ic and I/O
Logic-High VIH 2.4 -- --
EN Threshold
Voltage Logic-Low VIL -- -- 0.8
V
EN Current IEN V
EN = 5V -- 12 -- μA
PGOOD Output Low Voltage PGOOD sinking 1mA -- -- 0.1 V
PGOOD Output High Leakage
Current 0 < V PGOOD < VIN −1 -- 1 μA
Dynamics
PGOOD Propagation Delay tPGOOD Rising edge within 5% of regulation
level 1 -- 4 ms
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Typical Operating Characteristics
Quiescent Current vs. Temperature
130
140
150
160
170
180
190
200
210
-50 -25 0 25 50 75 100 125
Temperature (°C)
Quiescent Current (μA)1
VDD = 5V, VIN = 3.3V, VOUT = 2V, IOUT = 0mA
EN Threshold Voltage v s. Temperature
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Threshold Voltage (V)
Rising
VDD = 5V, VOUT = 1V
Falling
Current Limit vs. Temperature
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
-50 -25 0 25 50 75 100 125
Temperature (°C)
Current Limit (A)
VDD = 5V, VIN = 3.3V, VOUT = 2V, IOUT = 0mA
Reference Voltage vs. Temperature
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
-50 -25 0 25 50 75 100 125
Temperature (°C)
Reference Voltage (V)
VDD = 5V, VIN = 3.3V, VADJ = 0.8V, IOUT = 0mA
Output Voltage vs. Temperature
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Voltage (V)
VDD = 5V, VIN = 3.3V, VOUT = 2V, IOUT = 0mA
Dropout Voltage vs. Output Current
0
100
200
300
400
500
600
0 100 200 300 400 500
Output Current (mA)
Dropout Voltage (mV)
VDD = 5V
−40°C
25°C
125°C
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Line Transient Response
Time (500μs/Div)
VOUT
(5mV/Div)
VDD = 5V, VIN = 3V to 4V, VOUT = 1V, IOUT = 10mA
VIN
(V)
4
3
PGOOD Response
Time (2.5ms/Div)
PGOOD
(1V/Div)
VEN
(5V/Div)
VOUT
(1V/Div)
VDD = 5V, VIN = 4V, IOUT = 40mA
VIN UVLO vs. Temperature
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
UVLO (V)
Rising
VDD = 5V, VOUT = 1V
Falling
Load Transient Response
Time (100μs/Div)
IOUT
(500mA/Div)
VOUT
(50mV/Div)
VDD = 5V, VIN = 3.3V, VOUT = 2V
IOUT = 10mA to 0.5A
VDD UVLO vs. Tem pe rature
2.0
2.2
2.4
2.6
2.8
3.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
UVLO (V)
Rising
VDD = 5V, VOUT = 1V
Falling
PGOOD Timing vs. Temperature
0
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (°C)
PGOOD Timing (ms)
VDD = 5V, VIN = 3.3V, VOUT = 1V
Rising
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Noise
Time (10ms/Div)
VOUT
(200μV/Div)
VDD = VIN = 4.5V (By Battery),
VOUT = 1V, IOUT = 10mA
Noise
Time (10ms/Div)
VOUT
(200μV/Div)
VDD = VIN = 4.5V (By Battery),
VOUT = 1V, IOUT = 1mA
EN Response
Time (500μs/Div)
VEN
(5V/Div)
VOUT
(500mV/Div)
VDD = 5V, VIN = 3.3V, VOUT = 1V, IOUT = 0.5A
Line Transient Response
Time (500μs/Div)
VOUT
(5mV/Div)
VDD = 5V, VIN = 3V to 4V, VOUT = 1V, IOUT = 100mA
VIN
(V)
4
3
PSRR
-100
-80
-60
-40
-20
0
10 100 1000 10000 100000 1000000
Frequency (Hz)
PSRR (dB)
VDD = 5V, VIN = 3.3V to 3.4V, CIN = 1μF, COUT = 10μF
IOUT = 10mA
IOUT = 100mA
10 100 1k 10k 100k 1M
RT9041E
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Application Information
The RT9041E is a low voltage, low dropout linear regulator
with an external bias supply input, capable of supporting
an input voltage range from 1V to 5.5V with a fixed output
voltage from 1V to 2V in 0.1V increments.
Supply Voltage Setting
The bias supply voltage (VDD) operates from 3V to 5.5V.
For better efficiency, it is suggested to operate VDD at 5V
when the output voltage is higher than 1V. Figure 1 shows
the curves of the recommended VDD − VOUT range vs. the
dropout voltage (VIN − VOUT) values.
Figure 1. Dropout Voltage vs.VDD − VOUT
Output Voltage Setting
The RT9041E output voltage is also adjustable from 0.8V
to 2.5V via the external resistive voltage divider. The voltage
divider resistors can have values up to 800kΩ because of
the very high impedance and low bias current of the sense
comparator. The output voltage is set according to the
following equation :
⎛⎞
⎜⎟
⎝⎠
OUT REF R1
V = V x 1 + R2
where VREF is the reference voltage with a typical value of
0.8V.
Chip Enable Operation
The RT9041E goes into sleep mode when the EN pin is in
a logic low condition. In this condition, the pass transistor,
error amplifier, and band gap are all turned off, reducing
the supply current to 1μA (typ.). The EN pin can be directly
tied to VIN to keep the part on.
Current Limit
The RT9041E contains an independent current limit
circuitry, which monitors and controls the pass transistor’s
gate voltage, limiting the output current to 0.7A (typ.).
CIN and COUT Selection
Like any low dropout regulator, the external capacitors of
the RT9041E must be carefully selected for regulator
stability and performance. Using a capacitor of at least
10μF is suitable. The input capacitor must be located at a
distance of not more than 0.5 inch from the input pin of
the IC. Any good quality ceramic capacitor can be used.
However, a capacitor with larger value and lower ESR
(Equivalent Series Resistance) is recommended since it
will provide better PSRR and line transient response.
The RT9041E is designed specifically to work with low
ESR ceramic output capacitor for space saving and
performance consideration. Using a ceramic capacitor with
value at least 10μF and ESR larger than 40mΩ on the
RT9041E output ensures stability. Nevertheless, the
RT9041E can still work well with other types of output
capacitors due to its wide range of stable ESR. Figure 2
shows the allowable ESR range as a function of load
current for various output capacitance. Output capacitors
with larger capacitance can reduce noise and improve load
transient response, stability, and PSRR. The output
capacitor should be located at a distance of not more than
0.5 inch from the output pin of the RT9041E.
Dropout Voltage vs. VDD - VOUT
0
50
100
150
200
250
300
350
400
450
500
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
VDD - VOUT (V)
Dropout Voltage (mV)
IO = 500mA
IO = 300mA
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Figure 2. Region of Stable COUT ESR vs. the Load
Current
Figure 3. Derating Curve for the RT9041E Package
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT9041E, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For WDFN-
8L 2x2 packages, the thermal resistance, θJA, is 120°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for
WDFN-8L 2x2 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT9041E package, the derating
curve in Figure 3 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W)1
Four-Layer PCB
Region of Stable COUT ESR vs . Loa d Current
0.01
0.10
1.00
10.00
100.00
0 100 200 300 400 500
Load Current (mA)
Region of Stable COUT ESR ( )
VDD = 5, VIN = 2.5V, VOUT = 1V,
CVDD = 0.1μF, C IN = COUT = 10μF/X7R
Unstable Range
Ω
Stable Range
Simulation Verify
RT9041E
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DS9041E-01 April 2011www.richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Outline Dimension
W-Type 8L DFN 2x2 Package
Dimensions In Millimeters Dimen sions In Inches
Symb ol Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.200 0.300 0.008 0.012
D 1.950 2.050 0.077 0.081
D2 1.000 1.250 0.039 0.049
E 1.950 2.050 0.077 0.081
E2 0.400 0.650 0.016 0.026
e 0.500 0.020
L 0.300 0.400
0.012 0.016
11
2
2
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
DETAIL A
Pin #1 ID and Tie Bar Mark Options
D
1
E
A3
A
A1
D2
E2
L
b
e
SEE DETAIL A
