r [\ /\ q PMC-Sierra, inc. PM7380 FREEUM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PM7380 FREEDM-32P672 FRAME ENGINE AND DATALINK MANAGER 32P672 DATASHEET PROPRIETARY AND CONFIDENTIAL ISSUE 4: JULY 2000 PMC-Sierra, Inc. 105 - 8555 Baxter Place Bumaby, BC Canada V5A 4V7 604 .415.6000 PMCSS00237r[\ y/ co PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee DATASHEET pMc-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 CONTENTS 1 FEATURES ..cesssscssesessevessssecsecsvessesscssesssuesssessssssuvesssnesssesseeassaseesseesssesesin 1 2 APPLICATIONS ...cesesesccssesssecsecsecsecsssessesssecsssssseesssssvessavsavsessseseaseseseeesseees 4 3 REFERENCES ..oeesececsccsccssessecscestsssessessasesssesssssssevesssetessvenesansaseenseesssesteen 5 4 APPLICATION EXAMPLES .......essccsscssesesssesssseseteesssesssesecsstsstessseeessessssees 6 5 BLOCK DIAGRAM 0. sssseccssessecsesesesecssesssesssesssssseseessnsessevseteanssseesseessseesssn 8 6 DESCRIPTION ov escescsecscssesssseseessssessesesssessecesssuseesssssessseneatsneessesasessaneesseees 9 7 PIN DIAGRAM oe ccececcsesscssesseeseseeseesssessucssereessssseecssetessevsesenssnvessetesneesen 12 8 - PIN DESCRIPTION. .....c.:scssssesessecsuessessessstessvsssssssessseveveveatsssesneseeteaeeen 13 Q FUNCTIONAL DESCRIPTION ......ssccsssesssessssssssessessseessessessessseessttenseeesn 38 9.1 HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL (H-MVIP) ...cceccscessssssessesecsevsscsssecsecsseesssssssecsessuesssessssessaeessseesseessn 38 9.2 HIGH-LEVEL DATALINK CONTROL (HDLC) PROTOCOL........ 38 9.3. RECEIVE CHANNEL ASSIGNER ........scsccccssseessesseseesseessessseenseen 39 9.3.1. LINE INTERFACE TRANSLATOR (LIT)........c:sseessseeee 4 9.3.2 LINE INTERFACE......eeceeecssecsssssetesseesesetestessstssseensee 42 9.3.3. PRIORITY ENCODER oo.e.eescssscssssesscseessessteseesseesseesseee 42 9.3.4 CHANNELASSIGNER..w.....ccccccsssecssseeseseesessessseesseensees 42 9.3.5 LOOPBACK CONTROLLER ..ww...sscssssceseeseeseesssessesesees 43 9.4 RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER.. 43 9.4.1 HDLC PROCESSOR ...... oc cecceecee cece eeeeeeeeneeeneeeeeneeaes 44 9.4.2 PARTIAL PACKET BUFFER PROCESSOR .............4.. 44 9.5 RECEIVE DMA CONTROLLER ....0.....ccecccceceeeeeeeeseereessanerereseaes 46 9.5.1 DATA STRUCTURES... ees cece eens eee eeseneeneeeeee 46 PROPRIETARY AND CONFIDENTIAL ir> [\ | Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.5.2 DMATRANSACTION CONTROLLER .........0. eee: 56 9.5.3 WRITE DATA PIPELINE/MUX ....0..0 cee eeeeeeeeteeeeeeeees 56 9.5.4 DESCRIPTOR INFORMATION CACHE .............. 56 9.5.5 FREE QUEUE CACHE ....0.. i ceeeeeeeeeeeneeteeeteeeeees 57 9.6 PCI CONTROLLER... eeccceecenceeeteeseeeesseceanaeeeeeeeenseeseees 57 9.6.1 MASTER MACHINE. ...0.0......ecececceeseeeeeneeeeeeeeeteeeeeeenneeens 58 9.6.2 MASTERLOCAL BUS INTERFACE ............: cece 60 9.6.3 TARGET MACHINE .0.000. ec eeeeeeeeeeeeeeeteeeesnseeeeeeaee 61 9.6.4 CBI BUS INTERFACE. ..00. ee ceeeeeeeserseetesereeeenes 63 9.6.5 ERROR/ BUS CONTROL ..0.0. cee cece eee teeennereeeees 63 9.7 TRANSMIT DMA CONTROLLER... eee eee eee eeeeeeeeeee 63 9.7.1 DATA STRUCTURES |... eect eenee eee eee eee eetenneneeeens 64 9.7.2 TASK PRIORITIES ...00. eee eee eeeeeeernateeeeenneereeee 76 9.7.3 DMATRANSACTION CONTROLLER ...........::0c: cco 76 9.7.4 READ DATAPIPELINE ...0.. ec eeeeeceseeaeenneeeereeas 76 9.7.5 DESCRIPTOR INFORMATION CACHE ............ 76 9.7.6 FREE QUEUE CACHE 0... ees cceee ee eeereeeeens 77 9.8 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER77 9.8.1 TRANSMIT HDLC PROCESSOR ......00. coer 77 9.8.2 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR78 9.9 TRANSMIT CHANNEL ASSIGNER....... eee eeeeeereereeeeees 80 9.9.1 LINE INTERFACE TRANSLATOR (LIT).............: ee 82 9.9.2 LINE INTERFACE... eee cece ec ee renee ree neenantens 82 9.9.3. PRIORITY ENCODER ...... cece eee e neces eee eeeeeens 83 PROPRIETARY AND CONFIDENTIAL ivr- I\ AI Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 EE) DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.9.4 CHANNELASSIGNER....0.0.... cece eeeeeceeeseeececeeeeeeseeeees 83 9.10 PERFORMANCE MONITOR... eeeeeeeeeeeeeeeeeteteseseaeeseeea 84 9.11 JTAG TEST ACCESS PORT INTERFACE ........... eee 84 9.12 PCIHOST INTERFACE .......... ccc eeeceeceeeeeeeeeceeeeeeseneeeeneesteeee 84 10 NORMAL MODE REGISTER DESCRIPTION ..000. ee eeeeeeereeereeee 89 10.1 PCI HOST ACCESSIBLE REGISTERS .......... ec eeeeeeeeeteeee 89 11 PCI CONFIGURATION REGISTER DESCRIPTION ......... eee 252 11.1 PCI CONFIGURATION REGISTERS... ceeeeeeceeeeeeeneeetteee 252 12 TEST FEATURES DESCRIPTION ...000... 0c. cccecseeeseeeeeesetseeeeeneeeeneennees 263 12.1 TEST MODE REGISTERS... cece ee ceeeeeeeeeneeteneneeeeaes 263 12.2 JTAG TEST PORT 00. cece cece cece eeeensee eae e ee eee eeeeesaneeecneeennes 264 12.2.1 IDENTIFICATION REGISTER ........0. eee 265 12.2.2 BOUNDARY SCAN REGISTER............ ees 265 13, OPERATIONS... cece ceeeee cence eeeeeeeeeee renee cceeaeaageseeeeeeeneneesenseeenies 282 13.1 TOCTL CONNECTIONS o.oo. ee eeceeeceneee nee seeaeetnaesneeeees 282 13.2 JTAG SUPPORT 00.0... ccc eee eeeeeneseneeaee ae eeeeaaaaaeeeeerenneneeneee 282 14. FUNCTIONAL TIMING ...0000. eee eee r een eecee ae errr eeetaeeneeeeneeeenaas 289 14.1. RECEIVE H-MVIP LINK TIMING...0o ener reece 289 14.2 TRANSMIT H-MVIP LINK TIMING 0000. eee ee eereeeneees 290 14.3 RECEIVE NON H-MVIP LINK TIMING... ees 291 14.4 TRANSMIT NON H-MVIP LINK TIMING ...W00 reine 293 14.5 PCILINTERFACE u00. oc cee asec eee rece eeeeeeaanaeeeeeeeeeeeresineeee 294 14.6 BERT INTERFACE ..............cccccccsceeceeecesceesseeeeneeaaseenaceeeenetssaeeees 303 15 ABSOLUTE MAXIMUM RATINGS ......... ccc ceeee erent eee tneceeeneeed 305 PROPRIETARY AND CONFIDENTIAL iffr- [\ | co PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 16 D.C. CHARACTERISTICS 2.0.0... ceeeeeee eee eee ete tesenssesenseneeeneeane 306 17 FREEDM-32P672 TIMING CHARACTERISTICS ..00. eee 308 18 ORDERING AND THERMAL INFORMATION....0000.0. eee eeeeseeeeeeees 318 19 MECHANICAL INFORMATION ..........0:c:cccccesceeeeeeeeeeteeteseeeeeneeneerentensas 319 PROPRIETARY AND CONFIDENTIAL ivr > [\ v/ co PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 LIST OF FIGURES FIGURE 1 H-MVIP PROTOCOL............eccccect eee eee teee pees ee eee nnene sete trae snaetneeee 38 FIGURE 2 HDLC FRAME 1.0.0... e eens seer ceeeeeaee ee eeeeeeeseseeesenseeennreneiees 39 FIGURE 3 CRC GENERATOR... . cece ete tece tent eee e ee etna eee eeeteeae enna teeta 39 FIGURE 4 PARTIAL PACKET BUFFER STRUCTURE .............. ee 45 FIGURE 5 RECEIVE PACKET DESCRIPTOR ....... ccc eeeeeceeeeeeeseeeeeeens 47 FIGURE 6 RECEIVE PACKET DESCRIPTOR TABLE ..............ccesssssseeseeeeees 50 FIGURE 7 RPDRF AND RPDRR QUEUES... cecceeeeececeeeeeeneeeeeeneereeeertaes 52 FIGURE 8 RPDRR QUEUE OPERATION .........0. ee cc eee eee eee terete 54 FIGURE 9 RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE......... 55 FIGURE 10 GPIC ADDRESS MAP. .......... cece ccc cee eeee sree renee aaaaeeseeereanee 62 FIGURE 11 TRANSMIT DESCRIPTOR... eee cece eee e terete tener 64 FIGURE 12 TRANSMIT DESCRIPTOR TABLE .............. cc ceceeesseeeetesseereeteeeees 68 FIGURE 13 TDRRAND TDRF QUEUES ...00o. ese ete terete teers 70 FIGURE 14 TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE.... 72 FIGURE 15 TD LINKING 2000... eee cece cence teee ee eeeeeeeeeaseneeeeseeeneeeeeees 75 FIGURE 16 PARTIAL PACKET BUFFER STRUCTURE .........0.. eee 79 FIGURE 17 INPUT OBSERVATION CELL (IN_CELL) ............ cece 279 FIGURE 18 OUTPUT CELL (OUT_CELL)........ eee renner etree 280 FIGURE 19 BI-DIRECTIONAL CELL (IO_CELL).......... 2. cece eeesesseeeertees 280 FIGURE 20 LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL are FIGURE 21 - BOUNDARY SCAN ARCHITECTURE ....... 0... ee cecsteeereteeees 283 FIGURE 22 TAP CONTROLLER FINITE STATE MACHINE ............0.008 285 PROPRIETARY AND CONFIDENTIAL vr? [\ fl c PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FIGURE 23 RECEIVE 8.192 MBPS H-MVIP LINK TIMING .........cccssseese0 289 FIGURE 24 RECEIVE 2.048 MBPS H-MVIP LINK TIMING .........cccsseees 290 FIGURE 25 TRANSMIT 8.192 MBPS H-MVIP LINK TIMING ........ccs.sece-0 290 FIGURE 26 TRANSMIT 2.048 MBPS H-MVIP LINK TIMING... 291 FIGURE 27 UNCHANNELISED RECEIVE LINK TIMING ........0:..ecsssecseee 292 FIGURE 28 CHANNELISED T1/J1 RECEIVE LINK TIMING... 292 FIGURE 29 CHANNELISED E1 RECEIVE LINK TIMING .......c0ccscesseeecseee 293 FIGURE 30 UNCHANNELISED TRANSMIT LINK TIMING ......0...ccsseecee 293 FIGURE 31 CHANNELISED T1/J1 TRANSMIT LINK TIMING ............0e 294 FIGURE 32 CHANNELISED E1 TRANSMIT LINK TIMING..........0...ces 294 FIGURE 33 PCI READ CYCLE o....escccssssesssessssesseessssesseessvessesssveeseeesssseeeeeee 296 FIGURE 34 PCI WRITE CYCLE ..o...sccessesssessssstessssessetssuesessetssessessssvessetees 297 FIGURE 35 PCI TARGET DISCONNECT oo..eeessecsesseeseveevseessetssstesteesseeeen 298 FIGURE 36 PCI TARGET ABORT o.eseesseessssessstessesstesetssstsstsstsssesseessseessseees 299 FIGURE 37 PCI BUS REQUEST CYCLE... esssccsscsssesssessesssessstessseesssneesesen 299 FIGURE 38 PCI INITIATOR ABORT TERMINATION .......csscssceesseessseesssseees 300 FIGURE 39 PCI EXCLUSIVE LOCK CYCLE oo.sessccceecsessesseeseessseessseeetsee 301 FIGURE 40 PCI FAST BACK TO BACK ....ccessssscssssssessseessesseessesssseessseessnsnees 303 FIGURE 41 RECEIVE BERT PORT TIMING .......ccccsscsssesssseessesssesssessssseesse 303 FIGURE 42 - TRANSMIT BERT PORT TIMING .......ccccsssessesseessseessseeseseeeeeee 304 FIGURE 43 RECEIVE DATA & FRAME PULSE TIMING (2.048 MBPS H-MVIP MODE) .oessseesessesssssessessessevecesecsssessassssusesssssssusessavssessessuesacesseessstsseessen 310 FIGURE 44 RECEIVE DATA & FRAME PULSE TIMING (8.192 MBPS H-MVIP MODE) ...escsscscssssecsessevessssvesecsessucssseesssessseveesessssesssessussuesavesssestsneessaevecees 310 FIGURE 45 RECEIVE DATA TIMING (NON H-MVIP MODE)... 311 PROPRIETARY AND CONFIDENTIAL vir>i\ /\ es PMC-Sierra, Inc. PM7380 FREEDM-32P672 seen ee eee cee ee eee eee eee DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FIGURE 46 BERT INPUT TIMING... cee eee eceeneeeeerereeeteeeseteeeeeeeaeeeees 311 FIGURE 47 TRANSMIT DATA & FRAME PULSE TIMING (2.048 MBPS H-MVIP MODE ).......... cece eeeee cece ecneeeeeneteeeeteeeeeeetennerestieeeeeeneeaaenes 313 FIGURE 48 TRANSMIT DATA & FRAME PULSE TIMING (8.192 MBPS H-MVIP MODE )........... cece eee eeee teen scence cnee terres enaeneepeseesesauaeeniaeseeena eres 314 FIGURE 49 TRANSMIT DATA TIMING (NON H-MVIP MODE).................. 314 FIGURE 50 BERT OUTPUT TIMING... eee eee e cece sceserneeeetneeereneeea eee? 315 FIGURE 51 PCI INTERFACE TIMING... eee cece sees cece eens n eee reneeteeereeeaneee 316 FIGURE 52 JTAG PORT INTERFACE TIMING.........000 eee reeees 317 FIGURE 53 329 PIN PLASTIC BALL GRID ARRAY (PBGA)..................28 319 PROPRIETARY AND CONFIDENTIAL vilr? [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 LIST OF TABLES TABLE 1 LINE SIDE INTERFACE SIGNALS (154) 2000.0. eeereeeeeereeeeees 13 TABLE 2 - PCI HOST INTERFACE SIGNALS (52)..0........ccccccecseeeeeertetesteeeeees 23 TABLE 3 MISCELLANEOUS INTERFACE SIGNALS (58)... eee 32 TABLE 4 PRODUCTION TEST INTERFACE SIGNALS (0 - MULTIPLEXED)33 TABLE 5 - POWER AND GROUND SIGNALS (65)........0.00 eee eeeeeeeee 35 TABLE 6 RECEIVE PACKET DESCRIPTOR FIELDS... eee 47 TABLE 7 RPDRR QUEUE ELEMENT ...........cceceeeeeeeeeeeeeeeeeesenaeeteneeeeeneneeneeea 53 TABLE 8 RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE ELS TABLE 9 ~ TRANSMIT DESCRIPTOR FIELDS ....... eee teeeeeees 65 TABLE 10 TRANSMIT DESCRIPTOR REFERENCE .....000.. eee eeeeeeeee 71 TABLE 11 TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE FIELDS oo cece eeeseeeeee cece ane eeaeeeeeeseeeeeeeseneeeesaaaeseseteneeeeseseeetesaeeeenseeeneneees 73 TABLE 12 - NORMAL MODE PCI HOST ACCESSIBLE REGISTER MEMORY MAP... eee eeececce tee ceteeeeee ee ee eee e eee ee tees setae ete tee eee eee eee sees egeeeseeeeteaeeeteneenneeee 84 TABLE 13 ~- PC] CONFIGURATION REGISTER MEMORY MAP........0.000..2.. 88 TABLE 14 BIG ENDIAN FORMAT ..... oc eeeccecceeeeeneeene cess treet tense eeeeeeeaeeeees 119 TABLE 15 LITTLE ENDIAN FORMAT ...000 o.oo eeeeeeeence eee teneeceeerneeeereeeees 119 TABLE 16 - RECEIVE LINKS #0 TO #2 CONFIGURATION.............:c: eee 130 TABLE 17 - RECEIVE LINKS #3 TO #31 CONFIGURATION... ee 132 TABLE 18 CRC[1:0] SETTINGS... eee e rere eee neee eee eeeeteeieeteeeeeneseea 139 TABLE 19 RPQ_RDYN[2:0] SETTINGS... cence eee e teeter tees tenaeereeeees 150 TABLE 20 RPQ_LFN[1:0] SETTINGS 0.0. e eect ee seenenrereeerenerenees 151 TABLE 21 RPQ_SFN[1:0] SETTINGS |... eee cece ee ceresreeeersresensneees 151 PROPRIETARY AND CONFIDENTIAL villr > [\ /\ oy PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee eee DATASHEET pmc-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32672 TABLE 22 TDQ_RDYN[2:0] SETTINGS ..o...cccccscsecsesssessseessstesseesssseteateeen 185 TABLE 23 TDQ_FRN[1:0] SETTINGS ....cessccsccsscsscssssseseseesstsssetsesssessesseveees 185 TABLE 24 CRC[1:0] SETTINGS wo... cceccssecscsssssessessessstessessseessssesessavsaeeasen 213 TABLE 25 FLAG[2:0] SETTINGS ....cccecscssccssssssessessessetsssesseseesssseeseeseneeeeees 219 TABLE 26 LEVEL[3:0])/TRANS SETTINGS o.....cccsccsscssccssessseessteessssteeteeeees 221 TABLE 27 - TRANSMIT LINKS #0 TO #2 CONFIGURATION ......esseeceeeeees 239 TABLE 28 - TRANSMIT LINKS #3 TO #31 CONFIGURATION ......ssssesseeeees 241 TABLE 29 TEST MODE REGISTER MEMORY MAP.........cssccsssssseeseesseesees 264 TABLE 30 INSTRUCTION REGISTER. ......sscc:ssssccssessetesseesssessssseessseessneseen 265 TABLE 31 BOUNDARY SCAN CHAIN ....ccsscesccssscssessseessesssessssseetssetsseeseen 265 TABLE 32 FREEDMTOCTL CONNECTIONS 0.0. sccsssesssesssesssseessssessesseeees 282 TABLE 33 FREEDM-32P672 ABSOLUTE MAXIMUM RATINGS...........00.0+. 305 TABLE 34 FREEDM-32P672 D.C. CHARACTERISTICS .......sscecccceseseeeee: 306 TABLE 35 FREEDM-32P672 LINK INPUT (FIGURE 43 TO FIGURE 46)... 308 TABLE 36 FREEDM-32P672 LINK OUTPUT (FIGURE 47 TO FIGURE 50) 311 TABLE 37 PCI INTERFACE (FIGURE 51)...000.0. 00.0. eee eee eee eee eeeeeereeeee 315 TABLE 38 JTAG PORT INTERFACE (FIGURE 52)..0000... eee eeeees 316 TABLE 39 FREEDM-32P672 ORDERING INFORMATION............... eee 318 TABLE 40 FREEDM-32P672 THERMAL INFORMATION ........0.. ce eceeees 318 PROPRIETARY AND CONFIDENTIAL ixed fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 1 FEATURES e = Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/ gather capabilities. e Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are grouped into 4 logical groups of 8 links. A common clock and a type 0 frame pulse is shared among links in each logical group. The number of time-siots assigned to an HDLC channel is programmable from 1 to 32. e Supports up to 672 bi-directional HDLC channels assigned to a maximum of 8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a common clock and a type 0 frame pulse. The number of time-slots assigned to an HDLC channel is programmable from 1 to 128. e Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 channelised T1/J1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1). e Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link, subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a clock rate of up to 10 MHz. e Supports three bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running | at 45 MHz. e Supports a mix of up to 32 channelised, unchannelised and H-MVIP links, subject to the constraint of a maximum of 672 channels and a maximum aggregate link clock rate of 64 MHz in each direction. e Links configured for channelised T1/J1/E1 or unchannelised operation support the gapped-clock method for determining time-slots which is backwards compatible with the FREEDM-8 and FREEDM-32 devices. e For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver PROPRIETARY AND CONFIDENTIAL 1DATASHEET PMC-1990262 r- I\ y/ PMC-Sierra, Inc. PM7380 FREEDM-32P672 a ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 supports the validation of both CRC-CCITT and CRC-32 frame check sequences. For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. The receiver supports filtering of packets that are larger than a user specified maximum value. Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots. For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format. For each channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows. Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted. Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots. Provides 32 Kbytes of on-chip memory for partial packet buffering in both the transmit and receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of buffering. Supports PCI burst sizes of up to 256 bytes for transfers of packet data. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. Supports 3.3 Voit PCI signaling environments. Supports 5 Volt tolerant I/O (except PCI). Low power 2.5 Volt 0.25 um CMOS technology. PROPRIETARY AND CONFIDENTIAL 2r- [\ fi o* PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 e 329 pin plastic ball grid array (PBGA) package. PROPRIETARY AND CONFIDENTIAL 3r 2 [\ fl Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 2 APPLICATIONS e ETF PPP interfaces for routers e TDM switches e Frame Relay interfaces for ATM or Frame Relay switches and multiplexors e FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors. e Internet/Intranet access equipment. e Packet-based DSLAM equipment. PROPRIETARY AND CONFIDENTIAL 4DATASHEET PMC-1990262 r-i\ / | ra PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee eee eee anne ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 3 REFERENCES 1. International Organization for Standardization, ISO Standard 3309-1993, "Information Technology - Telecommunications and information exchange between systems - High-level data link control (HDLC) procedures - Frame structure", December 1993. RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1. GO-MVIP, MVIP-90 Standard, October 1994, release 1.1. GO-MVIP, H-MVIP Standard, January 1997, release 1.1a. PROPRIETARY AND CONFIDENTIAL 5r- [\ I Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET eS PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 4 APPLICATION EXAMPLES x aN Lecter.) z = 3 < z ws COMET-QUAG U < @ 2 vu 7 @ 2 n PM4354 COMET-QUAG Packet mi | Memory TDM PM7380 H+ Switch FREEDM- a eee Fabric ever a COME T-QUAT PCI H_ Controller Bus Arbite PM4354 COME T-QUAL Uv o 2 w Packet Memory DS3 SVEN mee Js Liu Taso Bae 32P672 PCI Controller Bus Arbite PROPRIETARY AND CONFIDENTIAL 6rit fi a PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PROPRIETARY AND CONFIDENTIAL 7PM7380 FREEDM-32P672 PMV Cc PMC-Sierra, Inc. ISSUE 4 DATASHEET FRAME ENGINE AND DATA LINK MANAGER 32P672 PMC-1990262 BLOCK DIAGRAM 5 NA99W OW13919d M1IOIId @LNilOd gyys guuddd @1NO gosuy gx901 1asdl 14sA3zq adO0is aAgul gAgul g3WVvus Yvd fo:e]aaag/o [o:Lelav FE O_x an oa qaan0zLf mom FPREERE Fe 0d OVIT +-_ > > <j .<g (ZZ990VWL) (Zz9SVOL) < corona (Z2910H1) yeublssy PS <-> Pina seyngreysed eed Lge! jouueyo 7 + > yusuesy /40SS990ld O10H wsued]| wwsuesy <?Jj : }- Bt (Z2991d9) ( 4) Pr} ayjo1ju0D NOW <-> Idd JOWUOW BDURWOEd ' <-> (ZZ99VWy) (zz9SVOu) q <P (Z2910HY) jeubissy <qpP- J9/OsUOD <-> VWG JOyNg JOYOed |EIMed om jauueuyg < i aajaoey /JOSS3890Jd O10H BAIBD9Y aniaday <-> at, 2 Xo < o 23 e ge > Oo wv os a gedsi Od4d8AWL OasAWL foe] MOAWL fo:elddal lo:Lelw190L [o:relar asdiuy Od4a8AWY oasAWwy [oe] HOAWY lo:-e]ad4uy fo:-elH190 fo:relay PROPRIETARY AND CONFIDENTIALr- [\ I c PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 6 DESCRIPTION The PM7380 FREEDM-32P672 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 672 bi-directional channels. The FREEDM-32P672 may be configured to support H-MVIP, channelised T1/J1/E1 or unchannelised traffic across 32 physical links. The FREEDM-32P672 may be configured to interface with H-MVIP digital telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, the FREEDM- 32P672 allows up to 672 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DSO) up to a maximum of 32 concatenated time-slots for each 2.048 Mbps H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link. When configured for 2.048 Mbps H-MVIP operation, the FREEDM-32P672 partitions the 32 physical links into 4 logical groups of 8 links. Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 make up the 4 logical groups. Links in each logical group share a common clock and a common type 0 frame pulse in each direction. The FREEDM-32P672 may be configured to interface with H-MVIP digital telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP links, the FREEDM- 32P672 allows up to 672 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 8 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DSO) up to a maximum of 128 concatenated time-slots for each 8.192 H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link. When configured for 8.192 Mbps H-MVIP operation, the FREEDM-32P672 partitions the 32 physical links into 8 logical groups of 4 links. Only the first link, which must be located at physical links numbered 4m (O<ms7), of each logical group can be configured for 8.192 Mbps operation. The remaining 3 physical links in the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused. All links configured for 8.192 Mops H-MVIP operation will share a common type 0 frame pulse, a common frame pulse clock and a common data clock. For channelised T1/J1/E1 links, the FREEDM-32P672 allows up to 672 bi- directional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1/J1 or E1 links. The gapped clock method to determine time-slot positions as per the FREEDM-8 and FREEDM-32 devices is retained. The channel assignment supports the concatenation of time-slots (N x DSO) up to a maximum of 24 concatenated time-slots for a T1/J1 PROPRIETARY AND CONFIDENTIAL 9i > [\ fl c PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within the T1/J1 or E1 link. For unchannelised links, the FREEDM-32P672 processes up to 32 bi-directional HDLC channels within 32 independently timed links. The links can be of arbitrary frame format. When limited to three unchannelised links, each link can be rated at up to 51.84 MHz provided SYSCLK is running at 45 MHz. Forlower | rate unchannelised links, the FREEDM-32P672 processes up to 32 links each rated at up to 10 MHz. In this case, the aggregate clock rate of all the links is limited to 64 MHz. The FREEDM-32P672 supports mixing of up to 32 channelised T1/J1/E1, unchannelised and H-MVIP links. The total number of channels in each direction is limited to 672. The aggregate instantaneous clock rate over all 32 possible links is limited to 64 MHz. In the receive direction, the FREEDM-32P672 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-32P672 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as sharing of zeros between flags are supported. The resulting packet data is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMAd out of the RAM, across the PCI bus and into host packet memory. The FREEDM-32P672 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum length. The receive packet status is updated before linking the packet into a receive ready queue. The FREEDM- 32P672 alerts the PCI Host that there are packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus. Alternatively, in the receive direction, the FREEDM-32P672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32P672 directly transfers the received octets into host memory verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-siots. In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM- 32P672 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by the FREEDM-32P672 and a frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag sequence is automatically inserted when there is no packet data for a particular channel. Sequential packets are PROPRIETARY AND CONFIDENTIAL 10r? [\ f\ PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 optionally separated by two flags (an opening flag and a closing flag) or a single flag (combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may cause one or more channels to underflow, in which case, the packets are aborted, and the host is notified. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or all- ones bytes) until a new packet is sourced from the PCI host. No attempt is made to automatically re-transmit an aborted packet. Alternatively, in the transmit direction, the FREEDM-32P672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32P672 directly inserts the transmitted octets from host memory. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive PCI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-32P672 receives new data from the host. The FREEDM-32P672 is configured, controlled and monitored using the PCI bus interface. The PCI bus supports 3.3 Volt signaling. The FREEDM-32P672 is implemented in low power 2.5 Volt 0.25 um CMOS technology. All non-PCl FREEDM-32P672 I/O pins are 5 volt tolerant. The FREEDM-32P672 is packaged in a 329 pin plastic ball grid array (PBGA) package. PROPRIETARY AND CONFIDENTIAL 1> [\ A PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 7 PIN DIAGRAM The FREEDM-32P672 is manufactured in a 329 pin plastic ball grid array package. 22 ar 20 1g 38 a? 3 15 14 13 12 11 a 8 7 5 4 3 2 2 A Preverte| worver facuxtazi|rcuxiis;| aotzz1 | ep'2z) | rola; | ectza! fecuxiasi|renK(271/reuxize:| vopave | omc me Ke ne we we A Bo fapreczi frcamiaei} epiae; | roczo) | vooays |reueti2r] erreiy factmizar{ecumizes{ mize) | eoisor fecuatay:| omc. | oc Nc Nc woos | xc. fos nc. fo we. 8 2 beans. | aera fecurtiss| ecurtier| ecetzo1 wanes tat] ei28: | eoia7t fecumtzatiacirier! aisar | owe. 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Freumizer|zcteizaifrecetse}| Tectx api21 | aplat | apcs) |] AA AB vote! | teefal | TOLK7} | renKial | vEbzvs | tots) | reexii2}] tora] | TRPAL2) }TCLR(16]} Teits: | TCuRI 29] TDi23] Prever a); TCUX(25]] TOI27' | TCLK(ze]) vbpave | TDI32: | PMCTEST we ADL) Ac [frcexts: | ore | roe | cotes | reunter freuxiior|reunsausfrewetys:| mis) | mael | tore; | vepavs |reuiais rewwi2a)| ro(261 | tore; | tBI28, | so:201 xc. fo mscm | apco) | ac 22 2h 20 1g 1B 17468 is 14 13 22 12 1s 8 7 6 5 4 3 2 l PROPRIETARY AND CONFIDENTIAL 12DATASHEET PMC-1990262 r>i\ /\ Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 8 PIN DESCRIPTION Table 1 Line Side Interface Signals (154) Pin Name Type Pin Function No. RCLK[O] Input N23 The receive line clock signals (RCLK[31:0]) RCLK[1] N21 contain the recovered line clock for the 32 RCLK[2] M22 independently timed links. Processing of RCLK[3} L21 the receive links are on a priority basis, in RCLK[4] L20 descending order from RCLK[O] to RCLK[5] K22 RCLK[31]. Therefore, the highest rate link RCLK[6] J22 should be connected to RCLK[O] and the RCLK[7] J23 lowest to RCLK[31]. RCLKIS) 29 _ | For channelised T1/J1 or E1 links, RCLK{n] RCLK[10] F992 must be gapped during the framing bit (for RCLK[11] F241 T1/J1 interfaces) or during time-slot 0 (for RCLKI12] E04 E1 interfaces) of the RD[n] stream. The RCLK[13] D23 FREEDM-32P672 uses the gapping RCLK[14] D241 information to determine the time-slot RCLK[15] C24 alignment in the receive stream. RCLK/16] B22 RCLK[31:0] is nominally a 50% duty cycle RCLK[17] A24 clock of frequency 1.544 MHz for T1/J1 links RCLK[18] C20 and 2.048 MHz for E71 links. RCLK[19] A20 For unchannelised links, RCLK[n] must be RCLK[20] C19 externally gapped during the bits or time- RCLK[21] C18 slots that are not part of the transmission RCLK[22] B18 format payload (i.e. not part of the HDLC RCLK[23] D1i7 packet). RCLK[2:0] is nominally a 50% duty RCLK[24] B16 cycle clock between 0 and 51.84 MHz. RCLK[25] A15 RCLK[31:3] is nominally a 50% duty cycle RCLK[26] B15 clock between 0 and 10 MHz. RCLK[27] A14 | The RCLK[n] inputs are invalid and should RCLK[28] C14 be forced to a low state when their RCLK 30] an associated link is configured for operation in H-MVIP mode. RCLK[31] B12 PROPRIETARY AND CONFIDENTIAL 13DATASHEET PMC-1990262 r-i\ fi fr PMC-Sierra, Inc. PM7380 FREEDM-32P672 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin Function No. RD[O] Input N20 The receive data signals (RD[31:0]) contain RD[1] N22 the recovered line data for the 32 RD[2] M21 independently timed links in normal mode RD[3] L22 (PMCTEST set low). Processing of the RD[4] L23 receive links is on a priority basis, in RD[5] K21 descending order from RD[O] to RD[31}. RD[6] J21 Therefore, the highest rate link should be RD[7] J20 connected to RD[0] and the lowest to RD[8] H23 RD[31]. RDI} 05 For H-MVIP links, RD[n] contains 32/128 RD[11] F23 time-slots, depending on the H-MVIP data RD[12] E23 rate configured (2.048 or 8.192 Mbps). RD[13] p22 When configured for 2.048 Mbps H-MVIP RD[14] E20 operation, RD[31:24], RD[23:16], RD[15:8] RD[15] C23 and RD[7:0] are sampled on every 2 rising RD[16] A22 edge of RMVCK[3], RMVCK[2], RMVCK[1] RD[17] D20 and RMVCK[0] respectively (at the % point RD[18] B21 of the bit interval). When configured for 8.192 Mbps H-MVIP operation, RD[4m] RD[19] D19 <7 led "4 Fisi RD[20] B20 (O<ms<7) are sampled on every rising | RD[21] A19 edge 3 RMV8DC (at the % point of the bit RD[22] Aig | imerval). RD[23] A17 For channelised links, RD[n] contains the 24 RD[24}] A16 (11/J1) or 31 (E1) time-siots that comprise RD[25] C16 the channelised link. RCLK[n] must be RD[26] D15 gapped during the T1/J1 framing bit position RD[27] C15 or the E1 frame alignment signal (time-siot RD[28] B14 0). The FREEDM-32P672 uses the location RD[29] D13 of the gap to determine the channel RD[30] B13 alignment on RD[n]. RD[31:0] are sampled RD[31] C12 on the rising edge of the corresponding RCLK[31:0]. For unchannelised links, RD[n] contains the HDLC packet data. For certain transmission formats, RD[n] may contain place holder bits or time-slots. RCLK[n] must be externally gapped during the place holder positions in the RD[n] stream. The FREEDM-32P672 supports a maximum data rate of 10 Mbit/s PROPRIETARY AND CONFIDENTIAL 14r > I\ /\ o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin Function No. on an individual RD[31:3] link and a maximum data rate of 51.84 Mbit/s on RD[2:0]. RD[31:0] are sampled on the rising edge of the corresponding RCLK[31:0]. RMVCK[0] Input P21 The receive MVIP data clock signals RMVCK[1] H22 (RMVCK[3:0]) provide the receive data RMVCK[2] A23 clock for the 32 links when configured to RMVCK[3] Ci7 operate in 2.048 Mbps H-MVIP mode. When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common data clock. RMVCK[0O], RMVCK[1], RMVCK[2] and RMVCK[3] sample the data on links RD[7:0], RD[15:8], RD[23:16] and RD[31:24] respectively. Each RMVCK)[n] is nominally a 50% duty cycle clock with a frequency of 4.096 MHz. RMVCK[n] is ignored and should be tied low when no physical link within the associated logical group of 8 links is configured for operation in 2.048 Mbps H-MVIP mode. RFPB[O] Input P22 The receive frame pulse signals RFPB[1] H21 (RFPB[3:0]) reference the beginning of each RFPB[2] B23 frame for the 32 links when configured for RFPB[3] B17 operation in 2.048 Mbps H-MVIP mode. When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common frame pulse. RFPB[0], RFPB[1], RFPB[2] and RFPBJ3] reference the beginning of a frame on links RD[7:0], RD[15:8], RD[23:16] and RD[31:24] respectively. When configured for operation in 2.048 Mbps H-MVIP mode, RFPB[n] is sampled on the falling edge of RMVCK[n]. Otherwise, RFPB[n] is ignored and should be tied low. PROPRIETARY AND CONFIDENTIAL 15r-i\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin Function No. RFP8B Input R21 The receive frame pulse for 8.192 Mbps H- MVIP signal (RFP8B) references the beginning of each frame for links configured for operation in 8.192 Mbps H-MVIP mode. RFP8B references the beginning of a frame for any link configured for 8.192 Mbps H- MVIP operation. Only links 4m (O<ms<7) may be configured for 8.192 Mbps H-MVIP operation. When one or more links are configured for 8.192 Mbps H-MVIP operation, RFP8B is sampled on the falling edge of RMV8FPC. When no links are configured for 8.192 Mbps H-MVIP operation, RFP8B is ignored and should be tied low. RMV8FPC Input P23 The receive 8.192 Mbps H-MVIP frame pulse clock signal (RMV8FPC) provides the receive frame pulse clock for links configured for operation in 8.192 Mbps H- MVIP mode. RMV8FPC is used to sample RFP8B. RMV8FPC is nominally a 50% duty cycle, clock with a frequency of 4.096 MHz. The falling edge of RAV8FPC must be aligned with the falling edge of RMV8DC with no more than +10 ns skew. RMV8FPC is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode. PROPRIETARY AND CONFIDENTIAL 16r-y\ fl oy PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin Function No. RMV8DC input R22 The receive 8.192 Mbps H-MVIP data clock signal (RMV8DC) provides the receive data clock for links configured to operate in 8.192 Mbps H-MVIP mode. RMV8DC is used to sample data on RD[4m] (O<ms<7) when link 4m is configured for 8.192 Mbps H-MVIP operation. RMV8DC is nominally a 50% duty cycle clock with a frequency of 16.384 MHz. RMV8DC is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode. RBD Tristate | R23 The receive BERT data signal (RBD) Output contains the receive bit error rate test data. RBD reports the data on the selected one of the receive data signals (RD[31:0]) and is updated on the falling edge of RBCLK. RBD may be tristated by setting the RBEN bit in the FREEDM-32P672 Master BERT Control register low. BERT is not supported for H-MVIP links. RBCLK Tristate | R20 The receive BERT clock signal (RBCLK) Output contains the receive bit error rate test clock. RBCLK is a buffered version of the selected one of the receive clock signals (RCLK[31:0]). RBCLK may be tristated by setting the RBEN bit in the FREEDN- 32P672 Master BERT Control register low. BERT is not supported for H-MVIP links. PROPRIETARY AND CONFIDENTIAL 17DATASHEET PMC-1990262 i 2 [\ /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee eee eee eee ee ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin Function No. TCLK[0} Input W214 The transmit line clock signals (TCLK[31:0)) TCLK[(1] Y23 contain the transmit clocks for the 32 TCLK[2] Y21 independently timed links. Processing of TCLK[3] AA23_ | the transmit links is on a priority basis, in TCLK[4] AB22_ | descending order from TCLK[O] to TCLK[5] AC23 | TCLK[31]. Therefore, the highest rate link TCLK[6] AA21 should be connected to TCLK[0] and the TCLK[7] AB21 lowest to TCLK[31]. TCLK[8] Nor For channelised T1/J1 or E1 links, TCLK[n] TeLK10) AC18 must be gapped during the framing bit (for T1/J1 interfaces) or during time-slot 0 (for TCLK(11] ACI? E1 interfaces) of the TD[n] stream. The TCLK(12] AB17 | FREEDM-32P672 uses the gapping TCLK[13} AC16 information to determine the time-siot TOLKut8 oe alignment in the transmit stream. TCLK[16 AB14 For unchannelised links, TCLK[n] must be TeLky' 1 Y13 externally gapped during the bits or time- TCLK[18] AA13 slots that are not part of the transmission TCLK[19] AB12 evoke (i.e. not part of the HDLC TCLK[20] AA11 Packet). TCLK[21] AC11 | TCLK[2:0] is nominally a 50% duty cycle TCLK[22] AA10 | clock between 0 and 51.84 MHz. TCLK[23] AC10 | TCLK[31:3] is nominally a 50% duty cycle TCLK[24] ACY clock between 0 and 10 MHz. Typical TCLK[25] AB8 | values for TCLK[31:0] include 1.544 MHz reLKp7 om (for T1/J1 links) and 2.048 MHz (for E1 links). AB6 TOLK(29I AAG The TCLK[n] inputs are invalid and should TCLK[30] AA5 be tied low when their associated link is TCLK[31] AC4 configured for operation in H-MVIP mode. PROPRIETARY AND CONFIDENTIAL 18r= M Nes PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin Function No. TD[0] Output | w23 The transmit data signals (TD[31:0]) contain TD[1] Y22 the transmit data for the 32 independently TD[2] W20 timed links in normal mode (PMCTEST set TD[3] AA22_ | low). Processing of the transmit links is on TD[4] Y20 a priority basis, in descending order from TD[5] AB23 | TD[O] to TD[31]. Therefore, the highest rate TD[6] AC22_ | link should be connected to TD[0] and the TDI7] AC21_ | lowest to TD[31]. TD[8] AC20 For H-MVIP links, TD[n] contain 32/128 TDN) Nate time-slots, depending on the H-MVIP data TDI] AB18 rate configured (2.048 or 8.192 Mbps). TDI12] v17 When configured for 2.048 Mbps H-MVIP TDI13] AAI7 operation, TD[31:24], TD[23:16], TD[15:8] TD[14] ABIG and TD[7:0] are updated on every 2 falling TDI15] AC15 edge of TMVCK[3], TMVCK[2], TMVCK[1] TDI16] ACI4 and TMVCK[0] respectively. When configured for 8.192 Mbps H-MVIP TD[17] AA14 operation, TD[4m] (O<m<7) are updated on TD/18) ACTS | every 2 falling edge of TMV8DC TD[19] AB13 ry g ecg TD[20] AA12 For channelised links, TD[n] contains the 24 TD[21] AB11 (T1/J1) or 31 (E1) time-slots that comprise TD[22] Y11 the channelised link. TCLK[n] must be TD[23] ABi0 | gapped during the T1/J1 framing bit position TD[24] Y9 or during the E1 frame alignment signal TD[25] AA8 (time-slot 0). The FREEDM-32P672 uses TD[26] AC8 the location of the gap to determine the TD[27] AB7 channel alignment on TD[n]. TD[31:0] are TD[28] AC7 updated on the falling edge of the TD[29] AC6 corresponding TCLK[31:0]. TD[80] ACS For unchannelised links, TD[n] contains the TD[31] AB4 HDLC packet data. For certain transmission formats, TD[n] may contain place holder bits or time-siots. TCLK[n] must be externally gapped during the place holder positions in the TD[n] stream. The FREEDM-32P672 supports a maximum data rate of 10 Mbit/s on an individual TD[31:3] link and a maximum data rate of 51.84 Mbit/s on TD[2:0]. PROPRIETARY AND CONFIDENTIAL 19DATASHEET PMC-1990262 ri A c PMC-Sierra, Inc. PM7380 FREEDM-32P672 a ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin No. Function TD[31:0] are updated on the falling edge of the corresponding TCLK[31:0] clock. TMVCK[O] TMVCK[1] TMVCK[2] TMVCK[3} Input V21 Y19 AA15 ABY9 The transmit MVIP data clock signals (TMVCK[3:0]) provide the transmit data clocks for the 32 links when configured to operate in 2.048 Mbps H-MVIP mode. When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common clock. TMVCK[0], TMVCK[1], TMVCK[2] and TMVCK[3] update the data on links TD[7:0], TD[15:8], TD[23:16] and TD[31:24] respectively. Each TMVCK[n] is nominally a 50% duty cycle clock with a frequency of 4.096 MHz. TMVCK[n] is ignored and should be tied low when no physical link within the associated group of 8 logical links is configured for operation in 2.048 Mbps H-MVIP mode. TFPB[O] TFPB[1] TFPB[2] TFPB[3] Input V23 AA20 AB15 AAQ The transmit frame pulse signals (TFPB[3:0]) reference the beginning of each frame when configured for operation in 2.048 Mbps H-MVIP mode. When configured for 2.048 Mbps H-MVIP operation, the 32 links are partitioned into 4 groups of 8, and each group of 8 links share a common frame pulse. TFPB[0O], TFPB[1], TFPB[2] and TFPB[3] reference the beginning of a frame on links TD[7:0], TD[15:8], TD[23:16] and TD[31:24] respectively. When configured for operation in 2.048 Mbps H-MVIP mode, TFPB[n] is sampled on the falling edge of TMVCKj{n]. Otherwise, TFPB[n] is ignored and should be tied low. PROPRIETARY AND CONFIDENTIAL 20DATASHEET PMC-1990262 ri I o PMC-Sierra, Inc. PM7380 FREEDM-32P672 Cee eee reer a ee eS ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin No. Function TFP8B Input U23 The transmit frame pulse for 8.192 Mbps H- MVIP signal (TFP8B) references the beginning of each frame for links configured to operate in 8.192 Mbps H-MVIP mode. TFP8B references the beginning of a frame for any link configured for 8.192 Mbps H- MVIP operation. Only links 4m (0<m<7) may be configured for 8.192 Mbps H-MVIP operation. When one or more links are configured for 8.192 Mbps H-MVIP operation, TFP8B is sampled on the falling edge of TMV8FPC. When no links are configured for 8.192 Mbps H-MVIP operation, TFPB[n] is ignored and should be tied low. TMV8FPC Input V22 The transmit 8.192 Mbps H-MVIP frame pulse clock signal (TMV8FPC) provides the transmit frame pulse clock for links configured for operation in 8.192 Mbps H- MVIP mode. TMV8FPC is used to sample TFP8B. TMV8FPC is nominally a 50% duty cycle, clock with a frequency of 4.096 MHz. The falling edge of TMV8FPC must be aligned with the falling edge of TMV8DC with no more than +10 ns skew. TMV8FPC[n] is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode. PROPRIETARY AND CONFIDENTIAL 21r [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin Function No. TMV8DC Input U20 The transmit 8.192 Mbps H-MVIP data clock signal (TMV8DC) provides the transmit data clock for links configured to operate in 8.192 Mbps H-MVIP mode. TMV8DC is used to update data on TD[4m] (O<ms7) when link 4m is configured for 8.192 Mbps H-MVIP operation. TMV8DC is nominally a 50% duty cycle clock with a frequency of 16.384 MHz. TMV8DC is ignored and should be tied low when no physical links are configured for operation in 8.192 Mbps H-MVIP mode. TBD Input Y5 The transmit BERT data signal (TBD) contains the transmit bit error rate test data. When the TBERTEN bit in the BERT Control register is set high, the data on TBD is transmitted on the selected one of the transmit data signals (TD[31:0]). TBD is sampled on the rising edge of TBCLK. BERT is not supported for H-MVIP links. TBCLK Tristate | AA4 The transmit BERT clock signal (TBCLK) Output contains the transmit bit error rate test clock. TBCLK is a buffered version of the selected one of the transmit clock signals (TCLK[31:0]). TBCLK may be tristated by setting the TBEN bit in the FREEDM- 32P672 Master BERT Control register low. BERT is not supported for H-MVIP links. PROPRIETARY AND CONFIDENTIAL 22DATASHEET PMC-1990262 r> [\ f\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 Ge ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 2 PCI Host Interface Signals (52) Pin Name _ | Type Pin Function No. PCICLK Input G3 The PCI clock signal (PCICLK) provides timing for PCI bus accesses. PCICLK is a nominally 50% duty cycle, 25 to 66 MHz clock. PCICLKO | Output | G4 The PCI clock output signal (PCICLKO) is a buffered version of the PCICLK. PCICLKO may be used to derive the SYSCLK input. C/BEB[0] /O Y2 The PCI bus command and byte enable bus C/BEB[1] U3 (C/BEB[3:0]) contains the bus command or the C/BEB[2] P3 byte valid indications. During the first clock C/BEB[3] L4 cycle of a transaction, C/BEB[3:0] contains the bus command code. For subsequent clock cycles, C/BEB[3:0] identifies which bytes on the AD[31:0] bus carry valid data. C/BEB[3] is associated with byte 3 (AD[31:24]) while C/BEB[0] is associated with byte 0 (AD[7:0)). When C/BEB)Jn] is set high, the associated byte is invalid. When C/BEBj[n] is set low, the associated byte is valid. When the FREEDM-32P672 is the initiator, C/BEB[3:0] is an output bus. When the FREEDM-32P672 is the target, C/BEB[3:0] is an input bus. When the FREEDM-32P672 is not involved in the current transaction, C/BEB[3:0] is tristated. As an output bus, C/BEB[3:0] is updated on the rising edge of PCICLK. As an input bus, C/BEBJ3:0] is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL 23DATASHEET PMC-1990262 ISSUE 4 r? [\ fi cy PMC-Sierra, Inc. PM7380 FREEDM-32P672 | FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name | Type Pin Function No. ADO} /O AC1 | The PCi address and data bus (AD[31:0}) AD[1] AB1 carries the PCI bus multiplexed address and AD[2] AA3 | data. During the first clock cycle of a AD[3] AA1 transaction, AD[31:0] contains a physical byte AD[4] AA2_ | address. During subsequent clock cycles of a AD[5] Y3 transaction, AD[31:0] contains data. ADI7] ee A transaction is defined as an address phase ADI8} W3 followed by one or more data phases. When ADI9] W141 Little-Endian byte formatting is selected, ADI10} V3 AD[31:24] contain the most significant byte of a ADI11] V1 DWORD while AD[7:0] contain the least AD[12] V2 significant byte. When Big-Endian byte ADI13] U4 formatting is selected. AD[7:0] contain the most AD[14] U4 significant byte ofa DWORD while AD[31:24] AD[15] U2 contain the least significant byte. When the AD[16] N4 FREEDM-32P672 is the initiator, AD[31:0] is an AD[17] N14 output bus during the first (address) phase of a AD[18] N3 transaction. For write transactions, AD[31:0] ADI19 N2 remains an output bus for the data phases of ADO M2 the transaction. For read transactions, AD[31:0] AD[21] M3 is an input bus during the data phases. AD[22] L3 When the FREEDM-32P672 is the target, AD[23] L2 AD[31:0] is an input bus during the first AD[24] K3 (address) phase of a transaction. For write AD[25] K2 transactions, AD[31:0] remains an input bus AD[26] K1 during the data phases of the transaction. For AD[27] J3 read transactions, AD[31:0] is an output bus AD[28] J2 during the data phases. AD[29] J4 | When the FREEDM-32P672 is not involved in ADS} 43 the current transaction, AD[31:0] is tristated. As an output bus, AD[31:0] is updated on the rising edge of PCICLK. As an input bus, AD[31:0] is sampied on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL 24DATASHEET PMC-1990262 ISSUE 4 i > [\ A o PMC-Sierra, Inc. PM7380 FREEDM-32P672 a] FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin No. Function PAR /O T1 The parity signal (PAR) indicates the parity of the AD[31:0] and C/BEBJ[3:0] buses. Even parity is calculated over all 36 signals in the buses regardless of whether any or all the bytes on the AD[31:0] are valid. PAR always reports the parity of the previous PCICLK cycle. Parity errors detected by the FREEDM-32P672 are indicated on output PERRB and in the FREEDM-32P672 Interrupt Status register. When the FREEDM-32P672 is the initiator, PAR is an output for writes and an input for reads. When the FREEDM-32P672 is the target, PAR is an input for writes and an output for reads. When the FREEDM-32P672 is not involved in the current transaction, PAR is tristated. As an output signal, PAR is updated on the rising edge of PCICLK. As an input signal, PAR is sampled on the rising edge of PCICLK. FRAMEB /O P2 The active low cycle frame signal (FRAMEB) identifies a transaction cycle. When FRAMEB transitions low, the start of a bus transaction is indicated. FRAMEB remains low to define the duration of the cycle. When FRAMEB transitions high, the last data phase of the current transaction is indicated. When the FREEDM-32P672 is the initiator, FRAMEB is an output. When the FREEDM-32P672 is the target, FRAMEB is an input. When the FREEDM-32P672 is not involved in the current transaction, FRAMEB is tristated. As an output signal, FRAMEB is updated on the rising edge of PCICLK. As an input signal, FRAMEB is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL 25DATASHEET r > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 ae PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name | Type Pin Function No. TRDYB 0 R3 The active low target ready signal (TRDYB) indicates when the target is ready to start or continue with a transaction. TRDYB works in conjunction with IRDYB to complete transaction data phases. During a transaction in progress, TRDYB is set high to indicate that the target cannot complete the current data phase and to force a wait state. TRDYB is set low to indicate that the target can complete the current data phase. The data phase is completed when TRDYB is set low and the initiator ready signal (IRDYB) is also set low. When the FREEDM-32P6772 is the initiator, TRDYB is an input. When the FREEDM-32P672 is the target, TRDYB is an output. During accesses to FREEDM-32P672 registers, TRDYB is set high to extend data phases over multiple PCICLK cycles. When the FREEDM-32P672 is not involved in the current transaction, TRDYEB is tristated. As an output signal, TRDYB is updated on the rising edge of PCICLK. As an input signal, TRDYB is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL 26DATASHEET PMC-1990262 ISSUE 4 r > [\ A PMC-Sierra, Inc. PM7380 FREEDM-32P672 es FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name | Type Pin Function No. IRDYB /O P4 The active low initiator ready (IRDYB) signal is used to indicate whether the initiator is ready to start or continue with a transaction. IRDYB works in conjunction with TRDYB to complete transaction data phases. When IRDYB is set high and a transaction is in progress, the initiator is indicating it cannot complete the current data phase and is forcing a wait state. When !IRDYEB is set low and a transaction is in progress, the initiator is indicating it has completed the current data phase. The data phase is completed when IRDYB is set low and the target ready signal (IRDYB) is also set low. When the FREEDM-32P672 is the initiator, IRDYB is an output. When the FREEDM-32P672 is the target, IRDYB is an input. When the FREEDM-32P672 is not involved in the current transaction, IRDYB is tristated. IRDYB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input. PROPRIETARY AND CONFIDENTIAL 27DATASHEET PMC-1990262 ISSUE 4 rf fi oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 a FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin No. Function STOPB /O R4 The active low stop signal (STOPB) requests the initiator to stop the current bus transaction. When STOPB is set high by a target, the initiator continues with the transaction. When STOPEB is set low, the initiator will stop the current transaction. When the FREEDM-32P672 is the initiator, STOPEB is an input. When STOPB is sampled low, the FREEDM-32P672 wiil terminate the current transaction in the next PCICLK cycle. When the FREEDM-32P672 is the target, STOPEB is an output. The FREEDM-32P672 only issues transaction stop requests when responding to reads and writes to configuration space (disconnecting after 1 DWORD transferred) or if an initiator introduces wait states during a transaction. When the FREEDM-32P672 is not involved in the current transaction, STOPB is tristated. STOPEB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input. IDSEL Input L1 The initialization device select signal (IDSEL) enables read and write access to the PCI configuration registers. When IDSEL is set high during the address phase of a transaction and the C/BEBJ[3:0] code indicates a register read or write, the FREEDM-32P672 performs a PCI configuration register transaction and asserts the DEVSELB signal in the next PCICLK period. IDSEL is sampled on the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL 28DATASHEET PMC-1990262 r-f\ y/ ra PMC-Sierra, Inc. PM7380 FREEDM-32P672 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin No. Function DEVSELB /O R2 The active low device select signal (DEVSELB) indicates that a target claims the current bus transaction. During the address phase of a transaction, all targets decode the address on the AD[31:0] bus. When a target, recognizes the address as its own, it sets DEVSELB low to indicate to the initiator that the address is valid. If no target claims the address in six bus clock cycles, the initiator assumes that the target does not exist or cannot respond and aborts the transaction. When the FREEDM-32P672 is the initiator, DEVSELB is an input. If no target responds to an address in six PCICLK cycles, the FREEDM- 32P672 will abort the current transaction and alerts the PCI Host via an interrupt. When the FREEDM-32P672 is the target, DEVSELB is an output. DELSELB is set low when the address on AD[31:0] is recognised. When the FREEDM-32P672 is not involved in the current transaction, DEVSELB is tristated. FREEDM-32P672 is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether it is an output or an input. LOCKB Input R1 The active low bus lock signal (LOCKB) locks a target device. When LOCKB and FRAME are set low, and the FREEDM-32P672 is the target, an initiator is locking the FREEDM-32P672 as an "owned" target. Under these circumstances, the FREEDM-32P672 will reject all transaction with other initiators. The FREEDM-32P672 will continue to reject other initiators until its owner releases the lock by forcing both FRAMEB and LOCKB high. As a initiator, the FREEDM- 32P672 will never lock a target. LOCKB is sampled using the rising edge of PCICLK. PROPRIETARY AND CONFIDENTIAL 29r- I\ /I ce PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name | Type Pin Function No. REQB Tristate | H2 The active low PCI bus request signal (REQB) Output requests an external arbiter for control of the PCi bus. REQB is set low when the FREEDM- 32P672 desires access to the host memory. REQB is set high when access is not desired. REQB is updated on the rising edge of PCICLK. GNTB Input H1 The active low PCI bus grant signal (GNTB) indicates the granting of control over the PCI in response to a bus request via the REQB output. When GNTB is set high, the FREEDM-32P672 does not have control over the PCI bus. When GNTB is set low, the external arbiter has granted the FREEDM-32P672 control over the PCI bus. However, the FREEDM-32P672 will not proceed until the FRAMEB signal is sampled high, indicating no current transactions are in progress. GNTB is sampled on the rising edge of PCICLK. PCIINTB OD G1 The active low PCI interrupt signal (PCIINTB) is Output set low when a FREEDM-32P672 interrupt source is active, and that source is unmasked. The FREEDM-32P672 may be enabled to report many alarms or events via interrupts. PCIINTB returns high when the interrupt is acknowledged via an appropriate register access. PCIINTB is an open drain output and is asynchronous to PCICLK. PROPRIETARY AND CONFIDENTIAL 30r[\ fi ce PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name | Type Pin Function No. PERRB V/O T3 The active low parity error signal (PERRB) indicates a parity error over the AD[31:0] and C/BEB[3:0] buses. Parity error is signalled when even parity calculations do not match the PAR signal. PERRB is set low at the cycle immediately following an offending PAR cycle. PERRB is set high when no parity error is detected. PERRB is enabled by setting the PERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of PERREN, parity errors are always reported by the PERR bit in the Control/Status register in the PC! Configuration registers space. PERRB is updated on the rising edge of PCICLK. SERRB OD T2 The active low system error signal (SERRB) Output indicates an address parity error. Address parity errors are detected when the even parity calculations during the address phase do not match the PAR signal. When the FREEDIM- 32P672 detects a system error, SERRB is set low for one PCICLK period. SERRB is enabled by setting the SERREN bit in the Control/Status register in the PCI Configuration registers space. Regardless of the setting of SERREN, parity errors are always reported by the SERR bit in the Control/Status register in the PCI Configuration registers space. SERRB is an open drain output and is updated on the rising edge of PCICLK. M66EN Input AC2 The active high 66 MHz mode enable signal (M66EN) reflects the speed of operation of the PCI bus. M66EN should be set high for 66 MHz operation on the PCI bus. M66EN should be set low for 33 MHz operation on the PCI bus. PROPRIETARY AND CONFIDENTIAL 31DATASHEET PMC-1990262 ISSUE 4 r? [\ /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 ae FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 3 Miscellaneous Interface Signals (58) Pin Name Type Pin No. Function SYSCLK Input K23 The system clock (SYSCLK) provides timing for the core logic. SYSCLK is nominally a 50% duty cycle, 25 to 45 MHz clock. RSTB Input C22 The active low reset signal (RSTB) signal provides an asynchronous FREEDM-32P672 reset. RSTB is an asynchronous input. When RSTB is set low, all FREEDM-32P672 registers are forced to their default states. In addition, TD[81:0] are forced high and all PCI output pins are forced tristate and will remain high or tristated, respectively, until RSTB is set high. PMCTEST Input AB3 The PMC production test enable signal (PMCTEST) places the FREEDM-32P672 is test mode. When PMCTEST is set high, production test vectors can be executed to verify manufacturing via the test mode interface signals TA[11:0], TA[12]/TRS, TRDB, TWRB and TDAT[15:0]. PMCTEST must be tied low for normal operation. TCK Input T23 The test clock signal (TCK) provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. TMS and TDI are sampled on the rising edge of TCK. TDO is updated on the falling edge of TCK. TMS Input T22 The test mode select signal (TMS) controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. TDI Input U21 The test data input signal (TDI) carries test data into the FREEDM-32P672 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. PROPRIETARY AND CONFIDENTIAL 32DATASHEET PMC-1990262 r- [\ fA PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin No. Function TDO Tristate Output U22 The test data output signal (TDO) carries test data out of the FREEDM-32P672 via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress. TRSTB Input T21 The active low test reset signal (TRSTB) provides an asynchronous FREEDM-32P672 test access port reset via the IEEE P1149.1 test access port. TRSTB is an asynchronous input with an integral pull up resistor. Note that when TRSTB is not being used, it must be connected to the RSTB input. NC1-50 Open These pins must be left unconnected. Table 4 Production Test Interface Signals (0 - Multiplexed) Pin Name | Type Pin Function No. TA[O] Input G23 | The test mode address bus (TA[11:0]) selects TA[1] F23 | specific registers during production test TA[2] E23 | (PMCTEST set high) read and write accesses. TA(3] D22 | TA[11:0] replace RD[21:10] when PMCTEST is TA[4] E20 | set high. TA[5] C23 TA[6] A22 TA[7] D20 TA[8] B21 TA[9] D19 TA[10] B20 TA[11] A19 TA[12]/TR | Input A16_ | The test register select signal (TA[12]/TRS) S selects between normal and test mode register accesses during production test (PMCTEST set high). TRS is set high to select test registers and is set low to select normal registers. TA[12]/TRS replaces RD[24] when PMCTEST is set high. PROPRIETARY AND CONFIDENTIAL 33DATASHEET PMC-1990262 ISSUE 4 r [\ fi a PMC-Sierra, Inc. PM7380 FREEDM-32P672 a FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name | Type Pin Function No. TRDB Input A18 | The test mode read enable signal (TRDB) is set low during FREEDM-32P672 register read accesses during production test (PMCTEST set high). The FREEDM-32P672 drives the test data bus (TDAT[15:0]) with the contents of the addressed register while TRDB is low. TRDB replaces RD[22] when PMCTEST is set high. TWRB Input A17 | The test mode write enable signal (TWRB) is set low during FREEDM-32P672 register write accesses during production test (PMCTEST set high). The contents of the test data bus (TDAT[15:0]) are clocked into the addressed register on the rising edge of TVWRB. TWRB replaces RD[23] when PMCTEST is set high. TDAT{(O] VO AC1_ | The bi-directional test mode data bus TDAT{[1] 4 (TDAT[15:0]) carries data read from or written to TDAT[2] AA14 | FREEDM-32P672 registers during production TDAT[3] AC1_ | test. TDAT[15:0] replace TD[31:16] when TDAT[4] 3 PMCTEST is set high. TDAT[S5] AB13 TDAT[6] AA1i2 TDAT[7] AB11 TDAT[8] Y11 TDAT[9] AB10 TDAT[10] Y9 TDAT[11] AA8 TDAT[12] AC8 TDAT[13] AB7 TDAT[14] AC7 TDAT{15] AC6 AC5 AB4 PROPRIETARY AND CONFIDENTIAL 34r? [\ f\ oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 5 Power and Ground Signals (65) Pin Name Type Pin Function No. VDD3V3[1] Power D6 The VDD3V3[14:1] DC power pins should be VDD3V3[2] D10 | connected to a well decoupled +3.3 V DC VDD3V3[3] D14 | supply. These power pins provide DC current VDD3V3/4] D18 | to the I/O pads. VDD3V3[5] H4 VDD3V3{6] H20 VDD3V3[7] M4 VDD3V3[8] M20 VDD3V3{9] T4 VDD3V3[10] T20 VDD3V3[11] Y6 VDD3V3[12] Y10 VDD3V3[13] Y14 VDD3V3[14] Y18 VDD2V5/1] Power E2 The VDD2V5[12:1] DC power pins should be VDD2V5[2} M1 connected to a well decoupled +2.5 V DC VDD2V5[3] W2 supply. These power pins provide DC current VDD2V5[4] AB5 | to the digital core. VDD2V5[5] AC1 VDD2V5[6] 2 VDD2V5[7] AB19 VDD2V5[8] W22 VDD2V5[9] M23 VDD2V5/10] E22 VDD2V5[11] B19 VDD2V5[12] A12 B5 PROPRIETARY AND CONFIDENTIAL 35DATASHEET PMC-1990262 r > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 es ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin Name Type Pin | Function No. VSS[1] Ground | D8 The VSS[14:1] DC ground pins should be VSS[2] D12 | connected to ground. They provide a ground VSSJ[3] D16 | reference for the 3.3 V rail. They also provide VSS[4] F4 a ground reference for the 2.5 V rail. VSS[5] F20 VSS[6] K4 VSS[7] K20 VSS[8] P4 VSS[9] P20 VSS[10] V4 VSS[11] V20 VSS[12] Y8 VSS[13] Y12 VSS[14] Y16 VSS[15] K10 | The VSS[39:15] DC ground pins should be VSS[16] K11 | connected to ground. They provide improved VSS[17] K12 | thermal properties for the 329 PBGA package. VSS[18] K13 VSS[19] K14 VSS[20] L10 VSS[21] L11 VSS[22] L12 VSS[23] L413 VSS[24] L14 VSS[25] M10 VSS[26] M11 VSS[27] M12 VSS[28] M13 VSS[29] M14 VSS[30] N10 VSS[31] N11 VSS[32] N12 VSS[33] N13 VSS[34] N14 VSS[35] P10 VSS[36] P11 VSS[87] P12 VSS[38] P13 VSS[39] P14 PROPRIETARY AND CONFIDENTIAL 36DATASHEET PMC-1990262 f VM C* PMC-Sierra, Inc. PM7380 FREEDM-32P672 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Notes on Pin Description: 1. All FREEDM-32P672 non-PCl inputs and bi-directionals present minimum capacitive loading and are 5 Volt tolerant. PCI signals conform to the 3.3 Volt signaling environment. All FREEDM-32P672 non-PClI outputs and bi-directionals have 4 mA drive capability, except the PCICLKO, RBCLK, TBCLK and RBD outputs which have 8 mAdrive capability. All FREEDM-32P672 outputs can be tristated under control of the IEEE P1149.1 test access port, even those which do not tristate under normal operation. All non-PCI outputs and bi-directionals are 5 V tolerant when tristated. All non-PCl inputs are Schmitt triggered. Inputs TMS, TDI and TRSTB have internal pull-up resistors. Power to the VDD3V3 pins should be applied before power to the VDD2V5 pins is applied. Similarly, power to the VDD2V5 pins should be removed before power to the VDD3V3 pins is removed. PROPRIETARY AND CONFIDENTIAL 37r > [\ I PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET eee ence rene ee eee eee eee eee es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9 FUNCTIONAL DESCRIPTION 9.1 High Speed Multi-Vendor Integration Protocol (H-MVIP) H-MVIP defines a synchronous, time division multiplexed (TDM) bus of Nx64 Kbps constant bit rate (CBR) data streams. Each 64 Kbps data stream (time- slot) carries an 8-bit byte of HDLC traffic, as described in the following section, and is characterised by 8 KHz framing. H-MVIP supports higher bandwidth applications on existing telephony networks by fitting more time-slots into a 125 us frame. The FREEDM-32P672 supports H-MVIP data rates of 2.048 Mbps and 8.192 Mbps with 32 or 128 time-slots per frame and associated clocking frequencies of 4.096 and 16.384 MHz respectively. Figure 1 shows a diagram of the H-MVIP protocol supported by the FREEDM-32P672 device. Figure 1 H-MVIP Protocol 125 us Data Clock (4, 16 MHz) Frame Puise Clock (he LIT Ls LI LJ lee | 1 Frame nulse a ese Lt serialData X07 Yee \ e1 \ e2 (ooo \ co | oe | 2 Yeoel a \ oe X | | TS0 | TS 1 ec0o TS 31/127 TS 31/127 9.2 High-Level Data Link Control (HDLC) Protocol Figure 2 shows a diagram of the synchronous HDLC protocol supported by the FREEDM-32P672 device. The incoming stream is examined for flag bytes (01111110 bit pattern) which delineate the opening and closing of the HDLC packet. The packet is bit de-stuffed which discards a "0" bit which directly follows five contiguous "1" bits. The resulting HDLC packet size must be a multiple of an octet (8 bits) and within the expected minimum and maximum packet length limits. The minimum packet length is that of a packet containing two information bytes (address and control) and FCS bytes. For packets with CRC-CCITT as FCS, the minimum packet length is four bytes while those with CRC-32 as FCS, the minimum length is six bytes. An HDLC packet is aborted when seven contiguous "1" bits (with no inserted "0" bits) are received. At least PROPRIETARY AND CONFIDENTIAL 38r? [\ fi ra PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET one flag byte must exist between HDLC packets for delineation. Contiguous flag bytes, or all ones bytes between packets are used as an "inter-frame time fill". Adjacent flag bytes may share zeros. Figure 2 HDLC Frame Flag Information FCS Flag Flag |} HDLC Packet > The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. Figure 3 shows a CRC encoder block diagram using the generating polynomial g(X) = 1 + g1X + goX?2 +...+ gn-4X-1 + X". The CRC-CCITT FCS is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 FCS is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X44 X5 + X7 + X8 + X10 + X11 + X12 + X16 + K22 + X23 + X26 + X32. The first FCS bit received is the residue of the highest term. Figure 3 - CRC Generator Dy Te D, | 4) D5 To ) D,.1 | Message LSB Parity Check Digits MSB 9.3 Receive Channel Assigner The Receive Channel Assigner block (RCAS672) processes up to 32 serial links. Links may be configured to support 2.048 or 8.192 Mbps H-MVIP traffic, to support T1/J1/E1 channelised traffic or to support unchannelised traffic. When configured to support 2.048 Mbps H-MVIP traffic, each group of 8 links share a clock and frame pulse. All links configured for 8.192 Mops H-MVIP traffic share a common clock and frame pulse. For T1/J1/E1 channelised traffic or for unchannelised traffic, each link is independent and has its own associated clock. For each link, the RCAS672 performs a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL672) at SYSCLK PROPRIETARY AND CONFIDENTIAL 39rv PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee ees PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 rate. In the event where multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis with link #0 having the highest priority and link #31 the lowest. From the point of view of the RCAS672, links configured for H-MVIP traffic behave identically to links configured for T1/J1/E1 channelised or unchannelised traffic in the back end, only differing on the link side as described herein. First, the number of time-slots in each frame is programmable to be 32 or 128 and has an associated data clock frequency that is double the data rate. This provides more bandwidth per link for applications requiring higher data densities on a single link. Second, H-MVIP links reference the start of each frame with a frame pulse, thereby avoiding having to gap the link clock during the framing bits/bytes of each frame. The frame pulse is provided by an H-MVIP bus master and ensures that all agents sharing the H-MVIP bus remain synchronized. When configured for operation in 2.048 Mbps mode, the frame pulse is sampled using the same clock which samples the data. When configured for operation in 8.192 Mbps H-MVIP mode, the frame pulse is sampled using a separate frame pulse clock provided by an H-MVIP bus master. The frame pulse clock has a synchronous timing relationship to the data clock. Third, not all links are independent. When configured for operation in 2.048 Mbps H-MVIP mode, each group of 8 links share a clock and a frame pulse. Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 each share a clock and a frame pulse. Not all 8 links within each group need to be configured for operation in 2.048 Mbps H-MVIP mode. However, any link within each logical group of 8 which is configured for 2.048 Mbps H-MVIP operation will share the same clock and frame pulse. When configured for operation in 8.192 Mbps H-MVIP mode, links 4m (0<m<7) share a frame pulse, a data clock and a frame pulse clock. Again, not all eight 4m (O<m<7) links need to be configured for operation in 8.192 Mbps H-MVIP mode, however, any link which is configured for 8.192 Mbps H-MVIP operation will share the same frame pulse, data clock and frame pulse clock. If link 4m is configured for 8.192 Mbps H-MVIP operation, then data transferred on that link is spread over links 4m, 4m+1, 4m+2 and 4m+3 from a channel assigner point of view. Accordingly, when link 4m is configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 must also be configured for operation in 8.192 Mbps H-MVIP mode. In the back end, the RCAS672 extracts and processes the time-slots in the same way as channelised T1/J1/E1 traffic. Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to a different channel. The RCAS672 performs a table lookup to associate the link and time-slot identity with a channel. T1/J1 and E1 framing bits/bytes are identified by observing the gap in the link clock which is squelched during the framing bits/bytes. For unchannelised links, clock rates are limited to 51.84 MHz for links #0 to #2 and | limited to 10 MHz for the remaining links. All data on each link belongs to one PROPRIETARY AND CONFIDENTIAL 40DATASHEET i [\ I PMC-Sierra, Inc. PM7380 FREEDM-32P672 ne PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.3.1 channel. For the case of a mixture of channelised, unchannelised and H-MVIP links, the total instantaneous link rate over all the links is limited to 64 MHz. The RCAS672 performs a table lookup using only the link number to determine the associated channel, as time-slots are non-existent in unchannelised links. The RCAS672 provides diagnostic loopback that is selectable on a per channel basis. The RCAS672 does not support diagnostic loopback for links configured as H-MVIP. When a channel is in diagnostic loopback, stream data on the received links originally destined for that channel is ignored. Transmit data of that channel is substituted in its place. Line Interface Translator (LIT) The LIT block translates the information on the 32 physical links into a suitable format for interpretation by the Line Interface block. The LIT block performs three functions: data translation, clock translation and frame pulse generation. When link 4m (O<m<7) is configured for operation in 8.192 Mbps H-MVIP mode, the LIT block translates the 128 time-slots on link 4m to the Line Interface block across links 4m, 4m+1, 4m+2 and 4m+3. The LIT block provides time-slots 0 through 31, 32 through 63, 64 through 95 and 96 through 127 to the Line Interface block on links 4m, 4m+1, 4m+2 and 4m+3 respectively. When link 4m is configured for operation in 8.192 Mbps H-MVIP mode, data cannot be received on inputs RD[4m+3:4m+1]. However, links 4m+1, 4m+2 and 4m+3 must be programmed in the RCAS672 Link Configuration register for 8.192 Mbps H-MVIP operation. When links are configured for operation in 2.048 Mbps H- MVIP mode, channelised T1/J1/E1 mode or unchannelised mode, the LIT block does not perform any translation on the link data. When a link is configured for operation in H-MVIP mode, the LIT block divides the appropriate clock (RMVCK\[n] for 2.048 Mbps H-MVIP and RMV8DC for 8.192 Mbps H-MVIP) by two and provides this divided down clock to the Line Interface block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the LIT block does not perform any translation on the link clock. When a link is configured for operation in H-MVIP mode, the LIT block samples the appropriate frame pulse (RF PB[n] for 2.048 Mbps H-MVIP and RFP8B for 8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the gapped clock is passed to the LIT block unmodified. PROPRIETARY AND CONFIDENTIAL 41DATASHEET r [\ /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 A PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.3.2 9.3.3 9.3.4 Line Interface There are 32 identical line interface blocks in the RCAS672. Each line interface block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and the other H-MVIP streams. Based on configuration, only one of the sub-blocks are active at one time; the other is held reset. Each sub-block contains a bit counter, an 8-bit shift register and a holding register. Each sub-block performs serial to parallel conversion. Whenever the holding register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface would respond with the data residing in the holding register in the active sub-block. To support H-MVIP links, each line interface block contains a time-slot counter. The time-siot counter is incremented each time the holding register is updated. When a frame pulse occurs, the time-slot counter is initialised to indicate that the next bit is the most significant bit of the first time-slot. To support non H-MVIP channelised links, each line interface block contains a time-slot counter and a clock activity monitor. The time-slot counter is incremented each time the holding register is updated. The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is cleared by a rising edge of the receive clock (RCLK[n]). A framing bit (T1/J1) or a framing byte (E1) is detected when the counter reaches a programmable threshold, in which case, the bit and time-slot counters are initialised to indicate that the next bit is the most significant bit of the first time-slot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset. Priority Encoder The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from the line interface attached to RD[0] to that attached to RD[31]. Thus, simultaneous requests from RD[m] will be serviced ahead of RD[n], if m <n. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for host microprocessor accesses to the provisioning RAMs. Channel Assigner The channel assigner block determines the channel number of the data byte currently being processed. The block contains a 1024 word channel provision RAM. The address of the RAM is constructed from concatenating the link PROPRIETARY AND CONFIDENTIAL 42DATASHEET rit fi cf PMC-Sierra, Inc. PM7380 FREEDM-32P672 eae PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.3.5 number and the time-slot number of the current data byte. The fields of each RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. Loopback Controller The loopback controller block implements the channel based diagnostic loopback function. Every valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer block (THDL672) is written into a 64 word FIFO. The loopback controller monitors for an idle time-slot or a time-slot carrying a channel with diagnostic loopback enabled. If either conditions hold, the current data byte is replaced by data retrieved from the loopback data FIFO. 9.4 Receive HDLC Processor / Partial Packet Buffer The Receive HDLC Processor / Partial Packet Buffer block (RHDL672) processes up to 672 synchronous transmission HDLC data streams. Each channel can be individually configured to perform flag sequence detection, bit de-stuffing and CRC-CCITT or CRC-32 verification. The packet data is written into the partial packet buffer. At the end of a frame, packet status including CRC error, octet alignment error and maximum length violation are also loaded into the partial packet buffer. Alternatively, a channel can be provisioned as transparent, in which case, the HDLC data stream is passed to the partial packet buffer processor verbatim. There is a natural precedence in the alarms detectable on a receive packet. Once a packet exceeds the programmable maximum packet length, no further processing is performed on it. Thus, octet alignment detection, FCS verification and abort recognition are squelched on packets with a maximum length violation. An abort indication squelches octet alignment detection, minimum packet length violations, and FCS verification. In addition, FCS verification is only performed on packets that do not have octet alignment errors, in order to allow the RHDL672 to perform CRC calculations on a byte-basis. The partial packet buffer is an 32 Kbyte RAM that is divided into 16-byte blocks. Each block has an associated pointer which points to another block. A logical FIFO is created for each provisioned channel by programming the block pointers to form a circular linked list. A channel FIFO can be assigned a minimum of 3 blocks (48 bytes) and a maximum of 2048 blocks (32 Kbytes). The depth of the channel FIFOs are monitored in a round-robin fashion. Requests are made to the Receive DMA Controller block (RMAC672) to transfer, to the PCI host memory, data in channel FIFOs with depths exceeding their associated threshold. PROPRIETARY AND CONFIDENTIAL 43DATASHEET r? [\ MA c PMC-Sierra, Inc. PM7380 FREEDM-32P672 ae PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.4.1 9.4.2 HDLC Processor The HDLC processor is a time-slice state machine which can process up to 672 independent channels. The state vector and provisioning information for each channel is stored ina RAM. Whenever new channel data arrives, the appropriate state vector is read from the RAM, processed and written back to the RAM. The HDLC state-machine can be configured to perform flag delineation, bit de-stuffing, CRC verification and length monitoring. The resulting HDLC data and status information is passed to the partial packet buffer processor to be stored in the appropriate channel FIFO buffer. The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle generated by the upstream Receive Channel Assigner block (RCAS672). Writing new provisioning data to a channel resets the channel's entire state vector. Partial Packet Buffer Processor The partial packet buffer processor controls the 32 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of the RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. System software is responsible for the assignment of blocks to individual channel FIFOs. Figure 4 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO. The partial packet buffer processor is divided into three sections: writer, reader and roamer. The writer is a time-sliced state machine which writes the HDLC data and status information from the HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers channel FIFO data from the packet buffer RAM to the downstream Receive DMA Controller block (RMAC672). The roamer is a time-sliced state machine which tracks channel FIFO buffer depths and signals the reader to service a particular channel. If a buffer over-run occurs, the writer ends the current packet from the HDLC processor in the channel FIFO with an over-run flag and ignores the rest of the packet. PROPRIETARY AND CONFIDENTIAL 44i > [\ f\ co PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 4 Partial Packet Buffer Structure Partial Packet Block Buffer RAM Pointer RAM Block 0 16 bytes Block 0 XX Block1| 16 bytes Block 1 oxo3Stsd* Block 2 16 bytes Block 2 XX Block 3 16 bytes Block 3 OxC8 ' I I I 1 i} I { i I I i i l 1 1 i] ' Block 200 16 bytes Block 200 0x01 I I t I I I U | t I I I ( I I I ' I Block 2047 16 bytes Block 2047 XX The FIFO algorithm of the partial packet buffer processor is based on a programmable per-channel transfer size. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of transactions. Whenever the partial packet writer fills a transfer-sized number of blocks or writes an end-of-packet flag to the channel FIFO, a transaction is created. Whenever the partial packet reader transmits a transfer-size number of blocks or an end-of-packet flag to the RMAC672 block, a transaction is deleted. Thus, small packets less than the transfer size will be naturally transferred to the RMAC672 block without having to precisely track the number of full blocks in the channel FIFO. The partial packet roamer performs the transaction accounting for all channel FIFOs. The roamer increments the transaction count when the writer signals a new transaction and sets a per-channel flag to indicate a non-zero transaction count. The roamer searches the flags in a round-robin fashion to decide for which channel FIFO to request transfer by the RMAC672 block. The roamer informs the partial packet reader of the channel to process. The reader transfers the data to the RMAC672 until the channel transfer size is reached or an end of PROPRIETARY AND CONFIDENTIAL 45DATASHEET r- [\ fi cy PMC-Sierra, Inc. PM7380 FREEDM-32P672 a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 packet is detected. The reader then informs the roamer that a transaction is consumed. The roamer updates its transaction count and clears the non-zero transaction count flag if required. The roamer then services the next channel with its transaction flag set high. The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The writer declares a channel FIFO overrun whenever the writer tries to store data to a block with a set flag. In order to support optional removal of the FCS from the packet data, the writer does not declare a block as filled (set the block flag nor increment the transaction count) until the first double word of the next block in channel FIFO is filled. If the end of a packet resides in the first double word, the writer declares both blocks as full at the same time. When the reader finishes processing a transaction, it examines the first double word of the next block for the end-of-packet flag. If the first double word of the next block contains only FCS bytes, the reader would, optionally, process next transaction (end-of-packet) and consume the block, as it contains information not transferred to the RMAC672 block. 9.5 Receive DMA Controller 9.5.1 The Receive DMA Controller block (RMAC672) is a DMA controller which stores received packet data in host computer memory. The RMAC672 is not directly connected to the host memory PCI bus. Memory accesses are serviced by a downstream PCI controller block (GPIC). The RMAC672 and the host exchange information using receive packet descriptors (RPDs). The descriptor contains the size and location of buffers in host memory and the packet status information associated with the data in each buffer. RPDs are transferred from the RMAC6/72 to the host and vice versa using descriptor reference queues. The RMAC672 maintains all the pointers for the operation of the queues. The RMAC672 provides two receive packet descriptor reference (RPDR) free queues to support small and large buffers. The RMAC672 acquires free buffers by reading RPDRs from the free queues. After a packet is received, the RMAC672 places the associated RPDR onto a RPDR ready queue. To minimize host bus accesses, the RMAC672 maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 672 receive channels. Data Structures For packet data, the RMAC672 communicates with the host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), the PROPRIETARY AND CONFIDENTIAL 46i > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Receive Packet Descriptor Reference Ready (RPDRR) queue and the Receive Packet Descriptor Reference Small and Large Buffer Free (RPDRF) queues. The RMACG672 copies packet data to data buffers in host memory. The RPD, RPDR, RPDRR queue, and Small and Large RPDRF queues are data structures which are used to transfer host memory data buffer information. All five data structures are manipulated by both the RMAC672 and the host computer. The RPD holds the data buffer size, data buffer address, and packet status information. The RPDR is a pointer which is used to index into a table of RPDs. The RPDRR queue and RPDRF queues allow the RMAC672 and the host to pass RPDRs back and forth. These data structures are described in more detail in the following sections. Receive Packet Descriptor The Receive Packet Descriptors (RPDs) pass buffer and packet information between the RMAC672 and the host. Both the RMAC672 and the host read and write information in the RPDs. The host writes RPD fields which describe the size and address of data buffers in host memory. The RMAC672 writes RPD fields which provide number of bytes used in each data buffer, RPD link information, and the status of the received packet. RPDs are stored in host memory in a Receive Packet Descriptor Table which is described in a later section. The Receive Packet Descriptor structure is shown in Figure 5. Figure 5 Receive Packet Descriptor Bit 31 0 Data Buffer Start Address [31:0] Bytes in Buffer [15:0] Status [5:0] Offset(1:0] |} CE RCC(9:0] Res {4} Next RPD Pointer [14:0] Receive Buffer Size (15:0) Table 6 Receive Packet Descriptor Fields Field Description Data Buffer Start The Data Buffer Start Address[31:0] bits point to the data Address[31:0] buffer in host memory. This field is expected to be configured by the Host during initialisation. The Data Buffer Start Address field is valid in all RPDs. PROPRIETARY AND CONFIDENTIAL 47DATASHEET PMC-1990262 r > [\ / PMC-Sierra, Inc. PM7380 FREEDM-32P672 Eee ener ee es ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Field Description | CE The Chain End (CE) bit indicates the end of a linked list of RPDs. When CE is set to logic one, the current RPD is the last RPD of a linked list of RPDs. When CE is set to logic zero, the current RPD is not the last RPD of a linked list. The CE bit is valid for all RPDs written by the RMAC672 to the Receive Ready Queue. When a packet requires only one RPD, the CE bit is set to logic one. The CE bit is | ignored for all RPDs read by the RMAC672 from the Receive Free Queues, each of which is assumed to point to only one buffer, i.e. not a chain. Offset[1:0] The Offset[1:0] bits indicate the byte offset of the data packet from the start of the buffer. If this value is non- zero, there will be dummy (i.e. undefined) bytes at the start of the data buffer prior to the packet data proper. For a linked list of RPDs, only the first RPD's Offset field is valid. All other RPD Offset fields of the linked list are set to 0. Status [5:0] The Status[5:0] bits indicate the status of the received packet. Status[0] Rx buffer overrun Status[1] Packet exceeds max. allowed size Status[2] CRC error Status[3] Packet Length not an exact no. of bytes Status[4] HDLC abort detected Status[5] Unused (set to 0) For a linked list of RPDs, only the last RPD's Status field is valid. All other RPD Status fields of the linked list are invalid and should be ignored. When a packet requires only one RPD, the Status field is valid. Bytes in Buffer [15:0] The Bytes in Buffer[15:0] bits indicate the number of bytes actually used in the current RPD's data buffer to store packet data. The count excludes the 'dummy' bytes inserted as a result of a non-zero Offset field. A count greater than 32767 bytes indicates a packet that is shorter than the expected length of the FCS field. The Bytes in Buffer field is invalid when Status[0] or Status[4] is asserted . PROPRIETARY AND CONFIDENTIAL 48r? [\ fi cr PMC-Sierra, Inc. PM7380 FREEDM-32P672 nn DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Field Description Next RPD Pointer | The Next RPD Pointer[14:0] bits store a RPDR which [14:0] enables the RMAC672 to support linked lists of RPDs. This field, which is only valid when CE is equal to logic zero, contains the RPDR to the next RPD in a linked list. The RMAC672 links RPDs when more than one buffer is needed to store a packet. The Next RPD Pointer is not valid for the last RPD ina linked list (when CE=1). When a packet requires only one RPD, the Next RPD Pointer field is not valid. RCC[9:0] The Receive Channel Code (RCC[9:0]) bits are used by the RMAC672 to associate a RPD with a channel. For a linked list of RPDs, all the RPDs RCC[9:0] fields are valid. i.e. all contain the same channel value. Receive Buffer Size | The Receive Buffer Size[15:0] bits indicate the size in [15:0] bytes of the current RPD's data buffer. This field is expected to be configured by the Host during initialisation. The Receive Buffer Size must be a non-zero integer multiple of sixteen and less than or equal to 32752. The Receive Buffer Size field is valid in all RPDs. The Receive Buffer Size and Data Buffer Start Address fields are written only by the host. The RMAC672 reads these fields to determine where to store packet data. All other fields are written only by the RMAC672. Receive Packet Descriptor Table The Receive Packet Descriptor Table resides in host memory and stores all the RPDs. The RPD Table can contain a maximum of 32768 RPDs. The base of the RPD table is user programmable using the Rx Packet Descriptor Table Base (RPDTB) register. The table is indexed by a Receive Packet Descriptor Reference (RPDR) which is a 15-bit pointer defining the offset of a RPD from the table base. Thus, as shown in the following diagram, a RPD can be located by adding the RPDR to the Rx Packet Descriptor Table Base register. PROPRIETARY AND CONFIDENTIAL 49r> [\ fl c" PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 6 - Receive Packet Descriptor Table RPDTB[31:4] = Rx Packet Descriptor Table Base register RPDR[14:0] = Receive Packet Descriptor Reference RPD_ADDRJ31:0] = Receive Packet Descriptor Address Bit 31 Bit 0 | RPDTB[31:4] _ | 0000} + RPDR[14:0 = | | RPD_ ADDR(31:0] | Bit 31 Bit O RPD Dword 0 Dword 1 Dword 2 Dword 3 Dword 0 RPD 1 RPD_ADDR RPD 2 Dword 3 Dword 0 RPD 32768 Dword 3 The Receive Packet Descriptor Table resides in host memory. The Rx Packet Descriptor Table Base register resides in the RMAC672; this register is initialised by the host. The RPDRs reside in host memory and are accessed using receive packet queues which are described in the next section. PROPRIETARY AND CONFIDENTIAL 50r> [\ y/ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Receive Packet Queues Receive Packet Queues are used to transfer RPDRs between the host and the RMAC672. There are three queues: a RPDR Large Buffer Free Queue (RPDRLFQ), aRPDR Small Buffer Free Queue (RPDRSFQ) and a RPDR Ready Queue (RPDRRQ). The free queues contain RPDRs referencing RPDs that define free buffers. The ready queue contains RPDRs referencing RPDs that define buffers ready for host processing. The RMAC672 pulls RPDRs from the free queues when it needs free data buffers. The RMAC672 places an RPDR onto the ready queue after it has filled the buffers with data from each complete packet. The host removes RPDRs from the ready queue to process the data buffers. The host places the RPDRs back onto the free queues after it finishes reading the data from the buffers. When starting to process a packet, the RMAC672 uses a small buffer RPD to store the first buffer of packet data. If the packet data requires more than one buffer, the RMAC672 uses large buffer RPDs to store the remainder of the packet. The RMAC672 links together all the RPDs required to store the packet and returns the RPDR associated with the first RPD onto the ready queue. All receive packet queues reside in host memory and are defined by the Rx Queue Base (RQB) register and index registers which reside in the RMAC672. The Rx Queue Base is the base address for the receive packet queues. Each packet queue has four index registers which define the start and end of the queue and the read and write locations of the queue. Each index register is 16 bits in length and defines an offset from the Rx Queue Base. Thus, as shown in the Figure 7, the host address of a RPDR is calculated by adding the index register to the Rx Queue Base register. The host initializes the Rx Queue Base register and all the index registers. When an entity (either the RMAC672 or the host) removes elements from a queue, the entity updates the read pointer for that queue. When an entity (either the RMAC672 or the host) places elements onto a queue, the entity updates the write pointer for that queue. The read index for each queue points to the last valid RPDR read while the write index points to where the next RPDR can be written. The start index points to the first valid location within the queue; an RPDR can be written to this location. However, the end index points to a location that is beyond a queue; an RPDR can not be written to this location. Note however, the start index of one queue can be set to the end index of another queue. A queue is empty when the read index is one less than the write index; a queue is also empty if the read index is one less than the end index and the write index equals the start index. A queue is full when the read index is equal to the write index. Figure 7 shows the RPDR reference queues. PROPRIETARY AND CONFIDENTIAL 51r Vi Cc" PMC-Sierra, Inc. DATASHEET PMC-1990262 ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 7 - RPDRF and RPDRR Queues Base Address: RQB[31:2] = Rx Queve Base register Index Registers: Large Buffer Free Queue: RPORLFQS(15:0] = RPOR Large Free Quaue Start register RPDRLFOQW/[15:0] = RPDR Large Free Queue Write register RPDRLFQR[15:0] = RPOR Large Free Queue Read register RPDORLFQE[15:0) = RPDR Large Free Queue End register Ready Queue: RPDRROS[15:0] = RPOR Ready Queue Start register RPDRROW([15:0] = RPDR Ready Queue Write register RPDRRQR[15:0] = RPDR Ready Queue Read register RPDRRQE[15:0] = RPDR Ready Queue End register Small Buffer Free Queue: RPORSFQS[15:0] = RPBR Smalii Free Queue Start register RPORSFQW[15:0] = RPDR Small Free Queue Write register RPDRSFQR[15:0] = RPDR Small Frea Queue Read register RPDRSFQE[15:0] = RPOR Small Free Queue End register Base Address PRB 31:2) fog + Index Register + | indexi15:0] _[ od Host Address Rx Packet Descriptor Reference Queue Memory Map Bit 31 Bit O RPDRRQS Status + RPDR RPDRROAR Status + RPDR Status + Status + RPDR RPDRRQW Status + RPDR Status + RPOR RPDRRQE RPORLFQS RPORLFQAR RPDRLFQW RPDRLFOE RPDRSFQS RPDRSFQR RPORSFQW RPDRSFQE Host Memory ROB RPD Reference Queues 256KB PROPRIETARY AND CONFIDENTIAL 52r- [\ A Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1)) = 3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue. As shown in Figure 7, the ready queue elements have a status field as well as an RPDR field. The RMAC672 fills in the status field to mark whether a packet was successfully received or not. The host reads the status field. The ready queue element is shown in Table 7 below along with the definition of the status bits. If the RMAC672 requires a buffer of a particular size (i.e. small or large) and no RPDR is available in the corresponding free queue, a RPDR from the other free queue is substituted. The host may, therefore, force the RMAC672 to store received data in buffers of only one size by setting one of the free queues to zero length, i.e. by setting the start and end index registers of one of the queues to equal values. If the RMAC672 requires a buffer and neither free queue contains RPDRs, an RPQ_ERRI interrupt is generated. Table 7 RPDRR Queue Element Bit 16 Bit 0 STATUS[1:0] RPDR[14:0] Field Description STATUS[1:0] | The encoding for the status field is as follows: 00 Successful reception of packet. 01 Unsuccessful reception of packet. 10 Unprovisioned partial packet. 11 - Partial packet returned due to RAWMAX limit being reached. RPDR[14:0} The RPDR[14:0] field defines the offset of the first RPD in a linked chain of RPDs, each pointing to a buffer containing the received data. As described previously, the RMAC672 links RPDs together if more than one buffer is needed for a packet. The RMAC672 links additional buffer RPDs to the end of the chain as required until the entire packet is copied to host memory (provided that the host has not disabled use of both the small and large free queues by setting one of them to length zero). After storing the packet data, the RMAC672 places the STATUS+RPDR for the first RPD onto the ready queue. Only the RPDR associated with the first RPD is placed onto the ready queue. All other required RPDs are linked to the first RPD as shown in Figure 8. PROPRIETARY AND CONFIDENTIAL 53ri AI o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Although a STATUS+RPDR only totals to 17 bits, each queue entry is a dword, i.e. 32 bits. When the RMAC672 block writes a STATUS+RPDR to the ready queue, it sets the remaining 7 bits in the third byte to zero and the fourth byte is unmodified. Figure 8 - RPDRR Queue Operation Rx Packet Descriptor Reference Ready Queue Bit 31 Bit 0 buffer -packet M RPDRRQ_START_ADDR RPDRRQ_READ_ADDR RPD - 16 bytes buffer -packet N RPDRRQ_WRITE_ADDR RPD - 16 bytes RPD - 16 bytes buffer -Start of packet O RPD - 16 bytes buffer -middle of packet O RPD - 16 bytes buffer -end of packet O RPDRRQ_END_ADDR Receive Channel Descriptor Reference Table On a per-channel basis, the RMAC672 caches information such as the current DMA information in a Receive Channel Descriptor Reference (RCDR) Table. The RMAC672 can process 672 channels and stores three dwords of information per channel. This information is cached internally in order to PROPRIETARY AND CONFIDENTIAL 54i 2 [\ fl \ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 decrease the number of host bus accesses required to process each data packet. The structure of the RCDR table is shown in Figure 9. Figure 9 Receive Channel Descriptor Reference Table Bit 31 Bit 0 RCC O | Bytes Avail. in Buffer[14:0} |RBC[1:0] RPD Pointer[14:0] Buffer Size[14:0] Res} V | Start RPD Pointer[14:0] DMA Current Address[3 1:0] RCC 1 | Bytes Avail. in Buffer[14:0] |RBC[1:0] RPD Pointer[14:0] Buffer Size[14:0] Res| V | Start RPD Pointer[14:0] DMA Current Address[31:0] RCC 671 | Bytes Avail. in Buffer[14:0] |RBC[1:0] RPD Pointer[14:0] Buffer Size[14:0] Res] V | Start RPD Pointer[14:0] DMA Current Address[31:0] Table 8 Receive Channel Descriptor Reference Table Fields Field Description Bytes Available in This field is used to keep track of the number of bytes Buffer[15:0] available in the current data buffer. The RMAC672 initialises the Bytes Available in Buffer to the Receive Buffer Size minus the offset at the head of the buffer. The field is decremented each time a byte is written into the buffer. RBC[1:0] This field is used to keep track of the number of buffers used when storing raw (i.e. non packet delimited) data. The RMAC672 initialises the RBC field to the value of the RAWMAX[1:0] field in the RMAC Control Register. The field is decremented each time a buffer is filled with data. If the field reaches zero, the chain of RPDs is placed on the ready queue and a new chain started. RPD Pointer[{14:0] This field contains the pointer to the current RPD. PROPRIETARY AND CONFIDENTIAL 55r> [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET cece ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Field Description Buffer Size[14:0] This field contains the size in bytes of the buffer currently being written to. V This bit (Valid) indicates whether a packet is currently being received on the DMA channel. When the V bit is set to 1, the other fields in the RCDR table entry for the DMA channel contain valid information. Start RPD This field contains the pointer to the first RPD for the Pointer[14:0] packet being received. DMA Current The DMA Current Address [31:0] bits holds the host Address[31:0] address of the next dword in the current buffer. The RMAC672 increments this field on each access to the buffer. 9.5.2 DMA Transaction Controller The DMA Transaction Controller coordinates the reception of data packets from the Receive Packet Interface and their subsequent storage in host memory. A packet may be received over a number of separate transactions, interleaved with transactions belonging to other DMA channels. As well as sending the received data to host memory, the DMA Transaction Controller initiates data transactions of its own for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory. 9.5.3 Write Data Pipeline/Mux The Write Data Pipeline/Mux performs two functions. First, it pipelines receive data between the RHDL672 block and the GPIC block, inserting enough delay to enable the DMA Transaction Controller to generate appropriate control signals at the GPIC interface. Second, it provides a multiplexor to the data out lines on the GPIC interface, allowing the DMA Transaction Controller to output data relating to the transactions the controller itself initiates. 9.5.4 Descriptor Information Cache The Descriptor Information Cache provides the storage for the Receive Channel Descriptor Reference (RCDR) Table described above (Figure 9). PROPRIETARY AND CONFIDENTIAL 56r-[\ fA o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.5.5 Free Queue Cache The Free Queue Cache block implements the 6 element RPDR Small Buffer Free Queue cache and the 6 element RPDR Large Buffer Free Queue cache. These caches are used to store free small buffer and large buffer RPDRs. Caching RPDRs reduces the number of host bus accesses that the RMAC672 makes. Each cache is managed independently. The elements of the cache are consumed one at a time as they are needed by the RMAC672. The RPDR small buffer cache is reloaded when it is empty and the RMAC672 requires a new small buffer RPDR. The large buffer RPDR cache is reloaded when it is empty and the RMAC672 requires a new large buffer RPDR. When reloading either of the caches, the appropriate cache controller will read up to six new elements. The cache controller may read fewer than six elements if there are fewer than six new elements available, or the read pointer index is within six elements of the end of the free queue. If the read pointer is near the end of the free queue, the cache controller reads only to the end of the queue and does not start reading from the top of the queue until the next time a reload is required. To do so would require two host memory transactions and would be of no benefit. 9.6 PCI Controller The General-Purpose Peripheral Component Interconnect Controller block (GPIC) provides a 32-bit Master and Target interface core which contains all the required control functions for full Peripheral Component Interconnect (PCI) Bus Revision 2.1 compliance. Communications between the PCI bus and other FREEDM-32P672 blocks can be made through either an internal asynchronous 16-bit bus or through one of two synchronous FIFO interfaces. One of the FIFO interfaces is dedicated to servicing the Receive DMA Controller block (RMAC672) and the other to the Transmit DMA Controller block (TMAC672). The GPIC supports a 32-bit PC] bus operating at up to 66 MHz and bridges between the timing domain of the DMA controllers (SYSCLK) and the timing domain of the PCI bus (PCICLK). The GPIC is backwards compatible and will operate at 33 MHz when connected to a 33 MHz PCI bus. By itself, the GPIC does not generate any PCI bus accesses. All transactions on the bus are initiated by another PCI bus master or by the core device. The GPIC transforms each access to and from the PCI bus to the intended target or initiator in the core device. Except for the configuration space registers and parity generating/checking, the GPIC performs no operations on the data. The GPIC is made up of four sections: master state machine, a target state machine, internal microprocessor bus interface and error/bus controller. The PROPRIETARY AND CONFIDENTIAL 57DATASHEET roi / ri PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.6.1 target and master blocks operate independent of each other. The error/bus control block monitors the control signals from the target and master blocks to determine the state of the PC! I/O pads. This block also generates and/or checks parity for all data going to or coming from the PCI bus. The internal microprocessor bus interface block contains configuration and status registers together with the production test logic for the GPIC block. Master Machine The GPIC master machine translates requests from the RMAC672 and TMAC672 block interfaces into PCI bus transactions. The GPIC initiates four types of PCI cycles: memory read (burst or single), memory read multiple, memory read line and memory write (burst or single). The number of data transfers in any cycle is controlled by the DMA controllers. The maximum burst size is determined by the particular data path. Aread cycle to the RMAC6772 is restricted to a maximum burst size of 8 dwords and a write cycle is limited to a maximum of 64. The TMAC672 interface has a limit of 64 dwords on a read cycle and 8 on a write cycle. In response to a DMA controller requesting a cycle, the GPIC must arbitrate for control of the PCI bus. In the event that the RMAC672 and TMAC672 request service simultaneously, the GPIC66 processes the RMAC672 DMA operation first. When an external PCI bus arbitrator issues a Grant in response to the Request from the GPIC, the master state machine monitors the PCI bus to insure that the previous master has completed its transaction and has released the bus before beginning the cycle. Once the GPIC has control of the bus, it will assert the FRAME signal and drive the bus with the address and command. The value for the address is provided by the selected DMA controller. After the initial data transfer, the GPIC tracks the address for all remaining transfers in the burst internally in case the GPIC is disconnected by the target and must retry the transaction. The target of the GPIC master burst cycle has the option of stopping or disconnecting the burst at any point. In the event of a target disconnect the GPIC will terminate the present cycle and release the PCI bus. if the GPIC is asserting the REQUEST line at the time of the disconnect, it will remove the REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator returns the GRANT, the GPIC will restart the burst access at the next address and continue until the burst is completed or repeat the sequence if the target disconnects again. During burst reads, the GPIC accepts the data without inserting any wait states. Data is written directly into the read FIFO where the RMAC672 or TMAC672 can PROPRIETARY AND CONFIDENTIAL 58i > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET TT PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 remove it at its own rate. During burst writes, the GPIC will output the data without inserting any wait states, but may terminate the transaction early if the local master fails to fill the write FIFO with data before the GPIC requires it. (If a write transaction is terminated early due to data starvation, the GPIC will automatically initiate a further transaction to write the remaining data when it becomes available. ) Normally, the GPIC will begin requesting the PCI bus for a write transaction shortly after data starts to be loaded into the write FIFO by the RMAC672 or TMAC672. The RMAC672, however, is not required to supply a transaction length when writing packet data and in addition, may insert pauses during the transfer. In the case of packet data writes by the RMAC672, the GPIC will hold off requesting the PCI bus until the write FIFO has filled up with a number of dwords equal to a programmable threshold. If the FIFO empties without reaching the end of the transition, the GPIC will terminate the current transaction and restart a new transaction to transfer any remaining data when the RMAC672 signals an end of transaction. Beginning the PCI transaction before all the data is in the write FIFO allows the GPIC to reduce the impact of the bus latency on the core device. Each master PCI cycle generated by the GPIC can be terminated in three ways: Completion, Timeout or Master Abort. The normal mode of operation of the GPIC is to terminate after transferring all the data from the master FIFO selected. As noted above this may involve multiple PCI accesses because of the inability of the target to accept the full burst or data starvation during writes. After the completion of the burst transfer the GPIC will release the bus unless another FIFO is requesting service, in which case if the GRANT is asserted the GPIC will insert one idle cycle on the bus and then start a new transfer. The maximum duration of the a master burst cycle is controlled by the value set in the LATENCY TIMER register in the GPIC Configuration Register block. This value is set by the host on boot and is loaded into a counter in the GPIC master state at the start of each access. If the counter reaches zero and the GRANT signal has been removed the GPIC will release the bus regardless of whether it has completed the present burst cycle. This type of termination is referred to as a Master Time-out. In the case of a Master Time-out the GPIC will remove the REQUEST signal for two PCI clocks and then reassert it to complete the burst cycle. If no target responds to the address placed on the bus by the GPIC after 4 PCI clocks the GPIC will terminate the cycle and flag the cycle in the PCI Command/ Status Configuration Register as a Master Abort. If the Stop on Error enable (SOE_E) bit is set in the GPIC Command Register, the GPIC will not process any more requests until the error condition is cleared. If the SOE_E is not set, the GPIC will discard the REQUEST and indicate to the local master that the cycle is PROPRIETARY AND CONFIDENTIAL 59DATASHEET r Vi ees PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee eee eee eee eee eee eee eee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.6.2 complete. This action will result in any write data being lost and any read data being erroneous. Master Local Bus Interface The master local bus is a 32 bit data bus which connects the local master device to the GPIC. The GPIC contains two local master interface blocks, with one supporting the RMAC672 and the other the TMAC672. Each local master interface has been optimised to support the traffic pattern generated by the RMAC672 or the TMAC672 and are not interchangeable. The data path between the GPIC and local master device provides a mechanism to segregate the system timing domain of the core from the PCI bus. Transfers on each of the RMAC672 and TMAC672 interfaces are timed to its own system clock. The DMA controllers isolated from all aspects of the PCI bus protocol, and instead sees a simple synchronous protocol. Read or write cycles on the local master bus will initiate a request for service to the GPIC which will then transfer the data via the PCI bus. The GPIC maximises data throughput between the PCI bus and the local device by paralleling local bus data transfers with PCI access latency. The GPIC allows either DMA controller to write data independent of each other and independent of PCI bus control. The GPIC temporarily buffers the data from each DMA controller while it is arbitrating for control of the PCI bus. After completion of a write transfer, the DMA controller is then released to perform other tasks. The GPIC can buffer only a single transaction from each DMA controller. Read accesses on the local bus are optimised by allowing the DMA controllers access to the data from the PCI bus as soon as the first data becomes available. After the initial synchronisation and PC! bus latency data is transferred at the slower of PCI bus rate or the core logic SYSCLK rate. Once a read transaction is started, the DMA controller is held waiting for the ready signal while the GPIC is arbitrating for the PCI bus. All data is passed between the GPIC and the DMA controllers in little Endian format and, in the default mode of operation, the GPIC expects all data on the PCI bus to also be in little Endian format. The GPIC provides a selection bit in the internal Control register which allows the Endian format of the PCI bus data to be changed. If enabled, the GPIC will swizzle all packet data on the PC! bus (but not descriptor references and the contents of descriptors). The swizzling is performed according to the byte address invariance rule, i.e. the only change to the data is the mirror-imaging of byte lanes. The interface for the RMAC672 provides for byte addressability of write transactions whereas the interface for the TMAC672 provides for byte PROPRIETARY AND CONFIDENTIAL 60DATASHEET r-i\ Mi ri PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.6.3 addressability of read transactions. Other transactions must be dword aligned. For byte-addressable transactions, the data transferred between the local device and the GPIC need not be dword aligned with the data as it is presented on the PCl bus. The GPIC will perform any byte-realignment required. In order to complete a transfer involving byte re-alignment, the GPIC may need to add an extra burst cycle to the PCI transaction. Target Machine The GPIC target machine performs all the required functions of a stand alone PCI target device. The target block performs three main functions. The first is the target state machine which controls the protocol! of PCI target accesses to the GPIC. The second function is to provide all PCI Configuration registers. Last, the target block provides a Target Interface to the CBI registers in the other FREEDM-32P672 blocks. The GPIC tracks the PCI bus and decodes all addresses and commands placed on the bus to determine whether to respond to the access. The GPIC responds to the following types of PCI bus commands only: Configuration read and write, memory read and write, memory-read-multiple and memory-read-line which are aliased to memory read and memory-write-and-invalidate which is aliased to memory write. The GPIC will ignore any access that falls within the address range but has any other command type. After accepting a target access as a medium speed device, the FREEDM- 32P672 inserts one wait state for a configuration read/write and five wait states for other command types before completing the transaction by asserting TRDYB. Burst accesses to the GPIC are accepted provided they are of linear type. Ifa master makes a memory access to the GPIC with the lower two address bits set to any value but "00" (linear burst type) the GPIC ignores the cycle. Burst accesses of any length are accepted, but the FREEDM-32P672 will disconnect if the master inserts any wait states during the transaction. The FREEDM-32P672 will also disconnect on every read and write access to configuration space after transferring one Dword of data. Figure 10 illustrates the GPIC address space. PROPRIETARY AND CONFIDENTIAL 61r =4\\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET el PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 10 GPIC Address Map PCI ADDRESS MAP ob ~ CBI Registers Base Address CBI Registers 8KB 4GB _- The GPIC responds with medium timing to master accesses. (i.e. DEVSELB is asserted 2 PCICLK cycles after FRAMEB asserted). The GPIC inserts five wait states on reads to the internal CBI register space (six wait states for the 2nd and subsequent dwords of a burst read). The target machine will only terminate an access with a Retry if the target is locked and another master tries to access the GPIC. The GPIC will terminate any access to a non-burst area with a Disconnect and always with data transferred. The target does not support delayed transactions. The GPIC will perform a Target-Abort termination only in the case of an address parity error in an address that the GPIC claims. PROPRIETARY AND CONFIDENTIAL 62DATASHEET r-[\ / I ie PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.6.4 CBI Bus Interface 9.6.5 The CBI bus interface provides access to the CBI address space of the FREEDM-32P672 blocks. The CBI address space is set by the associated BAR in the PCI Configuration registers. Write transfers to the CBI space always write all 32 bits provided that at least one byte enable is asserted. A write command with all byte enables negated will be ignored. Read transfers always return the 32 bits regardless of the status of the byte enables, as long as at least one byte enable is asserted. Aread command with all byte enables negated will be ignored. Error / Bus Control The Error/Bus Control block monitors signals from both the Target block and Master Block to determine the direction of the PC! bus pads and to generate or check parity. After reset, the GPIC sets all bi-directional PC! bus pads to inputs and monitors the bus for accesses. The Error/Bus control unit remains in this state unless either the Master requests the PCI bus or the Target responds to a PCI Master Access. The Error/Bus control unit decodes the state of each state machine to determine the direction of each PCI bus signal. All PCI bus devices are required to check and generate even parity across AD[31:0] and C/BEBJ[3:0] signals. The GPIC generates parity on Master address and write data phases; the target generates parity on read data phases. The GPIC is required to check parity on all PCI bus phases even if it is not participating in the cycle. But, the GPIC will report parity errors only if the GPIC is involved in the PCI cycle or if the GPIC detects an address parity error or data parity is detected in a PCI special cycle. The GPIC updates the PCI Configuration Status register for all detected error conditions. 9.7 Transmit DMA Controller The Transmit DMA Controller block (TMAC672) is a DMA controller which retrieves packet data from host computer memory for transmission. The minimum packet data length is two bytes. The TMAC672 communicates with the host computer bus through the master interface connected to PCI Controller block (GPIC) which translates host bus specific signals from the host to the master interface format. The TMAC672 uses the master interface whenever it wishes to initiate a host bus read or write; in this case, the TMAC672 is the initiator and the host memory is the target. The TMAC672 and the host exchange information using transmit descriptors (TDs). The descriptor contains the size and location of buffers in host memory PROPRIETARY AND CONFIDENTIAL 63DATASHEET r[\ fi on PMC-Sierra, Inc. PM7380 FREEDM-32P672 | PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.7.1 and the packet status information associated with the data in each buffer. TDs are transferred from the TMAC672 to the host and vice versa using descriptor reference queues. The TMAC672 maintains all the pointers for the operation of the queues. The TMAC672 acquires buffers with data ready for transmission by reading TDRs from a TDR ready queue. After a packet has been transmitted, the TMAC672 places the associated TDR onto a TDR free queue. To minimise host bus accesses, the TMAC672 maintains a descriptor reference table to store current DMA information. This table contains separate DMA information entries for up to 672 transmit channels. The TMAC672 also performs per-channel sorting of packets received in the TDR ready queue to eliminate head-of-line blocking. Data Structures The TMAC672 communicates with the host using Transmit Descriptors (TD), Transmit Descriptor References (TDR), the Transmit Data Reference Ready (TDRR) queue and the Transmit Data Reference Free (TDRF) queue. The TMAC672 reads packet data from data buffers in host memory. The TD, TDR, TDRR queue, and TDRF queue are data structures which are used to transfer host memory data buffer information. All four data structures are manipulated by both the TMAC672 and the host computer. The TD holds the data buffer size, data buffer address, and other packet information. The TDR is a pointer which is used to index into a table of TDs. The TDRR queue and TDRF queue allow the TMAC672 and the host to pass TDRs back and forth. These data structures are described in more detail in the following sections. Transmit Descriptor The Transmit Descriptors (TDs) pass buffer and packet information between the TMAC672 and the host. Both the TMAC672 and the host read and write information in the TDs. TDs are stored in host memory in a Transmit Descriptor Table. The Transmit Descriptor structure is shown in Figure 11. Figure 11 Transmit Descriptor Bit 34 0 Data Buffer Start Address [31:0] TCC{9:0) Bytes tn Buffer (15:0) P lastiioc|cetRes' (2 v TMAC Next TD Pointer[14:0] M Host Next TD Pointer[14:0] Reserved (16) oe Transmit Buffer Size(15:0] PROPRIETARY AND CONFIDENTIAL 64DATASHEET PMC-1990262 ISSUE 4 ri fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 as FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 9 Transmit Descriptor Fields Field Description Data Buffer Start Address [31:0] The Data Buffer Start Address[31:0] bits point to the data buffer in host memory. The Data Buffer Start Address field is valid in all TDs Bytes In Buffer [15:0] The Bytes In Buffer[15:0] field is used by the host to indicate the total number of bytes to be transmitted in the current TD. Zero length buffers are illegal. The Priority bit is set by the host to indicate the priority of the associated packet in a two level quality of service scheme. Packets with its P bit set high are queued in the high priority queue in the TMAC672. Packets with the P bit set low are queued in the low priority queue. Packets in the low priority queue will not begin transmission until the high priority queue is empty. ABT The Abort (ABT) bit is used by the host to abort the transmission of a packet. When ABT is set to logic 1, the packet will be aborted after all the data in the buffer has been transmitted. If ABT is set to logic 1 in the current TD, the M bit must be set low and the CE bit must be set to high. lOC The Interrupt On Complete (lOC) bit is used by the host to instruct the TMAC672 to interrupt the host when the current TD's data buffer has been read. When IOC is logic 1, the TMAC672 asserts the lOCI interrupt when the data buffer has been read. Additionally, the Free Queue FIFO will be flushed. If IOC is logic zero, the TMAC672 will not generate an interrupt and the Free Queue FIFO will operate normally. PROPRIETARY AND CONFIDENTIAL 65DATASHEET PMC-1990262 ISSUE 4 ri /\ co PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee FRAME ENGINE AND DATA LINK MANAGER 32P672 Field Description CE The Chain End (CE) bit is used by the host to indicate the end of a linked list of TDs presented to the TMAC672. The linked list can contain one or more packets as delineated by the M bit (see above). When CE is set to logic 1, the current TD is the last TD of a linked list of TDs. When CE is set to logic 0, the current TD is not the last TD of a linked list. When the current TD is not the last of the linked list, the Host Next TD Pointer[14:0] field is valid, otherwise the field is not valid. Note: When CE is set to logic 1, the only valid value for M is logic 0. Note: When presenting raw (i.e. unpacketised) data for transmission, the host should code the M and CE bits as for a single packet chain, i.e. M=1, CE=0 for all TDs except the last in the chain and M=0, CE=1 for the last TD in the chain. TCC[9:0] The Transmit Channel Code (TCC[9:0]) bits are used by the host to associate a channel with a TD pointed to by a TOR. All TCC[9:0] fields in a linked list of TDs must be set to the same value. The V bit is used to indicate that the TMAC Next TD Pointer field is valid. When set to logic 1, the TMAC Next TD Pointer[14:0] field is valid. When V is set to logic 0, the TMAC Next TD Pointer[14:0] field is invalid. The V bit is used by the host to reclaim data buffers in the event that data presented to the TMAC672 is returned to the host due to a channel becoming unprovisioned. The V bit is expected to be initialised to logic 0 by the host. PROPRIETARY AND CONFIDENTIAL 66DATASHEET r [\ A o PMC-Sierra, Inc. PM7380 FREEDM-32P672 a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Field Description TMAC Next TD Pointer | The TMAC Next TD Pointer[14:0] bits are used to [14:0] store TDRs which permits the TMAC672 to create linked lists of TDs passed to it via the TDRR queue. The TDs are linked with other TDs belonging to the same channel and same priority level. in the case that data presented to the TMAC672 is returned to the host due to a channel becoming unprovisioned, a TDR pointing to the start of the per-channel linked list of TDs is placed on the TDRF queue. It is the responsibility of the host to follow the TMAC672 and host links in order to recover all the buffers. The More (M) bit is used by the host to support packets that require multiple TDs. If Mis set to logic 1, the current TD is just one of several TDs for the current packet. If M is set to logic 0, this TD either describes the entire packet (in the single TD packet case) or describes the end of a packet (in the multiple TD packet case). Note: When M is set to logic 1, the only valid value for CE is logic 0. Host Next TD Pointer [14:0] The Host Next TD Pointer[{14:0] bits are used to store TDRs which permits the host to support linked lists of TDs. As described above, linked lists of TDs are terminated by setting the CE bit to logic 1. Linked lists of TDs are used by the host to pass multiple TD packets or multiple packets associated with the same channel and priority level to the TMAC672. Transmit Buffer Size [15:0] The Transmit Buffer Size[15:0] field is used to indicate the size in bytes of the current TD's data buffer. (N.B. The TMAC672 does not make use of this field.) Transmit Descriptor Table The Transmit Descriptor Table, which resides in host memory, contains all of the Transmit Descriptors referenced by the TMAC672. To access a TD, the TMAC672 takes a TDR from a TDRR queue or from the TCDR table and adds 16 times its value (because each TD is 16 bytes in size) to the Transmit Descriptor Table Base (TDTB) pointer to form the actual address of the TD in host memory. Each TD must reside in the Transmit Descriptor Table. The PROPRIETARY AND CONFIDENTIAL 67r? [\ f\ o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Transmit Descriptor Table can contain a maximum of 32768 TDs. The base of the Transmit Descriptor Table is user programmable using the TMAC Tx Descriptor Table Base register. Thus, as shown below, each TD can be located using a Transmit Descriptor Reference (TDR) combined with the TMAC Tx Descriptor Table Base register. Figure 12 Transmit Descriptor Table TDTB[31:4] = Tx Descriptor Table Base register TDR[14:0] = Transmit Descriptor Reference TD_ADDR[31:0] = Transmit Descriptor Address Bit 31 Bit O | TDTB[31:4] | c000] + TDR(14:0] = | | TD ADDRI31:0] Bit 31 Bit 0 TDTB Dword 0 Dword 1 Dword 2 Dword 3 Dword 0 TD1 TD_ADDR TD2 Dword 3 Dword 0 TD 32768 Dword 3 PROPRIETARY AND CONFIDENTIAL 68ri A ra PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Transmit Queues Pointers to the transmit descriptors (TDs) containing packet(s) ready for transmission are passed from the host to the TMAC672 using the Transmit Descriptor Reference Ready (TDRR) queue, which resides in host memory. Pointers to transmit descriptor structures whose buffers have been read by the TMAC672 are passed from the TMAC672 to the host using the Transmit Descriptor Reference Free (TDRF) queue, which also resides in host memory. The TMAC672 contains a Free Queue cache which can store up to six TDRs. If caching is enabled, free TDRs are written into the TDRF queue six at a time, to reduce the number of host memory accesses. The Free Queue cache is flushed to the TDRF queue if the Interrupt On Completion (IOC) bit is set in the TD, which sends the corresponding TDR directly to the TDRF queue. The Free Queue cache is also flushed to the TDRF queue if the FQFLUSH register bit is set high. The FQFLUSH register bit is self clearing. The queues, shown in Figure 13 are defined by a common base pointer residing in the Transmit Queue Base register and eight offset pointers, four per queue. For each queue, two pointers define the start and the end of the queue, and two pointers keep track of the current read and write locations within the queue. The read pointer for each queue points to the offset of the last valid TDR read, and the write pointer points to the offset where next TDR can be written. The end of a queue is not a valid location for a TDR to be read or written. A queue is empty when the read pointer is one less than the write pointer or if the read pointer is one less than the end pointer and the write pointer equals the start pointer. A queue is full when the read pointer is equal to the write pointer. Each queue element is 32 bits in size, but only the least significant 18 bits are valid. The 18 least significant bits consist of a 15-bit TDR and three status bits for the TD pointed at by this TDR. The status bits are used by the TMAC672 to inform the host of the success or failure of transmission (see Table 10). When the TMAC672 writes TDRs to the TDRF queue, it sets bits [23:18] of the queue element to 0 and leaves bits [31:24] unaltered. Once a TDR is placed on the TDRF queue, the FREEDM-32P672 will make no further accesses to the TD nor the associated buffer. Note that the maximum value to which an end pointer may be set is FFFF hex, resulting in a maximum offset from the queue base address of (4*(FFFF-1)) = 3FFF8 hex. An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue. PROPRIETARY AND CONFIDENTIAL 69rf\ / | C PMC-Sierra, Inc. DATASHEET PMC-1990262 ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 13 - TDRR and TDRF Queues Transmit Descriptor Referance Queues Base Address: TQB{31:2] = Tx Queue Base register Index Registers: Ready: TDRRAS(15:0] = TOR Ready Queue Start register TDRRQW([15:0] = TOR Ready Queue Write register TDRRQR[15:0] = TDR Ready Queue Read register TDRRQE[15:0] = TDR Ready Queue End register Free: TDRFQS/(15:0] = TDR Free Queue Start register TDRFQW/[15:0] = TOR Free Queue Write register TDRFQR{([15:0] = TDR Free Queue Read register TDRFQE/[15:0) = TDR Free Queue End register Tx Descriptor Reference Queue Memory Map Bit 34 Bit Status + TOR TDRFOQS TORFQR + Status + TOR Status + TOR TORFQW Status + TOR Status + TDR TDRFQE >- TDRRQS TDRROR TDRRQW TDRRQE Base Address + Index Register PCI Address TQB ros] Jo) + PCI Host Memory TDR Reference Queues 256KB PROPRIETARY AND CONFIDENTIAL 70r > [\ fi ae PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 10 Transmit Descriptor Reference Bit 17 Bit 0 STATUS[2:0] TDR[14:0] Field Description Status[2:0] The TMAC672 fills in the Status field to indicate to the host the results of processing the TD. The encoding is: Status[1:0] Description 00 Last or only buffer of packet, buffer read. 01 Buffer of partial packet, buffer read. 10 Unprovisioned channel, buffer not read. 11 Malformed packet (e.g. Bytes In Buffer field set to 0), buffer not read. Status[2] Description 0 No underflow detected. 1 Underflow detected. TDR[14:0] The TDR[14:0] field contains the offset of the TD returned. If a TDR is returned to the host with the status field set to 10 (unprovisioned channel), the TDR may point to a binary tree of TDs and buffers (as indicated by the CE and V bits in the TDs). It is the responsibility of the host to traverse the tree to reclaim all the buffers. If a TDR is returned to the host with the status field set to any other value, the TDR will only point to one TD and buffer regardless of the values of V and CE in that TD. The underflow status bit (Status[2]) is normally attached to the TDR belonging to a packet experiencing underflow. For long packets spanning multiple buffers, underflow is reported only once at the first available TDR of that channel. All subsequent TDRs of that packet will be returned normally without the underflow status. In rare cases, due to internal buffering by the FREEDM-32P672, a packet may experience underflow at the very end of a packet, just as the TDR is being returned to the TDR free queue. The underflow status will then be reported in the first TDR of the immediate next packet of that channel. Because of the uncertainty with the reporting of underflows between the current verse the subsequent packet, the underflow status should only be used to gather performance statistics on channels and not for initiating packet specific responses such as retransmission. PROPRIETARY AND CONFIDENTIAL 71DATASHEET PMC-1990262 rf\ AI c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Transmit Channel Descriptor Reference Table The TMAC672 maintains a Transmit Channel Descriptor Reference (TCDR) table in which is stored certain information relating to DMA activity on each channel together with TD pointers which are used by the TMAC672 to sort packet chains supplied by the host into per-channel linked lists (see below). The caching of DMA-related information reduces the number of host bus accesses required to process each data packet, while the sorting into per-channel linked lists eliminates head of line blocking. Each channel is provided with two entries in the TCDR table, one for high priority packets (Pri 1) and one for fow priority packets (Pri 0). The structure of the TCDR table is shown in Figure 14 below. Figure 14 - Transmit Channel Descriptor Reference Table Bit 33 Bit 0 TCC 0, Prid Reserved.(12) NA|Ab}ioc] MCE) A 1D] Current TD Pointer [14:0] Res Bytes to Tx [15:0] Ra Host TD Pointer [14:0] Res DMA Current Address[31:0] i ree| Ul] = Last TD Pointer [14:0] |v] Next TD Pointer [14:0] | TCC 1, Prio Reserved (12) |Nalaee|ioclm|ce| al] Current TD Pointer [14:0] _ rw | Bytes to Tx [15:0] rel Host TD Pointer [14:0] DMA Current Address[31:0] Res. Ree| U [PIP Last TD Pointer [14:0] Vv Next TD Pointer [14:0] TCC 671, Pri Res Res INA JAbrt}ioc] M ICE Reserved .(12) D Current TD Pointer [14:0] Bytes to Tx [15:0] Res DMA Current Host TD Pointer [14:0] | Address[31:0] Res. PiP Last TD Pointer [14:0] Vv Next TD Pointer [14:0] PROPRIETARY AND CONFIDENTIAL 72DATASHEET PMC-1990262 PMV Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 11 - Transmit Channel Descriptor Reference Table Fields Field Description NA Indicates that a null abort is to be sent to the downstream block when it next requests data on this channel. The NA bit is set if a mal-formed TD is encountered while searching down a host chain. ABRT A copy of the ABRT bit in the TD currently being read. lOc Acopy of the IOC bit in the TD currently being read. M A copy of the M bit in the TD currently being read. CE Acopy of the CE bit in the TD currently being read. A Indicates if this channel is active (i.e. provisioned). If the channel is active, the A bit is set to logic 1. If the channel is inactive, the A bit is set to logic 0. D Indicates whether the linked list of packets for this channel is empty or not. If the D bit is set to logic 1, the list is not empty and the current TD pointer field is valid (i.e., it points to a valid TD). If the D bit is set to logic 0, the list is empty and the current TD pointer field is invalid. Current TD Pointer [14:0] Offset to the TD currently being read. (See Figure 15) Bytes To Tx[15:0] The Bytes to Tx[15:0] bits are used to indicate the total number of bytes that remain to be read in the current buffer. Each access to the data buffer decrements this value. A value of zero in this field indicates the buffer has been completely read. Host TD Pointer [14:0] A copy of the Host Next TD Pointer field of the TD currently being read, i.e. a pointer to the next TD in the chain currently being read. (See Figure 15) DMA Current Address[31:0] The DMA Current Address [31:0] bits hold the address | of the next dword in the current buffer. This field is incremented on each access to the buffer. U Indicates that an underflow has occurred on this channel. This bit is set in response to an underflow indication for the downstream THDL672 block and is cleared when a TDR is written to the TDR Free Queue (or to the free queue cache). PROPRIETARY AND CONFIDENTIAL 73r> i\ /| PMC-Sierra, Inc. PM7380 FREEDM-32P672 | DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 . ae | Field Description PiP The Packet Transfer in Progress bit indicates that a packet is currently being transmitted on this channel at this priority level. Last TD Pointer [14:0] | Offset to the head of the last host-linked chain of TDs to be read. (See Figure 15) V Indicates if the linked list of packets for this channel contains more than one host-linked chain (See Figure 15). If the V bit is set to logic 1, the list contains more than one chain and the next and last TD pointer fields are valid. If the V bit is set to logic 0, the list is either empty or contains only one host-linked chain and the next and last TD pointer fields are invalid. Next TD Pointer [14:0] | Offset to the head of the next host-linked chain of TDs to be read. (See Figure 15) Transmit Descriptor Linking As described above, the TCDR table contains pointers which the TMAC672 uses to construct linked lists of data packets to be transmitted. After the host places a new TDR in the TDR Ready queue, the TMAC672 retrieves the TDR and links it to the TD pointed at by the Last TD Pointer field. The TMAC672 may create up to 1,344 linked lists, viz. a high-priority list and a low-priority list for each DMA channel. Whenever a new data packet is requested by the downstream block, the TMAC672 picks a packet from the high-priority linked list unless it is empty, in which case, a packet from the low-priority linked list is used. PROPRIETARY AND CONFIDENTIAL 74i > [\ /\ c* PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 15 TD Linking T Y TD | TD Curr.} Next| Last | Host P1 = _J P3) P4 TDR] TDR] TDR] TDR Vat TMAC Link v=1 TMAG Link V=0 | Mo | M=1 M=0 CEs0 CE=0 CE=1 TCDR Tabie Data Data Host Link Host Link TD TD P1 P3 oO o a = Data Data Host Link TD P1 M=0 CE=0 Data Host Link TD P2 M=0 CE=1 Data The host links the TDs vertically while the TMAC672 links TDs horizontally. Figure 15 shows the TDs for packets P1 and P2 linked by the host before the TDR is placed on the TDRR queue, as are the TDs for packet P3 and P4. Packet P3 is linked to packet P1 by the TMAC672, as is packet P4 linked to PROPRIETARY AND CONFIDENTIAL 75DATASHEET r [\ f I ot PMC-Sierra, Inc. PM7380 FREEDM-32P672 | PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.7.2 9.7.3 9.7.4 9.7.5 packet P3. The TMAC672 indicates valid horizontal links by setting the V bit to logic 1. Task Priorities The TMAC672 must perform a number of tasks concurrently in order to maintain a steady flow of data through the system. The main tasks of the TMAC672 are managing the Ready Queue (i.e. removing chains of data packets from the queue and attaching them to the appropriate per-channel linked list) and servicing requests for data from the Transmit Packet Interface. The priority of service for each of the tasks is fixed by the TMAC672 as follows: e Top priority is given to servicing expedited read requests from the Transmit HDLC Processor / Partial Packet Buffer block (THDL672). e Second priority is given to removing chains of data packets from the TDRR queue and attaching them to the appropriate per-channel linked list. e Third priority is given to servicing non-expedited read requests from the THDL672. DMA Transaction Controller The DMA Transaction Controller coordinates the processing of requests from the THDL672 with the reading of data stored in host memory. The reading of a data packet may require a number of separate host memory transactions, interleaved with transactions of other DMA channels. As well as reading data from the Host Master Interface, the DMA Transaction Controller initiates read and write transactions to the PCI Controller block (GPIC) for the purposes of maintaining the data structures (queues, descriptors, etc.) in host memory. Read Data Pipeline The Read Data Pipeline inserts delay in the data stream between the GPIC interface and the THDL672 interface to enable the DMA Transaction Controller to generate appropriate control signals at the Transmit Packet Interface. Descriptor Information Cache The Descriptor Information Cache provides the storage for the Transmit Channel Descriptor Reference (TCDR) Table. PROPRIETARY AND CONFIDENTIAL 76DATASHEET ri fi PMC-Sierra, inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.7.6 Free Queue Cache The Free Queue Cache block implements the 6 element TDR Free Queue cache. Caching TDRs reduces the number of host bus accesses that the TMAC672 makes. TDRs are written to the cache one at a time as they are released by the TMAC672. The cache is then flushed to host memory when it becomes full, when a TD with the IOC bit set high is released, when the FQFLUSH register bit is set high or when a TD is released as the result of unprovisioning a channel. The cache controller may also flush the cache when it contains fewer than six elements or if the pointer index is within six elements of the end of the free queue. When the write pointer is near the end of the free queue, the cache controller writes only to the end of the queue and does not start writing from the top of the queue until the next time a flush is required. To do so would require two host memory transactions and would be of no benefit. 9.8 Transmit HDLC Controller / Partial Packet Buffer 9.8.1 The Transmit HDLC Controller / Partial Packet Buffer block (THDL672) contains a partial packet buffer for PCI latency control and a transmit HDLC controller. Packet data retrieved from the PCI host memory by the Transmit DMA Controller block (TMAC672) is stored in channel specific FIFOs residing in the partial packet buffer. When the amount of data in a FIFO reaches a programmable threshold, the HDLC controller is enabied to initiate transmission. The HDLC controller performs flag generation, bit stuffing and, optionally, frame check sequence (FCS) insertion. The FCS is software selectable to be CRC-CCITT or CRC-32. The minimum packet size, excluding FCS, is two bytes. A single byte payload is illegal. The HDLC controller delivers data to the Transmit Channel Assigner block (TCAS672) on demand. A packet in progress is aborted if an under-run occurs. The THDL672 is programmable to operate in transparent mode where packet data retrieved from the PCI host is transmitted verbatim. Transmit HDLC Processor The HDLC processor is a time-slice state machine which can process up to 672 independent channels. The state vector and provisioning information for each channel is stored ina RAM. Whenever the TCAS672 requests data, the appropriate state vector is read from the RAM, processed and finally written back to the RAM. The HDLC state-machine can be configured to perform flag insertion, bit stuffing and CRC generation. The HDLC processor requests data from the partial packet processor whenever a request for channel data arrives. However, the HDLC processor does not start transmitting a packet until the entire packet is stored in the channel FIFO or until the FIFO free space is less than the PROPRIETARY AND CONFIDENTIAL 77DATASHEET ri fi c PMC-Sierra, Inc. PM7380 FREEDM-32P672 | PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.8.2 software programmable limit. If a channel FIFO under-runs, the HDLC processor aborts the packet. The configuration of the HDLC processor is accessed using indirect channel read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle inserted by the TCAS672 block. Writing new provisioning data to a channel resets the channel's entire state vector. Transmit Partial Packet Buffer Processor The partial packet buffer processor controls the 32 Kbyte partial packet RAM which is divided into 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular channel FIFO buffers. Thus, non-contiguous sections of RAM can be allocated in the partial packet buffer RAM to create a channel FIFO. Figure 16 shows an example of three blocks (blocks 1, 3, and 200) linked together to form a 48 byte channel FIFO. The three pointer values would be written sequentially using indirect block write accesses. When a channel is provisioned with this FIFO, the state machine can be initialised to point to any one of the three blocks. The partial packet buffer processor is divided into three sections: reader, writer and roamer. The roamer is a time-sliced state machine which tracks each channel's FIFO buffer free space and signals the writer to service a particular channel. The writer requests data from the TMAC672 block and transfers packet data from the TMAC672 to the associated channel FIFO. The reader is a time- sliced state machine which transfers the HDLC information from a channel FIFO to the HDLC processor when the HDLC processor requests it. If a buffer under- run occurs for a channel, the reader informs the HDLC processor and purges the rest of the packet. PROPRIETARY AND CONFIDENTIAL 78r [\ AI PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee eee ee ccc PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 16 ~ Partial Packet Buffer Structure Partial Packet Block Buffer RAM Pointer RAM Block 0 16 bytes Block 0 XX Block 1 16 bytes Block 4 0x03 Block 2 16 bytes Block 2 XX Block 3 16 bytes Block 3 OxC8 i} 1 I i t i) J i i J I I 1 1 i} I I 1 Block 200 16 bytes Block 200 0x01 l ' k ! ' 1 ' 1 I ! ! 1 ! ! ! t t I Block 2047 16 bytes Block 2047 XX The writer and reader determine empty and full FIFO conditions using flags. Each block in the partial packet buffer has an associated flag. The writer sets the flag after the block is written and the reader clears the flag after the block is read. The flags are initialized (cleared) when the block pointers are written using indirect block writes. The reader declares a channel FIFO under-run whenever it tries to read data from a block without a set flag. The FIFO algorithm of the partial packet buffer processor is based on per- channel software programmable transfer size and free space trigger level. Instead of tracking the number of full blocks in a channel FIFO, the processor tracks the number of empty blocks, called free space, as well as the number of end of packets stored in the FIFO. Recording the number of empty blocks instead of the number of full blocks reduces the amount of information the roamer must store in its state RAM. The partial packet roamer records the FIFO free space and end-of-packet count for all channel FIFOs. When the reader signals that a block has been read, the roamer increments the FIFO free space and sets a per-channel request flag if PROPRIETARY AND CONFIDENTIAL 79r > [\ fl co PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 the free space is greater than the limit set by XFER[3:0]. The roamer also decrements the end-of-packet count when the reader signals that it has passed an end of a packet to the HDLC processor. If the HDLC is transmitting a packet and the FIFO free space is greater than the starving trigger level and there are no complete packets within the FIFO (end-of-packet count equal to zero), a per- channel starving flag is set. The roamer searches the starving flags in a round- robin fashion to decide which channel FIFO should make expedited data requests to the TMAC672 block. If no starving flags are set, the roamer searches the request flags in a round-robin fashion to decide which channel FIFO should make regular data requests to the TMAC672 block. The roamer informs the partial packet writer of the channel FIFO to process, the FIFO free space and the type of request it should make. The writer sends a request for data to the TMAC672 block, writes the response data to the channel FIFO, and sets the block full flags. The writer reports back to the roamer the number of blocks and end-of-packets transferred. The maximum amount of data transferred during one request is limited by a software programmable limit (XFERJ[3:0)). The configuration of the HDLC processor is accessed using indirect channel read and write operations as well as indirect block read and write operations. When an indirect operation is performed, the information is accessed from RAM during a null clock cycle identified by the TCAS672 block. Writing new provisioning data to a channel resets the entire state vector. 9.9 Transmit Channel Assiqner The Transmit Channel Assigner block (TCAS672) processes up to 672 channels. Data for all channels is sourced from a single byte-serial stream from the Transmit HDLC Controller / Partial Packet Buffer block (THDL672). The TCAS672 demultiplexes the data and assigns each byte to any one of 32 links. Each link may be configured to support 2.048 or 8.192 H-MVIP traffic, to support T1/J1/E1 channelised traffic or to support unchannelised traffic. When configured to support H-MVIP traffic, each group of 8 links share a clock and frame pulse, otherwise each link is independent and has its own associated clock. For each high-speed link (TD[2:0]), the TCAS provides a six byte FIFO. For the remaining links (TD[31:3]), the TCAS provides a single byte holding register. The TCAS672 also performs parallel to serial conversion to form a bit- serial stream. In the event where multiple links are in need of data, TCAS672 requests data from upstream blocks on a fixed priority basis with link TD[O] having the highest priority and link TD[31] the lowest. From the point of view of the TCAS672, links configured for H-MVIP traffic behave identically to links configured for T1/J1/E1 channelised or unchannelised traffic in the back end, only differing on the link side as described herein. First, the number of time-siots in each frame is programmable to be 32 or 128 and has PROPRIETARY AND CONFIDENTIAL 80r [\ fi cr PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 an associated data clock frequency that is double the data rate. This provides more bandwidth per link for applications requiring higher data densities on a single link. Data at each time-slot may be independently assigned to be sourced from a different channel. Second, H-MVIP links reference the start of each frame with a frame pulse, thereby avoiding having to gap the link clock during the framing bits/bytes of each frame. The frame pulse is provided by an H-MVIP bus master and ensures that all agents sharing the H-MVIP bus remain synchronized. When configured for operation in 2.048 Mbps H-MVIP mode, the frame pulse is sampled using the same clock which samples the data. When configured for operation in 8.192 Mbps H-MVIP mode, the frame pulse is sampled using a separate frame pulse clock provided by an H-MVIP bus master. The frame pulse clock has a synchronous timing relationship to the data clock. Third, not all links are independent. When configured for operation in 2.048 Mbps H-MVIP mode, each group of 8 links share a clock and a frame pulse. Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 each share a clock and a frame pulse. Not all 8 links within each group need to be configured for operation in 2.048 Mbps H-MVIP mode. However, any link within each logical group of 8 which is configured for 2.048 Mbps H-MVIP operation will share the same clock and frame pulse. When configured for operation in 8.192 Mbps H- MVIP mode, links 4m (O<m<7) share a frame pulse, a data clock and a frame pulse clock. Again, not all eight 4m (0<ms<7) links need to be configured for operation in 8.192 Mbps H-MVIP mode, however, any link which is configured for 8.192 Mbps H-MVIP operation will share the same frame pulse, data clock and frame pulse clock. If link 4m is configured for 8.192 Mbps H-MVIP operation, then data transferred on that link is spread over links 4m, 4m+1 4m+2 and 4m+3 from a channel assigner point of view. Accordingly, when link 4m is configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 must also be configured for operation in 8.192 Mbps H-MVIP mode. In the back end, the TCAS672 extracts and processes the time-slots identically to channelised T1/J1/E1 traffic. Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to be sourced from a different channel. The link clock is only active during time-slots 1 to 24 of a T1/J1 stream and is inactive during the frame bit. Similarly, the clock is only active during time-siots 1 to 31 of an E1 stream and is inactive during the FAS and NFAS framing bytes. The most significant bit of time-slot 1 of a channelised link is identified by noting the absence of the clock and its re-activation. With knowledge of the transmit link and time-slot identity, the TCAS672 performs a table look-up to identify the channel from which a data byte is to be sourced. Links may also be unchannelised. Then, all data bytes on that link belong to one channel. The TCAS672 performs a table look-up to identify the channel to which a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelised links. Link clocks are no longer limited to T1/J1 PROPRIETARY AND CONFIDENTIAL 8&7i > [\ /I cr PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 or E1 rates and may range up to a maximum clock rate of 51.84 MHz for | TCLK[2:0] and 10 MHz for TCLK[31:3]. The link clock is only active during bit times containing data to be transmitted and inactive during bits that are to be ignored by the downstream devices, such as framing and overhead bits. For the case of two unchannelised links, the maximum link rate is 51.84 MHz. For the | case of more numerous unchannelised links or a mixture of channelised, unchannelised and H-MVIP links, the total instantaneous link rate over all the links is limited to 64 MHz. 9.9.1 Line Interface Translator (LIT) The LIT block translates the information between the 32 physical links and the Line Interface block. The LIT block performs three functions: data translation, clock translation and frame pulse generation. When link 4m (O<ms7) is configured for operation in 8.192 Mbps H-MVIP mode, the LIT block translates the data arriving from the Line Interface block on links 4m, 4m+1, 4m+2 and 4m+3 onto the 128 time-siot link 4m. The LIT block translates data arriving from the Line Interface block on link 4m, 4m+1, 4m+2 and 4m+3 onto time-slots 0 through 31, 32 through 63, 64 through 95 and 96 through 127 respectively. When link 4m is configured for operation in 8.192 Mbps H-MVIP mode, outputs TD[4m+3:4m+1] are driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be programmed in the TCAS672 Link Configuration register for 8.192 Mbps H-MVIP operation. When links are configured for operation in 2.048 Mbps H-MVIP mode, channelised T1/J1/E1 mode or unchannelised mode, the LIT block does not perform any translation on the link data. When a link is configured for operation in H-MVIP mode, the LIT block divides the appropriate clock (TMVCK[n] for 2.048 Mbps H-MVIP and TMV8DC for 8.192 Mbps H-MVIP) by two and provides this divided down clock to the Line Interface block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the LIT block does not perform any translation on the link clock. When a link is configured for operation in H-MVIP mode, the LIT block samples the appropriate frame pulse (TFPB[n] for 2.048 Mbps H-MVIP and TFP8B for 8.192 Mbps H-MVIP) and presents the sampled frame pulse to the Line Interface block. When a link is configured for operation in channelised T1/J1/E1 or unchannelised mode, the gapped clock is passed to the LIT block unmodified. 9.9.2 Line Interface There are 32 identical line interface blocks in the TCAS672. Each line interface block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and PROPRIETARY AND CONFIDENTIAL 82DATASHEET r? [\ I c PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 9.9.3 9.9.4 the other H-MVIP streams. Based on configuration, only one of the sub-blocks are active at one time; the other is held reset. Each sub-block contains a bit counter, an 8-bit shift register and a holding register. Each sub-block performs parallel to serial conversion. Whenever the shift register is updated, a request for service is sent to the priority encoder block. When acknowledged by the priority encoder, the line interface would respond by writing the data into the holding register in the active sub-block. To support H-MVIP links, each line interface block contains a time-slot counter. The time-slot counter is incremented each time the holding register is updated. When a frame pulse occurs, the time-slot counter is cleared to indicate that the next byte belongs to the first time-slot. To support non H-MVIP channelised links, each line interface block contains a time-slot counter and a clock activity monitor. The time-siot counter is incremented each time the shift register is updated. The clock activity monitor is a counter that increments at the system clock (SYSCLK) rate and is cleared by a rising edge of the transmit clock (TCLK[n]). A framing bit (T1/J1) or a framing byte (E1) is detected when the counter reaches a programmable threshold, at which point, the bit and time-slot counters are initialised to indicate that the next bit sampled is the most significant bit of the first time-slot. For unchannelised links, the time-slot counter and the clock activity monitor are held reset. Priority Encoder The priority encoder monitors the line interfaces for requests and synchronises them to the SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from line interface TD[0] to line interface TD[31]. Thus, simultaneous requests from line interface TD[m] will be serviced ahead of line interface TD[n], if m <n. The priority encoder selects the request from the link with the highest priority for service. When there are no pending requests, the priority encoder generates an idle cycle. In addition, once every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced. This cycle is used by the channel assigner downstream for CBI accesses to the channel! provision RAM. Channel Assigner The channel assigner block determines the channel number of the request currently being processed. The biock contains a 1024 word channel provision RAM. The address of the RAM is constructed from concatenating the link number and the time-slot number of the highest priority requester. The fields of each RAM word include the channel number and a time-silot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. For time-slots that are enabled, the PROPRIETARY AND CONFIDENTIAL 83rf\ fi a PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET Reece eee cece eee eee eeeeeeeee ceee ey PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 channel assigner issues a request to the THDL672 block which responds with packet data within one byte period of the transmit stream. 9.10 Performance Monitor The Performance Monitor block (PMON) contains four counters. The first two accumulate receive partial packet buffer FIFO overrun events and transmit partial packet buffer FIFO underflow events, respectively. The remaining two counters are software programmable to accumulate a variety of events, such as receive packet count, FCS error counts, etc. All counters saturate upon reaching maximum value. The accumulation logic consists of a counter and holding register pair. The counter is incremented when the associated event is detected. Writing to the FREEDM-32P672 Master Clock / BERT Activity Monitor and Accumulation Trigger register transfer the count to the corresponding holding register and clear the counter. The contents of the holding register is accessible via the PCI interface. 9.11 JTAG Test Access Port Interface The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The FREEDM-32P672 identification code is 073800CD hexadecimal. 9.12 PCI Host Interface The FREEDM-32P672 supports two different normal mode register types as defined below: 1. PCi Host Accessible registers (PA) - these registers can be accessed through the PCI Host interface. 2. PCI Configuration registers (PC) - these register can only be accessed through the PCI Host interface during a PC! configuration cycle. The PCI registers are addressable on dword boundaries only. The PCI offset shown in the table below must be combined with a base address to form the PCI Interface address. The base address can be found in the FREEDM-32P672 Memory Base Address register in the PCI Configuration memory space. Table 12 - Normal Mode PCI Host Accessible Register Memory Map PCI Offset Register 0x000 FREEDM-32P672 Master Reset PROPRIETARY AND CONFIDENTIAL 84DATASHEET r-[\ A ra PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee reer eee eee e eee eee eee ee eee eee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PCI Offset Register 0x004 FREEDM-32P672 Master Interrupt Enable 0x008 FREEDM-32P672 Master Interrupt Status 0x00C FREEDM-32P672 Master Ciock / Frame Pulse / BERT Activity Monitor and Accumulation Trigger 0x010 FREEDM-32P672 Master Link Activity Monitor 0x014 FREEDM-32P672 Master Line Loopback #1 0x018 FREEDM-32P672 Master Line Loopback #2 0x01C FREEDM-32P672 Reserved 0x020 FREEDM-32P672 Master BERT Control 0x024 FREEDM-32P672 Master Performance Monitor Control | 0Ox028 -0x07C | Reserved 0x080 GPIC Control 0x084 - OxOFC | GPIC Reserved 0x100 RCAS Indirect Channel and Time-slot Select 0x104 RCAS Indirect Channel Data 0x108 RCAS Framing Bit Threshold 0x10C RCAS Channel Disable 0x110-0x17C | RCAS Reserved 0x180 Ox1FC | RCAS Link #0 through #31 Configuration 0x200 RHDL Indirect Channel Select 0x204 RHDL Indirect Channel Data Register #1 0x208 RHDL Indirect Channel Data Register #2 0x20C RHDL Reserved 0x210 RHDL Indirect Block Select | 0x214 RHDL Indirect Block Data Register | 0x218-0x21C | RHDL Reserved : 0x220 RHDL Configuration 0x224 RHDL Maximum Packet Length | 0x228 - 0x23C | RHDL Reserved PROPRIETARY AND CONFIDENTIAL 85DATASHEET r> [\ f I H PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee eee cece ees PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PCI Offset Register 0x240 - Ox27C | Reserved 0x280 RMAC Control 0x284 RMAC Indirect Channel Provisioning 0Qx288 RMAC Packet Descriptor Table Base LSW 0x28C RMAC Packet Descriptor Table Base MSW 0x290 RMAC Queue Base LSW 0x294 RMAC Queue Base MSW 0x298 RMAC Packet Descriptor Reference Large Buffer Free Queue Start 0x29C RMAC Packet Descriptor Reference Large Buffer Free Queue Write Ox2A0 RMAC Packet Descriptor Reference Large Buffer Free Queue Read Ox2A4 ee Packet Descriptor Reference Large Buffer Free Queue n Ox2A8 RMAC Packet Descriptor Reference Small Buffer Free Queue Start Ox2AC RMAC Packet Descriptor Reference Small Buffer Free Queue Write 0x2BO0 RMAC Packet Descriptor Reference Small Buffer Free Queue Read ' Ox2B4 RMAC Packet Descriptor Reference Small Buffer Free Queue End 0x2B8 RMAC Packet Descriptor Reference Ready Queue Start 0x2BC RMAC Packet Descriptor Reference Ready Queue Write 0x2C0 RMAC Packet Descriptor Reference Ready Queue Read Ox2C4 RMAC Packet Descriptor Reference Ready Queue End Ox2C8 - Ox2FC | RMAC Reserved 0x300 TMAC Control 0x304 TMAC Indirect Channel Provisioning 0x308 TMAC Descriptor Table Base LSW PROPRIETARY AND CONFIDENTIAL 86DATASHEET r- [\ I e PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee eee eee errr reer reece eee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PCI Offset Register 0x30C TMAC Descriptor Table Base MSW 0x310 TMAC Queue Base LSW 0x314 TMAC Queue Base MSW 0x318 TMAC Descriptor Reference Free Queue Start 0x31C TMAC Descriptor Reference Free Queue Write 0x320 TMAC Descriptor Reference Free Queue Read 0x324 TMAC Descriptor Reference Free Queue End 0x328 TMAC Descriptor Reference Ready Queue Start 0x32C TMAC Descriptor Reference Ready Queue Write 0x330 TMAC Descriptor Reference Ready Queue Read 0x334 TMAC Descriptor Reference Ready Queue End 0x338 - Ox37C | TMAC Reserved 0x380 THDL Indirect Channel Select 0x384 THDL Indirect Channel Data #1 0x388 THDL Indirect Channel Data #2 0x38C THDL Indirect Channel Data #3 0x390 - Ox39C | THDL Reserved 0x3A0 THDL Indirect Block Select 0x3A4 THDL Indirect Block Data Ox3A8 - Ox3AC | THDL Reserved 0x3B0 THDL Configuration 0x3B4 - Ox3BC | THDL Reserved Ox3CO - Ox3FC | Reserved 0x400 TCAS Indirect Channel and Time-slot Select 0x404 TCAS Indirect Channel Data 0x408 TCAS Framing Bit Threshold 0x40C TCAS Idle Time-slot Fill Data 0x410 TCAS Channel Disable 0x414 - Ox47C | TCAS Reserved PROPRIETARY AND CONFIDENTIAL 87DATASHEET rl /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PCI Offset Register 0x480 - Ox4FC | TCAS Link #0 through #31 Configuration 0x500 PMON Status 0x504 PMON Receive FIFO Overflow Count 0x508 PMON Transmit FIFO Underflow Count 0x50C PMON Configurable Count #1 0x510 PMON Configurable Count #2 0x514 - Ox51C | PMON Reserved | 0x520 - Ox7FC Reserved The following PCI configuration registers are implemented by the PCI Interface. These registers can only be accessed when the PCI Interface is a target and a configuration cycle is in progress as indicated using the IDSEL input. Table 13 PCI Configuration Register Memory Map PCI Offset Register 0x00 Vendor Identification/Device Identification 0x04 Command/Status 0x08 Revision Identifier/Class Code 0x0C Cache Line Size/Latency Timer/Header Type/BIST 0x10 CBI Memory Base Address Register 0x14 - Ox24 Unused Base Address Register 0x28 - 0x38 Reserved 0x3C Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT PROPRIETARY AND CONFIDENTIAL 88DATASHEET i > [\ fi co PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 10 NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the FREEDM-32P672. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-32P672 to determine the programming state of the block. 3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect FREEDM-32P672 operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM- 32P672 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided. 10.1 PCI Host Accessible Registers PCI host accessible registers can be accessed by the PCI host. For each register description below, the hexadecimal register number indicates the PCI offset from the base address in the FREEDM-32P672 CBI Register Base Address Register when accesses are made using the PCI Host Port. Note These registers are not byte addressable. Writing to any one of these registers modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to the register. PROPRIETARY AND CONFIDENTIAL 89r oi fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET Ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x000 : FREEDM-32P672 Master Reset Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W Reset 8) Bit 14 Unused XXXXH to Bit 0 This register provides software reset capability. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. RESET: The RESET bit allows the FREEDM-32P672 to be reset under software control. If the RESET bit is a logic one, the entire FREEDM-32P672 except the PCI Interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM-32P672 out of reset. Holding the FREEDM-32P672 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Note Unlike the hardware reset input (RSTB), RESET does not force the FREEDM- 32P672's PCI pins tristate. Transmit link data pins (TD[31:0]) are forced high. In addition, all registers except the GPIC PCI Configuration registers, are reset to their default values. PROPRIETARY AND CONFIDENTIAL 90DATASHEET PMC-1990262 r? Mi c PMC-Sierra, inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x004 : FREEDM-32P672 Master Interrupt Enable Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TFUDRE 0 Bit 14 R/W IOCE 0 Bit 13 R/W TDFQEE 0 Bit 12 R/W TDQRDYE 0 Bit 11 R/W TDQFE 0 Bit 10 R/W RPDRQEE 0 Bit 9 R/W RPDFQEE 0 Bit 8 R/W RPQRDYE 0 Bit 7 R/W RPQLFE 0 Bit 6 R/W RPQSFE 0 Bit 5 R/W RFOVRE 0 Bit 4 R/W RPFEE 0 Bit 3 R/W RABRTE 0 Bit 2 R/W RFCSEE 0 Bit 1 R/W PERRE 9) Bit 0 R/W SERRE 0 This register provides interrupt enables for various events detected or initiated by the FREEDM-32P672. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 91lr > [\ fi c PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 SERRE: The system error interrupt enable bit (SERRE) enables PCI system error interrupts to the PCI host. When SERRE is set high, any address parity error, data parity error on Special Cycle commands, reception of a master abort or detection of a target abort will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when SERRE is set low. However, the SERRI bit remains valid when interrupts are disabled and may be polled to detect PCI system error events. PERRE: The parity error interrupt enable bit (PERRE) enables PCI parity error interrupts to the PCI host. When PERRE is set high, data parity errors detected by the FREEDM-32P672 or parity errors reported by a target will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when PERRE is set low. However, the PERRI bit remains valid when interrupts are disabled and may be polled to detect PCI parity error events. RFECSEE: The receive frame check sequence error interrupt enable bit (RFCSEE) enables receive FCS error interrupts to the PCI host. When RFCSEE is set high, a mismatch between the received FCS code and the computed CRC residue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit remains valid when interrupts are disabled and may be polled to detect receive FCS error events. RABRTE: The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort interrupts to the PCI host. When RABRTE is set high, receipt of an abort code (at least 7 contiguous 1's) will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RABRTE is set low. However, the RABRTI bit remains valid when interrupts are disabled and may be polled to detect receive abort events. RPFEE: The receive packet format error interrupt enable bit (RPFEE) enables receive packet format error interrupts to the PCI host. When RPFEE is set high, receipt of a packet that is longer than the maximum specified in the RHDL Maximum Packet Length register, of a packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPFEE is set low. However, the RPFEI bit remains valid when PROPRIETARY AND CONFIDENTIAL 92r > [\ A PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 interrupts are disabled and may be polled to detect receive packet format error events. RFOVRE: The receive FIFO overrun error interrupt enable bit (RFOVRE) enables receive FIFO overrun error interrupts to the PCI host. When RFOVRE is set high, attempts to write data into the logical FIFO of a channel when it is already full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun events. RPQSFE: The receive packet descriptor small buffer free queue cache read interrupt enable bit (RPQSFE) enables receive packet descriptor small free queue cache read interrupts to the PCI host. When RPQSFE is set high, reading a programmable number of RPDR blocks from the RPDR Small Buffer Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQSFE is set low. However, the RPQSFI bit remains valid when interrupts are disabled and may be polled to detect RPDR small buffer free queue cache read events. RPQLFE: The receive packet descriptor large buffer free queue cache read interrupt enable bit (RPQLFE) enables receive packet descriptor large free queue cache read interrupts to the PCI host. When RPQLFE is set high, reading a programmable number of RPDR blocks from the RPDR Large Buffer Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQLFE is set low. However, the RPQLFI bit remains valid when interrupts are disabled and may be polled to detect RPDR large buffer free queue cache read events. RPQRDYE: The receive packet descriptor ready queue write interrupt enable bit (RPQRDYE) enables receive packet descriptor ready queue write interrupts to the PCI host. When RPQRDYE is set high, writing a programmable number of RPDRs to the RPDR Ready Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQRDYE is set low. However, the RPQRDY!I bit remains valid when interrupts are disabled and may be polled to detect RPDR ready queue write events. PROPRIETARY AND CONFIDENTIAL 93rfl fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDFQEE: The receive packet descriptor free queue error interrupt enable bit (RPDFQEE) enables receive packet descriptor free queue error interrupts to the PCI host. When RPDFQEE is set high, attempts to retrieve an RPDR when both the large buffer and small buffer free queues are empty will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPDFQEE is set low. However, the RPDFQEI bit remains valid when interrupts are disabled and may be polled to detect RPDR free queue empty error events. RPDRQEE: The receive packet descriptor ready queue error interrupt enable bit (RPDRQEE) enables receive packet descriptor ready queue error interrupts to the PCI host. When RPDRQEE is set high, attempts to write an RPDR when ready queue is ready full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when RPDRGEE is set low. However, the RPDRQEI bit remains valid when interrupts are disabled and may be polled to detect RPDR ready queue full error events. TDQFE: The transmit packet descriptor free queue write interrupt enable bit (TDQFE) enables transmit packet descriptor free queue write interrupts to the PCI host. When TDOQFE is set high, writing a programmable number of TDRs to the TDR Free Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDQFE is set low. However, the TDQFI bit remains valid when interrupts are disabled and may be polled to detect TDR free queue write events. TDQRDYE: The transmit descriptor ready queue cache read interrupt enable bit (TDQRDYE) enables transmit descriptor ready queue cache read interrupts to the PCI host. When TDQRDYE is set high, reading a programmable number of TDRs from the TDR Ready Queue will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDQRDYE is set low. However, the TDQRDYI bit remains valid when interrupts are disabled and may be polled to detect TDR ready queue cache read events. TDFQEE: The transmit descriptor free queue error interrupt enable bit (TDFQEE) enables transmit descriptor free queue error interrupts to the PCI host. When TDFQEE is set high, attempting to write to the transmit free queue while the queue is full will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TDFQEE is set low. However, the TDFQEI bit PROPRIETARY AND CONFIDENTIAL 94r > [\ fi cy PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 remains valid when interrupts are disabled and may be polled to detect TD free queue error events. IOCE: The transmit interrupt on complete enable bit ((OCE) enables transmission complete interrupts to the PCI host. When IOCE is set high, complete transmission of a packet with the IOC bit in the TD set high will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when IOCE is set low. However, the IOCI bit remains valid when interrupts are disabled and may be polled to detect transmission of |OC tagged packets. TFUDRE: The transmit FIFO underflow error interrupt enable bit (TFUDRE) enables transmit FIFO underflow error interrupts to the PCI host. When TFUDRE is set high, attempts to read data from the logical FIFO when it is already empty will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when TFUDRE is set low. However, the TFUDRI bit remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events. PROPRIETARY AND CONFIDENTIAL 95DATASHEET PMC-1990262 r-[\ /I C* PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x008 : FREEDM-32P672 Master Interrupt Status Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R TFUDRI X Bit 14 R IOC! X Bit 13 R TDFQEI xX Bit 12 R TDQRDY! Xx Bit 11 R TDOFI Xx Bit 10 R RPDRQEI! X Bit 9 R RPDFQEI X Bit 8 R RPQRDYI X Bit 7 R RPQLFI Xx Bit 6 R RPQSFI Xx Bit 5 R RFOVRI X Bit 4 R RPFE| X Bit 3 R RABRTI X Bit 2 R RFCSE]I X Bit 1 R PERRI x Bit 0 R SERRI Xx This register reports the interrupt status for various events detected or initiated by the FREEDM-32P672. Reading this registers acknowledges and clears the interrupts. Note This register is not byte addressable. Reading this register clears all the interrupt bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 96r- [\ y, PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET cee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 SERRI: The system error interrupt status bit (SERRI) reports PCI system error interrupts to the PC! host. SERRI is set high upon detection of any address parity error, data parity error on Special Cycle commands, reception of a master abort or detection of a target abort event. The SERR! bit remains valid when interrupts are disabled and may be polled to detect PCI system error events. PERRI: The parity error interrupt status bit (PERRI) reports PCI parity error interrupts to the PCI host. PERRI is set high when data parity errors are detected by the FREEDM-32P672 while acting as a master, and when parity errors are reported to the FREEDM-32P672 by a target via the PERRB input. The PERRI bit remains valid when interrupts are disabled and may be polled to detect PCI parity error events. RFCSEI: The receive frame check sequence error interrupt status bit (RFCSElI) reports receive FCS error interrupts to the PCI host. RFCSEI is set high, when a mismatch between the received FCS code and the computed CRC residue is detected. RFCSEI remains valid when interrupts are disabled and may be polled to detect receive FCS error events. RABRTI: The receive abort interrupt status bit (RABRT1) reports receive HDLC abort interrupts to the PCI host. RABRTI is set high upon receipt of an abort code (at least 7 contiguous 1's). RABRTI remains valid when interrupts are disabled and may be polled to detect receive abort events. RPFEI: The receive packet format error interrupt status bit (RPFE!) reports receive packet format error interrupts to the PCI host. RPFEI is set high upon receipt of a packet that is longer than the maximum programmed length, of a packet that is shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned. RPFEI remains valid when interrupts are disabled and may be polled to detect receive packet format error events. RFOVRI: The receive FIFO overrun error interrupt status bit (RFOVRI) reports receive FIFO overrun error interrupts to the PCI host. RFOVRI is set high on attempts to write data into the logical FIFO of a channel when it is already full. RFOVRI remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun events. PROPRIETARY AND CONFIDENTIAL 97r > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 seen renee ccc ee es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET RPQSFI: The receive packet descriptor small buffer free queue cache read interrupt status bit (RPQSF1) reports receive packet descriptor small free queue cache read interrupts to the PCI host. RPQSFI is set high when the programmable number of RPDR blocks is read from the RPDR Small Buffer Free Queue. RPQSFI remains valid when interrupts are disabled and may be polled to detect RPDR small buffer free queue cache read events. RPQLFI: The receive packet descriptor large buffer free queue cache read interrupt status bit (RPQLFl) reports receive packet descriptor large free queue cache read interrupts to the PCI host. RPQLFI is set high when the programmable number of RPDR blocks is read from the RPDR Large Buffer Free Queue. RPQLFI remains valid when interrupts are disabled and may be polled to detect RPDR large buffer free queue cache read events. RPQRDYI: The receive packet descriptor ready queue write interrupt status bit (RPQRDY1) reports receive packet descriptor ready queue write interrupts to the PCI host. RPQRDY!I is set high when the programmable number of RPDRs is written to the RPDR Ready Queue. RPQRDYI remains valid when interrupts are disabled and may be polled to detect RPDR ready queue write events. RPDFQEI: The receive packet descriptor free queue error interrupt status bit (RPDFQEl) reports receive packet descriptor free queue error interrupts to the PCI host. RPDFQEL is set high upon attempts to retrieve an RPDR when both the large buffer and small buffer free queues are empty. RPDFQEI remains valid wnen interrupts are disabled and may be polled to detect RPDR free queue empty error events. RPDRQEI: The receive packet descriptor ready queue error interrupt status bit (RPDRQE)) reports receive packet descriptor ready queue error interrupts to the PCI host. RPDRQEI is set high upon attempts to write an RPDR when ready queue is ready full. RPDRQEI remains valid when interrupts are disabled and may be polled to detect RPDR ready queue full error events. TDQFI: The transmit packet descriptor free queue write interrupt status bit (TDQF1}) reports transmit packet descriptor free queue write interrupts to the PCI host. TDQFI is set high when the programmable number of TDRs is written to the PROPRIETARY AND CONFIDENTIAL 98r> [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET eee reer eee eee e eee ee ence T PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDR Free Queue. TDQFI remains valid when interrupts are disabled and may be polled to detect TDR free queue write events. TDQRDY1: The transmit descriptor ready queue cache read interrupt status bit (TDQRDY!1) reports transmit descriptor ready queue cache read interrupts to the PCI host. TDQRDY1 is set high when the programmable number of TDRs is read from the TDR Ready Queue. TDQRDYI remains valid when interrupts are disabled and may be polled to detect TDR ready queue cache read events. TDFQEI: The transmit descriptor free queue error interrupt status bit (TDFQE]) reports transmit descriptor free queue error interrupts to the PCI host. TDFQEI is set high when an attempt to write to the transmit free queue fail due to the queue being already full. TDFQEI bit remains valid when interrupts are disabled and may be polled to detect TD free queue error events. 1OCI: The transmit interrupt on complete status bit (IOCI) reports transmission complete interrupts to the PCI host. IOCI is set high, when a packet with the IOC bit in the TD set high is completely transmitted. IOC! remains valid when interrupts are disabled and may be polled to detect transmission of |OC tagged packets. TFUDRI: The transmit FIFO underflow error interrupt status bit (TFUDRI) reports transmit FIFO underflow error interrupts to the PCI host. TFUDRI is set high upon attempts to read data from the logical FIFO when it is already empty. TFUDRI remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events. PROPRIETARY AND CONFIDENTIAL 99r [\ /\ co PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x00C : FREEDM-32P672 Master Clock / Frame Pulse / BERT Activity Monitor and Accumulation Trigger Bit Type Function Default Bit 31 Unused XXXXXH to Bit 12 Bit 11 R TFPA[3] Xx Bit 10 R TFPA[2] xX Bit 9 R TFPA[1] X Bit 8 R TFPA[O] X Bit 7 R RFPA[3] X Bit 6 R RFPA[2] Xx Bit 5 R RFPA[1] Xx Bit 4 R RFPA[O] Xx Bit 3 R TFP8A Xx Bit 2 R RFP8A X Bit 1 R TBDA X Bit O R SYSCLKA X This register provides activity monitoring on FREEDM-32P672 system clock, H-MVIP frame pulse and BERT port inputs. When a monitored input makes a transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read periodically to detect for stuck at conditions. Writing to this register delimits the accumulation intervals in the PMON accumulation registers. Counts accumulated in those registers are transferred to holding registers where they can be read. The counters themselves are then cleared to begin accumulating events for a new accumulation interval. The bits in this register are not affected by write accesses. Note This register is not byte addressable. Reading this register clears all the activity bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not PROPRIETARY AND CONFIDENTIAL 100ri /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 implemented. However, when all four byte enables are negated, no access is made to this register. SYSCLKA: The system clock active bit (SYSCLKA) monitors for low to high transitions on the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read. TBDA: The transmit BERT data active bit (TBDA) monitors for low to high transitions on the TBD input. TBDA is set high on a rising edge of TDB, and is set low when this register is read. RFP8A: The receive 8.192 Mbps H-MVIP frame pulse activity bit (RFP8A) monitors for low to high transitions on the RFP8B input. RFP8A is set high when RFP8B has been sampled low and sampled high by falling edges of the RMV8FPC, and is set low when this register is read. TFP8A: The transmit 8.192 Mbps H-MVIP frame pulse activity bit (TFP8A) monitors for low to high transitions on the TFP8B input. TFP8A is set high when TFP8B has been sampled low and sampled high by falling edges of the TMV8FPC, and is set low when this register is read. RFPA[3:0]: The receive frame pulse activity bits (RFPA[3:0]) monitor for low to high transitions on the RFPB[3:0] inputs. RFPA[n] is set high when RFPB[n] has been sampled low and sampled high by falling edges of the corresponding RMVCK)In], and is set low when this register is read. TEPAI3:01: The transmit frame pulse activity bits (TFPA[3:0]) monitor for low to high transitions on the TFPB[3:0] inputs. TFPA[n] is set high when TFPB[n] has been sampled low and sampled high by falling edges of the corresponding TMVCK[n], and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL 101r- [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET eee errr ee ee eee eee eee ey PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x010 : FREEDM-32P672 Master Link Activity Monitor Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R TLGA[7] xX Bit 14 R TLGAJ6] x Bit 13 R TLGA[5] X Bit 12 R TLGA[4] Xx Bit 11 R TLGA[3] Xx Bit 10 R TLGA[2] Xx Bit 9 R TLGA[1]} Xx Bit 8 R TLGA[O] Xx Bit 7 R RLGA|7] x Bit 6 R RLGAJ[6] Xx Bit 5 R RLGA[5] Xx Bit 4 R RLGA[4] Xx Bit 3 R RLGA[3} x Bit 2 R RLGA[2] Xx Bit 1 R RLGA|[1] x Bit 0 R RLGAJ0] x This register provides activity monitoring on FREEDM-32P672 receive and transmit link inputs. When a monitored input makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. Alack of transitions is indicated by the corresponding register bit reading low. This register should be read periodically to detect for stuck at conditions. Note This register is not byte addressable. Reading this register clears all the activity bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not PROPRIETARY AND CONFIDENTIAL 102r 2 [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET | PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 implemented. However, when all four byte enables are negated, no access is made to this register. RLGAJO}: The receive link group #0 active bit (RLGA[0]) monitors for transitions on the RD[3:0] and RCLK[3:0]//,RMVCK[O//RMV8DC inputs. RLGA[O] is set high when either: 1. Each of RD[3:0] has been sampled low and sampled high by rising edges of the corresponding RCLK[3:0] inputs, or 2. Each of RD[3:0] nas been sampled low and sampled high by rising edges of the RMVCK[0] input, or 3. RD[0] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGA|0] is set low when this register is read. RLGAJ1]: The receive link group #1 active bit (RLGA[1]) monitors for transitions on the RD[7:4] and RCLK[7:4]/RMVCK[0//RMV8DC inputs. RLGA[1] is set high when either: 1. Each of RD[7:4] has been sampled low and sampled high by rising edges of the corresponding RCLK[7:4] inputs, or 2. Each of RD[7:4] has been sampled low and sampled high by rising edges of the RMVCK[0] input, or 3. RD[4] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGA|1] is set low when this register is read. RLGA[2]: The receive link group #2 active bit (RLGA[2]) monitors for transitions on the RD[11:8] and RCLK[11:8]/RMVCK[1]/RMV8DC inputs. RLGA[2] is set high when either: 1. Each of RD[11:8] has been sampled low and sampled high by rising edges of the corresponding RCLK[11:8] inputs, or 2. Each of RD[11:8] has been sampled low and sampled high by rising edges of the RMVCK[1] input, or 3. RD[8] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGA[2] is set low when this register is read. RLGAJ3]: The receive link group #3 active bit (RLGA[3]) monitors for transitions on the RD[15:12] and RCLK[15:12]/RMVCK[1]/RMV8DC inputs. RLGA[3] is set high when either: PROPRIETARY AND CONFIDENTIAL 103r- [\ /\ PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 1. Each of RD[15:12] has been sampled low and sampled high by rising edges of the corresponding RCLK[15:12] inputs, or 2. Each of RD[15:12] has been sampled low and sampled high by rising edges of the RMVCK[1] input, or 3. RD[12] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGAJ3} is set low when this register is read. RLGAJ41: The receive link group #4 active bit (RLGA[4]) monitors for transitions on the RD[19:16] and RCLK[19:16]/RMVCK[2]/RMV8DC inputs. RLGA|4] is set high when either: 1. Each of RD[19:16] has been sampled low and sampled high by rising edges of the corresponding RCLK[19:16] inputs, or 2. Each of RD[19:16] has been sampled low and sampled high by rising edges of the RMVCK[2] input, or 3. RD[16] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGA|4] is set low when this register is read. RLGAJ5]: The receive link group #5 active bit (RLGA[5]) monitors for transitions on the RD[23:20] and RCLK[23:20)//RMVCK[2]/RMV8DC inputs. RLGA[5] is set high when either: 1. Each of RD[23:20] has been sampled low and sampled high by rising edges of the corresponding RCLK[23:20] inputs, or 2. Each of RD[23:20] has been sampled low and sampled high by rising edges of the RMVCK[2] input, or 3. RD[20] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGA|5] is set low when this register is read. RLGAJ6]: The receive link group #6 active bit (RLGA[6]) monitors for transitions on the RD[27:24] and RCLK[27:24]/RMVCK[3]/RMV8DC inputs. RLGA[6] is set high when either: 1. Each of RD[27:24] has been sampled low and sampled high by rising edges of the corresponding RCLK[27:24] inputs, or 2. Each of RD[27:24] has been sampled low and sampled high by rising edges of the RMVCK[3] input, or 3. RD[24] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGAJ[6] is set low when this register is read. PROPRIETARY AND CONFIDENTIAL 104i > [\ I as PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RLGAI7]: The receive link group #7 active bit (RLGA[7]) monitors for transitions on the RD[31:28] and RCLK[31:28]/RMVCK[3]/RMV8DC inputs. RLGA[7] is set high when either: 1. Each of RD[31:28] has been sampled low and sampled high by rising edges of the corresponding RCLK[31:28] inputs, or 2. Each of RD[31:28] has been sampled low and sampled high by rising edges of the RMVCK{3] input, or 3. RD[28] has been sampled low and sampled high by rising edges of the RMV8DC input. RLGA|7] is set low when this register is read. TLGAJO}: The transmit link group #0 active bit (TLGA[0]) monitors for low to high transitions on the TCLK[3:0] & TMVCK[O] inputs. TLGA[0] is set high when either: 1. Rising edges have been observed on all four TCLK[3:0] inputs, or 2. Arising edge has been observed on the TMVCK[O] input. TLGA|0O] is set low when this register is read. TLGAJ1]: The transmit link group #1 active bit (TLGA[1]) monitors for low to high transitions on the TCLK[7:4] & TMVCK[1] inputs. TLGA[1] is set high when either: 1. Rising edges have been observed on all four TCLK[7:4] inputs, or 2. Arising edge has been observed on the TMVCK[1] input. TLGAJ1] is set low when this register is read. TLGA[2]: The transmit link group #2 active bit (TLGA[2]) monitors for low to high transitions on the TCLK[11:8] & TMVCK[2] inputs. TLGA[2] is set high when either: 1. Rising edges have been observed on all four TCLK[11:8] inputs, or 2. Arising edge has been observed on the TMVCK[2] input. TLGAJ2] is set low when this register is read. TLGAJ31: The transmit link group #3 active bit (TLGA[3]) monitors for low to high transitions on the TCLK[15:12] & TMVCK[3] inputs. TLGA[3] is set high when either: 1. Rising edges have been observed on ail four TCLK[15:12] inputs, or 2. Arising edge has been observed on the TMVCK[3] input. TLGAJ3] is set low when this register is read. PROPRIETARY AND CONFIDENTIAL 105r-i\ y, PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee sce cena eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TLGAI4]: The transmit link group #4 active bit (TLGA[4]) monitors for low to high transitions on the TCLK[19:16] inputs. TLGAJ[4] is set high when rising edges have been observed on all four TCLK[19:16] inputs, and is set low when this register is read. TLGAJ5)]: The transmit link group #5 active bit (TLGA[5]) monitors for low to high transitions on the TCLK[23:20] inputs. TLGAJ[5] is set high when rising edges have been observed on all four TCLK[23:20] inputs, and is set low when this register is read. TLGAJ6]: The transmit link group #6 active bit (TLGA[6]) monitors for low to high transitions on the TCLK[27:24] inputs. TLGAJ6] is set high when rising edges have been observed on all four TCLK[27:24] inputs, and is set low when this register is read. TLGAJ71: The transmit link group #7 active bit (TLGA[7]) monitors for low to high transitions on the TCLK[31:28] & TMV8DC inputs. TLGA[7] is set high when either: 1. Rising edges have been observed on all four TCLK[31:28] inputs, or 2. Arising edge has been observed on the TMV8DC input. TLGAJ|7] is set low when this register is read. PROPRIETARY AND CONFIDENTIAL 106DATASHEET PMC-1990262 r? iV Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x014 : FREEDM-32P672 Master Line Loopback #1 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W LLBEN[15] 0 Bit 14 R/W LLBEN[14] 0 Bit 13 R/W LLBEN[13] 0 Bit 12 R/W LLBEN[12] 0 Bit 11 R/AWV LLBEN[11] 0 Bit 10 R/W LLBEN[10] 0 Bit 9 R/W LLBEN[9] 0 Bit 8 R/W LLBEN[8] 0 Bit 7 RAV LLBEN[7] 0 Bit 6 R/W LLBEN[6] 0 Bit 5 R/W LLBEN[5] 0 Bit 4 R/W LLBEN[4] 0 Bit 3 R/W LLBEN{3] 0 Bit 2 R/W LLBEN[2] 0 Bit 1 R/W LLBEN[1] 0 Bit 0 R/W LLBEN[O] 0 This register controls line loopback for links #0 to #15. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. LLBEN[15:0): The line loopback enable bits (_LBEN[15:0]) controls line loopback for links #15 to #0. When links #0 through #15 are configured for channelised PROPRIETARY AND CONFIDENTIAL 107r- [\ I PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET Ce PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 T1/J1/E1 or unchannelised traffic and LLBEN[n] is set high, the data on RD[n] is passed verbatim to TD[n] which is then updated on the failing edge of RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed normally. Line loopback is not supported for H-MVIP traffic. PROPRIETARY AND CONFIDENTIAL 108DATASHEET PMC-1990262 PMV Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x018 : FREEDM-32P672 Master Line Loopback #2 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W LLBEN[31] 0 Bit 14 R/W LLBEN[30] 0 Bit 13 R/W LLBEN[29] 0 Bit 12 R/W LLBEN[28] 0 Bit 11 R/W LLBEN[27] 0 Bit 10 R/W LLBEN[26] 0 Bit 9 R/W LLBEN[25] 0 Bit 8 R/W LLBEN[24] 0 Bit 7 R/W LLBEN[23] 0 Bit 6 R/W LLBEN[22] 0 Bit 5 R/W LLBEN[21] 0 Bit 4 R/W LLBEN[20] 0 Bit 3 R/W LLBEN[19] 0 Bit 2 R/W LLBEN(18] 0 Bit 1 R/W LLBEN[17] 0 Bit 0 R/W LLBEN[16] 0 This register controls line loopback for links #16 to #31. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. LLBEN{31:16]: The line loopback enable bits (LLBEN[31:16]) controls line loopback for links #31 to #16. When links #16 through #31 are configured for channelised PROPRIETARY AND CONFIDENTIAL 109r? [\ A PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET T1/J1/E1 or unchannelised traffic and LLBEN[n] is set high, the data on RD[n] is passed verbatim to TD[n] which is then updated on the falling edge of RCLK[n]. TCLK[n] is ignored. When LLBENJn] is set low, TD{[n] is processed normally. Line loopback is not supported for H-MVIP traffic. PROPRIETARY AND CONFIDENTIAL 110rN I cf PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x01C : FREEDM-32P672 Reserved Bit Type Function Default Bit 15 Unused XXXXH to Bit 1 Bit 0 R/W Reserved 0 Note This register is not byte addressable. Reading this register clears all the activity bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. Reserved: The reserved bit must be set low for correct operation of the FREEDM- 32P672 device. PROPRIETARY AND CONFIDENTIAL 117DATASHEET PMC-1990262 ri C PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x020 : FREEDM-32P672 Master BERT Control Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TBEN 0 Bit 14 Unused X Bit 13 Unused X Bit 12 R/W TBSEL[4] 0 Bit 11 R/W TBSEL[3] 0 Bit 10 R/W TBSEL[2] 0 Bit 9 R/W TBSEL[1] 0 Bit 8 R/W TBSEL[0] 0 Bit 7 R/W RBEN 0 Bit 6 Unused X Bit 5 Unused X Bit 4 R/W RBSEL[4] 0 Bit 3 R/W RBSELJ[3] 0 Bit 2 R/W RBSEL[2] 0 Bit 1 R/W RBSEL[1] 0 Bit 0 R/W RBSEL/[0] 0 This register controls the bit error rate testing of the receive and transmit links. Bit error rate testing is not supported for links configured for H-MVIP traffic. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB/[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 112r > [\ fi o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RBSEL[4:0}: The receive bit error rates testing link select bits (RBSEL[4:0]) controls the source of data on the RBD and RBCLK outputs when receive bit error rate testing is enabled (RBEN set high). RBSEL[4:0] is a binary number that selects a receive link configured for non H-MVIP traffic (RD[31:0]/RCLK[31:0]) to be the source of data for RBD and RBCLK outputs. RBSEL[4:0] is ignored when RBEN is set low. RBSEL[4:0] cannot select a link configured for H- MVIP traffic. RBEN: The receive bit error rates testing link enable bit (RBEN) controls the receive bit error rate testing port. When RBEN is set high, RBSEL[4:0] is a binary number that selects a receive link configured for non H-MVIP traffic (RD[31:0]/RCLK[31 :0]) to be the source of data for RBD and RBCLK outputs. When RBEN is set low, RBD and RBCLK are held tristated. TBSEL[4:0]: The transmit bit error rates testing link select bits (TBSEL[4:0]) controls the over-writing of ttansmit data on TD[31:0] by data on TBD when transmit bit error rate testing is enabled (TBEN set high) and the selected link is not in line loopback (LLBEN{[n] set low). TBSEL[4:0] is a binary number that selects a transmit link configured for non H-MVIP traffic (TD[31:0]/TCLK[31:0]) to carry the dataon TBD. The TBCLK output is a buffered version of the selected one of TCLK[31:0]. TBSEL[4:0] is ignored when TBEN is set low. TBSEL[4:0] cannot select a link configured for H-MVIP traffic. TBEN: The transmit bit error rates testing link enable bit (TBEN) controls the transmit bit error rate testing port. When TBEN is set high and the associated link in not in line loopback (LLBEN set low), TBSEL[4:0] is a binary number that selects a transmit link data configured for non H-MVIP traffic (TD[31:0]) to carry the data on TBD and selects a transmit link clock (TCLK[31:0]) as the source of TBCLK. When TBEN is set low, all transmit links are processed normally and TBCLK is held tristated. PROPRIETARY AND CONFIDENTIAL 193DATASHEET PMC-1990262 rf fi C PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x024 : FREEDM-32P672 Master Performance Monitor Control Bit Type Function Default Bit 31 Unused XXXXXH to Bit 15 Bit 14 R/W TP2EN 0 Bit 13 R/W TABRT2EN 0 Bit 12 R/W RP2EN 0 Bit 11 R/W RLENE2EN 0 Bit 10 R/W RABRT2EN 0 Bit 9 R/W RFCSE2EN 0 Bit 8 R/W RSPE2EN 0 Bit 7 Unused Xx Bit 6 R/W TP1EN 0 Bit 5 R/W TABRT1EN 0 Bit 4 R/W RP1EN 0 Bit 3 R/W RLENE1EN 0 Bit 2 R/W RABRT1EN 0 Bit 1 R/W RFCSE1EN 0 Bit O R/W RSPE1EN 0 This register configures the events that are accumulated in the two configurable performance monitor counters in the PMON block. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. RSPE1EN: The receive small packet error accumulate enable bit (RSPE1EN) enables counting of minimum packet size violation events. When RSPE1EN is set PROPRIETARY AND CONFIDENTIAL 114r [\ /\ f PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable Accumulator #1 register to increment. Small packet errors are ignored when RSPE1EN is set low. RFCSE1EN: The receive frame check sequence error accumulate enable bit (RFCSE1EN) enables counting of receive FCS error events. When RFCSE1EN is set high, a mismatch between the received FCS code and the computed CRC residue will cause the PMON Configurable Accumulator #1 register to increment. Receive frame check sequence errors are ignored when RFCSE1EN is set low. RABRT1EN: The receive abort accumulate enable bit (RABRT1EN) enables counting of receive HDLC abort events. When RABRT1EN is set high, receipt of an abort code (at least 7 contiguous 1's) will cause the PMON Configurable Accumulator #1 register to increment. Receive aborts are ignored when RABRT1EN is set low. RLENE1EN: The receive packet length error accumulate enable bit (RLENE1EN) enables counting of receive packet length error events. When RLENEEN is set high, receipt of a packet that is longer than the programmable maximum or of a packet that in not octet aligned will cause the PMON Configurable Accumulator #1 register to increment. (Receipt of a packet that is both too long and not octet aligned results in only one increment.) Receive packet length errors are ignored when RLENE1EN is set low. RP1EN: The receive packet enable bit (RP1EN) enables counting of receive error-free packets. When RP1EN is set high, receipt of an error-free packet will cause the PMON Configurable Accumulator #1 register to increment. Receive error- free packets are ignored when RP1EN is set low. TABRT1EN: The transmit abort accumulate enable bit (TABRT1EN) enables counting of transmit HDLC abort events. When TABRT1EN is set high, insertion of an abort in the outgoing stream will cause the PMON Configurable Accumulator #1 register to increment. Transmit aborts are ignored when TABRT1EN is set low. PROPRIETARY AND CONFIDENTIAL 115i > [\ /I cr PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TP1EN: The transmit packet enable bit (TP1EN) enables counting of transmit error-free packets. When TP1EN is set high, transmission of an error-free packet will cause the PMON Configurable Accumulator #1 register to increment. Transmit error-free packets are ignored when TP1EN is set low. RSPE2EN: The receive small packet error accumulate enable bit (RSPE2EN) enables counting of minimum packet size violation events. When RSPE2EN is set high, receipt of a packet that is shorter than 32 bits (CRC-CCITT, Unspecified CRC or no CRC) or 48 bits (CRC-32) will cause the PMON Configurable Accumulator #2 register to increment. Small packet errors are ignored when RSPEZ2EN is set low. RFECSE2EN: The receive frame check sequence error accumulate enable bit (RFCSE2EN) enables counting of receive FCS error events. When RFCSE2EN is set high, a mismatch between the received FCS code and the computed CRC residue will cause the PMON Configurable Accumulator #2 register to increment. Receive frame check sequence errors are ignored when RFCSE2EN is set low. RABRTZ2EN: The receive abort accumulate enable bit (RABRT2EN) enables counting of receive HDLC abort events. When RABRTZEN is set high, receipt of an abort code (at least 7 contiguous 2's) will cause the PMON Configurable Accumulator #2 register to increment. Receive aborts are ignored when RABRTZEN is set low. RLENE2EN: The receive packet length error accumulate enable bit (RLENE2EN) enables counting of receive packet length error events. When RLENE2EN is set high, receipt of a packet that is longer than the programmable maximum or of a packet that in not octet aligned will cause the PMON Configurable Accumulator #2 register to increment. (Receipt of a packet that is both too long and not octet aligned results in only one increment.) Receive packet length errors are ignored when RLENEZEN is set low. RP2EN: The receive packet enable bit (RP2EN) enables counting of receive error-free packets. When RP2EN is set high, receipt of an error-free packet will cause the PMON Configurable Accumulator #2 register to increment. Receive error- free packets are ignored when RP2EN is set low. PROPRIETARY AND CONFIDENTIAL 116rf\ fi ra PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee eee cere cere ee ee ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET TABRT2EN: The transmit abort accumulate enable bit (TABRT2EN) enables counting of transmit HDLC abort events. When TABRTZEN is set high, insertion of an abort in the outgoing stream will cause the PMON Configurable Accumulator #2 register to increment. Transmit aborts are ignored when TABRTZ2EN is set low. TP2EN: The transmit packet enable bit (TP2EN) enables counting of transmit error-free packets. When TP2EN is set high, transmission of an error-free packet will cause the PMON Configurable Accumulator #2 register to increment. Transmit error-free packets are ignored when TPZEN is set low. PROPRIETARY AND CONFIDENTIAL 117DATASHEET PMC-1990262 PMC PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x080 : GPIC Control Bit Type Function Default Bit 31 Unused XXXXXH to Bit 14 Bit 13 R/W RPWTH[5] 0 Bit 12 R/W RPWTH[4] 0 Bit 11 R/W RPWTH[3] 0 Bit 10 R/W RPWTH[2] 0 Bit 9 R/W RPWTH(1} 0 Bit 8 R/W RPWTH[0] 0 Bit 7 Unused X Bit 6 Unused xX Bit 5 Unused Xx Bit 4 Unused Xx Bit 3 R/W PONS_E 0 Bit 2 R/W SOE_E 0 Bit 1 R/W LENDIAN 1 Bit 0 R/W Reserved 0 This register configures the operation of the GPIC. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. Reserved: The Reserved bit must be set low for correct operation of the FREEDM- 32P672. PROPRIETARY AND CONFIDENTIAL 118PM7380 FREEDM-32P672 rlVi c* PMC-Sierra, Inc. ISSUE 4 DATASHEET PMC-1990262 FRAME ENGINE AND DATA LINK MANAGER 32P672 LENDIAN: The Little Endian mode bit (LENDIAN) selects between Big Endian or Little Endian format when reading packet data from and writing packet data to PCI host memory. When LENDIAN is set low, Big Endian format is selected. When LENDIAN is set high, Little Endian format is selected. Descriptor references and the contents of descriptors are always transferred in Little Endian Format. Please refer below for each format's byte ordering. Table 14 - Big Endian Format The stop on error enable (SOE_E) bit determines the action the PCI 00-sO#Bit 31 24 23 16 15 8 7 Bit O DWORD Address 04 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 e e e e e s e e e e e e n-4 BYTE n-4 BYTE n-3 BYTE n-2 BYTE n-1 Tabie 15 Little Endian Format 00~s Bit 31 24 23 16 15 7 Bit 0 DWORD Address 04 BYTE 3 BYTE 2 BYTE 1 BYTE O BYTE 7 BYTE 6 BYTE 5 BYTE 4 e e Sd e e e e e n-4 BYTE n-1 BYTE n-2 BYTE n-3 BYTE n-4 SOE E: controller will take when a system or parity error occurs. When set high the PCI controller will disconnect the PC! REQB signal from the PCI bus. This prevents the GPIC from the becoming a master device on the PCI bus in event of one of the following bits in the PCI Configuration Command/Status register being set: DPR, RTABT, MABT and SERR. When the SOE _E bit is set low the PCi controller will continue to allow master transactions on the PCI bus. Setting this bit low after an error has occurred or clearing the appropriate bit the PCI Configuration Command/Status register will reactivate the PC] REQB signal and allow the GPIC to resume servicing the local PROPRIETARY AND CONFIDENTIAL 179r> [\ fl PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET ener ee ee eee cence eee ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 masters. In the event of a system or parity error it is recommended that the core device be reset unless the cause of the fault can be determined. PONS E: The Report PERR on SERR enable (PONS_E) bit controls the source of system errors. When set high all parity errors will be signaled to the host via the SERRB output signal. RPWTH[5:0]: The Receive Packet Write Threshold bits (RPWTH[5:0]) controls the amount of data in the write FIFO before the GPIC begins arbitrating for the bus. The GPIC will begin requesting access to the PCI bus when the number of dwords of packet data loaded by the RMAC672 reaches the threshold specified by RPWTH[5:0]. If the FREEDM-32P672 is being operated with PCICLK at a higher frequency than SYSCLK, RPWTH must be set to a value that ensures that the write FIFO does not underflow due to data being read out of the FIFO faster than data is written into the FIFO. It is recommended that RPWTH be set toa value not less than [4x (XFER + Hf - sees -|: SSCL PCICLKfreq. PCICLKfreg. where rg is the minimum number of clock cycles in which GNTB can be received after REQB has been asserted. PROPRIETARY AND CONFIDENTIAL 120DATASHEET PMC-1990262 PV c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x100 : RCAS Indirect Link and Time-slot Select Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY X Bit 14 R/W RWB 0 Bit 13 Unused X Bit 12 R/W Reserved 0 Bit 11 R/W Reserved 0 Bit 10 R/W LINK[4] 0 Bit 9 R/W LINK[3] 0 Bit 8 R/W LINK[2] 0 Bit 7 R/W LINK[1] 0 Bit 6 R/W LINK[O] 0 Bit 5 Unused Xx Bit 4 R/W TSLOT[4] 0 Bit 3 R/W TSLOT[3] 0 Bit 2 R/W TSLOT[2] 0 Bit 1 R/W TSLOT[1] 0 Bit 0 R/W TSLOT/[O] 0 This register provides the receive link and time-slot number used to access the channel provision RAM. Writing to this register triggers an indirect register access. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEBJ[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 121rl I PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee eee eee e cece cece eee eee es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET TSLOT[4:0]: The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. For a channelised T1/J1 link, time-slots 1 to 24 are valid. For a channelised E71 link, time-slots 1 to 31 are valid. For an H-MVIP link, time-slots 0 to 31 are valid. For unchannelised links, only time-slot 0 is valid. LINK[4:0]: The indirect link number bits (LINK[4:0]) select amongst the 32 receive links to be configured or interrogated in the indirect access. Reserved: The reserved bits must be set low for correct operation of the FREEDM- 32P672 device. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. The address to the channel provision RAM is constructed by concatenating the TSLOT[4:0} and LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV, the CDLBEN and the CHAN{9:0] bits of the RCAS Indirect Channel Data register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect write operation. The data read can be found in the PROV, the CDLBEN and the CHAN[9:0] bits of the RCAS Indirect Channel Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RCAS Indirect Channel Data register or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 122DATASHEET PMC-1990262 rPiVi C PMC-Sierra, inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x104 : RCAS Indirect Channel Data Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W CDLBEN Bit 14 R/W PROV Bit 13 Unused XH to Bit 10 Bit 9 R/IW CHAN[9] 0 Bit 8 R/W CHAN[8] 0 Bit 7 RW CHAN[7] 0 Bit 6 RW ~sSCHAANN[6] 0 Bit 5 R/W CHAN[5] 0 Bit 4 R/W CHAN/4] 0 Bit 3 R/W CHAN[3] 0 Bit 2 R/W CHAN[2] 0 Bit 1 R/W CHAN[1] 0 Bit 0 R/W CHAN[O] 0 This register contains the data read from the channel provision RAM after an indirect read operation or the data to be inserted into the channel provision RAM in an indirect write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHAN{9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the channel provision RAM after an indirect read operation has completed. PROPRIETARY AND CONFIDENTIAL 123r- [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Channel number to be written to the channel provision RAM in an indirect write operation must be set up in this register before triggering the write. CHAN{9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the current receive data byte is processed as part of the channel as indicated by CHAN[9:0]. When PROV is set low, the current time-slot does not belong to any channel and the receive data byte ignored. PROV reflects the value written until the completion of a subsequent indirect read operation. CDLBEN: The indirect channel! based diagnostic loopback enable bit (CDLBEN) reports the loopback enable flag read from channel provision RAM after an indirect read operation has complete. The loopback enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When CDLBEN is set high, the current receive data byte is to be over-written by data retrieved from the loopback FIFO of the channel as indicated by CHAN[9:0]. When CDLBEN is set low, the current receive data byte is processed normally. CDLBEN reflects the value written until the completion of a subsequent indirect read operation. PROPRIETARY AND CONFIDENTIAL 124i > [\ /\ co PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x108 : RCAS Framing Bit Threshold Bit Type Function Default Bit 31 Unused XXXXXXXH to Bit 7 Bit 6 R/W FTHRESJ6] 0 Bit 5 R/W FTHRES[5] 1 Bit 4 R/W FTHRES/4] 0 Bit 3 R/W FTHRES[3] 0 Bit 2 R/W FTHRES[2] 1 Bit 1 R/W FTHRES[1] 0 Bit 0 R/W FTHRES[0] 1 This register contains the threshold used by the clock activity monitor to detect for framing bits/bytes. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. FTHRESJ6:0}: The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by the clock activity monitor to detect for the presence of framing bits. A counter in the clock activity monitor of each receive link increments on each rising edge of SYSCLK and is cleared, when the BSYNC bit of that link is set low, by each rising edge of the corresponding RCLK[n]. When the BSYNC bit of that link is set high, the counter is cleared at every fourth rising edge of the corresponding RCLK[n]. When the counter exceeds the threshold given by FTHRESJ[6:0], a framing bit/byte has been detected. FTHRESJ[6:0] should be set as a function of the SYSCLK period and the expected gapping width of RCLK[n] during data bits and during framing bits/bytes. Legal range of FTHRESH{[6:0] is 'b0000001 to 'b1111110. PROPRIETARY AND CONFIDENTIAL 125i [\ A PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Note: For operation with T1/J1 links and SYSCLK = 45 MHz, FTHRESH{(6:0] should be set to 00100101. The default value of this register reflects this mode of operation. PROPRIETARY AND CONFIDENTIAL 126DATASHEET PMC-1990262 rV Cc PMC-Sierra, inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x10C : RCAS Channel Disable Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W CHDIS 0 Bit 14 Unused XXH to Bit 10 Bit 9 R/W DCHAN[9] 0 Bit 8 R/W DCHANJ[8] 0 Bit 7 R/W DCHAN[7] 0 Bit 6 R/W DCHANJ[6] 0 Bit 5 R/W DCHAN[5] 0 Bit 4 R/W DCHAN[4] 0 Bit 3 R/W DCHAN{3] 0 Bit 2 R/W DCHAN[2] 0 Bit 1 R/W DCHAN[1] 0 Bit 0 R/W DCHAN(0] 0 This register controls the disabling of one specific channel to allow orderly provisioning of time-slots associated with that channel. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. DCHAN9:01: The disable channel number bits (DCHAN[9:0]) selects the channel to be disabled. When CHDIS is set high, the channel specified by DCHAN{[9:0] is disabled. Data in time-slots associated with the specified channel is ignored. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally. PROPRIETARY AND CONFIDENTIAL 127r? [\ A ra PMC- Sierra, Inc. PM7380 FREEDM-32P672 en aa ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET CHDIS: The channel disable bit (CHDIS) controls the disabling of the channels specified by DCHAN[9:0]. When CHDIS is set high, the channel selected by DCHANJ[9:0] is disabled. Data in time-slots associated with the specified channel is ignored. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally. PROPRIETARY AND CONFIDENTIAL 128i 2 [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x180 0x188 : RCAS Links #0 to #2 Configuration Bit Type Function Default Bit 31 Unused XXXXXXXH to Bit 5 Bit 4 R/W BSYNC 0 Bit 3 Unused x Bit 2 R/W MODE[2] 0 Bit 1 R/W MODE{1] 0 Bit 0 R/W MODE[O] 0 This register configures operational modes of receive links #0 to #2. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. MODE[2:0}: The mode select bits (MODE[2:0]) configures the corresponding receive link. Table 16 details this procedure. When link 4m (O<m<7) is configured for operation in 8.192 Mbps H-MVIP mode (MODE[2:0]="111), data cannot be received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and 4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation of the RCAS672. From a channel assignment point of view in the RCAS672 (Registers 0x100, 0x104), time-slots 0 through 31 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m, time-slots 32 through 63 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64 through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as time- slots 0 through 31 of link 4m+3. PROPRIETARY AND CONFIDENTIAL 129r [\ fi co PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 16 - Receive Links #0 to #2 Configuration MODE[2:0] Link Configuration 000 Unchannelised 001 Channelised T1/J1 (24 time slots labeled 1-24) 010 Channelised E1 (31 time slots labeled 1-31) 011 2 Mbps H-MVIP (32 time slots labeled 0-31) 100 Reserved 101 Reserved 110 Reserved 111 8 Mbps H-MVIP (128 time slots mapped to time- slots 0 through 31 of links 4m, 4m+1, 4m+2 and 4m+3) BSYNC: The byte synchronization enable bit (BSYNC) controls the interpretation of gaps in RCLK[n] when link #n is in unchannelised mode (MODE[2:0]="000). When BSYNC is set high, the data bit on RD[n] clocked in by the first rising edge of RCLK[n] after an extended quiescent period is considered to be the most significant bit of a data byte. When BSYNC is set low, gaps in RCLK([n] carry no special significance. BSYNC is ignored when MODE[2:0]#000. PROPRIETARY AND CONFIDENTIAL 130r- Vi q PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x18C 0x1FC : RCAS Links #3 to #31 Configuration Bit Type Function Default Bit 31 Unused XXXXXXXXH to Bit 3 Bit 2 R/W MODE[2] Bit 1 R/W MODE[1] Bit 0 R/W MODE[O] This register configures operational modes of receive links #3 to #31. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. MODE/[2:0]: The mode select bits (MODE[2:0]) configures the corresponding receive link. Table 17 details this procedure. When link 4m (O<m<7) is configured for operation in 8.192 Mbps H-MVIP mode (MODE[2:0]="111), data cannot be received on links 4m+1, 4m+2 and 4m+3. However, links 4m+1, 4m+2 and 4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation of the RCAS672. From a channel assignment point of view in the RCAS672 (Registers 0x100, 0x104), time-slots 0 through 31 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m, time-slots 32 through 63 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m+1, time-slots 64 through 95 of the H-MVIP link are treated as time-slots 0 through 31 of link 4m+2 and time-slots 96 through 127 of the H-MVIP link are treated as time- slots 0 through 31 of link 4m+3. PROPRIETARY AND CONFIDENTIAL 137r [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ey PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 17 - Receive Links #3 to #31 Configuration MODE[2:0] | Link Configuration 000 Unchannelised 001 Channelised T1/J1 (24 time slots labeled 1-24) | 010 Channelised E1 (31 time slots labeled 1-31) 011 2 Mbps H-MVIP (32 time slots labeled 0-31) 100 Reserved 101 Reserved 110 Reserved 111 8 Mbps H-MVIP (128 time slots mapped to time- slots 0 through 31 of links 4m, 4m+1, 4m+2 and 4m+3) PROPRIETARY AND CONFIDENTIAL 132DATASHEET PMC-1990262 PV Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x200 : RHDL Indirect Channel Select Bit Type Function Defauit Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY Bit 14 R/W CRWB 0 Bit 13 Unused XH to Bit 10 Bit 9 R/W CHAN[9] 0 Bit 8 R/W CHAN[8] 0 Bit 7 R/W CHAN[7] ) Bit 6 R/W CHAN{[6] 0 Bit 5 R/W CHAN[5] 0 Bit 4 R/W CHAN[4] 0 Bit 3 R/W CHAN[3] 0 Bit 2 R/W CHAN[2] ) Bit 1 R/W CHAN[1] 0 Bit O R/W CHAN[0] 0 This register provides the channel number used to access the receive channel provision RAM. Writing to this register triggers an indirect channel register access. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEBJ[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHAN[9:01: The indirect channel number bits (CHAN[9:0]) indicate the receive channel to be configured or interrogated in the indirect access. PROPRIETARY AND CONFIDENTIAL 133r? [\ fl c PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the receive channel provision RAM. Writing a logic zero to CRWB triggers an indirect write operation. Data to be written is taken from the Indirect Channel Data registers. Writing a logic one to CRWB triggers an indirect read operation. The data read can be found in the Indirect Channel Data registers. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RHDL Indirect Channel Data #1 and #2 registers or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 134DATASHEET PMC-1990262 r- VM Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x204 : RHDL Indirect Channel Data Register #1 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W PROV 0 Bit 14 R/W STRIP 0 Bit 13 R/W DELIN 0 Bit 12 R TAVAIL X Bit 11 WwW Reserved X Bit 10 W FPTR[10] X Bit 9 W FPTR[9] X Bit 8 WwW FPTR[8] X Bit 7 W FPTR[7] X Bit 6 W FPTR[6] X Bit 5 W FPTR[5] X Bit 4 W FPTR[4] X Bit 3 W FPTR[3}] X Bit 2 WwW FPTR[2] X Bit 1 W FPTR[1] X Bit O WwW FPTR[O}] X This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 135r-i\ fi ae PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FPTRI10:0): The indirect FIFO block pointer (FPTR[10:0]) identifies one of the blocks of the circular linked list in the partial packet buffer used in the logical FIFO of the current channel. The FIFO pointer to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. The FIFO pointer value can be any one of the blocks provisioned to form the circular buffer. Reserved: The reserved bit must be set low for correct operation of the FREEDM- 32P672 device. TAVAIL: The indirect transaction available bit (TAVAIL) reports the fill level of the partial packet buffer used in the logical FIFO of the current channel. TAVAIL is set high when the FIFO of the current channel contains sufficient data, as controlled by XFER[3:0], to request a DMA transfer to the host memory. TAVAIL is set low when the amount of receive data is too small to require a transfer to host memory. TAVAIL is updated by an indirect channel read operation. DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence delineation and bit de-stuffing on the incoming data stream. The delineate enable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DELIN is set high, flag sequence delineation and bit de-stuffing is performed on the incoming data stream. When DELIN is set low, the HDLC processor does not perform any processing (flag sequence delineation, bit de-stuffing nor CRC verification) on the incoming stream. DELIN reflects the value written until the completion of a subsequent indirect channel read operation. STRIP: The indirect frame check sequence discard bit (STRIP) configures the HDLC processor to remove the CRC from the incoming frame when writing the data to the channel FIFO. The FCS discard bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When STRIP is set high and CRC[1:0] is not equal to "00", the received CRC value is not written to the FIFO. When STRIP is set low, the received CRC value is written to the FIFO. The bytes in buffer field of the RPD correctly reflect the presence/absence of CRC bytes in the buffer. The value of STRIP is ignored when DELIN is low. STRIP reflects PROPRIETARY AND CONFIDENTIAL 136r 2 [\ Sf c PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 the value written until the completion of a subsequent indirect channel read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the HDLC processor will process data on the channel specified by CHAN[9:0]. When PROV is set low, the HDLC processor will ignore data on the channel specified by CHAN[9:0]. PROV reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL 137DATASHEET PMC-1990262 PevMCc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x208 : RHDL Indirect Channel Data Register #2 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W 7BIT 0 Bit 14 R/W PRIORITY 0 Bit 13 R/W INVERT 0 Bit 12 Unused Xx Bit 11 R/W CRC[1] 0 Bit 10 R/W CRC[0] 0 Bit 9 R/W OFFSET[1]} 0 Bit 8 R/W OFFSET[O] 0 Bit 7 Unused x Bit 6 Unused x Bit 5 Unused xX Bit 4 Unused Xx Bit 3 R/W XFER[3] 0 Bit 2 R/W XFER[2] 0 Bit 1 R/W XFER[1] 0 Bit 0 R/W XFER[O} 0 This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 138r- [\ i Y PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 XFERJ3:0]: The indirect channel transfer size (XFER[3:0]) configures the amount of data transferred in each transaction. The channel transfer size to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When the channel FIFO depth reaches the depth specified by XFER[3:0] or when an end-of-packet exists in the FIFO, a request will be made to the RMAC6/72 to initiate a PCI write access to transfer the data to the PCI host. Channel transfer size is measured in 16 byte blocks. The amount of data transferred and the depth threshold are specified by given setting is: XFER[3:0] + 1 blocks = 16 * (XFER[3:0] + 1) bytes XFER[3:0] should be set such that the number of blocks transferred is at least two fewer than the total allocated to the associated channel. XFER[3:0} reflects the value written until the completion of a subsequent indirect channel read operation. OFFSET{[1:0]: The packet byte offset (OFFSET[1:0]) configures the partial packet processor to insert invalid bytes at the beginning of a packet stored in the channel FIFO. The value of OFFSET[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. The number of bytes inserted before the beginning of a HDLC packet is defined by the binary value of OFFSET[1:0]. OFFSET[1:0] reflects the value written until the completion of a subsequent indirect channel read operation. CRC[1:0]: The CRC algorithm bits (CRC[1:0]) configures the HDLC processor to perform CRC verification on the incoming data stream. The value of CRC[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value written until the completion of a subsequent indirect channel read operation. Table 18 CRC[1:0] Settings CRC[1] CRC[0] Operation 0 0 No Verification 0 1 CRC-CCITT 1 0 CRC-32 PROPRIETARY AND CONFIDENTIAL 139i Vi a PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 CRC[1] CRC[0] Operation 1 1 Reserved INVERT: The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the incoming HDLC stream from the RCAS672 before processing it. The value of INVERT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When INVERT is set to one, the HDLC stream is logically inverted before processing. When INVERT is set to zero, the HDLC stream is not inverted before processing. INVERT reflects the value written until the completion of a subsequent indirect channel read operation. PRIORITY: The channel FIFO priority bit (PRIORITY) informs the partial packet processor that the channel has precedence over other channels when being serviced by the RMAC672 block for transfer to the PCI host. The value of PRIORITY to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Channel FIFOs with PRIORITY set to one are serviced by the RMAC672 before channel FIFOs with PRIORITY set to zero. Channels with an HDLC data rate to FIFO size ratio that is significantly higher than other channels should have PRIORITY set to one. PRIORITY reflects the value written until the completion of a subsequent indirect channel read operation. 7BIT: The 7BIT enable bit (7BIT) configures the HDLC processor to ignore the least significant bit of each octet in the corresponding link RD[n]. The value of 7BIT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet received), is ignored. When 7BIT is set low, the entire receive data stream is processed. 7BIT reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL 140DATASHEET PMC-1990262 PV C PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x210 : RHDL Indirect Block Select Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY X Bit 14 R/W BRWB X Bit 13 Unused x Bit 12 Unused X Bit 11 Unused xX Bit 10 R/W BLOCK[10] x Bit 9 R/W BLOCK{[9] X Bit 8 R/W BLOCK[8] X Bit 7 R/W BLOCK[7] Xx Bit 6 R/W BLOCKJ[6] X Bit 5 R/W BLOCK[5] X Bit 4 R/W BLOCK[4] Xx Bit 3 R/W BLOCK[3] Xx Bit 2 R/W BLOCK[2] x Bit 1 R/W BLOCK[1]} xX Bit O R/W BLOCK[0} x This register provides the block number used to access the block pointer RAM. Writing to this register triggers an indirect block register access. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 141r- [\ /\ Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET A PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 BLOCK/10:0]: The indirect block number (BLOCK[10:0}]) indicate the block to be configured or interrogated in the indirect access. Reserved: The reserved bit must be set low for correct operation of the FREEDN- 32P672 device. BRWB: The block indirect access control bit (BRWB) selects between a configure (write) or interrogate (read) access to the block pointer RAM. Writing a logic zero to BRWB triggers an indirect block write operation. Data to be written is taken from the Indirect Block Data register. Writing a logic one to BRWB triggers an indirect block read operation. The data read can be found in the Indirect Block Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the RHDL Indirect Block Data register or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 142DATASHEET PMC-1990262 PMC PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x214 : RHDL Indirect Block Data Bit Type Function Default Bit 31 Unused XXXXXH to Bit 12 Bit 11 R/W Reserved X Bit 10 R/W BPTR[10] 0 Bit 9 R/W BPTRI[9] 0 Bit 8 R/W BPTR[8] 0 Bit 7 R/W BPTR[7] 0 Bit 6 R/W BPTR[6] 0 Bit 5 R/W BPTR{[5] 0 Bit 4 R/W BPTR[4] 0 Bit 3 R/W BPTR[3] 0 Bit 2 R/W BPTR[2] 0 Bit 1 R/W BPTR[1] 0 Bit 0 R/AW BPTRI[O] 0 This register contains data read from the block pointer RAM after an indirect block read operation or data to be inserted into the block pointer RAM in an indirect block write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB([3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. BPTR[10:0): The indirect block pointer (BPTR[10:0}) configures the block pointer of the block specified by the Indirect Block Select register. The block pointer to be written to the block pointer RAM, in an indirect write operation, must be set up in this register before triggering the write. The block pointer value is the block number of the next block in the linked list. A circular list of blocks must be formed in order to use the block list as a receive channel FIFO buffer. PROPRIETARY AND CONFIDENTIAL 143i 2 [\ fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 BPTR[10:0] reflects the value written until the completion of a subsequent indirect block read operation. When provisioning a channel FIFO, all block pointers must be re-written to properly initialize the FIFO. Reserved: The reserved bit must be set low for correct operation of the FREEDM- 32P672 device. PROPRIETARY AND CONFIDENTIAL 144DATASHEET PMC-1990262 PV Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x220 : RHDL Configuration Bit Type Function Default Bit 31 Unused XXXXXXH to Bit 10 Bit 9 R/W LENCHK 0 Bit 8 R/W TSTD 0 Bit 7 Unused X Bit 6 Unused xX Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 Unused X Bit 1 Unused Xx Bit O | Unused X This register configures all provisioned receive channels. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB(3:0]) are not implemented. However, when ail four byte enables are negated, no access is made to this register. TSTD: The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred to the PCI host. When TSTD is set low, the least significant bit of the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24)}) is the first HDLC bit received and the most significant bit of each byte (AD[7], AD[15], AD[23] and AD[31]) is the last HDLC bit received (datacom standard). When TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC bit received and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit received (telecom standard). PROPRIETARY AND CONFIDENTIAL 145r 2 [\ fi cr PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 LENCHK: The packet length error check bit (LENCHK) controls the checking of receive packets that are longer than the maximum programmed length. When LENCHK is set high, receive packets are aborted and the remainder of the frame discarded when the packet exceeds the maximum packet length given by MAX[15:0]. When LENCHK is set low, receive packets are not checked for maximum size and MAX[15:0] must be set to 'hNFFFF. PROPRIETARY AND CONFIDENTIAL 146DATASHEET PMC-1990262 r> [\ f\ c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x224 : RHDL Maximum Packet Length Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W MAX[15] 1 Bit 14 R/W MAX[14] 1 Bit 13 R/W MAX[13] 1 Bit 12 R/W MAX[12] 1 Bit 11 R/W MAX[11] 1 Bit 10 R/W MAX{[10] 1 Bit 9 R/W MAX[9] 1 Bit 8 R/W MAX[8] 1 Bit 7 R/W MAX[7] 1 Bit 6 R/W MAX[6] 1 Bit 5 R/W MAX[5] 1 Bit 4 R/W MAX[4] 1 Bit 3 R/W MAX[3] 1 Bit 2 R/W MAX[2] 1 Bit 1 R/W MAX[1] 1 Bit O R/W MAX[0] 1 This register configures the maximum legal HDLC packet byte length. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. MAX[15:0]: The maximum HDLC packet length (MAX[15:0]) configures the FREEDM- 32P672 to reject HDLC packets longer than a maximum size when LENCHK PROPRIETARY AND CONFIDENTIAL 147r> [\ / PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET Ree es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 is set high. Receive packets with total length, including address, control, information and FCS fields, greater than MAX[15:0] bytes are aborted. When LENCHK is set low, aborts are not generated regardless of packet length and MAX[15:0] must be set to 'hFFFF. PROPRIETARY AND CONFIDENTIAL 148DATASHEET PMC-1990262 r [\ I Cc PMC-Sierra, inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x280 : RMAC Control Bit Type Function Default Bit 31 Unused XXXXXH to Bit 13 Bit 12 R/W Reserved 0 Bit 11 R/W RPQ_SFN[1] 0 Bit 10 R/W RPQ_SFN[0] 0 Bit 9 R/W RPQ_LFN[14] 0 Bit 8 R/W RPQ_LFN[O] 0 Bit 7 R/W RPQ_RDYN[2] 0 Bit 6 R/AW RPQ_RDYN(1] 0 Bit 5 R/W RPQ_RDYN(0] 0 Bit 4 R/V RAWMAX[(1] 1 Bit 3 R/W RAW MAX[0] 1 Bit 2 R/W SCACHE 1 Bit 1 R/W LCACHE 1 Bit 0 R/W ENABLE 0 This register configures the RMAC672 block. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. ENABLE: The ENABLE bit determines whether or not the RMAC672 accepts data from the RHDL672 block and sends it to host memory. When set to 1, these tasks are enabled. When set to 0, they are disabled. PROPRIETARY AND CONFIDENTIAL 149DATASHEET r- [\ I q PMC-Sierra, inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 LCACHE: The large buffer cache enable bit (L.CACHE) enables caching of Large Buffer RPDRs. When LCACHE is set high, RPDRs are fetched from the RPDR Large Buffer Free Queue in groups of up to six. When LCACHE is set low, RPDRs are fetched one at a time. SCACHE: The small buffer cache enable bit (SCACHE) enables caching of Small Buffer RPDRs. When SCACHE is set high, RPDRs are fetched from the RPDR Small Buffer Free Queue in groups of up to six. When SCACHE is set low, RPDRs are fetched one at a time. RAWMAX{1:01: The RAWMAX[1:0] field determines how raw (i.e. non packet delimited) data is written to host memory. Raw data is written to buffers in host memory in the same manner as packet delimited data. Whenever RAWMAX[1:0] + 1 buffers have been filled, the resulting buffer chain is placed in the ready queue. RPQ_RDYN/[2:0]: The RPQ_RDYN|[2:0] field sets the number of receive packet descriptor references (RPDRs) that must be placed onto the RPDR ready queue before the RPDR ready interrupt (RPQRDY]) is asserted, as follows: Table 19 - RPQ_RDYN[2:0] settings RPQ_RDYN[2:0] No of RPDRs 000 4 001 4 010 6 011 8 100 16 101 32 110 Reserved 111 Reserved If the value of RPQ_RDYN|[2:0] is altered, the new value does not become effective until after the RPQRDY!1 interrupt is next generated. PROPRIETARY AND CONFIDENTIAL 150i [\ fi q PMC-Sierra, Inc. PM7380 FREEDM-32P672 A DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPQ_LFNJ1:0): The RPQ_LFN[1:0] field sets the number of times that a block of RPDRs are read from the Large Buffer Free Queue to the RMAC672s internal cache before the RPDR Large Buffer Free Queue interrupt (RPQLF1) is asserted, as follows: Table 20 - RPQ_LFN[1:0] Settings RPQ_LFN[1:0] No of Reads 00 1 01 4 10 8 11 Reserved If the value of RPQ_LFN[1:0] is altered, the new value does not become effective until after the RPQLFI interrupt is next generated. RPQ_ SFN{1:0]: The RPQ_SFN{1:0] field sets the number of times that a block of RPDRs are read from the Small Buffer Free Queue to the RMAC672s internal cache before the RPDR Smail Buffer Free Queue interrupt (RPQSFI) is asserted, as follows: Table 21 - RPQ_SFN[1:0] Settings RPQ_SFN[1:0] No of Reads 00 1 01 4 10 8 11 Reserved If the value of RPQ_SFN[1:0] is altered, the new value does not become effective until after the RPQSFI interrupt is next generated. Reserved: The reserved bit must be set low for correct operation of the FREEDM- 32P672 device. PROPRIETARY AND CONFIDENTIAL 151DATASHEET PMC-1990262 PM C PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x284 : RMAC Indirect Channel Provisioning Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY Bit 14 R/W RWB 0 Bit 13 Unused XH to Bit 11 Bit 10 R/W PROV 0 Bit 9 R/W CHAN[9] 0 Bit 8 R/W CHAN[8] 0 Bit 7 R/W CHAN[7] 0 Bit 6 R/W CHAN[6] 0 Bit 5 R/W CHAN[5] 0 Bit 4 R/W CHAN[4] 0 Bit 3 R/W CHANJ3] 0 Bit 2 R/W CHAN[2} 0 Bit 1 R/W CHAN[1] 0 Bit 0 R/W CHANJ[0] 0 The Channel Provisioning Register is used to temporarily unprovision channels, and also to query the provision status of channels. Channel is permanently provisioned and can only be unprovisioned transiently. When a channel is unprovisioned, a partially received packet, if any, will be flushed and marked as unprovisioned in the RPDRR queue status field. The channel then returns to being provisioned automatically. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 182r-[\ fi ri PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET eT PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 CHAN[9:01: The indirect data bits (CHAN[9:0]) report the channel number read from the RMAC672 internal memory after an indirect read operation has completed. Channel number to be written to the RMAC672 internal memory in an indirect write operation must be set up in this register before triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the RMAC672 internal memory after an indirect read operation has completed. The provision enable flag to be written to the RMAC672 internal memory, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the channel indicated by CHAN[9:0] is provisioned. When PROV is set low, the channel indicated by CHAN[9:0] is unprovisioned temporarily. Any partially received packets are flushed and the status in the RPDRR queue is marked unprovisioned. The channel then returns to being provisioned and PROV will report a logic high after the next indirect read operation. PROV reflects the value written until the completion of a subsequent indirect read operation. RWB: The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning operation (write) or a query operation (read). Writing a logic O to RWB triggers the provisioning or unprovisioning of a channel as specified by CHAN[9:0] and PROV. Writing a logic 1 to RWB triggers a query of the channel specified by CHAN{9:0]. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 153DATASHEET PMC-1990262 PV Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x288 : RMAC Packet Descriptor Table Base LSW Bit Type Function Default Bit 34 Unused XXXXH to Bit 16 Bit 15 R/W RPDTB[15] 0 Bit 14 R/W RPDTB[14] 0 Bit 13 R/W RPDTB[13] 0 Bit 12 R/W RPDTB[12] 0 Bit 114 R/W RPDTB[11] 0 Bit 10 R/W RPDTB[10] 0 Bit 9 R/W RPDTB[9] 0 Bit 8 R/W RPDTB[8} 0 Bit 7 R/W RPDTB[7] 0 Bit 6 R/W RPDTB[6] 0 Bit 5 R/W RPDTB[5] 0 Bit 4 R/W RPDTB[4] 0 Bit 3 R/W RPDTB[3] 0 Bit 2 R/W RPDTB[2] 0 Bit 1 R/W RPDTB[1] 0 Bit 0 R/W RPDTB[O] 0 This register provides the less significant word of the Receive Descriptor Table Base address. The contents of this register is held in a holding register until a write access to the companion RMAC Receive Descriptor Table Base MSW register. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIALDATASHEET PMC-1990262 PV Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x28C : RMAC Packet Descriptor Table Base MSW Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDTB[31] 0 Bit 14 R/W RPDTB[30] 0 Bit 13 R/W RPDTB[29] 0 Bit 12 R/W RPDTB[28] 0 Bit 11 R/W RPDTB[27] 0 Bit 10 R/W RPDTB[26] 0 Bit 9 R/W RPDTB[25] 0 Bit 8 R/W RPDTB[24] 0 Bit 7 R/W RPDTB[23] 0 Bit 6 R/W RPDTB[22] 0 Bit 5 R/W RPDTB[21] 0 Bit 4 R/W RPDTB[20] 0 Bit 3 R/W RPDTB[19] 0 Bit 2 R/W RPDTB[18] 0 Bit 1 R/W RPDTB[17] 0 Bit 0 R/W RPDTB[16] 0 This register provides the more significant word of the Receive Descriptor Table Base address. The contents of the companion RMAC Receive Descriptor Table Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the receive packet descriptor table is updated. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 155r [\ fi PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDTB[31:0]: The receive packet descriptor table base bits (RPDTB[31:0]) provides the base address of the Receive Packet Descriptor Table in PC! host memory. This register is initialised by the host. To caiculate the physical address of a RPD, the 15 bit RPD offset must be added to bits 31 to 4 of the Receive Packet Descriptor Table Base (RPDTB[31:4]). The table must be on a 16 byte boundary and thus the least significant four bits must be written to logic zero. PROPRIETARY AND CONFIDENTIAL 156DATASHEET PMC-1990262 PV c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x290 : RMAC Queue Base LSW Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RQB[15] 0 Bit 14 R/W RQB[14] 0 Bit 13 R/W RQB[13] ) Bit 12 R/W RQB[12] 0 Bit 11 R/W RQB[11] 0 Bit 10 R/W RQB[10] 0 Bit 9 R/W RQB[9] 0 Bit 8 R/AW RQB[8] 0 Bit 7 R/W RQB[7] 0 Bit 6 R/W RQB[6] 0 Bit 5 R/W RQB[5] 0 Bit 4 R/W RQB[4] 0 Bit 3 R/W RQB[3] 0 Bit 2 R/W RQB[2] 0 Bit 1 R/W RQB[1] 0 Bit O R/W RQB[0] 0 This register provides the less significant word of the Receive Queue Base address. The contents of this register is held in a holding register until a write access to the companion RMAC Receive Queue Base MSW register. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 157DATASHEET PMC-1990262 r- Vi Cc" PMC-Sierra, inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x294 : RMAC Queue Base MSW Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RQB[31] 0 Bit 14 R/W RQB[30] 0 Bit 13 R/W RQB[29] 0 Bit 12 R/W RQB[28] 0 Bit 11 R/W RQB[27] 0 Bit 10 R/W RQB[26] 0 Bit 9 RW RQB[25] 0 Bit 8 R/W RQB[24] 0 Bit 7 R/W RQB[23] 0) Bit 6 R/W RQB[22] 0 Bit 5 R/W RQB[21] 0 Bit 4 R/W RQB[20] 0 Bit 3 R/W RQB[19] 0 Bit 2 R/W RQB[18] 0 Bit 1 R/W RQB[17] ) Bit O R/W RQB[16] 0 This register provides the more significant word of the Receive Queue Base address. The contents of the companion RMAC Receive Queue Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the receive queue is updated. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 158ris v/ o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RQB/[31:0]: The receive queue base bits (RQB[31:0]) provides the base address of the Large Buffer RPDR Free, Small Buffer RPDR Free and RPDR Ready queues in PCI host memory. This register is initialised by the host. To calculate the physical address of a particular receive queue element, the RQB bits are added with the appropriate queue start, end, read or write index registers to form the physical address. The base address must be dword aligned and thus the least significant two bits must be written to logic zero. PROPRIETARY AND CONFIDENTIAL 159roi fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x298 : RMAC Packet Descriptor Reference Large Buffer Free Queue Start Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRLFQS[15] 0 Bit 14 R/W RPDRLFQS[14] 0 Bit 13 R/W RPDRLFQS[13] 0 Bit 12 R/W RPDRLFQS[12] 0 Bit 11 R/W RPDRLFQSJ11] 0 Bit 10 R/W RPDRLFQS[10] 0 Bit 9 R/W RPDRLFQSJ9] 0 Bit 8 R/W RPDRLFQSJ[8] 0 Bit 7 R/W RPDRLFQSJ7] 0 Bit 6 R/W RPDRLFQSJ6] 0 Bit 5 R/W RPDRLFQSJ[5] 0 Bit 4 R/W RPDRLFQS[4] 0 Bit 3 R/W RPDRLFQSJ3] 0 Bit 2 R/W RPDRLFQS[2] 0 Bit 1 R/W RPDRLFQS[1] 0 Bit 0 R/W RPDRLFQSj[0] 0 This register provides the Packet Descriptor Reference Large Buffer Free Queue start address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 160r-i\ fi rau PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET nea PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRLFQS/15:0]: The receive packet descriptor reference (RPDR) large buffer free queue start bits (RPDRLFQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue start address. This register is initialised by the host. The physical start address of the RPDRLF queue is the sum of RPDRLFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 161r-f\ fi ri PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x29C : RMAC Packet Descriptor Reference Large Buffer Free Queue Write Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit15 | RW | RPDRLFQW(15] 0 Bit14 | RW | RPDRLFQW(14] 0 Bit13 | RW | RPDRLFQW(13] 0 Bit12 | RW | RPDRLFQW(12] 0 Bit 11 RW | RPDRLFQW[11] 0 Bit10 | RW | RPDRLFQW[10] 0 Bit 9 RW RPDRLFQW(9] 0 Bit 8 RW RPDRLFQW(8] 0 Bit 7 RW RPDRLFQW(7] 0 Bit 6 RW RPDRLFQW[6] 0 Bit 5 RW RPDRLFQWI5] 0 Bit 4 RW RPDRLFQW([4] 0 Bit 3 RW RPDRLFQW[3] 0 Bit 2 RW RPDRLFQW(2] 0 Bit 1 RW RPDRLFQW(1] 0 Bit 0 R/W RPDRLFQW(0] 0 This register provides the Packet Descriptor Reference Large Buffer Free Queue write address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 162roi fi as PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRLFQW[15:0]: The receive packet descriptor reference (RPDR) large buffer free queue write bits (RPDRLFQW/[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue write pointer. This register is initialised by the host. The physical write address in the RPDRLF queue is the sum of RPDRLFQW/[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 163r[\ fi ae PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2A0 : RMAC Packet Descriptor Reference Large Buffer Free Queue Read Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRLFOR[15] 0 Bit 14 R/W RPDRLFQR[14] 0 Bit 13 R/W RPDRLFQR[13] 0 Bit 12 R/W RPDRLFQR[12] 0 Bit 11 R/W RPDRLFQR[11] 0 Bit 10 R/W RPDRLFQR[10] 0 Bit 9 R/W RPDRLFORJ9] 0 Bit 8 R/W RPDRLFQRJ8] 0 Bit 7 R/W RPDRLFQR[7] 0 Bit 6 R/W RPDRLFOR{J6] 0 Bit 5 R/W RPDRLFQR[5] 0 Bit 4 R/W RPDRLFQR[4] 0 Bit 3 R/W RPDRLFQR[3] 0 Bit 2 R/W RPDRLFQR[2] 0 Bit 1 R/W RPDRLFOR[1] 0 Bit 0 R/W RPDRLFQR[O] 0 This register provides the Packet Descriptor Reference Large Buffer Free Queue read address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL. 164r 2 [\ fi co PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRLFQRI15:0]: The receive packet descriptor reference (RPDR) large buffer free queue read bits (RPDRLFQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue read pointer. This register is initialised by the host. The physical read address in the RPDRLF queue is the sum of RPDRLFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 165DATASHEET PMC-1990262 rly c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2A4 : RMAC Packet Descriptor Reference Large Buffer Free Queue End Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRLFQE[15] 0 Bit 14 R/W RPDRLFQE[14] 0 Bit 13 R/W RPDRLFQE[13] 0 Bit 12 R/W RPDRLFQE[12] 0 Bit 11 R/W RPDRLFQE[11] 0 Bit 10 R/W RPDRLFQE[10] 0 Bit 9 R/AW RPDRLFQE[9] 0 Bit 8 RAW RPDRLFQE[8} 0 Bit 7 R/W RPDRLFQE[7] 0 Bit 6 RAW RPDRLFQE[6] 0 Bit 5 R/W RPDRLFQE[5] 0 Bit 4 R/W RPDRLFQE[4] 0 Bit 3 R/W RPDRLFQE[3}] 0 Bit 2 R/W RPDRLFQE[2] 0 Bit 1 R/W RPDRLFQE[1] 0 Bit 0 R/W RPDRLFQE[O] 0 This register provides the Packet Descriptor Reference Large Buffer Free Queue end address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when ail four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 166i > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRLFQE[15:0]: The receive packet descriptor reference (RPDR) large buffer free queue end bits (RPDRLFQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Large Buffer Free Queue end address. This register is initialised by the host. The physical end address in the RPDRLF queue is the sum of RPDRLFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 167DATASHEET PMC-1990262 PMV c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2A8 : RMAC Packet Descriptor Reference Small Buffer Free Queue Start Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRSFQS[15] 0 Bit 14 R/W RPDRSFQS[14] 0 Bit 13 R/W RPDRSFQS[13] 0 Bit 12 R/W RPDRSFQS[12] 0 Bit 11 R/W RPDRSFQS[11] 0 Bit 10 R/W RPDRSFQS[10] 0 Bit 9 R/W RPDRSFQS[9] 0 Bit 8 R/W RPDRSFQSJ[8] 0 Bit 7 R/W RPDRSFQS[7] 0 Bit 6 R/W RPDRSFQSJ6] 0 Bit 5 R/W RPDRSFQS[5] 0 Bit 4 R/W RPDRSFQS[4] 0 Bit 3 R/W RPDRSFQS[3] 0 Bit 2 R/W RPDRSFQS[2] 0 Bit 1 R/V RPDRSFQS[1] 0 Bit O R/W RPDRSFQS[0] 0 This register provides the Packet Descriptor Reference Small Buffer Free Queue start address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 168r- [\ fi oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRSFQS[15:0]: The receive packet descriptor reference (RPDR) small! buffer free queue start bits (RPDRSFQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue start address. This register is initialised by the host. The physical start address of the RPDRSF queue is the sum of RPDRSFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 169r > [\ fi oy PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register Ox2AC : RMAC Packet Descriptor Reference Small Buffer Free Queue Write Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRSFQW[15] 0 Bit 14 R/W RPDRSFQW[14] 0 Bit 13 R/W RPDRSFQW[13] 0 Bit 12 R/W RPDRSFQW[12] 0 Bit 11 R/W RPDRSFQW[11] 0 Bit 10 R/W RPDRSFQW[10] 0 Bit 9 RAV RPDRSFQWI{9] 0 Bit 8 R/W RPDRSFQWJ8] 0 Bit 7 RW RPDRSFQW[7] 0 Bit 6 R/W RPDRSFQWIJ6] 0 Bit 5 R/W RPDRSFQW[5] 0 Bit 4 R/W RPDRSFQWJ[4] 0 Bit 3 R/W RPDRSFQWJ3] 0 Bit 2 R/W RPDRSFQW[2] 0 Bit 1 R/W RPDRSFQW[1] 0 Bit 0 R/W RPDRSFQW[0] 0 This register provides the Packet Descriptor Reference Small Buffer Free Queue write address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 170r- [\ /\ oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRSFQW/15:0]: The receive packet descriptor reference (RPDR) small buffer free queue write bits (RPDRSFQW([15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue write pointer. This register is initialised by the host. The physical write address in the RPDRSF queue is the sum of RPDRSFQW([15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 171l > [\ / c PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2B0 : RMAC Packet Descriptor Reference Small Buffer Free Queue Read Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRSFQR[15] 0 Bit 14 R/W RPDRSFQR[14] 0 Bit 13 R/W RPDRSFQR[13] 0 Bit 12 R/iW RPDRSFQR[12] ) Bit 11 R/W RPDRSFQR[11] 0 Bit 10 R/W RPDRSFQR/10] 0 Bit 9 R/W RPDRSFQR{9] 0 Bit 8 R/W RPDRSFQRI8] 0 Bit 7 R/IW RPDRSFQR[7] 0 Bit 6 R/W RPDRSFQRJ6] 0 Bit 5 R/W RPDRSFQR[5] 0 Bit 4 R/AW RPDRSFQRJ4] 0 Bit 3 R/AW RPDRSFQR[3] 0 Bit 2 R/W RPDRSFQR[2] 0 Bit 1 R/W RPDRSFQR[1] 0 Bit O R/W RPDRSFQR)(0] 0 This register provides the Packet Descriptor Reference Small Buffer Free Queue read address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 172r > [\ A c PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. RPDRSFQR/15:0]: The receive packet descriptor reference (RPDR) small buffer free queue read bits (RPDRSFQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue read pointer. This register is initialised by the host. The physical read address in the RPDRSF queue is the sum of RPDRSFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 173DATASHEET PMC-1990262 Pv Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2B4 : RMAC Packet Descriptor Reference Small Buffer Free Queue End Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRSFQE/[15] 0 Bit 14 R/W RPDRSFQE[14] 0 Bit 13 R/W RPDRSFQE[13] 0 Bit 12 R/W RPDRSFQE[12] 0 Bit 11 R/W RPDRSFQE[11] 0 Bit 10 R/W RPDRSFQE[10] 0 Bit 9 R/W RPDRSFQE[9] 0 Bit 8 R/W RPDRSFQE[8] 0 Bit 7 R/W RPDRSFQE[7] 0 Bit 6 R/W RPDRSFQE[6] 0 Bit 5 R/W RPDRSFQE{5] 0 Bit 4 R/W RPDRSFQE[4] 0 Bit 3 R/W RPDRSFQE[3] 0 Bit 2 R/W RPDRSFQE[2] 0 Bit 1 R/W RPDRSFQE[1] 0 Bit 0 R/W RPDRSFQE[0] 0 This register provides the Packet Descriptor Reference Small Buffer Free Queue end address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when ail four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 174r-[\ Y)| ae PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRSFQEI15:0]: The receive packet descriptor reference (RPDR) small buffer free queue end bits (RPDRSFQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Small Buffer Free Queue end address. This register is initialised by the host. The physical end address in the RPDRSF queue is the sum of RPDRSFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 175DATASHEET PMC-1990262 PV - PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2B8 : RMAC Packet Descriptor Reference Ready Queue Start Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRRQS[15] 0 Bit 14 R/W RPDRRQS[14] 0 Bit 13 R/W RPDRRQS[13] 0 Bit 12 R/W RPDRRQS[12] 0 Bit 11 R/W RPDRRQS[11] 0 Bit 10 R/W RPDRRQS[10] 0 Bit 9 R/W RPDRRQSJ[9] 0 Bit 8 R/W RPDRRQS{[8] 0 Bit 7 R/W RPDRRQS[7] 0 Bit 6 R/W RPDRRQS[6] 0 Bit 5 R/W RPDRRQS{[5] 0 Bit 4 R/W RPDRRQSJ[4] 0 Bit 3 RIW RPDRRQSJ3] 0 Bit 2 R/W RPDRRQS[2] 0 Bit 1 R/W RPDRRQS[1]J 0 Bit 0 R/W RPDRRQS[0] 0 This register provides the Packet Descriptor Reference Ready Queue start address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 176r- [\ / I PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRRQS/15:0]: The receive packet descriptor reference (RPDR) ready queue start bits (RPDRRQS[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue start address. This register is initialised by the host. The physical start address of the RPDRR queue is the sum of RPDRRQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 177DATASHEET PMC-1990262 ISSUE 4 ri fl as PMC-Sierra, Inc. PM7380 FREEDM-32P672 | FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2BC : RMAC Packet Descriptor Reference Ready Queue Write Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRRQW[15] 0 Bit 14 R/AW RPDRRQW([14] 0 Bit 13 R/W RPDRRQW([13] 0 Bit 12 R/W RPDRRQW([12] 0 Bit 11 R/W RPDRRQW([11] 0 Bit 10 R/W RPDRRQW/[10] 0 Bit 9 R/IW RPDRRQW([9] 0 Bit 8 R/W RPDRRQW/{[8] 0 Bit 7 R/W RPDRRQW/([7] 0 Bit 6 R/W RPDRRQWJ6] 0 Bit 5 R/W RPDRRQW/[5] 0 Bit 4 R/W RPDRRQW[4] 0 Bit 3 R/W RPDRRQW{[3] 0 Bit 2 R/W RPDRRQW|[2] 0 Bit 1 R/W RPDRRQW[1] 0 Bit 0 R/W RPDRRQW/(0} 0 This register provides the Packet Descriptor Reference Ready Queue write address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. PROPRIETARY AND CONFIDENTIAL 178i > [\ fi q PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET RS PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRRQW/[15:0]: The receive packet descriptor reference (RPDR) ready queue write bits (RPDRRQW([15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue write pointer. This register is initialised by the host. The physical write address in the RPDRR queue is the sum of RPDRRQW/[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 179DATASHEET PMC-1990262 ror /\ Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2C0 : RMAC Packet Descriptor Reference Ready Queue Read Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRRQR[15] 0 Bit 14 R/IW RPDRRQR[14] 0 Bit 13 R/W RPDRRQR[13] 0 Bit 12 R/W RPDRRQR[12] 0 Bit 11 R/W RPDRRQR[11] 9) Bit 10 R/W RPDRRQR[10] 0 Bit 9 R/W RPDRRQR[9] 0 Bit 8 R/W RPDRRQR[8] 0 Bit 7 R/W RPDRRQR[7] 0 Bit 6 R/W RPDRRQR{6] 0 Bit 5 R/W RPDRRQR{5] 0) Bit 4 R/W RPDRRQRI4] 0 Bit 3 R/W RPDRRQR{3] 0 Bit 2 R/W RPDRRQR[2] 0 Bit 1 R/W RPDRRQR[1] 0) Bit O RW RPDRRQR([O] 0 This register provides the Packet Descriptor Reference Ready Queue read address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. PROPRIETARY AND CONFIDENTIALr> [\ /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee eee es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRRQRI15:0]: The receive packet descriptor reference (RPDR) ready queue read bits (RPDRRQR[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue read pointer. This register is initialised by the host. The physical read address in the RPDRR queue is the sum of RPDRRQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 181DATASHEET PMC-1990262 r? [\ fA Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x2C4 : RMAC Packet Descriptor Reference Ready Queue End Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W RPDRRQE[15] 0 Bit 14 R/W RPDRRQE[14] 0 Bit 13 R/W RPDRRQE[13] 0 Bit 12 R/iW RPDRRQE[12] 0 Bit 11 R/W RPDRRQEJ11] 0 Bit 10 R/W RPDRRQE[10] 0 Bit 9 R/W RPDRRQE[9] 0 Bit 8 R/W RPDRRQE[8]} 0 Bit 7 R/W RPDRRQE[7] 0 Bit 6 RW RPDRRQE[6] 0 Bit 5 R/W RPDRRQE[5] 0 Bit 4 R/W RPDRRQE/[4] 0 Bit 3 R/W RPDRRQE{[3] 0 Bit 2 R/W RPDRRQE[2] 0 Bit 1 R/W RPDRRQE[1] 0 Bit 0 R/iW RPDRRQE/[0} 0 This register provides the Packet Descriptor Reference Ready Queue end address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when ail four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 182r-[\ / ae PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 RPDRRQE[15:0}: The receive packet descriptor reference (RPDR) ready queue end bits (RPDRRQE[15:0]) define bits 17 to 2 of the Receive Packet Descriptor Reference Ready Queue end address. This register is initialised by the host. The physical end address in the RPDRR queue is the sum of RPDRRQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL 183DATASHEET PMC-1990262 PV Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x300 : TMAC Control Bit Type Function Default Bit 31 Unused XXXXXXH to Bit 8 Bit 7 R/W FQFLUSH 0 Bit 6 R/W TDQ_FRN{1] 0 Bit 5 R/W TDQ_FRN{0] 0 Bit 4 R/W TDQ_RDYN[2] 0 Bit 3 R/W TDQ_RDYN[(1] 0 Bit 2 R/W TDQ_RDYN{(0] 0 Bit 1 R/W CACHE 1 Bit 0 R/W ENABLE 0 This register provides control of the TMAC672 block. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. ENABLE: The transmit DMA controller enable bit (ENABLE) enables the TMAC672 to accept TDRs from the TDR Ready Queue and reads packet data from host memory. When ENABLE is set high, the TMAC672 is enabled. When ENABLE is set low, the TDR Ready Queue is ignored. Once all linked lists of TDs built up by the TMAC672 have been exhausted, no more data will be transmitted on the TD[31:0] links. CACHE: The transmit descriptor reference cache enable bit (CACHE) controls the frequency at which TDRs are written to the TDR Free Queue. When CACHE is set high, freed TDRs are cached and then written up to six at a time. When CACHE is set low, freed TDRs are written one at a time. PROPRIETARY AND CONFIDENTIAL 184r > [\ Y,| PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDQ_RDYN/[2:0]: The TDQ_RDYN[2:0] field sets the number of transmit descriptor references (TDRs) that must be read from the TDR Ready Queue before the TDR Ready interrupt (TDQRDY]) is asserted, as follows: Table 22 - TDQ_RDYN[2:0] Settings TDQ_RDYN[2:0] No of TDRs 000 1 001 4 010 6 011 8 100 16 101 32 110 Reserved 111 Reserved TDQ_FRN{1:0]: The TDQ_FRN[1:0] field sets the number of times that a block of TDRs are written to the TDR Free Queue from the TMAC672s internal cache before the TDR Free Queue Interrupt (TDQFI) is asserted, as follows: Table 23 - TDQ_FRN[1:0] Settings TDQ_FRN[1:0] No of Reads 00 1 01 4 10 8 11 Reserved FQFLUSH: The Free Queue Flush bit (FQFLUSH) may be used to initiate a dump of the free queue cache retained locally within the TMAC672 to the free queue located in PCI host memory. When the FQFLUSH bit is set high, the TMAC672 dumps the contents of the free queue cache to the free queue in PCI host memory. The FQFLUSH bit is self clearing and will reset to zero when the flush is complete. Setting the FQFLUSH bit to zero has no affect. PROPRIETARY AND CONFIDENTIAL 185DATASHEET PMC-1990262 PMV C* PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x304 : TMAC Indirect Channel Provisioning Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY X Bit 14 R/W RWB 0 Bit 13 R/W PROV 0 Bit 12 Unused XH to Bit 10 Bit 9 R/W CHAN{[9] 0 Bit 8 R/W CHAN[8] 0 Bit 7 R/W CHAN[7] 0 Bit 6 R/W CHAN[6] 0 Bit 5 R/W CHAN[5] 0 Bit 4 R/W CHAN[4] 0 Bit 3 R/W CHAN[3] 0 Bit 2 R/W CHAN[2] 0 Bit 1 R/W CHAN[1] ) Bit 0 R/W CHAN([O] 0 The Channel Provisioning Register is used to provision and unprovision channels, and also to query the provision status of channels. When a channel is provisioned, chains of packet data for that channel will be accepted by the TMAC672 and placed on the channel's linked list of packets to be transmitted. When a channel is unprovisioned, chains of packet data for that channel will be rejected by the TMAC672 and returned to the TDR Free Queue with the status bits in the queue element set to indicate the rejection. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not PROPRIETARY AND CONFIDENTIAL 186r- [\ /I or PMC-Sierra, Inc. PM7380 FREEDM-32P672 ennai nen nannies PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET implemented. However, when all four byte enables are negated, no access is made to this register. CHAN/9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the TMAC672 internal memory after an indirect read operation has completed. Channel number to be written to the TMAC672 internal memory in an indirect write operation must be set up in this register before triggering the write. CHAN{[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the TMAC672 internal memory after an indirect read operation has completed. The provision enable flag to be written to the TMAC672 internal memory, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the channel as indicated by CHAN[9:0] is provisioned. When PROV is set low, the channel indicated by CHAN[9:0] is unprovisioned. PROV reflects the value written until the completion of a subsequent indirect read operation. RWB: The Read/Write Bar (RWB) bit selects between a provisioning/unprovisioning operation (write) or a query operation (read). Writing a logic 0 to RWB triggers the provisioning or unprovisioning of a channel as specified by CHAN[9:0] and PROV. Writing a logic 1 to RWB triggers a query of the channel specified by CHAN[9:0]. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 187DATASHEET PMC-1990262 ri / | Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x308 : TMAC Descriptor Table Base LSW Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDTB[15] 0 Bit 14 R/W TDTB[14] 0 Bit 13 R/W TDTB[13] 0 Bit 12 R/W TDTB[12] 0 Bit 11 R/W TDTB[11] 0 Bit 10 R/W TDTB[10] 0 Bit 9 R/W TDTB[9] 0 Bit 8 R/W TDTB[8] 0 Bit 7 R/W TDTB[7] 0 Bit 6 R/W TDTB[6] 0 Bit 5 R/W TDTB[5] 0 Bit 4 R/W TDTB[4] 0 Bit 3 R/W TDTB[3] 0 Bit 2 R/W TDTB[2] 0 Bit 1 R/W TDTB[1] 0 Bit 0 R/W TDTB[O] 0 This register provides the less significant word of the Transmit Descriptor Table Base address. The contents of this register is held in a holding register until a write access to the companion TMAC Transmit Descriptor Table Base MSW register. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 188DATASHEET PMC-1990262 r MVM Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x30C : TMAC Descriptor Table Base MSW Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDTB[31]} 0 Bit 14 R/W TDTB[30] 0 Bit 13 R/W TDTB[29] 0 Bit 12 R/W TDTB[28} 0 Bit 11 R/W TDTB[27] 0 Bit 10 R/W TDTB[26] 0 Bit 9 R/W TDTB[25] 0 Bit 8 R/W TDTB[24] 0 Bit 7 R/W TDTB[23] 0 Bit 6 R/W TDTB[22] 0 Bit 5 R/W TDTB[21] 0 Bit 4 R/W TDTB[20] 0 Bit 3 R/W TDTB[19] 0 Bit 2 R/W TDTB[18] 0 Bit 1 R/W TDTB[17] 0 Bit 0 R/W TDTB[16] 0 This register provides the more significant word of the Transmit Descriptor Table Base address. The contents of the companion TMAC Transmit Descriptor Table Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the transmit descriptor table is updated. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 189rN fi o PMC-Sierra, Inc. PM7380 FREEDM-32P672 a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET TDTBj31:0]: The transmit descriptor table base bits (TDTB[31:0]) provides the base address of the Transmit Descriptor Table in PC! host memory. This register is initialised by the host. To calculate the physical address of a TD, the 15 bit TD offset must be added to bits 31 to 4 of the Transmit Descriptor Table Base (TDTB[31:4]). The table must be on a 16 byte boundary and thus the least significant four bits must be written to logic zero. PROPRIETARY AND CONFIDENTIAL 190DATASHEET PMC-1990262 PV Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x310 : TMAC Queue Base LSW Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TQB[15] ) Bit 14 R/W TQB[14] 0 Bit 13 R/W TQB[13] 0 Bit 12 R/W TQB[12] 0 Bit 11 R/W TQB[11] 0 Bit 10 R/W TQB[10] 0 Bit 9 R/W TQB[9] 0 Bit 8 R/W TQB[8] 0 Bit 7 R/W TQB[7] 0 Bit 6 R/W TQB[6] 0 Bit 5 R/W TQB[5] 0 Bit 4 R/W TQB[4] 0 Bit 3 R/W TQB[3] 0 Bit 2 R/W TQB[2] 0 Bit 1 R/W TQB[1] 0 Bit 0 R/W TQB[0] 0 This register provides the less significant word of the Transmit Queue Base address. The contents of this register is held in a holding register until a write access to the companion TMAC Transmit Queue Base MSW register. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 197DATASHEET PMC-1990262 fr? [\ f\ C" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x314 : TMAC Queue Base MSW Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TQB[31] 0 Bit 14 R/W TQB[30] 0 Bit 13 R/W TQB[29] 0 Bit 12 R/W TQB[28] 0 Bit 11 R/W TQB[27] 0 Bit 10 R/W TQB[26] 0 Bit 9 R/W TQB[25] 0 Bit 8 R/W TQB[24] 0 Bit 7 RAV TQB[23] 0 Bit 6 R/W TQB[22] 0 Bit 5 R/W TQB[21] 0 Bit 4 R/W TQB[20] 0 Bit 3 R/W TQB[19] 0 Bit 2 R/W TQB[18] 0 Bit 1 R/W TQB[17] 0 Bit O R/W TQB[16] 0 This register provides the more significant word of the Transmit Queue Base address. The contents of the companion TMAC Transmit Descriptor Table Base LSW register is held in a holding register until a write access to this register, at which point, the base address of the transmit queue is updated. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 192i > [\ A c PMC-Sierra, inc. PM7380 FREEDM-32P672 ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET TQBJ3 1:0]: The transmit queue base bits (TQB[31:0]) provides the base address of the Transmit Descriptor Reference Free and Transmit Descriptor Reference Ready queue in PC! host memory. This register is initialised by the host. To calculate the physical address of a particular transmit queue element, the TQB bits are added with the appropriate queue start, end, read or write index registers to form the physical address. The base address must be dword aligned and thus the least significant two bits must be written to logic zero. PROPRIETARY AND CONFIDENTIAL 193DATASHEET PMC-1990262 r? [\ fA Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x318 : TMAC Descriptor Reference Free Queue Start Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDRFQS[15] 0 Bit 14 R/W TDRFQS[14] 0 Bit 13 R/W TDRFQS[13] 0 Bit 12 R/W TDRFQS[12} 0 Bit 11 R/W TDRFQS[11] 0 Bit 10 R/W TDRFQS[10] 0 Bit 9 R/W TDRFQSJ9] 0 Bit 8 R/W TDRFQS[8] 0 Bit 7 R/W TDRFQS[7] 0 Bit 6 R/W TDRFQSJ[6] 0 Bit 5 R/W TDRFQS[5] 0 Bit 4 R/W TDRFQSJ4] 0 Bit 3 R/W TDRFQS[3] 0 Bit 2 R/W TDRFQS[2] 0 Bit 1 R/W TDRFQS[1] 0 Bit O R/W TDRFQS[0] 0 This register provides the Transmit Descriptor Reference Free Queue start address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 194ri A PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDREQS/15:0]: The transmit packet descriptor reference (TDR) free queue start bits (TDRFQS[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue start address. This register is initialised by the host. The physical start address of the TDRF queue is the sum of TDRFQS[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 195DATASHEET PMC-1990262 ISSUE 4 r? I\ y/ de PMC-Sierra, Inc. PM7380 FREEDM-32P672 Dn FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x31C TMAC Descriptor Reference Free Queue Write Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDRFQW[15] 0 Bit 14 R/W TDRFQW[14] 0 Bit 13 R/W TDRFQW[13] 0 Bit 12 R/W TDRFQW[12] 0 Bit 11 R/W TDRFQW[11] 0 Bit 10 R/W TDRFQW/[10] 0 Bit 9 R/W TDRFQW{[9] 0 Bit 8 R/W TDRFQW{8] 0 Bit 7 R/W TDRFQW[7] 0 Bit 6 R/W TDRFQWJ[6] ) Bit 5 R/W TDRFQW[5] 0 Bit 4 R/W TDRFQW{4] 0 Bit 3 R/W TDRFQW{[3] 0 Bit 2 RW | TDRFQWI2] 0 Bit 1 R/W TDRFQW[1] 0 Bit O R/W TDRFQW/0] 0 This register provides the Transmit Descriptor Reference Free Queue write address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. PROPRIETARY AND CONFIDENTIAL. 196i > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDREQW[15:01]: The transmit packet descriptor reference (TPDR) free queue write bits (TDRFQW[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue write pointer. This register is initialised by the host. The physical write address in the TDRF queue is the sum of TDRFQW[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 197DATASHEET PMC-1990262 r- [\ | Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x320 : TMAC Descriptor Reference Free Queue Read Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDRFQR[15] 0 Bit 14 R/W TDRFQR[14] 0 Bit 13 R/W TDRFQR[13] 0 Bit 12 R/W TDRFQR[12] 0 Bit 14 R/W TDRFQR[11] 0 Bit 10 R/W TDRFQR[10] 0 Bit 9 R/W TDRFQR[9] 0 Bit 8 R/W TDRFQR[8] 0 Bit 7 R/W TDRFQR[7] 0 Bit 6 R/W TDRFQR[6] 0 Bit 5 R/W TDRFQR[5] 0 Bit 4 R/W TDRFQR[4] 0 Bit 3 R/W TDRFQR[3] 0 Bit 2 R/W TDRFQR[2] 0 Bit 1 R/W TDRFQR[1] 0 Bit 0 R/W TDRFQR[O] 0 This register provides the Transmit Descriptor Reference Free Queue read address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. PROPRIETARY AND CONFIDENTIAL 198rf\ fi ra PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDRFQRI15:0]: The transmit packet descriptor reference (TPDR) free queue read bits (TDRFQR[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue read pointer. This register is initialised by the host. The physical read address in the TDRF queue is the sum of TDRFQR[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 199DATASHEET PMC-1990262 PMC PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x324 : TMAC Descriptor Reference Free Queue End Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDRFQE[15] 0 Bit 14 R/W TDRFQE[14] 0 Bit 13 R/W TDRFQE[13] 0 Bit 12 R/W TDRFQE[12] 0 Bit 11 R/W TDRFQE[11] 0 Bit 10 R/W TDRFQE[10] 0 Bit 9 R/W TDRFQE[9] 0 Bit 8 R/W TDRFQE[8] 0 Bit 7 R/W TDRFQE[7] 0 Bit 6 R/W TDRFQE[6] 0 Bit 5 R/W TDRFQE[5] 0 Bit 4 R/W TDRFQE[4] 0 Bit 3 R/W TDRFQE[3] 0 Bit 2 R/W TDRFQE[2] 0 Bit 1 R/W TDRFQE[1] 0 Bit 0 R/W TDRFQE/[0] 0 This register provides the Transmit Descriptor Reference Free Queue end address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 200rf I PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDRFQE[15:0]: The transmit packet descriptor reference (TDR) free queue end bits (TDRFQE[15:0}) define bits 17 to 2 of the Transmit Packet Descriptor Reference Free Queue end address. This register is initialised by the host. The physical end address of the TDRF queue is the sum of TDRFQE[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 201DATASHEET PMC-1990262 rf f\ Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x328 :TMAC Descriptor Reference Ready Queue Start Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDRRQS[15] 0 Bit 14 R/W TDRRQS[14] 0 Bit 13 R/W TDRRQS[13] 0 Bit 12 R/W TDRRQS[12] 0 Bit 11 R/W TDRRQS[11] 0 Bit 10 R/W TDRRQS[10] 0 Bit 9 R/W TDRRQS[9] 0 Bit 8 R/W TDRRQS{[8] 0 Bit 7 R/W TDRRQS[7] 0 Bit 6 R/W TORRQS{(6] 0 Bit 5 R/W TDRRQSJ5] 0 Bit 4 R/W TDRRQS/4] 0 Bit 3 R/W TDRRQS{[3] 0 Bit 2 R/W TDRRQS[2] 0 Bit 1 R/W TDRRQS[1] 0 Bit 0 R/W TDRRQS[0] 0 This register provides the Transmit Descriptor Reference Ready Queue start address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when ail four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 202r I\ /\ oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDRRQS[15:0]: The transmit packet descriptor reference (TDR) ready queue start bits (TDRRQS[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue start address. This register is initialised by the host. The physical start address of the TDRF queue is the sum of TDRRQS[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 203DATASHEET PMC-1990262 PV Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x32C : TMAC Descriptor Reference Ready Queue Write Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDRRQW([15] 0 Bit 14 R/W TDRRQW[14] 0 Bit 13 R/W TDRRQW([13] 0 Bit 12 R/W TDRRQW([12] 0 Bit 11 R/W TDRRQW [11] 0 Bit 10 R/W TDRRQW([10] 0 Bit 9 R/W TDRRQW{[9] 0 Bit 8 R/W TDRRQW[8] 0 Bit 7 R/W TDRRQWI[7] 0 Bit 6 R/W TDRRQW/[6] 0 Bit 5 R/W TDRRQW/[5] 0 Bit 4 R/W TDRRQWI[4] 0 Bit 3 R/W TDRRQW[3] 0 Bit 2 R/W TDRRQW[2] 0 Bit 1 R/W TDRRQW([1] 0 Bit O R/W TDRROQW/(0] 0 This register provides the Transmit Descriptor Reference Ready Queue write address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. PROPRIETARY AND CONFIDENTIAL 204r-i\ fi oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDRRQW/[15:0]: The transmit packet descriptor reference (TPDR) ready queue write bits (TDRRQW([15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue write pointer. This register is initialised by the host. The physical write address in the TDRF queue is the sum of TDRRQW/[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 205DATASHEET PMC-1990262 PMC PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x330 : TMAC Descriptor Reference Ready Queue Read Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TDRRQR[15] 0 Bit 14 R/W TDRRQR[14] 0 Bit 13 R/AW TDRRQR[13] 0 Bit 12 R/W TDRRQR[12] 0 Bit 11 R/W TDRROR[11] 0 Bit 10 R/W TDRRQR[10] 0 Bit 9 R/W TDRRQRI[Y] 0 Bit 8 R/W TDRRQRI8] 0 Bit 7 R/W TDRRQR[7] 0 Bit 6 R/W TDRRQRJ6] 0 Bit 5 R/W TDRRQRI5] 0 Bit 4 R/W TDRROQR[4] 0 Bit 3 R/W TDRRQRJ3} 0 Bit 2 R/W TDRRQR[2] 0 Bit 1 R/W TDRRQR[1] 0 Bit 0 R/W TDRRQRJ[O] 0 This register provides the Transmit Descriptor Reference Ready Queue read address. Notes 1. This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. 2. If consecutive write accesses to this register are performed, they must be spaced at least 4 SYSCLK periods apart. PROPRIETARY AND CONFIDENTIAL 206i > [\ /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDRRQRI15:0]: The transmit packet descriptor reference (TPDR) ready queue read bits (TDRRQR[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue read pointer. This register is initialised by the host. The physical read address in the TDRF queue is the sum of TDRRQR[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 207DATASHEET PMC-1990262 ISSUE 4 r> [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee e renee cence eee eee neces FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x334 : TMAC Descriptor Reference Ready Queue End Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/iW TDRRQE[15] 0 Bit 14 R/W TDRRQE[14] 0 Bit 13 R/W TDRRQE[13] 0 Bit 12 R/W TDRRQE[12] 0 Bit 11 R/W TDRRQE[11] 0 Bit 10 R/W TDRRQE[10] 0 Bit 9 R/W TDRRQE[9] 0 Bit 8 R/W TDRRQE[8] 0 Bit 7 R/W TDRRQE[7] 0 Bit 6 R/W TDRRQE{[6] 0 Bit 5 R/W TDRRQE[5] 0 Bit 4 R/W TDRRQE[4] 0 Bit 3 R/W TDRRQE{[3] 0 Bit 2 R/W TDRRQE[2] 0 Bit 1 R/W TDRRQE[1] 0 Bit 0 R/W TDRRQE[0] 0 This register provides the Transmit Descriptor Reference Ready Queue end address. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0}) are not implemented. However, when ail four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 208PMV PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TDORRQE[15:0]: The transmit packet descriptor reference (TDR) ready queue end bits (TDRRQE[15:0]) define bits 17 to 2 of the Transmit Packet Descriptor Reference Ready Queue end address. This register is initialised by the host. The physical end address of the TDRF queue is the sum of TDRRQE[15:0] left shifted by 2 bits with the TQB[31:0] bits in the TMAC Transmit Queue Base register. PROPRIETARY AND CONFIDENTIAL 209DATASHEET PMC-1990262 r-lV Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x380 : THDL Indirect Channel Select Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY Bit 14 R/iW CRWB 0 Bit 13 Unused XH to Bit 10 Bit 9 R/W CHAN[9] 0 Bit 8 R/W CHAN{[8] 0 Bit 7 R/W CHAN[7] 0 Bit 6 R/W CHANI[6] 0 Bit 5 R/W CHANJ[5] 0 Bit 4 R/W CHAN[4] 0 Bit 3 R/W CHAN[3] 0 Bit 2 R/W CHAN[2] 0 Bit 1 RIW CHAN[1] 0 Bit 0 R/W CHAN[O] 0 This register provides the channel number used to access the transmit channel provision RAM. Writing to this register triggers an indirect channel register access. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHANJ9:0]: The indirect channel number bits (CHAN[9:0]) indicate the channel to be configured or interrogated in the indirect access. PROPRIETARY AND CONFIDENTIAL 210PV c PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET CRWB: The channel indirect access control bit (CRWB) selects between a configure (write) or interrogate (read) access to the channel provision RAM. Writing a logic zero to CRWB triggers an indirect write operation. Data to be written is taken from the Indirect Channel Data registers. Writing a logic one to CRWB triggers an indirect read operation. The data read can be found in the Indirect Channel! Data registers. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the THDL Indirect Channel Data #1, #2 and #3 registers or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 21DATASHEET PMC-1990262 PV C* PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x384 : THDL Indirect Channel Data #1 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W PROV 0 Bit 14 R/W CRC[1] 0 Bit 13 R/W CRC[O] 0 Bit 12 R/W DELIN 0 Bit 11 W Reserved X Bit 10 W FPTR[10] 0 Bit 9 Ww FPTR[9] 0 Bit 8 WwW FPTR[8] 0 Bit 7 WwW FPTR[7] 0 Bit 6 WwW FPTR[6] 0 Bit 5 WwW FPTR[5] 0 Bit 4 WwW FPTR[4] 0 Bit 3 WwW FPTR[3] 0 Bit 2 Ww FPTR[2] 0 Bit 1 Ww FPTR{1] 0 Bit 0 WwW FPTR[0] 0 This register contains data read from the channel provision RAM after an indirect channel read operation or data to be inserted into the channel provision RAM in an indirect channel write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEBJ[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 212r IVI Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FPTR[10:0]: The indirect FIFO block pointer (FPTR[10:0]) informs the partial packet buffer processor the circular linked list of blocks to use for a FIFO for the channel. The FIFO pointer to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. The FIFO pointer value can be any one of the block numbers provisioned, by indirect block write operations, to form the circular buffer. Reserved: The reserved bit must be set low for correct operation of the FREEDM- 32P672 device. DELIN: The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag sequence insertion and bit stuffing on the outgoing data stream. The delineate enable bit to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DELIN is set high, flag sequence insertion, bit stuffing and ,optionally, CRC generation is performed on the outgoing HDLC data stream. When DELIN is set low, the HDLC processor does not perform any processing (flag sequence insertion, bit stuffing nor CRC generation) on the outgoing stream. DELIN reflects the value written until the completion of a subsequent indirect channel read operation. CRC[1:0]: The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform CRC generation on the outgoing HDLC data stream. The value of CRC[1:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value written until the completion of a subsequent indirect channel read operation. Table 24 CRC[1:0] Settings CRC[1] CRC[O] Operation 0 0 No CRC 0 1 CRC-CCITT 1 0 CRC-32 1 1 Reserved PROPRIETARY AND CONFIDENTIAL 273r> [\ A PMC-Sierra, inc. PM7380 FREEDM-32P672 eee esses cree e eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from the channel provision RAM after an indirect channel read operation has completed. The provision enable flag to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When PROV is set high, the HDLC processor will service requests for data from the TCAS672 block. When PROV is set low, the HDLC processor will ignore requests from the TCAS672 block. PROV reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL 214DATASHEET PMC-1990262 rf /\ Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x388 : THDL Indirect Channel Data #2 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W 7BIT 0 Bit 14 R/W PRIORITYB 0 Bit 13 R/W INVERT 0 Bit 12 R/W DFCS 0 Bit 11 WwW Reserved 0 Bit 10 WwW FLEN[10] 0 Bit 9 WwW FLEN{9] 0 Bit 8 WwW FLEN[8] 0 Bit 7 Ww FLEN[7] 0 Bit 6 W FLEN[6] 0 Bit 5 WwW FLEN[5] 0 Bit 4 WwW FLEN[4] 0 Bit 3 W FLEN{3] 0 Bit 2 W FLEN[2] 0 Bit 1 W FLEN[1] 0 Bit O WwW FLEN(O] 0 This register contains data to be inserted into the channel provision RAM in an indirect write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 215i > [\ fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET as PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FLEN[10:0]: The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that is provisioned to the circular channel FIFO specified by the FPTR[10:0] block pointer. The FIFO length to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Reserved: The reserved bit must be set low for correct operation of the FREEDM- 32P672 device. DFCS: The diagnose frame check sequence bit (DFCS) controls the inversion of the FCS field inserted into the transmit packet. The value of DFCS to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When DFCS is set to one, the FCS field in the outgoing HDLC stream is logically inverted allowing diagnosis of downstream FCS verification logic. The outgoing FCS field is not inverted when DFCS is set to zero. DFCS reflects the value written until the completion of a subsequent indirect channel read operation. INVERT: The HDLC data inversion bit (INVERT) configures the HDLC processor to logically invert the outgoing HDLC stream. The value of INVERT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When INVERT is set to one, the outgoing HDLC stream is logically inverted. The outgoing HDLC stream is not inverted when INVERT is set to zero. INVERT reflects the value written until the completion of a subsequent indirect channel read operation. PRIORITYB: The active low channel FIFO starving enable bit (PRIORITYB) informs the partial packet processor of the priority of the channel relative to other channels when requesting data from the DMA port. The value of PRIORITYB to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. Channel FIFOs with PRIORITYB set to one are inhibited from making expedited requests for data to the TMAC672. When PRIORITYB is set to zero, both normal and expedited requests can be made to the TMAC672. Channels with HDLC data rate to FIFO size ratio that is significantly lower than other channels should have PRIORITYB set to one. PRIORITYB reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL 216r> [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ey PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 7BIT: The least significant stuff enable bit (7BIT) configures the HDLC processor to stuff the least significant bit of each octet in the corresponding transmit link (TD[n]). The value of 7BIT to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When 7BIT is set high, the least significant bit (last bit of each octet transmitted) does not contain channel data and is forced to the value configured by the BIT8 register bit. When 7BIT is set low, the entire octet contains valid data and BIT8 is ignored. 7BIT reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL 217DATASHEET PMC-1990262 r [\ fA Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x38C : THDL Indirect Channel! Data #3 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W TRANS 0 Bit 14 R/W IDLE 0 Bit 13 Unused Xx Bit 12 Unused xX Bit 11 R/W LEVEL[3] 0 Bit 10 R/W LEVEL[2] 0 Bit 9 R/W LEVEL[1] 0 Bit 8 R/W LEVEL[0]} 0 Bit 7 R/W FLAG[2] 0 Bit 6 R/W FLAG[1] 0 Bit 5 R/W FLAG[O] 0 Bit 4 Unused x Bit 3 R/W XFER{[3] 0 Bit 2 R/W XFER[2] 0 Bit 1 R/IW XFER[1] 0 Bit 0 R/V XFER[0] 0 This register contains data read from the channel provision RAM after an indirect read operation or data to be inserted into the channel provision RAM in an indirect write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 218r? [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 XFERJ3:0]: The indirect channel transfer size (XFER[3:0]) specifies the amount of data the partial packet processor requests from the TMAC672 block. The channel transfer size to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. When the channel FIFO free space reaches or exceeds the limit specified by XFER[3:0], the partial packet processor will make a request for data to the TMAC672 to retrieve the XFER[3:0] + 1 blocks of data. FIFO free space and transfer size are measured in the number of 16-byte blocks. XFER[3:0] reflects the value written until the completion of a subsequent indirect channel read operation. To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set, such that, the total number of blocks in the logical channel FIFO minus the start transmission level is an integer multiple of the channel transfer size. The case of a single block transfer size is a special. When BURSTEN is set high and XFERJ[3:0] = 'b0000, the transfer size is variable. The THDL672 will request the TMAC672 to transfer as much data as there is free space in the FIFO, up to a maximum set by BURST[3:0]. FLAG[2:0]: The flag insertion control (FLAG[2:0]) configures the minimum number of flags or bytes of idle bits the HDLC processor inserts between HDLC packets. The value of FLAG[2:0] to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. The minimum number of flags or bytes of idle (8 bits of 1's) inserted between HDLC packets is shown in the table below. FLAG[2:0] reflects the value written until the completion of a subsequent indirect channel read operation. Table 25 FLAG[2:0] Settings FLAG[2:0] | Minimum Number of Flag/Idle Bytes 000 1 flag / O Idle byte 001 2 flags / 0 idle byte 010 4 flags / 2 idle bytes 011 8 flags / 6 idle bytes 100 16 flags / 14 idle bytes PROPRIETARY AND CONFIDENTIAL 219[ 2 [\ y/ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET |) PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FLAG[2:0] | Minimum Number of Flag/Idie Bytes 101 32 flags / 30 idle bytes 110 64 flags / 62 idle bytes 111 128 flags / 126 idle bytes LEVEL[3:0]: The indirect channel FIFO trigger level (LEVEL[3:0]), in concert with the TRANS bit, configure the various channel FIFO free space levels which trigger the HDLC processor to start transmission of a HDLC packet as well as trigger the partial packet buffer to make DMA request for data as shown in the following table. The channel FIFO trigger level to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. LEVEL[3:0] reflects the value written until the completion of a subsequent indirect channel read operation. The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is greater than or equal to the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedite requests to the TMAC672 to retrieve XFER[3:0] + 71 blocks of data. To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set such that the total number of blocks in the logical channel FIFO, minus the start transmission level, is an integer multiple of the channel transfer size. The starving trigger level must always be set to a number of blocks greater than or equal to the channel transfer size. IDLE: The interframe time fill bit (IDLE) configures the HDLC processor to use flag bytes or HDLC idle as the interframe time fill between HDLC packets. The value of IDLE to be written to the channel provision RAM, in an indirect channel write operation, must be set up in this register before triggering the write. When IDLE is set low, the HDLC processor uses flag bytes as the interframe time fill. When IDLE is set high, the HDLC processor uses HDLC idle (all one's bit with no bit-stuffing pattern is transmitted) as the interframe time fill. IDLE reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL 220DATASHEET PMC-1990262 r-\ /| c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 TRANS: The indirect transmission start bit (TRANS), in concert with the LEVEL[3:0] bits, configure the various channel FIFO free space levels which trigger the HDLC processor to start transmission of a HDLC packet as well as trigger the partial packet buffer to make DMA request for data as shown in the following table. The transmission start mode to be written to the channel provision RAM, in an indirect write operation, must be set up in this register before triggering the write. TRANS reflects the value written until the completion of a subsequent indirect channel read operation. The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is greater than or equal to the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedite requests to the TMAC672 to retrieve XFER[3:0] + 1 blocks of data. To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set, such that, the total number of blocks in the logical channel FIFO minus the start transmission level is an integer multiple of the channel transfer size. The starving trigger level must always be set to a number of blocks greater than or equal to the channel transfer size. Tabie 26 Level[3:0]/TRANS Settings LEVEL[3:0] Starving Start Start Transmission Trigger Level Transmission Level (TRANS=1) Level (TRANS=0) 0000 2 Blocks 1 Block 1 Block (32 bytes free) (16 bytes free) (16 bytes free) 0001 3 Blocks 2 Blocks 1 Block (48 bytes free) (32 bytes free) (16 bytes free) 0010 4 Blocks 3 Blocks 2 Blocks (64 bytes free) (48 bytes free) (32 bytes free) 0011 6 Blocks 4 Blocks 3 Blocks (96 bytes free) (64 bytes free) (48 bytes free) 0100 8 Blocks 6 Blocks 4 Blocks (128 bytes free) (96 bytes free) (64 bytes free) PROPRIETARY AND CONFIDENTIAL 221DATASHEET PMC-1990262 PV Cc" PMC-Sierra, Inc. ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PM7380 FREEDM-32P672 LEVEL[3:0] Starving Start Start Transmission Trigger Level Transmission Level (TRANS=1) Level (TRANS=0) 0101 12 Blocks 8 Blocks 6 Blocks (192 bytes free) (128 bytes free) (96 bytes free) 0110 16 Blocks 12 Blocks 8 Blocks (256 bytes free) (192 bytes free) (128 bytes free) 0111 24 Blocks 16 Blocks 12 Blocks (384 bytes free) (256 bytes free) (192 bytes free) 1000 32 Blocks 24 Blocks 16 Blocks (512 bytes free) (384 bytes free) (256 bytes free) 1001 48 Blocks 32 Blocks 24 Blocks (768 bytes free) (512 bytes free) (384 bytes free) 1010 64 Blocks 48 Blocks 32 Blocks (1 Kbytes free) (768 bytes free) (512 bytes free) 1011 96 Blocks 64 Blocks 48 Blocks (1.5 Kbytes free) (1 Kbytes free) (768 bytes free) 1100 192 Blocks 128 Blocks 96 Blocks (3 Kbytes free) (2 Kbytes free) (1.5 Kbytes free) 1104 384 Blocks 256 Blocks 192 Blocks (6 Kbytes free) (4 Kbytes free) (2 Kbytes free) 1110 768 Blocks 512 Blocks 384 Blocks (12 Kbytes free) (8 Kbytes free) (4 Kbytes free) 1111 1536 Blocks 1024 Blocks 768 Blocks (24 Kbytes free) (16 Kbytes free) (8 Kbytes free) PROPRIETARY AND CONFIDENTIAL 222DATASHEET PMC-1990262 rv Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x3A0 : THDL Indirect Block Select Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY Bit 14 R/W BRWB 0 Bit 13 Unused XH to Bit 12 Bit 11 R/W Reserved X Bit 10 R/W BLOCK[10] 0 Bit 9 R/W BLOCK[9] 0 Bit 8 R/W BLOCK[8] 0 Bit 7 R/W BLOCK[7] 0 Bit 6 R/W BLOCK[6] 0 Bit 5 R/W BLOCK[5] 0 Bit 4 R/W BLOCk[4] 0 Bit 3 R/W BLOCK{3] 0 Bit 2 R/W BLOCK[2] 0 Bit 1 R/W BLOCK[1] 0 Bit 0 R/W BLOCK[O] 0 This register provides the block number used to access the block pointer RAM. Writing to this register triggers an indirect block register access. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEBJ3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 223i > [\ /\ cf PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 BLOCK[10:0]: The indirect block number (BLOCK[10:0]) indicate the block to be configured or interrogated in the indirect access. Reserved: The reserved bit must be set low for correct operation of the FREEDM- 32P672 device. BRWB: The block indirect access control bit (BRWB) selects between a configure (write) or interrogate (read) access to the block pointer RAM. Writing a logic zero to BRWB triggers an indirect block write operation. Data to be written is taken from the Indirect Block Data register. Writing a logic one to BRWB triggers an indirect block read operation. The data read can be found in the Indirect Block Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the THDL Indirect Block Data register or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 224DATASHEET PMC-1990262 PMV c* PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x3A4 : THDL Indirect Block Data Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W Reserved 0 Bit 14 Unused XH to Bit 12 Bit 11 R/W Reserved X Bit 10 R/W BPTR[10] 0 Bit 9 R/W BPTR{9] 0 Bit 8 R/W BPTR{[8] 0 Bit 7 R/W BPTR[7] 0 Bit 6 R/W BPTR[6] 0 Bit 5 R/W BPTR[5] 0 Bit 4 R/W BPTR[4] 0 Bit 3 RIW BPTRI[3] 0 Bit 2 R/W BPTR[2] 0 Bit 1 R/W BPTR[1] 0 Bit O R/W BPTR[O] 0 This register contains data read from the transmit block pointer RAM after an indirect block read operation or data to be inserted into the transmit block pointer RAM in an indirect block write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIALr> [\ Y)| PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET se nce ee cee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 BPTR[10:0]: The indirect block pointer (BPTR[10:0]) configures the block pointer of the block specified by the Indirect Block Select register. The block pointer to be written to the transmit block pointer RAM, in an indirect write operation, must be set up in this register before triggering the write. The block pointer value is the block number of the next block in the linked list. A circular list of blocks must be formed in order to use the block list as a channel FIFO buffer. FPTR[10:0] reflects the value written until the completion of a subsequent indirect block read operation. When provisioning a channel FIFO, all blocks pointers must be re-written to properly initialize the FIFO. Reserved: The reserved bits must be set low for correct operation of the FREEDM- 32P672 device. PROPRIETARY AND CONFIDENTIAL 226DATASHEET PMC-1990262 Pv c PMC-Sierra, inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x3B0 : THDL Configuration Bit Type Function Default Bit 31 Unused XXXXXXH to Bit 10 Bit 9 R/W BIT8 0 Bit 8 R/W TSTD 0 Bit 7 R/W BURSTEN 0 Bit 6 Unused X Bit 5 Unused Xx Bit 4 Unused X Bit 3 R/W BURST[3] 0 Bit 2 R/W BURST[2] 0 Bit 1 R/W BURST[1] 0 Bit O R/W BURST(0] 0 This register configures all provisioned channels. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. BURST{[3:0]: The DMA burst length bits (BURST[3:0]) configure the maximum amount of transmit data that can be requested in a single DMA transaction for channels whose channel transfer size is set to one block (XFER[3:0] = 'b0000). BURST[3:0] has no effect when BURSTEN is set low, nor on channels configured with other transfer sizes. BURST[3:0] defines the maximum number of 16 byte blocks, less one, that is transferred in each DMA transaction. Thus, the minimum number of blocks is one (16 bytes) and the maximum is sixteen (256 bytes). PROPRIETARY AND CONFIDENTIAL 227r > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 BURSTEN: The burst length enable bit (BURSTEN) controls the use of BURST[3:0] in determining the amount of data requested in a single DMA transaction for channels whose channel transfer size is set to one block (XFER[3:0] = b0000). BURSTEN has no effect on channels configured with other transfer sizes. When BURSTEN is set high, the maximum size of DMA transfer is limited by BURST[3:0]. The transmit HDLC processor may combine several channel transfer size amounts into a single transaction. When BURSTEN is set low, the amount of data in a DMA transfer is limited to one block. TSTD: The telecom standard bit (TSTD) controls the bit ordering of the HDLC data transferred from the PCI host. When TSTD is set low, the least significant bit of the each byte on the PCI bus (AD[0], AD[8], AD[16] and AD[24)) is the first HDLC bit transmitted and the most significant bit of each byte (AD[7], AD[15}, AD[23] and AD[31]) is the last HDLC bit transmitted (datacom standard). When TSTD is set high, AD[0], AD[8], AD[16] and AD[24] are the last HDLC bit transmitted and AD[7], AD[15], AD[23] and AD[31] are the first HDLC bit transmitted (telecom standard). BIT8: The least significant stuff control bit (BIT8) carries the value placed in the least significant bit of each octet when the HDLC processor is configured (7BIT set high) to stuff the least significant bit of each octet in the corresponding transmit link (TD[n]). When BIT8 is set high, the least significant bit (last bit of each octet transmitted) is forced high. When BIT8 is set low, the least significant bit is forced low. BIT8 is ignored when 7BIT is set low. PROPRIETARY AND CONFIDENTIAL 228DATASHEET PMC-1990262 r- iV Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x400 : TCAS Indirect Link and Time-slot Select Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R BUSY X Bit 14 R/W RWB 0 Bit 13 Unused xX Bit 12 R/W Reserved 0 Bit 11 R/W Reserved 0 Bit 10 R/W LINK[4] 0 Bit 9 R/W LINK[3] 0 Bit 8 R/W LINK[2] 0 Bit 7 R/W LINK[1] 0 Bit 6 R/W LINK[0] 0 Bit 5 Unused xX Bit 4 R/W TSLOT{4] 0 Bit 3 R/W TSLOT[3] 0 Bit 2 R/W TSLOT{2] 0 Bit 1 R/W TSLOT[1] 0 Bit O R/W TSLOT[O] 0 This register provides the link number and time-slot number used to access the transmit channel provision RAM. Writing to this register triggers an indirect register access and transfers the contents of the Indirect Channel Data register to an internal holding register. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 229r- [\ fT Y PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET Se PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 TSLOT[4:01: The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or interrogated in the indirect access. For a channelised T1/J1 link, time-slots 1 to 24 are valid. For a channelised E71 link, time-slots 1 to 31 are valid. For a H-MVIP link, time-slots 0 to 31 are valid. For unchannelised links, only time-slot 0 is valid. LINK{4:0}: The indirect link number bits (LINK[4:0]) select amongst the 32 transmit links to be configured or interrogated in the indirect access. Reserved: The reserved bits must be set low for correct operation of the FREEDM- 32P672 device. RWB: The indirect access control bit (RWB) selects between a configure (write) or interrogate (read) access to the transmit channel provision RAM. The address to the transmit channel provision RAM is constructed by concatenating the TSLOT[4:0] and LINK[4:0] bits. Writing a logic zero to RWB triggers an indirect write operation. Data to be written is taken from the PROV and the CHAN[9:0] bits of the Indirect Data register. Writing a logic one to RWB triggers an indirect read operation. Addressing of the RAM is the same as in an indirect write operation. The data read can be found in the PROV and the CHAN[9:0] bits of the Indirect Channel Data register. BUSY: The indirect access status bit (BUSY) reports the progress of an indirect access. BUSY is set high when this register is written to trigger an indirect access, and will stay high until the access is complete. At which point, BUSY will be set low. This register should be polled to determine when data from an indirect read operation is available in the TCAS Indirect Channel Data register or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL 230DATASHEET PMC-1990262 PVG eucsiera ine ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x404 : TCAS Indirect Channel Data Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W PROV 0 Bit 14 Unused XXH to Bit 10 Bit 9 R/W CHAN[9] 0 Bit 8 R/W CHAN([8} 0 Bit 7 R/W CHAN[7] 0 Bit 6 R/W CHAN[6] 0 Bit 5 R/W CHAN[5] 0 Bit 4 R/W CHAN[4] 0 Bit 3 R/AW CHAN[3] 0 Bit 2 R/W CHAN[2] 0 Bit 1 R/W CHAN|1] 0 Bit 0 R/W CHAN[0] 0 This register contains the data read from the transmit channel provision RAM after an indirect read operation or the data to be inserted into the transmit channel provision RAM in an indirect write operation. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. CHAN[9:0]: The indirect data bits (CHAN[9:0]) report the channel number read from the transmit channel provision RAM after an indirect read operation has completed. Channel number to be written to the transmit channel provision RAM in an indirect write operation must be set up in this register before PROPRIETARY AND CONFIDENTIAL 231r[\ I PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 triggering the write. CHAN[9:0] reflects the value written until the completion of a subsequent indirect read operation. PROV: The indirect provision enable bit (PROV) reports the channel provision enable flag read from transmit channel provision RAM after an indirect read operation has completed. The provision enable flag to be written to the transmit channel provision RAM in an indirect write operation must be set up in this register before triggering the write. When PROV is set high, the current time-slot is assigned to the channel as indicated by CHAN[9:0]. When PROV is set low, the time-slot does not belong to any channel. The transmit link data is set to the contents of the Idle Time-slot Fill Data register. PROV reflects the value written until the completion of a subsequent indirect read operation. PROPRIETARY AND CONFIDENTIAL 232r- [\ /| Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET OE | PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x408 : TCAS Framing Bit Threshold Bit Type Function Default Bit 31 Unused XXXXXXXH to Bit 7 Bit 6 RAV FTHRES|6] 0 | Bit 5 R/W FTHRES[5] 1 Bit 4 R/W FTHRES[4] 0 Bit 3 R/W FTHRES[3] 0 Bit 2 R/W FTHRES[2] 1 Bit 1 R/W FTHRES[1] 0 Bit 0 R/W FTHRES[0] 1 This register contains the threshold used by the clock activity monitors to detect for framing bits/bytes. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. FTHRESJ6:0]: The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by the clock activity monitor to detect for the presence of framing bits. A counter in the clock activity monitor of each receive link increments on each rising edge of SYSCLK and is cleared, when the BSYNC bit of that link is set low, by each rising edge of the corresponding TCLK[n]. When the BSYNC bit of that link is set high, the counter is cleared at every fourth rising edge of the corresponding TCLK[n]. When the counter exceeds the threshold given by FTHRES[6:0], a framing bit/byte has been detected. FTHRESJ6:0] should be set as a function of the SYSCLK period and the expected gapping width of TCLK[n] during data bits and during framing bits/bytes. Legal range of FTHRESJ[6:0] is 'b0000001 to 'b1111110. PROPRIETARY AND CONFIDENTIAL 233r- [\ fi Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ND PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Note: For operation with T1/J1 links and SYSCLK = 45 MHz, FTHRESH{[6:0] should be set to b0100101. The default value of this register reflects this mode of operation. PROPRIETARY AND CONFIDENTIAL 234DATASHEET PMC-1990262 PMC PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x40C : TCAS Idle Time-slot Fill Data Bit Type Function Default Bit 31 Unused XXXXXXH to Bit 8 Bit 7 R/W FDATA[7] 1 Bit 6 R/W FDATA[6] 1 Bit 5 R/W FDATA[5] 1 Bit 4 R/W FDATA[4] 1 Bit 3 R/W FDATA[3] 1 Bit 2 R/W FDATA[2] 1 Bit 1 R/W FDATA([1] 1 Bit 0 R/W FDATA(O] 1 This register contains the data to be written to disabled time-slots of a channelised link. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when ail four byte enables are negated, no access is made to this register. FDATAI7:0]: The fill data bits (FDATA[7:0]) are transmitted during disabled (PROV set low) time-slots of channelised links. PROPRIETARY AND CONFIDENTIAL 235DATASHEET PMC-1990262 PV Cc" PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x410 : TCAS Channel Disable Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R/W CHDIS 0 Bit 14 Unused XXH to Bit 10 Bit 9 R/W DCHANI[9] 0 Bit 8 R/W DCHANJ[8}] 0 Bit 7 R/W DCHAN[7] 0 Bit 6 R/W DCHANJ[6] 0 Bit 5 R/W DCHANJ[5] 0 Bit 4 R/W DCHAN[4] 0 Bit 3 R/W DCHAN{[3] 0 Bit 2 R/W DCHAN[2] 0 Bit 1 R/W DCHAN[1] 0 Bit O R/W DCHAN[0] 0 This register controls the disabling of one specific channel to allow orderly provisioning of time-slots. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. DCHANJ9:0]: The disable channel number bits (DCHAN[9:0]) selects the channel to be disabled. When CHDIS is set high, the channel specified by DCHAN{9:0] is disabled. Data in time-slots associated with the specified channel is set to FDATA|7:0] in the Idle Time-slot Fill Data register. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally. PROPRIETARY AND CONFIDENTIAL 236i > [\ fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 CHDIS: The channel disable bit (CHDIS) controls the disabling of the channels specified by DCHAN[9:0]. When CHDIS is set high, the channel selected by DCHAN{9:0] is disabled. Data in time-slots associated with the specified channel is set to FDATA[7:0] in the Idle Time-slot Fill Data register. When CHDIS is set low, the channel specified by DCHAN[9:0] operates normally. PROPRIETARY AND CONFIDENTIAL 237i > [\ /\ oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x480 0x488 : TCAS Links #0 to #2 Configuration Bit Type Function Default Bit 31 Unused XXXXXXXH to Bit 5 Bit 4 R/W BSYNC 0 Bit 3 Unused Xx Bit 2 R/W MODE[2] 0 Bit 1 R/W MODE[1] 0 Bit O R/W MODE/[O] 0 This register configures operational modes of transmit links #0 to #2. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. MODE[2:0]: The mode select bits (MODE[2:0]) configures the corresponding transmit link. Table 27 details this procedure. When link 4m (O<ms7) is configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 are driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation of the TCAS672. From a channel assignment point of view in the TCAS672 (Registers 0x100, 0x104), time-slots 0 through 31 of link 4m are mapped to time-slots 0 through 31 of the H-MVIP fink, time-slots 0 through 31 of link 4m+1 are mapped to time-slots 32 through 63 of the H-MVIP link, time-slots 0 through 31 of link 4m+2 are mapped to time-slots 64 through 95 of the H- MVIP link and time-slots 0 through 31 of link 4m+3 are mapped to time-siots 96 through 127 of the H-MVIP link. PROPRIETARY AND CONFIDENTIAL 238DATASHEET PMC-1990262 r- [\ v/ o PMC-Sierra, Inc. PM7380 FREEDM-32P672 as ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 27 - Transmit Links #0 to #2 Configuration MODE[2:0] | Link Configuration 000 Unchannelised 001 Channelised T1/J1 (24 time slots labeled 1-24) 010 Channelised E1 (31 time slots labeled 1-31) 011 2 Mbps H-MVIP (32 time slots labeled 0-31) 100 Reserved 101 Reserved 110 Reserved 111 8 Mbps H-MVIP (128 time slots mapped to time- slots 0 through 31 of links 4m, 4m+1, 4m+2 and 4m+3) BSYNC: The byte synchronization enable bit (BSYNC) controls the interpretation of gaps in TCLK[n] when link #n is in unchannelised mode (MODE[2:0] When BSYNC is set high, the data bit on TD[n] clocked in by a downstream device on the first rising edge of TCLK[n] after an extended quiescent period is considered to be the most significant bit of a data byte. When BSYNC is set quiescent, gaps in TCLK[n] carry no special significance. BSYNC is ignored when MODE[2:0]#000. PROPRIETARY AND CONFIDENTIAL 239i [\ Mi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee eee rere eee eee cee eee eee es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x48C Ox4FC : TCAS Links #3 to #31 Configuration Bit Type Function Default Bit 31 Unused XXXXXXXXH to Bit 3 Bit 2 RW MODE[2] oC Bit 1 R/W MODE[1] Bit 0 R/W MODE/[0] 0 This register configures operational modes of transmit links #3 to #31. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. MODE[2:0]: The mode select bits (MODE[2:0]) configures the corresponding transmit link. Table 28 details this procedure. When link 4m (Osms7) is configured for operation in 8.192 Mbps H-MVIP mode, links 4m+1, 4m+2 and 4m+3 are driven with constant ones. However, links 4m+1, 4m+2 and 4m+3 must be configured for 8.192 Mbps H-MVIP mode for correct operation of the TCAS672. From a channel assignment point of view in the TCAS672 (Registers 0x400, 0x404), time-slots 0 through 374 of link 4m are mapped to time-slots 0 through 31 of the H-MVIP link, time-slots 0 through 31 of link 4m+1 are mapped to time-slots 32 through 63 of the H-MVIP link, time-slots 0 through 31 of link 4m+2 are mapped to time-slots 64 through 95 of the H- MVIP link and time-slots 0 through 31 of link 4m+3 are mapped to time-slots 96 through 127 of the H-MVIP link. PROPRIETARY AND CONFIDENTIAL 240r oT /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET as PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 28 - Transmit Links #3 to #31 Configuration MODE[2:0] | Link Configuration 000 Unchannelised 001 Channelised T1/J1 (24 time slots labeled 1-24) 010 Channelised E1 (31 time slots labeled 1-31) 011 2 Mbps H-MVIP (32 time slots labeled 0-31) 100 Reserved 101 Reserved 110 Reserved 111 8 Mbps H-MVIP (128 time slots mapped to time- slots 0 through 31 of links 4m, 4m+1, 4m+2 and 4m+3) PROPRIETARY AND CONFIDENTIAL 241DATASHEET PMC-1990262 ISSUE 4 r> [\ fi ot PMC-Sierra, Inc. PM7380 FREEDM-32P672 a FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x500 : PMON Status Bit Type | Function Default Bit 31 Unused XXXXXXXH to Bit 6 Bit 5 R C2DET X Bit 4 R C1DET x Bit 3 R UFDET X Bit 2 R OFDET X Bit 1 Unused X Bit 0 Unused xX This register contains status information indicating whether a non-zero count has been latched in the count registers. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. OFDET: The overflow detect bit (OFDET) indicates the status of the PMON Receive FIFO Overflow Count register. OFDET is set high when overflow events have occurred during the latest PMON accumulation interval. OFDET is set low if no overflow events are detected. UFDET: The underflow detect bit (UFDET) indicates the status of the PMON Transmit FIFO Underflow Count register. UFDET is set high when underflow events have occurred during the latest PMON accumulation interval. UFDET is set low if no underflow events are detected. C1DET: The configurable event #1 detect bit (C1DET) indicates the status of the PMON Configurable Count #1 register. C1DET is set high when selected PROPRIETARY AND CONFIDENTIAL 242i > [\ Y)| as PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET events have occurred during the latest PMON accumulation interval. C1DET is set low if no selected events are detected. C2DET: The configurable event #2 detect bit (C2DET) indicates the status of the PMON Configurable Count #2 register. C2DET is set high when selected events have occurred during the latest PMON accumulation interval. C2DET is set low if no selected events are detected. PROPRIETARY AND CONFIDENTIAL 243DATASHEET PMC-1990262 ISSUE 4 r? [\ fl c* PMC-Sierra, Inc. PM7380 FREEDM-32P672 a FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x504 : PMON Receive FIFO Overflow Count Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R OF[15] X Bit 14 R OF[14] X Bit 13 R OF[13] X Bit 12 R OF[12] Xx Bit 11 R OF[11] X Bit 10 R OF[10] X Bit 9 R OF[9] Xx Bit 8 R OF[8] Xx Bit 7 R OF[7] X Bit 6 R OF[6] X Bit 5 R OF[5] X Bit 4 R OF[4] X Bit 3 R OF[3] X Bit 2 R OF[2] X Bit 1 R OF[1] X Bit 0 R OF[0O] X This register reports the number of receive FIFO overflow events in the previous accumulation interval. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 244r > [\ fi PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 OF[15:0]: The OF[15:0] bits reports the number of receive FIFO overflow events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-32P672 Master Clock / BERT Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the FIFO overflow register and simultaneously resets the internal counter to begin a new cycle of error accumulation. PROPRIETARY AND CONFIDENTIAL 245DATASHEET PMC-1990262 ISSUE 4 [ Mi en PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x508 : PMON Transmit FIFO Underflow Count Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R UF[15] X Bit 14 R UF[14] X Bit 13 R UF[13] X Bit 12 R UF[12] X Bit 11 R UF[11] X Bit 10 R UF[10] X Bit 9 R UF[9] X Bit 8 R UF[8} X Bit 7 R UF[7] Xx Bit 6 R UF[6] X Bit 5 R UF[5} X Bit 4 R UF[4] X Bit 3 R UF[3]} X Bit 2 R UF[2] X Bit 1 R UF[1] X Bit O R UF[0] X This register reports the number of transmit FIFO underflow events in the previous accumulation interval. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 246r- [\ /\ Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ETT PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 UF[15:0}: The UF[15:0] bits reports the number of transmit FIFO underflow events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-32P672 Master Clock / BERT Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the FIFO underflow register and simultaneously resets the internal counter to begin a new cycle of error accumulation. PROPRIETARY AND CONFIDENTIAL 247DATASHEET PMC-1990262 ISSUE 4 r? [\ /\ ae PMC-Sierra, Inc. PM7380 FREEDM-32P672 Ceeeeee ee eee eee ee eee aS FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x50C : PMON Configurable Count #1 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R C1[15] Xx Bit 14 R C1[14] x Bit 13 R C1[13] x Bit 12 R C1[12] x Bit 11 R C1[11] x Bit 10 R C1[10] Xx Bit 9 R C1[9] xX Bit 8 R C1[8] x Bit 7 R C1[7] x Bit 6 R C1[6] X Bit 5 R C1[5] Xx Bit 4 R C1[4] Xx Bit 3 R C1[3] Xx Bit 2 R C1[2] Xx Bit 1 R C1[1] x Bit 0 R C1[0] Xx This register reports the number events, selected by the FREEDM-32P672 Master Performance Monitor Control register, that occurred in the previous accumulation interval. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 248r? [\ | PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 C1[15:0]: The C1[15:0] bits reports the number of selected events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-32P672 Master Clock / BERT Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the configurable count #1 register and simultaneously resets the internal counter to begin a new cycle of event accumulation. PROPRIETARY AND CONFIDENTIAL 249DATASHEET PMC-1990262 ri A C PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x510 : PMON Configurable Count #2 Bit Type Function Default Bit 31 Unused XXXXH to Bit 16 Bit 15 R C2[15] xX Bit 14 R C2[14] Xx Bit 13 R C2[13] xX Bit 12 R C2[12] X Bit 11 R C2[11] Xx Bit 10 R C2[10] x Bit 9 R C2[9] X Bit 8 R C2[8] Xx Bit 7 R C2[7] Xx Bit 6 R C2[6] X Bit 5 R C2[5] Xx Bit 4 R C2[4] x Bit 3 R C2[3] X Bit 2 R C2[2] Xx Bit 1 R C2[1] Xx Bit 0 R C2[0] Xx This register reports the number events, selected by the FREEDM-32P672 Master Performance Monitor Control register, that occurred in the previous accumulation interval. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. PROPRIETARY AND CONFIDENTIAL 250ri A PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET as PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 C2[15:0): The C2[15:0] bits reports the number of selected events that have been detected since the last time this register was polled. This register is polled by writing to the FREEDM-32P672 Master Clock / BERT Activity Monitor and Accumulation Trigger register. The write access transfers the internally accumulated error count to the configurable count #2 register and simultaneously resets the internal counter to begin a new cycle of event accumulation. PROPRIETARY AND CONFIDENTIAL 251DATASHEET PMC-1990262 i 2 iV Nn PMC-Sierra, Inc. PM7380 FREEDM-32P672 eee eee eee cece ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 11 PCI CONFIGURATION REGISTER DESCRIPTION PCI configuration registers are implemented by the PCI Interface. These registers can only be accessed when the PCI Interface is a target and a configuration cycle is in progress as indicated using the IDSEL input. Notes on PCI Configuration Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-32P672 to determine the programming state of the block. Writable PCI configuration register bits are cleared to logic zero upon reset unless otherwise noted. . Writing into read-only PCI configuration register bit locations does not affect FREEDM-32P672 operation unless otherwise noted. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM- 32P672 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided. 11.1 PCI Configuration Registers PCI configuration registers can only be accessed by the PCI host. For each register description below, the hexadecimal register number indicates the PCI offset. PROPRIETARY AND CONFIDENTIAL 252r > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x00 : Vendor Identification/Device Identification Bit Type Function Default Bit 31 R DEVID[15:0] 7380H to Bit 16 Bit 15 R VNDRID[15:0] 11F8H to Bit O VNDRID[15:0): The VNDRID[15:0] bits identifies the manufacturer of the device. Valid vendor identifiers are allocated by the PCI SIG. DEVID[15:0]: The DEVID[15:0] bits define the particular device. Valid device identifiers will be specified by PMC-Sierra. The default value of DEVID[15:0] is that of the FREEDM-32P672 device. PROPRIETARY AND CONFIDENTIAL 253DATASHEET PMC-1990262 ISSUE 4 [ Vi Neen PMC-Sierra, Inc. PM7380 FREEDM-32P672 CT FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x04 : Command/Status Bit Type Function Default Bit 31 R/W PERR 0 Bit 30 R/W SERR 0 Bit 29 R/W MABT 0 Bit 28 R/W RTABT 0 Bit 27 R/W TABT 0 Bit 26 R DVSLT[1] 0 Bit 25 R DVSLT{0] 1 Bit 24 R/W DPR 0 Bit 23 R FBTBE 1 Bit 22 R Reserved 0 Bit 21 R 66MHZ_CAPABLE 1 Bit 20 R Reserved OOH to Bit 16 Bit 15 R Reserved OOH to Bit 10 Bit 9 R FBTBEN 0 Bit 8 R/W SERREN 0 Bit 7 R ADSTP 0 Bit 6 R/W PERREN 0 Bit 5 R VGASNP 0 Bit 4 R MWAI 0 Bit 3 R SPCEN 0 Bit 2 R/W MSTREN 0 Bit 1 R/W MCNTRL 0 Bit 0 R IOCNTRL 0 The lower 16 bits of this register make up the Command register which provides basic control over the GPIC's ability to respond to PCI accesses. When a 0 is PROPRIETARY AND CONFIDENTIAL 254ri fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 written to all bits in the command register, the GPIC is logically disconnected from the PCI bus for all accesses except configuration accesses. The upper 16- bits is used to record status information for PCI bus related events. Reads to the status portion of this register behave normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a 1. lIOCNTRL: When IOCNTRL is set to zero, the GPIC will not respond to PCI bus I/O accesses. MCNTRL: When MCNTRL is set to one, the GPIC will respond to PCI bus memory accesses. Clearing MCNTRL disables memory accesses. MSTREN: When MSTREN is set to one, the GPIC can act as a Master. Clearing MSTREN disables the GPIC from becoming a Master. SPCEN: The GPIC does not decode PCI special cycles. The SPCEN bit is forced low. MWAI: The GPIC does not generate memory-write-and-invalidate commands. The MWAI bit is forced low. VGASNP: The GPIC is not a VGA device. The VGASNP bit is forced low. PERREN: When the PERREN bit is set to one, the GPIC can report parity errors. Clearing the PERREN bit causes the GPIC to ignore parity errors. ADSTP: The GPIC does not perform address and data stepping. The ADSTP bit is forced low. SERREN: When the SERREN bit is set high, the GPIC can drive the SERRB line. Clearing the SERREN bit disables the SERRB line. SERREN and PERREN must be set to report an address parity error. PROPRIETARY AND CONFIDENTIAL 255r? [\ f\ o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FBTBEN: As a master, the GPIC does not generate fast back-to-back cycles to different devices. This bit is forced low. The upper 16-bits make up the PCI Status field. The status field tracks the status of PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a one. 66MHZ CAPABLE: The 66 MHz Capable bit is hardwired to one to indicate the GPIC is capable of operating in 66 MHz mode. FBTBE: The FBTBE bit is hardwired to one to indicate the GPIC supports fast back- to-back transactions with other targets. DPR: The Data Parity Reported (DPR) bit is set high if the GPIC is an initiator and asserts or detects a parity error on the PERRB signal while the PERREN bit is set in the Command register. The DPR bit is cleared by the PCI Host. DVSLT[1:0]: The Device Select Timing (DEVSLT) bits specify the allowable timings for the assertion of DEVSELB by the GPIC as a target. These are encoded as 00B for fast, 01B for medium, 10B for slow and 11B is not used. The GPIC allows for medium timing. TABT: The Target Abort (TABT) bit is set high by the GPIC when as a target, it terminates a transaction with a target abort. The TABT bit is cleared by the PCI Host. RTABT: The Received Target Abort (RTABT) bit is set high by the GPIC when as an initiator, its transaction is terminated by a target abort. The RTABT bit is cleared by the PCI Host. MABT: The Master Abort (MABT) bit is set high by the GPIC when as an initiator, its transaction is terminated by a master abort and a special cycle was not in progress. The MABT bit is cleared by the PCI Host. PROPRIETARY AND CONFIDENTIAL 256rl /I cf PMC-Sierra, Inc. PM7380 FREEDM-32P672 LS FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET PMC-1990262 ISSUE 4 SER The System Error (SERR) bit is set high whenever the GPIC asserts the SERRB output. The SERR bit is cleared by the PCI Host. a PERR: The Parity Error (PERR) bit is set high whenever the GPIC detects a parity error, even if parity error handling is disabled by clearing PERREN in the Command register. The PERR bit is cleared by the PCI Host. PROPRIETARY AND CONFIDENTIAL 257r> [\ /\ X PMC-Sierra, Inc. PM7380 FREEDM-32P672 a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET Register 0x08 : Revision Identifier/Class Code Bit Type Function Default Bit 31 R CCODE[23:16] 02H to Bit 24 Bit 23 R CCODE[15:8] 80H to Bit 16 Bit 15 R CCODE[7:0] OOH to Bit 8 Bit 7 R REVID[7:0] 02H en) | Bit 0 REVID[7:0]: The Revision Identifier (REVID[7:0]) bits specify a device specific revision identifier and are chosen by PMC-Sierra. CCODE[23:0]: The class code (CCODE[23:0]) bits are divided into three groupings: CCODE[23:16] define the base class of the device, CCODE[15:8] define the sub-class of the device and CCODE[7:0] specify a register specific programming interface. Note: Base Class Code: 02H Network Controller Sub-Class Code: 80H Other Controllers Register Class Code: OOH None defined. PROPRIETARY AND CONFIDENTIAL 258i 2 [\ fl co PMC-Sierra, Inc. PM7380 FREEDM-32P672 PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET Register 0x0C : Cache Line Size/Latency Timer/Header Type Bit Type Function Default Bit 31 R Reserved OOH to Bit 24 Bit 23 R MLTFNC 0 Bit 22 R - HDTYPE[6:0] 00H to Bit 16 Bit 15 R/W LT[7:0] OOH to Bit 8 Bit 7 R/W CLSIZE OOH to Bit O CLSIZE[7:0]: The Cache Line Size (CLSIZE[7:0]) bits specify the size of the system cacheline in units of dwords. The GPIC uses this value to determine the type of read command to issue in a Master Read transfer. If the transfer size is equal to one, the GPIC will issue a Memory Read command. If the transfer size is equal to or less than the CLSIZE, the GPIC will issue a Memory Read Line command. For transfers larger than CLSIZE, the GPIC issues a Memory Read Multiple command. LT[7:0]: The Latency Timer (LT[7:0]) bits specify, in units of the PCI clock, the value of the Latency Timer for the GPIC. At reset the value is zero. The value of the LT is application specific and should be programmed by software. HDTYPEJ6:0}: The Header Type (HDTYPE[7:0]) bits specify the layout of the base address registers. Only the 00H encoding is supported. MLTENC: The Multi-Function (MLTFNC) bit specifies if the GPIC supports multiple PCI functions. If this bit is set low, the device only supports one function and if the bit is set high, the device supports multi-functions. The MLTFNC bit is set low to indicate the GPIC only supports one PCI function. PROPRIETARY AND CONFIDENTIAL 259r> [\ /\ Y PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x10 : CBI Memory Base Address Register Bit Type Function Default Bit 31 R/W BSAD[27:9] 00000H Bit | 3 Bit 12 R BSADJ[8:0] 000H to Bit 4 Bit 3 R PRFTCH 0 Bit 2 R TYPE[1] 0 Bit 1 R TYPE[O] 0 Bit O R MSI 0 The GPIC supports memory mapping only. At boot-up the internal registers space is mapped to memory space. The device driver can disable memory space through the PCI Configuration Command register. MSL MSI is forced low to indicate that the internal registers map into memory space. TYPE[1:0}: The TYPE field indicates where the internal registers can be mapped. The encoding 0OB indicates the registers may be located anywhere in the 32 bit address space, 01B indicates that the registers must be mapped below 1 Meg in memory space, 10B indicates the base register is 64 bits and the encoding 11B is reserved. The TYPE field is set to OOB to indicate that the CBI registers can be mapped anywhere in the 32 bit address space. PRFETCH: The Prefetchable (PRFTCH) bit is set if there are no side effects on reads and data is returned on all the lanes regardless of the byte enables. Otherwise the bit is cleared. TSBs contain registers, such as interrupt status registers, in which bits are cleared on a read. If the PCI Host is caching data there is a possibility an interrupt status could be lost if data is prefetched, but the cache is flushed and the data is not used. The PRFTCH bit is forced low to indicate that prefetching of data is not supported for internal registers. PROPRIETARY AND CONFIDENTIAL 260r- VM Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 BSAD[27:0]: The Base Address (BSAD[27:0]) bits defines the size and location of the memory space required for the CBI registers. The BSAD[27:0] bits correspond to the most significant 28 bits of the PCI address space. The size of the address space required can be determined by writing all ones to Base Address register and then reading from it. By scanning the returned value from the least significant bit upwards, the size of the required address space can be determined. The binary weighted value of the first one bit found (after the configuration bits) indicates the required amount of space. The BSAD[8:0] bits are forced low to indicate that the CBI registers require 8K bytes of memory space. After determining the memory requirements of the CBI registers, the PCI Host can map them to its desired location by modifying the BSAD[27:9] bits in the Base Address register. PROPRIETARY AND CONFIDENTIAL 261i > [\ / PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET nes PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Register 0x3C : Interrupt Line / Interrupt Pin / MIN_GNT / MAX_LAT Bit Type Function Default Bit 31 R MAXLAT[7:0] OFH to Bit 24 Bit 23 R MINGNT[7:0] 05H to Bit 16 Bit 15 R INTPIN{7:0] 01H to Bit 8 | Bit 7 R/W INTLNE[7:0] OOH to Bit 0 INTLNEJ7:0]: The Interrupt Line (INTLNE[7:0]) field is used to indicate interrupt line routing information. The values in this register are system specific and set by the PCi Host. INTPIN[7:01: The Interrupt Pin (INTPIN[7:0]) field is used to specify the interrupt pin the GPIC uses. Since the GPIC will use INTAB on the PCI bus, the value in this register is set to one. MINGNT{[?:0]: The Minimum Grant (MINGNT{7:0]) field specifies how long of a burst period the bus master needs (in increments of 250 nsec). MAXLAT{7:0]: The Maximum Latency (MAXLAT[7:0]) field specifies how often a bus master needs access to the PCI bus (in increments of 250 nsec). PROPRIETARY AND CONFIDENTIAL 262r-i\ fi cr PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 12. TEST FEATURES DESCRIPTION The FREEDM-32P672 also supports a standard IEEE 1149.1 five signal JTAG boundary scan test port for use in board testing. All device inputs may be read and all device outputs may be forced via the JTAG test port. 12.1 Test Mode Registers Test mode registers are used to apply test vectors during production testing of the FREEDM-32P672. Production testing is enabled by asserting the PMCTEST pin. During production tests, FREEDM-32P672 registers are selected by the TA[12:0] pins. The address of a register on TA[12:0] is identical to the PCI offset of that register when production testing is disabled (PMCTEST low). Read accesses are enabled by asserting TRDB low while write accesses are enabled by asserting TWRB low. Test mode register data is conveyed on the TDAT[15:0] pins. Test mode registers (as opposed to normal mode registers) are selected when TA[12]/TRS is set high. PROPRIETARY AND CONFIDENTIAL 263DATASHEET PMC-1990262 r? Vi C PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 29 - Test Mode Register Memory Map Address TA[12:0] Register 0x0000 - O0x07FC Normal Mode Registers 0x0800 - 0x107C Reserved 0x1080 - 0x10FC GPIC Test Registers 0x1100 - Ox11FC RCAS Test Registers 0x1200 - 0x123C RHDL Test Registers 0x1240 - 0x127C Reserved 0x1280 - Ox12FC RMAC Test Registers 0x1300 - 0x137C TMAC Test Registers 0x1380 - 0x13BC THDL Test Registers 0x13C0 - Ox13FC Reserved 0x1400 - Ox14FC TCAS Test Registers 0x1500 - 0x151C PMON Test Registers 0x1520 - Ox1FFC Reserved Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. Writable test mode register bits are not initialized upon reset unless otherwise noted. 12.2 JTAG Test Port The FREEDM-32P672 JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. PROPRIETARY AND CONFIDENTIAL 264r> Vi C PMC-Sierra, Inc. DATASHEET PMC-1990262 ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Table 30 Instruction Register Length - 3 bits Instructions | Selected Register | Instruction Code IR[2:0] EXTEST Boundary Scan 000 IDCODE Identification 001 SAMPLE Boundary Scan 010 BYPASS Bypass 011 BYPASS Bypass 100 STCTEST Boundary Scan 101 BYPASS Bypass 110 BYPASS Bypass 111 12.2.1 Identification Register Length - 32 bits Version number - 2H Part Number - 7380H Manufacturer's identification code - OCDH Device identification - 273800CDH 12.2.2 Boundary Scan Register The boundary scan register is made up of 365 boundary scan cells, divided into input observation (in_cell), output (out_cell), and bi-directional (io_cell) cells. These cells are detailed in the following pages. The first 32 cells form the ID code register, and carry the code 273800CDH. The cells are arranged as follows: Table 31 - Boundary Scan Chain Pin/ Enable Register Bit Cell Type Device I.D. RBCLK_OEN 0 OUT_CELL - RBCLK 1 OUT_CELL - PROPRIETARY AND CONFIDENTIAL 265r- VM C* PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. RBD_OEN 2 OUT_CELL - RBD 3 OUT_CELL - TMV8DC 4 IN_CELL - TFP8B 5 IN_CELL - TMV8FPC 6 IN_CELL - TFPB(0] 7 IN_CELL - TMVCK[O] 8 IN_CELL - TD_OEN[0] 9 OUT_CELL - TD[O} 10 OUT_CELL - TCLK[0] 11 IN_CELL - TD_OEN[1] 12 OUT_CELL - TD[1] 13 OUT_CELL - TCLK[1] 14 IN_CELL - TD_OEN[2] 15 OUT_CELL - TD[2} 16 OUT_CELL - TCLK{2] 17 IN_CELL - TD_OEN{[3] 18 OUT_CELL - TD[3] 19 OUT_CELL - TCLK[3] 20 IN_CELL - TD_OEN[4] 21 OUT_CELL - TD[4] 22 OUT_CELL - TCLK{4] 23 IN_CELL - TD_OEN[5] 24 OUT_CELL - TD[5} 25 OUT_CELL - TCLK[5] 26 IN_CELL - TD_OEN[6] 27 OUT_CELL - TD[6] 28 OUT_CELL - TCLK{6] 29 IN_CELL - TD_OEN{7] 30 OUT_CELL - PROPRIETARY AND CONFIDENTIAL 266rly Cc PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. TD[7] 31 OUT_CELL - TCLK[7] 32 IN_CELL - TFPB[1] 33 IN_CELL - TMVCK[1] 34 IN_CELL - TD_OEN[8] 35 OUT_CELL - TD[8] 36 OUT_CELL - TCLK[8] 37 IN_CELL - TD_OEN[9] 38 OUT_CELL - TD[9] 39 OUT_CELL - TCLK[9] 40 IN_CELL - TD_OEN[10] 41 OUT_CELL - TD[10] 42 OUT_CELL - TCLK[10] 43 IN_CELL - TD_OEN[11] 44 OUT_CELL - TD[11]} 45 OUT_CELL - TCLK[11] 46 IN_CELL - TD_OEN[12] 47 OUT_CELL - TD[12] 48 OUT_CELL - TCLK[12] 49 IN_CELL - TD_OEN[13] 50 OUT_CELL - TD[13} 51 OUT_CELL - TCLK[13] 52 IN_ CELL - TD_OEN[14] 53 OUT_CELL - TD[14] 54 OUT_CELL - TCLK[14] 55 IN_CELL - TD_OEN[15] 56 OUT_CELL - TD[15] 57 OUT_CELL - TCLK[15] 58 IN_CELL - TFPB[2] 59 IN_CELL - PROPRIETARY AND CONFIDENTIAL 267ri fi Cc PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. TMVCK[2] 60 IN_CELL - TD_OEN[16] 61 OUT_CELL - TD[16] 62 1IO_CELL - TCLK[16] 63 IN_CELL - TD_OEN[17] 64 OUT_CELL - TD[17] 65 1O_CELL - TCLK[17] 66 IN_CELL - TD_OEN[18] 67 OUT_CELL - TD[18] 68 1O_CELL - TCLK[18] 69 IN_CELL - TD_OEN[19] 70 OUT_CELL - TD[19] 71 lIO_CELL - TCLK[19] 72 IN_CELL - TD_OEN[20] 73 OUT_CELL - TD[20] 74 1O_CELL - TCLK[20] 75 IN_CELL - TD_OEN[21] 76 OUT_CELL - TD[21] 77 1O0_CELL - TCLK[21] 78 IN_CELL - TD_OEN[22] 79 OUT_CELL - TD[22]} 80 1IO_CELL - TCLK[22] 81 IN_CELL - TD_OEN[23] 82 OUT_CELL - TD[23] 83 1IO_CELL - TCLK[23] 84 IN_CELL - TFPB[3] 85 IN_CELL - TMVCK[3] 86 IN_CELL - TD_OEN[24] 87 OUT_CELL - TD[24] 88 lIO_CELL - PROPRIETARY AND CONFIDENTIAL 268r> Mi C PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. TCLK[24] 89 IN_CELL - TD_OEN[25] 90 OUT_CELL - TD[25] 91 1O_CELL - TCLK[25] 92 IN CELL - TD_OEN[26] 93 OUT_CELL - TD[26] 94 1O_CELL - TCLK[26] 95 IN_CELL - TD_OEN[27] 96 OUT_CELL - TD[27] 97 1IO_CELL - TCLK[27] 98 IN_CELL - TD_OEN[28] 99 OUT_CELL - TD[28] 100 lIO_CELL - TCLK[28] 101 IN_CELL - TD_OEN[29] 102 OUT_CELL - TD[29] 103 1O_CELL - TCLK[29] 104 IN_CELL - TD_OEN[30] 105 OUT_CELL - TD[30] 106 1IO_CELL - TCLK[30] 107 IN_CELL - TD_OEN[31] 108 OUT_CELL - TD[31] 109 1O_CELL - TCLK[31] 110 IN_CELL - TBD 111 IN_CELL - TBCLK_OEN 112 OUT_CELL - TBCLK 113 OUT_CELL - PMCTEST 114 IN_CELL - Logic 0 115 IN_CELL - Logic 0 116 IN_CELL - Logic 0 117 IN_ CELL - PROPRIETARY AND CONFIDENTIAL 269DATASHEET PMC-1990262 rf I c PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. M66EN 118 IN_ CELL - AD_OEN[(0] 119 OUT_CELL - AD(0] 120 lO_CELL - AD_OEN[1] 121 OUT_CELL - ! AD[1] 122 1IO_CELL - AD_OEN[2] 123 OUT_CELL - AD[2] 124 lIO_CELL - AD_OEN{[3] 125 OUT_CELL - AD[3] 126 lIO_CELL - AD_OEN[4] 127 OUT_CELL - AD[4] 128 lIO_CELL - AD_OEN[5] 129 OUT_CELL - AD[5] 130 1O_CELL - AD_OENJ[6] 131 OUT_CELL - AD[6] 132 IO_CELL - AD_OEN[7] 133 OUT_CELL - AD[7] 134 lIO_CELL - CBEB_OEN([0] 135 OUT_CELL - CBEB[0] 136 lIO_CELL - AD_OEN{8] 137 OUT_CELL - AD[8} 138 1O_CELL - AD_OEN[9] 139 OUT_CELL - AD[9] 140 lIO_CELL - AD_OEN[10] 141 OUT_CELL - AD[10] 142 lIO_CELL - AD_OEN[11] 143 OUT_CELL - AD[11] 144 1O_CELL - AD_OEN[12] 145 OUT_CELL - AD[12] 146 IO_CELL - PROPRIETARY AND CONFIDENTIAL 270PM7380 FREEDM-32P672 r-ivV Cc PMC-Sierra, Inc. ISSUE 4 DATASHEET PMC-1990262 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. AD_OEN[13] 147 OUT_CELL - AD[13] 148 1IO_CELL - AD_OEN[14] 149 OUT_CELL - AD[14] 150 1O_CELL - AD_OEN[15] 151 OUT_CELL - AD[15] 152 lIO_CELL - CBEB_OEN[1] 153 OUT_CELL - CBEB[1] 154 1O_CELL - PAR_OEN 155 OUT_CELL - PAR 156 IO_CELL - SERRB_OEN 157 OUT_CELL - SERRB 158 IO_CELL - PERRB_OEN 159 OUT_CELL - PERRB 160 1O_CELL - LOCKB 161 IN_CELL - STOPB_OEN 162 OUT_CELL - STOPB 163 lO_CELL - DEVSELB_OEN 164 OUT_CELL - DEVSELB 165 1O_CELL - TRDYB_OEN 166 OUT_CELL - TRDYB 167 IO_CELL - IRDYB_OEN 168 OUT_CELL IRDYB 169 1IO_CELL - FRAMEB_OEN 170 OUT_CELL - FRAMEB 171 1O_CELL - CBEB_OEN[2] 172 OUT_CELL - CBEB[2] 173 1O_CELL - AD_OEN{16] 174 OUT_CELL - AD[16] 175 IO_CELL - PROPRIETARY AND CONFIDENTIAL 271rev C PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. AD_OEN[17] 176 OUT_CELL - AD[17] 177 IO_CELL - AD_OEN[18] 178 OUT_CELL - AD[18] 179 lIO_CELL - AD_OEN[19] 180 OUT_CELL - AD[19] 181 1IO_CELL - AD_OEN[20] 182 OUT_CELL - AD[20] 183 1O_CELL - AD_OEN[21] 184 OUT_CELL - AD[21] 185 1O_CELL - AD_OEN[22] 186 OUT_CELL - AD[22] 187 IO_CELL - AD_OEN[23] 188 OUT_CELL - AD[23] 189 lIO_CELL - IDSEL 190 IN_CELL - CBEB_OEN[3] 191 OUT_CELL - CBEBJ3] 192 1O_CELL - AD_OEN[24] 193 OUT_CELL - AD[24} 194 1O_CELL - AD_OEN[25] 195 OUT_CELL - AD[25] 196 1O_CELL - AD_OEN/[26] 197 OUT_CELL - AD[26] 198 lO_CELL - AD_OEN[27] 199 OUT_CELL - AD[27] 200 IO_CELL - AD_OEN[28] 201 OUT_CELL - AD[28] 202 IO_CELL - AD_OEN[29] 203 OUT_CELL - AD[29] 204 IO_CELL - PROPRIETARY AND CONFIDENTIAL 272r= iV ees PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. AD_OEN[30] 205 OUT_CELL - AD[30] 206 lO_CELL - AD_OEN[31] 207 OUT_CELL - AD[31] 208 IO_CELL - REQB_OEN 209 OUT_CELL - REQB 210 lIO_CELL - Logic 0 211 IN_CELL - GNTB 212 IN_CELL - PCICLK 213 IN_CELL - Logic 0 214 IN_CELL - PCICLKO_OEN 215 OUT_CELL - PCICLKO 216 OUT_CELL - Logic 0 217 IN_CELL - PCIINTB_OEN 218 OUT_CELL - PCIINTB 219 1O_CELL - Logic 0 220 IN_CELL - Logic 0 221 IN_ CELL - Logic 0 222 IN_CELL - Logic 0 223 IN_CELL - Logic 0 224 IN - CELL - Logic 0 225 IN_CELL - Logic 0 226 IN_CELL - Logic 0 227 IN_ CELL - Unconnected 228 OUT_CELL - Unconnected 229 1O_CELL - Unconnected 230 OUT_CELL - Unconnected 231 lO_CELL - Unconnected 232 OUT_CELL - Unconnected 233 1O0_CELL - PROPRIETARY AND CONFIDENTIAL 273ri Mi Cc PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. Unconnected 234 OUT_CELL - Unconnected 235 1IO_CELL - Unconnected 236 OUT_CELL - Unconnected 237 IO_CELL - Unconnected 238 OUT_CELL - Unconnected 239 lO_CELL - Unconnected 240 OUT_CELL - Unconnected 241 lO_CELL - Unconnected 242 OUT_CELL - Unconnected 243 lO_CELL - Unconnected 244 OUT_CELL - Unconnected 245 1O_CELL - Unconnected 246 OUT_CELL - Unconnected 247 1O_CELL - Unconnected 248 OUT_CELL - Unconnected 249 1O0_CELL - Unconnected 250 OUT_CELL - Unconnected 251 1O_CELL - Unconnected 252 OUT_CELL - Unconnected 253 1O_CELL - Unconnected 254 OUT_CELL - Unconnected 255 lO_CELL - Unconnected 256 OUT_CELL - Unconnected 257 1O_CELL - Unconnected 258 OUT_CELL - Unconnected 259 1O_CELL - Unconnected 260 OUT_CELL - Unconnected 261 lO_CELL - Unconnected 262 OUT_CELL - PROPRIETARY AND CONFIDENTIAL 274r-i\ A ri PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device |.D. Unconnected 263 1O_CELL - Unconnected 264 OUT_CELL - Unconnected 265 lO_CELL - Unconnected 266 OUT_CELL - Unconnected 267 1O_CELL - Unconnected 268 OUT_CELL - Unconnected 269 JO_CELL - Unconnected 270 OUT_CELL - Unconnected 271 1O_CELL - Logic 0 272 IN_CELL - Logic 0 273 IN_CELL - Logic 0 274 IN_CELL - Logic 0 275 IN_CELL - Logic 0 276 IN_CELL - Logic 0 277 IN_CELL - Logic 0 278 IN_ CELL - Logic 0 279 IN_ CELL - Logic 0 280 IN_CELL - Logic 0 281 IN_ CELL - Logic 1 282 IN_CELL - Logic 1 283 IN_CELL - Logic 4 284 IN_- CELL - Logic 1 285 IN_CELL - Unconnected 286 OUT_CELL - Unconnected 287 OUT_CELL - RCLK{[31] 288 IN_ CELL - RD[31] 289 IN_CELL - RCLK[30] 290 IN_CELL - RD[S80] 291 IN_ CELL - PROPRIETARY AND CONFIDENTIAL 275PVA enc sora PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device |.D. RCLK[29] 292 IN_CELL - RD[29] 293 IN_CELL - RCLK[28] 294 IN_CELL - RD[28] 295 IN_CELL - RCLK[27] 296 IN_ CELL - RD[27] 297 IN_CELL - RCLK[26] 298 IN_CELL - ! RD[26] 299 IN_CELL . | RCLK[25] 300 IN_CELL - RD[25] 301 IN_CELL - RCLK[24] 302 IN_CELL - RD[24] 303 IN_CELL - RMVCK{3] 304 IN_ CELL - RFPB[3] 305 IN_CELL - RCLK[23] 306 IN_CELL - RD[23} 307 IN_CELL - RCLK[22] 308 IN_ CELL - RD[22] 309 IN_CELL - RCLK[21] 310 IN_CELL - RD[21] 311 IN_ CELL - RCLK[20} 312 IN_CELL - RD[20] 313 IN_CELL - RCLK[19] 314 IN_CELL - RD[19] 315 IN_CELL - RCLK[18] 316 IN_CELL - RD[18] 317 IN_CELL - RCLK[17] 318 IN_CELL - RD[17] 319 IN_CELL - RCLK[16] 320 IN_CELL - PROPRIETARY AND CONFIDENTIAL 276PMC PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device I.D. RD[16] 321 IN_CELL - RMVCK[2] 322 IN_ CELL - RFPB[2] 323 IN_ CELL - RCLK[15] 324 IN_CELL - RD[15] 325 IN_CELL - RSTB 326 IN_CELL - RCLK[14] 327 IN_CELL - RD[14] 328 IN_CELL - RCLK[13] 329 IN_CELL - RD[13] 330 IN_CELL - RCLK[12] 331 IN_CELL - RD[12] 332 IN_CELL - RCLK[11] 333 IN_CELL 1 RD[11] 334 IN_CELL 0 RCLK[10] 335 IN_ CELL 1 RD[10] 336 IN_CELL 1 RCLK[9] 337 IN_CELL 0 RD[9] 338 IN_CELL 0 RCLK[8] 339 IN_CELL 1 RD[8} 340 IN_ CELL 1 RMVCK[1] 341 IN_CELL 0 RFPB[1] 342 IN_CELL 0 RCLK[7] 343 IN_CELL 0 RD[7] 344 IN_CELL 0 RCLK[6] 345 IN_CELL 0 RD[6] 346 IN_CELL 0 SYSCLK 347 IN_ CELL 0 RCLK[5] 348 IN_CELL 0 RD[5] 349 IN_CELL 0 PROPRIETARY AND CONFIDENTIAL 277r? [\ v/| Cc PMC-Sierra, Inc. 1. RMV8DC is the first bit of the scan chain (closest to TDI). 2. Enable cell pinname_OEN, tristates pin pinname when set high. 3. Cells Logic 0 and Logic 1 are Input Observation cells whose input pad is bonded to VSS or VDD internally. Cells titled Unconnected are Output or Bi-directional cells whose pad is unconnected to the device package. In the case of bi-directional cells, the PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Pin/ Enable Register Bit Cell Type Device |.D. | RCLK[4] 350 IN_CELL 0 RD/[4] 351 IN_CELL 0 RCLK[3] 352 IN_CELL 1 RD[3] 353 IN_CELL 1 RCLK[2] 354 IN_CELL 1 RD[2] 355 IN_CELL 0 RCLK[1] 356 IN_CELL 0 RD[1] 357 IN_CELL 1 RCLK[O] 358 IN_CELL 1 RD[0] 359 IN_CELL 1 RMVCK[0] 360 IN_CELL 0 RFPB[O] 361 IN_ CELL 0 | RMV8FPC 362 IN_CELL { | RFP8B 363 IN_CELL 0 RMV8DC 364 IN_CELL 0 TDO TAP Output - TDI TAP input - TCK TAP Clock - TMS TAP Input - TRSTB TAP Input . | Notes: PROPRIETARY AND CONFIDENTIAL 278r-i\ I co PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 pad always drives (i.e. never tri-states) and the pad input is the same logic value as the pad output. Figure 17 Input Observation Cell (IN_CELL) IDCODE Scan Chain Out Input INPUT Pad to internal logic SHIFT-DR 2 MUX 12 12 |.D. Code bit CLOCK-DR Scan Chain In In this diagram and those that follow, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexor in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the table above. PROPRIETARY AND CONFIDENTIAL 279r> [\ I PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 18 Output Cell (OUT_CELL) Scan Chain Out EXTEST Output or Enable from system logic Output or Enable IDCODE SHIFT-DR |.D. code bit CLOCK-DR UPDATE-DR Scan Chain In Figure 19 Bi-directional Cell (IO_CELL) Scan Chain Out INPUT to internal EXTEST G1 logic OUTPUT from internal logic OUTPUT IDCODE to pin SHIFT-DR INPUT from pin |.D. code bit CLOCK-DR UPDATE-DR Scan Chain In PROPRIETARY AND CONFIDENTIAL 280r- [\ /| PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 20 Layout of Output Enable and Bi-directional Cells Scan Chain Out OUTPUT ENABLE from internal w| OUT_CELL logic (O = drive) Scan Chain In Scan i" Out INPUT to internal logic <4_-4 IO CELL \* OUTPUT from | +| internal logic n Scan Chain In PROPRIETARY AND CONFIDENTIAL 281r \ /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET Ecce ccc ccc ee eS PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 13. OPERATIONS This section presents connection details to the PM4388 TOCTL device, and operating details for the JTAG boundary scan feature. 13.1 TOCTL Connections The required connections between the PM4388 TOCTL and the FREEDM- 32P672 are shown in the following table: Table 32 FREEDM-TOCTL Connections FREEDM-32P672 I Direction TOCTL Pin Pin RCLK[n] ra ICLK/ISIG[m] RD{[n] - ID[m] n.c. ro IFP[m] TCLK[n] < EFP/RCLK/ESIG[m] TD[n] > ED[m]} All 8 framers in the TOCTL should be programmed to operate in Clock Master: NxDS0 mode in both the ingress and egress direction. 13.2 JTAG Support The FREEDM-32P672 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below. PROPRIETARY AND CONFIDENTIAL 282r- [\ fl PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET | PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 21 Boundary Scan Architecture > Boundary Scan Register _ Device Identification Register Bypass Register > Instruction Mux Register |__| oFF | DS and TDO Decode et Control Test Select Access Port ; 3 Controller | Tri-state Enable TRSTB TCK_> The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single bit delay from primary input, TDI to primary output , TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register placed in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be PROPRIETARY AND CONFIDENTIAL 283i ai\ fi o PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 sampled and shifted out on primary output TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs. TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below. PROPRIETARY AND CONFIDENTIAL 284DATASHEET PMC-1990262 r? [\ I Oo PMC-Sierra, Inc. PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 22 TAP Controller Finite State Machine J rastaco Test-Logic-Reseth@ 4 1 1 Run-Test-Idie Cc G A Select-DR-Scan 7 ]_ Select-IR-Scan v r Capture-DR Capture-IR Y! ye Shift-DR Shift-IR , 1 0 \ 1 0 1 1 Exit1-DR Exit1-IR v Ye Pause-DR Pause-IR \ 1 0 \ { 0 0 Exit2-DR Exit2-IR Y y Update-DR [| Update-IR \ 0 y' | v All transitions dependent on input TMS PROPRIETARY AND CONFIDENTIAL 285r ~ [\ fi \ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-ldle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. PROPRIETARY AND CONFIDENTIAL 286r > [\ y/ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects a serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. PROPRIETARY AND CONFIDENTIAL 287r 2 [\ AI PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET Es se nee ee ne ees PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state. INTEST The internal test instruction is used to exercise the device's internal core logic. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Update-DR state, patterns shifted in on input, TDI are used to drive primary inputs. During the Capture-DR state, primary outputs are sampled and loaded into the boundary scan register. PROPRIETARY AND CONFIDENTIAL 288r [\ Al c* PMC-Sierra, Inc. PM7380 FREEDM-32P672 ee en nanan PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 DATASHEET 14 | FUNCTIONAL TIMING 14.1 Receive H-MVIP Link Timing The timing relationship of the receive data clock (RMV8DC), frame pulse clock (RMV8FPC), data (RD[n]) and frame pulse (RFP8BJ[n]) signals of a link configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 23. The falling edges of each RMV8FPC are aligned to a falling edge of the corresponding RMV8DC for 8.192 Mbps H-MVIP operation. The FREEDM-32P672 samples RFP8B low on the falling edge of RMV8FPC and references this point as the start of the next frame. The FREEDM-32P672 samples the data provided on RD[n] at the % point of the data bit using the rising edge of RMV8DC as indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 23. B1 is the most significant bit and B8 is the least significant bit of each octet. Time-slots can be ignored by setting the PROV bit in the corresponding word of the receive channel provision RAM in the RCAS672 block to low. Figure 23 Receive 8.192 Mbps H-MVIP Link Timing (16 MHz) RMV8FPC (4 MHz) RFP8B on Ye [aye {= j= [= [eyo [eta] TS 127 | TS 0 | TS 14 The timing relationship of the receive data clock (RMVCK[n]), data (RD[m], where 8nsms8n+7) and frame pulse (RFPB[n]) signals of a link configured for 2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 24. The FREEDM-32P672 samples RFPB{[n] low on the falling edge of the corresponding RMVCK)[n] and references this point as the start of the next frame. The FREEDM-32P672 samples the data provided on RD[m] at the % point of the data bit using the rising edge of the corresponding RMVCKj[n] as indicated for bit 1 (B1) of time-slot 0 (TS 0) in Figure 24. B1 is the most significant bit and B8 is the least significant bit of each octet. Time-slots can be ignored by setting the PROV bit in the corresponding word of the receive channel provision RAM in the RCAS672 block to low. PROPRIETARY AND CONFIDENTIAL 289r> [\ /| PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 24 Receive 2.048 Mbps H-MVIP Link Timing RMVCK[n] (4 MHz) RFPBIn] om To [ule fe fu l= [= lolol} TS 31 | TS 0 | TS 1 14.2 Transmit H-MVIP Link Timing The timing relationship of the transmit data clock (TMV8DC), frame pulse clock (TMV8FPC), data (TD[n]) and frame pulse (TFP8B) signals of a link configured for 8.192 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 25. The falling edges of each TMV8FPC are aligned to a falling edge of the corresponding TMV8DC for 8.192 Mbps H-MVIP operation. The FREEDM- 32P672 samples TFP8B low on the falling edge of TMV8FPC and references this point as the start of the next fame. The FREEDM-32P672 updates the data provided on TD[n] on every second falling edge of TMV8DC as indicated for bit 2 (B2) of time-slot 0 (TS 0) in Figure 25. The first bit of the next frame is updated on TD[n] on the falling TMV8DC clock edge for which TFP8B is also sampled low. B1 is the most significant bit and B8 is the least significant bit of each octet. Time-slots that are not provisioned to belong to any channel (PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS672 block set low) transmits the contents of the Idle Fill Time-slot Data register. Figure 25 Transmit 8.192 Mbps H-MVIP Link Timing res UU Mawes) J LL [ TFP8B | TD[n] Yee Yer {a2 XY oo Y oe as Yao \ or Y oe Y a TS 127 | TS 0 | TS 1 PROPRIETARY AND CONFIDENTIAL 290[ VI PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee] PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 The timing relationship of the transmit data clock (TMVCK][n]), data (TD[m], where 8n<ms<8n+7) and frame pulse (TFPB[n]) signals of a link configured for 2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 26. The FREEDM-32P672 samples TFPB[n] low on the falling edge of the corresponding TMVCkK)[n] and references this point as the start of the next frame. The FREEDM-32P672 updates the data provided on TD[m] on every second falling edge of the corresponding TMVCK[n] as indicated for bit 2 (B2) of time- slot 0 (TS 0) in Figure 26. The first bit of the next frame is updated on TD[n] on the falling TMVCK[n] clock edge for which TFPBjn] is also sampled low. B1 is the most significant bit and B8 is the least significant bit of each octet. Time- slots that are not provisioned to belong to any channel (PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS672 block set low) transmits the contents of the Idle Fill Time-slot Data register. Figure 26 Transmit 2.048 Mbps H-MVIP Link Timing TMVCK[n] (4 MHz) TFPB[n] om Yo [ele {e [ela {elo [ote] TS 31 | TSO | TS 4 14.3 Receive non H-MVIP Link Timing The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of an unchannelised link is shown in Figure 27. The receive data is viewed as a contiguous serial stream. There is no concept of time-slots in an unchannelised link. Every eight bits are grouped together into a byte with arbitrary alignment. The first bit received (B1 in Figure 27) is deemed the most significant bit of an octet. The last bit received (B8) is deemed the least significant bit. Bits that are to be processed by the FREEDM-32P672 are clocked in on the rising edge of RCLK[n]. Bits that should be ignored (X in Figure 27) are squelched by hoiding RCLK[n] quiescent. In Figure 27, the quiescent period is shown to be a low level on RCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Selection of bits for processing is arbitrary and is not subject to any byte alignment nor frame boundary considerations. PROPRIETARY AND CONFIDENTIAL 291ri /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET errr reer reece c eee ee ee eeS PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 27 Unchannelised Receive Link Timing RcLKin} [ILLS nA RDjn] _ |B1}B2/B3| B84] x {B5] x | x} x [Be/B7] 88/1] x | The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of a channelised T1/J1 link is shown in Figure 28. The receive data stream is a T1/J1 frame with a single framing bit (F in Figure 28) followed by octet bound time-slots 1 to 24. RCLK[n] is held quiescent during the framing bit. The RD[n] data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the framing bit is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS24) clocked in by the last rising edge of RCLK[n] before the framing bit is the least significant bit of time-slot 24. In Figure 28, the quiescent period is shown to be a low level on RCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot TS24, is equally acceptable. In channelised T1/J1 mode, RCLK[n] can only be gapped during the framing bit. It must be active continuously at 1.544 MHz during all time-slot bits. Time-slots can be ignored by setting the PROV bit in the corresponding word of the receive channel provision RAM in the RCAS672 block to low. Figure 28 Channelised T1/J1 Receive Link Timing RcLKin) FUP RD[n] |B7|B8| F |B1|B21B3/B4/B5/B6| B7|B8|B1) B2|B3| TS 24 | | TS 1 | TS2 The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of a channelised E7 link is shown in Figure 29. The receive data stream is an E1 frame with a singe framing byte (F1 to F8 in Figure 29) followed by octet bound time-slots 1 to 31. RCLK[n] is held quiescent during the framing byte. The RD[n] data bit (B1 of TS1) clocked in by the first rising edge of RCLK[n] after the framing byte is the most significant bit of time-slot 1. The RD[n] bit (B8 of TS31) clocked in by the last rising edge of RLCLK[n] before the framing byte is the least significant bit of time-slot 31. In Figure 29, the quiescent period is shown to be a low level on RCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot TS31, is equally acceptable. In channelised E1 mode, RCLK[n] can only be gapped during the framing byte. It must be active continuously at 2.048 MHz during all time-slot bits. Time-slots can be ignored by setting the PROPRIETARY AND CONFIDENTIAL 292r> [\ f\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PROV bit in the corresponding word of the receive channel provision RAM in the RCAS672 block to low. Figure 29 Channelised E1 Receive Link Timing RotKin} FULL RD[n] _ [e6|87[B8/ F1/F2| F3| F4[ Fs] Fe|F7| Fe[81/B2]B3]B4|B5/B6|B7/88/B1/B2/B3]/B4 Ts 31 | FAS / NFAS | TS 1 | Ts2 14.4 Transmit non H-MVIP Link Timing The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of a unchannelised link is shown in Figure 30. The transmit data is viewed as a contiguous serial stream. There is no concept of time-slots in an unchannelised link. Every eight bits are grouped together into a byte with arbitrary byte alignment. Octet data is transmitted from most significant bit (B1 in Figure 30) and ending with the least significant bit (B8 in Figure 30). Bits are updated on the falling edge of TCLK[n]. A transmit link may be stalled by holding the corresponding TCLK[n] quiescent. In Figure 30, bits BS and B2 are shown to be stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure 30, the quiescent period is shown to be a low level on TCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame boundaries. Figure 30 Unchannelised Transmit Link Timing TeLKin) FIFA nA TD[n] [B1|B2/B3/B4] BS | Be |B7}Be/B1] B2 The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of a channelised T1/J1 link is shown in Figure 31. The transmit data stream is a T1/J1 frame with a single framing bit (F in Figure 31) followed by octet bound time-slots 1 to 24. TCLK[n] is held quiescent during the framing bit. The most significant bit of each time-slot is transmitted first (B1 in Figure 31). The least significant bit of each time-slot is transmitted last (B8 in Figure 31). The TD[n] bit (B8 of TS24) before the framing bit is the least significant bit of time-slot 24. In Figure 31, the quiescent period is shown to be a low level on TCLK[n]. A high level, effected by extending the high phase of bit B8 of time-slot TS24, is equally PROPRIETARY AND CONFIDENTIAL 293r> [\ /\ \ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 acceptable. In channelised T1/J1 mode, TCLK[n] can only be gapped during the framing bit. It must be active continuously at 1.544 MHz during all time-slot bits. Time-slots that are not provisioned to belong to any channel (PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS672 block set low) transmit the contents of the Idle Fill Time-slot Data register. Figure 31 Channelised T1/J1 Transmit Link Timing Tetkin) TULL TD[n} |87/B8| 81 |B2/B3|B4|/B5/B6/B7/B8/B1] B2/B3| TS 24 | F| TS 1 | s2 The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals of a channelised E1 link is shown in Figure 32. The transmit data stream is an E1 frame with a singe framing byte (FAS/NFAS in Figure 32) followed by octet bound time-slots 1 to 31. TCLK[n] is held quiescent during the framing byte. The most significant bit of each time-siot is transmitted first (B1 in Figure 32). The least significant bit of each time-slot is transmitted last (B8 in Figure 32). The TD{[n] bit (B8 of TS31) before the framing byte is the least significant bit of time-slot 31. In Figure 32, the quiescent period is shown to be a low level on TCLKjn]. A high level, effected by extending the high phase of bit B8 of time-slot 31, is equally acceptable. In channelised E1 mode, TCLK[n] can only be gapped during the framing byte. It must be active continuously at 2.048 MHz during all time-slot bits. Time-slots that are not provisioned to belong to any channel (PROV bit in the corresponding word of the transmit channel provision RAM in the TCAS672 block set low) transmit the contents of the Idle Time-slot Fill Data register. Figure 32 - Channelised E1 Transmit Link Timing TeLKin) ULLAL PULL TD[n] _ |Be|B7/B8| B1 |B2|B3/B4| B5|B6|B7|B8/B1/B2|B3/B4 Ts 31 | FAS / NFAS | TS 1 | Ts2 14.5 PCI Interface APCI burst read cycle is shown In Figure 33. The cycle is valid for target and initiator accesses. The target is responsible for incrementing the address during PROPRIETARY AND CONFIDENTIAL 294r = [\ fi q PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 the data burst. The 'T' symbol stands for a turn around cycle. A turn around cycle is required on all signals which can be driven by more than one agent. During Clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEBJ3:0] lines with the read command. In the example below, the command would indicate a burst read. The IRDYB, TRDYB and DEVSELB signals are in turnaround mode (i.e. no agent is driving the signals for this clock cycle). This cycle on the PCI bus is called the address phase. During Clock 2, the initiator ceases to drive the AD[31:0] bus in order that the target can drive it in the next cycle. The initiator also drives the C/BEB[3:0] lines with the byte enables for the read data. IRDYB is driven active by the initiator to indicate it is ready to accept the data transfer. All subsequent cycles on the PCI bus are called data phases. During Clock 3, the target claims the transaction by driving DEVSELB active. It also places the first data word onto the AD[31:0] bus and drives TRDYB to indicate to the initiator that the data is valid. During Clock 4, the initiator latches in the first data word. The target negates TRDYB to indicate to the initiator that it is not ready to transfer another data word. During Clock 5, the target places the second data word onto the AD[31:0] bus and drives TRDYB to indicate to the initiator that the data is valid. During Clock 6, the initiator latches the second data word and negates IRDYB to indicate to the target that it is not ready for the next transfer. The target shall drive the third data word until the initiator accepts it. During Clock 7, the initiator asserts IRDYB to indicate to the target it is ready for the third data word. It also negates FRAMEB since this shall be the last transfer. During Clock 8, the initiator latches in the last word and negates IRDYB. The target, having seen FRAMEB negated in the last clock cycle, negates TRDYB and DEVSELB. All of the above signals shall be driven to their inactive state in this clock cycle, except for FRAMEB which shall be tristated. The target shall stop driving the AD[31:0] bus and the initiator shall stop driving the C/BEB[3:0] bus; this shall be the turnaround cycle for these signals. PROPRIETARY AND CONFIDENTIAL 295r = [\ fi Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 33 PCI Read Cycle 4 pcicLK [of] ro [] PLL aa FRAMEB | pO AD[31:0] Data1_| Data2] Datas_ -)_ C/BEB[3:0] BusCmd] Byte Enable_| _ByteEnable | Byte Enable --(} IRDyB | | | TRDYB | | DEVSELB [StS A PCI burst write transaction is shown in Figure 34. The cycle is valid for target and initiator accesses. The target is responsible for incrementing the address for the duration of the data burst. The 'T' symbol stands for a turn around cycle. A turn around cycle is required on all signals which can be driven by more than one agent. During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command (in the above example the command would indicate a burst write). The IRDYB, TRDYB and DEVSELB signals are in turnaround mode (no agent is driving the signals for this clock cycle). This cycle on the PCI bus is called the address phase. During clock 2, the initiator ceases to drive the address onto the AD[81:0] bus and starts driving the first data word. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write data. IRDYB is driven active by the initiator to indicate it is ready to accept the data transfer. The target claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator that it is ready to accept the data. All subsequent cycles on the PCI bus are called data phases. During clock 3, the target latches in the first data word. The initiator starts to drive the next data word onto the AD[31:0] lines. During clock 4, the target latches in the second data word. Both the initiator and the target indicate that they are not ready to transfer any more data by negating the ready lines. PROPRIETARY AND CONFIDENTIAL 296r > [\ A PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET eee ee eee ne es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 During clock 5, the initiator is ready to transfer the next data word so it drives the AD[31:0] lines with the third data word and asserts IRDYB. The initiator negates FRAMEB since this is the last data phase of this cycle. The target is still not ready so a wait state shall be added. During clock 6, the target is still not ready so another wait state is added. During clock 7, the target asserts TRDYB to indicate that it is ready to complete the transfer. During clock 8, the target latches in the last word and negates TRDYB and DEVSELB, having seen FRAMEB negated previously. The initiator negates IRDYB. All of the above signals shall be driven to their inactive state in this clock cycle except for FRAMEB which shall be tristated. Figure 34 PCI Write Cycle 1 2 3 4 5 6 7 8 9 PeicLK | [LJoLJI LI LI Le LI LE LI L FRAMEB ~_| | @ AD[31:0] Address]Data1 | Data2 | Data 3 --_ C/BEB[3:0] Bus Cmd | Byte En] Byte En | Byte Enable tt) IRDYB. Ld | TRDYB | | | | DEVSELB | | The PCI Target Disconnect (Figure 35) illustrates the case when the target wants to prematurely terminate the current cycle. Note, when the FREEDM-32P672 is the target, it never prematurely terminates the current cycle. A target can terminate the current cycle by asserting the STOPB signal to the initiator. Whether data is transferred or not depends on the state of the ready signals at the time that the target disconnects. If the FREEDM-32P672 is the initiator and the target terminates the current access, the FREEDM-32P672 will retry the access after two PCI bus cycles. During clock 1, an access is in progress. PROPRIETARY AND CONFIDENTIAL 297rl fi ra PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET eee ee ener eee e eee cence eee eee eee ee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 During clock 2, the target indicates that it wishes to disconnect by asserting STOPB. Data may be transferred depending on the state of the ready lines. During clock 3, the initiator negates FRAMEB to signal the end of the cycle. During clock 4, the target negates STOPB and DEVSELB in response to the FRAMEB signal being negated. Figure 35 PCI Target Disconnect 3 4 5 6 1 2 PeictK | LJ |[_J LJ LI LI Le FRAMEB | Oo STOPB | | DEVSELB | The PCI Target Abort Diagram (Figure 36) illustrates the case when the target wants to abort the current cycle. Note, when the FREEDM-32P672 is the target, it never aborts the current cycle. A target abort is an indication of a serious error and no data is transferred. A target can terminate the current cycle by asserting STOPB and negating DEVSELB. If the FREEDM-32P672 is the initiator and the target aborts the current access, the abort condition is reported to the PCI Host. During clock 1, a cycle is in progress. During clock 2, the target negates DEVSELB and TRDYB and asserts STOPB to indicate an abort condition to the initiator. During clock 3, the initiator negates FRAMEB in response to the abort request. During clock 4, the target negates STOPB signal in response to the FRAMEB signal being negated. PROPRIETARY AND CONFIDENTIAL 298r > [\ y/ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 36 PCI Target Abort 1 2 3 4 5 6 PeickkK [| L_J LJ LJ Lo Lf | aN FRAMEB VY TRDYB ss STOPB | DEVSELB | The PCI Bus Request Cycle Diagram (Figure 37) illustrates the case when the initiator is requesting the bus from the bus arbiter. When the FREEDM-32P672 is the initiator, it requests the PCI bus by asserting its REQB output to the central arbiter. The arbiter grants the bus to the FREEDM-32P672 by asserting the GNTB line. The FREEDM-32P672 will wait till both the FRAMEB and IRDYB lines are idle before starting its access on the PCl bus. The arbiter can remove the GNTB signal at any time, but the FREEDM-32P672 will complete the current transfer before relinquishing the bus. Figure 37 PCI Bus Request Cycle 1 2 3 4 5 6 Peickk | LJ LI LJ LI LI | REQB | | GNTB Ld (TY FRAMEB | Y The PCI Initiator Abort Termination Diagram (Figure 38) illustrates the case when the initiator aborts a transaction on the PCI bus. An initiator may terminate a cycle if no target claims it within five clock cycles. A target may not have responded because it was incapable of dealing with the request or a bad address was generated by the initiator. IRDYB must be valid one clock after FRAMEB is deasserted as in a normal cycle. When the PROPRIETARY AND CONFIDENTIAL 299r- [\ /| q PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 FREEDM-32P672 is the initiator and aborts the transaction, it reports the error condition to the PCI Host. Figure 38 PCI Initiator Abort Termination 1 2 3 4 5 6 7 PcIcLK | [| | LJ LJ] LJ LI LJ | FRAMEB | (TY TRDYB Y IRDYB | | (T) DEVSELB YY The PCI Exclusive Lock Cycle Diagram (Figure 39) illustrates the case when the current initiator locks the PCI bus. The FREEDM-32P672 will never initiate an lock, but will behave appropriately when acting as a target. During clock 1, the present initiator has gained access of the LOCKB signal and the PCI bus. The first cycle of a locked access must be a read cycle. The initiator asserts FRAMEB and drives the address of the target on the AD[31:0] lines. During clock 2, the present initiator asserts LOCKB to indicate to the target that a locked cycle is in progress. During clock 3, the target samples the asserted LOCKB signal and marks itself locked. The data cycie has to complete in order for the lock to be maintained. If for some reason the cycle was aborted, the initiator must negate LOCKB. During clock 4, the data transfer completes and the target is locked. During clock 6, another initiator may use the PCI bus but it cannot use the LOCKB signal. If the other initiator attempts to access the locked target that it did not lock, the target would reject the access. During clock 7, the same initiator that locked this target accesses the target. The initiator asserts FRAMEB and negates LOCKB to re-establish the lock. During clock 8, the target samples LOCKB deasserted and locks itself. PROPRIETARY AND CONFIDENTIAL 300DATASHEET ee ee creer rece eee eee eee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 During clock 9, the initiator does not want to continue the lock so it negates LOCKB. The target samples LOCKB and FRAMEB deasserted it removes its lock. Figure 39 PCI Exclusive Lock Cycle 2 3 4 5 6 7 8 9 1 Peiclk [| |_| L_J L_] | fay FRAMEB _| | Oo, cree OO AD[31:0] . Locks | ee nn ee IRDvB. OO COO Trova OL Op DEVSELB~ Oe OFT Fast back-to-back transactions are used by an initiator to conduct two consecutive transactions on the PCI bus without the required idle cycle between them. This can only occur if there is a guarantee that there will be no contention between the initiator or targets involved in the two transactions. In the first case, an initiator may perform fast back-to-back transactions if the first transaction is a write and the second transaction is to the same target. All targets must be able to decode the above transaction. In the second case, all of the targets on the PCI bus support fast back-to-back transactions, as indicated in the PCI Status configuration register. The FREEDM-32P672 only supports the first type of fast back-to-back transactions and is shown in Figure 40. * e e , a a s oO n n During clock 1, the initiator drives FRAMEB to indicate the start of a cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command. In this example the command would indicate a single write. The IRDYB, TRDYB and DEVSELB signals are in turnaround mode and are not being driven for this clock cycle. This cycle on the PCI bus is called the address phase. During clock 2, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving the data element. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write data. IRDYB is driven active by the initiator to indicate that the data is valid. PROPRIETARY AND CONFIDENTIAL 301r [\ fl Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 The initiator negates FRAMEB since this the last data phase of this cycle. The target claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator that it is ready to accept the data. During clock 3, the target latches in the data element and negates TRDYB and DEVSELB, having seen FRAMEB negated previously. The initiator negates IRDYB and drives FRAMEB to start the next cycle. It also drives the address onto the AD[31:0] bus and drives the C/BEB[3:0] lines with the write command. in this example the command would indicate a burst write. During clock 4, the initiator ceases to drive the address onto the AD[31:0] bus and starts driving the first data element. The initiator also drives the C/BEB[3:0] lines with the byte enables for the write data. IRDYB is driven active by the initiator to indicate that the data is valid. The target claims the transaction by driving DEVSELB active and drives TRDYB to indicate to the initiator that it is ready to accept the data. During clock 5, the initiator is ready to transfer the next data element so it drives the AD[31:0] lines with the second data element. The initiator negates FRAMEB since this is the last data phase of this cycle. The target accepts the first data element and negates TRDYB to indicate its is not ready for the next data element. During clock 6, the target is still not ready so a wait state shall be added. During clock 7, the target asserts TRDYB to indicate that it is ready to complete the transfer. During clock 8, the target latches in the last element and negates TRDYB and DEVSELB, having seen FRAMEB negated previously. The initiator negates IRDYB. All of the above signals shall be driven to their inactive state in this clock cycle, except for FRAMEB which shall be tristated. The target stops driving the AD[31:0] bus and the initiator stops driving the C/BEB[3:0] bus. This shall be the turnaround cycle for these signals. PROPRIETARY AND CONFIDENTIAL 302r> [\ AI PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee eee ee es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 40 PCI Fast Back to Back 1 2 3 4 5 6 7 8 9 PcicLK |} LJ LJ} LI LJ LI LI LI | fa FRAMEB | | | DD AD[31:0] {Address] Data [Address] Data | Data (1) C/BEB[3:0] |Bus Cma] Byte En| Bus Cm Byte Enable Ha-_ IRDYB C | | | TRDYB | | | | | | DEVSELB | | | | 14.6 BERT Interface The timing relationship between the receive link clock and data (RCLK[n] / RD[n]) and the receive BERT port signals (RBCLK / RBD) is shown in Figure 41. BERT is not supported for H-MVIP links. For non H-MVIP links, the selected RCLKj[n] is placed on RBCLK after an asynchronous delay. The selected receive link data (RD[n]) is sampled on the rising edge of the associated RCLK[n] and transferred to RBD on the falling edge of RBCLK. Figure 41 Receive BERT Port Timing RCLKin) [ULLAL MALLS RD[n] |B1| B2}B3| B4] x [B5| x| x | x }B6]B7] Bs B1] x | RBD | |B1/B2/B3} B4 | BS |Be]B7|B8| Bt The timing relationship between the transmit link clock and data (TCLK[n] / TD[n]) and the transmit BERT port signals (TBCLK / TBD) is shown in Figure 42. BERT is not supported for H-MVIP links. TCLK[n] is shown to have an arbitrary gapping. When TCLK)[n] is quiescent, TBD is ignored (X in Figure 42). The selected TCLK[n] is buffered and placed on TBCLK. The transmit BERT data PROPRIETARY AND CONFIDENTIAL 303i > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 (TBD) is sampled on the rising edge of the TBCLK and transferred to the selected TDj[n] on the falling edge of TCLK[n]. Figure 42 Transmit BERT Port Timing TeLKin) PULLS MILL Tectk [IP LT_S AA] TBD [B1] B2]B3} B4| x |B5| x | x x |B6|B7| B8}B1| x |B2 TD[n] | |B1/B2|B3] B4 | B5 |B6|B7/B8| Bt PROPRIETARY AND CONFIDENTIAL 304DATASHEET PMC-1990262 PV Cc PMC-Sierra, Inc. PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 15 ABSOLUTE MAXIMUM RATINGS Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal operating conditions. Table 33 FREEDM-32P672 Absolute Maximum Ratings Case Temperature under Bias -40C to +85C | Storage Temperature -40C to +125C Supply Voltage (+3.3 Volt Vpp3.3) | -0.3V to +4.6V Supply Voltage (+2.5 Volt Vpp2.5) | -0.3V to +3.5V Voltage on Any non-PCl Pin -0.3V to +6.0V Voltage on Any PCI Pin -0.5V to Vpop3.3 + 0.5V Temperature Static Discharge Voltage +1000 V Latch-Up Current +100 mA DC Input Current +20 mA Lead Temperature +230C Absolute Maximum Junction +150C PROPRIETARY AND CONFIDENTIAL 305DATASHEET PMC-1990262 r- [\ fA Cc PMC-Sierra, Inc. ISSUE 4 PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 16 D.C. CHARACTERISTICS (Ta = -40C to +85C, Vpp3.3 = 3.0 V to 3.6 V, Vpp2.5 = 2.3 V to 2.7V) Table 34 - FREEDM-32P672 D.C. Characteristics Symbol Parameter Min Typ Max Units Conditions Vpp3.3.-| 3.3V Power Supply 3.0 3.3 3.6 Volts Note 4. Vpp2.5 | 2.5V Power Supply 2.3 2.5 2.7 Volts | Note 4. VIL PCI Input Low -0.5 0.8 Volts | Guaranteed Input LOW Voltage (Bidirs) Voltage for PCI bidirs. VIL PCI Input Low -0.5 0.6 Volts | Guaranteed Input LOW Voltage (Inputs) Voltage for PCI inputs (PCICLK, IDSEL, LOCKB, GNTB, M66EN). VIH PCI Input High 0.5 * Vpp3.3 | Volts | Guaranteed Input HIGH Voltage VpbD3.3 +0.5 Voltage for PCI inputs/bidirs. | VoL Output or Bi- 0.4 Volts | lo, = -4 mA for all outputs directional Low except TBCLK, RBCLK, Voltage RBD, PCICLKO, where lo. =-8 MA. Note 3. | VOH Output or Bi- 2.4 Volts | lon = 4 MA for all outputs directional High except TBCLK, RBCLK, Voltage RBD, PCICLKO, where lon =8 mA. Note 3. VT+ Schmitt Triggered 2.0 5.5 Volts Input High Voltage VT. Schmitt Triggered -0.2 0.6 Volts Input Low Voltage lLPU Input Low Current +10 45 +100 {YA VIL = GND, Notes 1, 3, 4. lHPU Input High Current -10 0 +10 WA VIH = Vpp, Notes 1, 3 lit Input Low Current -10 0 +10 yA VIL = GND, Notes 2, 3 HH input High Current -10 0 +10 AN VIH = Vpp. Notes 2, 3 PROPRIETARY AND CONFIDENTIAL 306DATASHEET PMC-1990262 r> MV Cc" PMC-Sierra, Inc. PM7380 FREEDM-32P672 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Symbol Parameter Min Typ Max Units Conditions Cin Input Capacitance 5 pF Excludes package. Package typically 2 pF. Note 4. CoutT Output 5 pF All pins. Excludes Capacitance package. Package typically 2 pF. Note 4. Clo Bi-directional 5 pF All pins. Excludes Capacitance package. Package typically 2 pF. Note 4. LPIN Pin Inductance 2 nH _All pins. Note 4. IDDOP Operating Current. 245 mA Vpp2.5 = 2.7V, Outputs Unloaded. RCLK[31:0] = TCLK[31:0] = 2.048 MHz. RMVCK[3:0], TMVCK[3}0], RMV8DC and TMV8DC tied low. Note 4. IDDOP Operating Current. 330 mA Vpp2.5 = 2.7V, Outputs Unloaded. RCLK[2:0] = TCLK[2:0] = 51.84 MHz RCLK[31:3], TCLK[31:3 RMVCK[3:0], TMVCK[3 RMV8DC and TMV8DC 0], tied low. Note 4. Notes on D.C. Characteristics: _ . Input pin or bi-directional pin with internal pull-up resistor. Input pin or bi-directional pin without internal pull-up resistor. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). Typical values are given as a design aid. The product is not tested to the typical values given in the data sheet. PROPRIETARY AND CONFIDENTIAL 307r > [\ fi PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET ee PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 17 FREEDM-32P672 TIMING CHARACTERISTICS (Ta = -40C to +85C, Vpp3.3 = 3.0 V to 3.6 V, Vop2.5 = 2.3 V to 2.7V) Table 35 FREEDM-32P672 Link Input (Figure 43 to Figure 46) Symbol Description Min Max Units RCLK[31:0] Frequency (See Note 3) 1.542 | 1.546 | MHz RCLK[31:0] Frequency (See Note 4) 2.046 | 2.050 | MHz RCLK[2:0] Frequency (See Note 5) 51.84 | MHz RCLK[31:3] Frequency (See Note 5) 10 MHz RCLK[31:0] Duty Cycle 40 60 % RMVCK[3:0] Frequency (See Note 6) 4.092 | 4.100 | MHz RMVCK[3:0] Duty Cycle 40 60 % RMV8DC Frequency (See Note 7) 16.368 | 16.400 | MHz RMV8DC Duty Cycle 40 60 % RMV8FPC Frequency (See Note 8) 4.092 | 4.100 | MHz RMV8FPC Duty Cycle 40 60 % tPavc RMV8DC to RMV8FPC skew -10 10 ns SYSCLK Frequency t 45 MHz SYSCLK Duty Cycle 40 60 %o tSrp RD[2:0] Set-Up Time 1 ns tHrp RD[2:0] Hold Time 2 ns tSrp RD[31:3] Set-Up Time 5 ns tHrp RD[31:3] Hold Time 5 ns tSrp_ 2uvip_ | RD[31:0] Set-Up Time (2.048 Mbps H- 5 ns MVIP Mode) tHrp 2mvip | RD[31:0] Hold Time (2.048 Mbps H- 5 ns MVIP Mode) tSrp_smvip | RD[31:0] Set-Up Time (8.192 Mbps H- 5 ns MVIP Mode) PROPRIETARY AND CONFIDENTIAL 308r- [\ | Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Symbol Description Min Max Units tHRb_smvip | RD[31:0] Hold Time (8.192 Mbps H- 5 ns MVIP Mode) tSrepp RFPB[3:0] Set-Up Time 50 ns tHrepB RFPBJ[3:0] Hold Time 50 ns TSREP8B RFP8B Set-Up Time 50 ns THRFpsB RFP8B Hold Time 50 ns tStpp TBD Set-Up Time (See Note 9) 15 ns tHtsp TBD Hold Time 0 ns + The minimum SYSCLK frequency is one half of PCICLK freqency or 25MHz, whichever is the greater. Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. Applicable only to channelised T1/J1 links and measured between framing bits. 4. Applicable only to channelised E1 links and measured between framing bytes. 5. Applicable only to unchannelised links of any format and measured between any two RCLK rising edges. 6. Applicable only to 2.048 Mbps H-MVIP links and measured between any two RMVCK[n] falling edges. 7. Applicable only to 8.192 Mbps H-MVIP links and measured between any two RMVS8DC falling edges. 8. Applicable only to H-MVIP links and measured between any two RMV8FPC falling edges. 9. TBD set-up time is measured with a 20 pF load on TBCLK. The set-up time increases by typically 1 ns for each 10 pF of extra load on TBCLK. PROPRIETARY AND CONFIDENTIAL 309r [\ /I PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET es PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 43 Receive Data & Frame Pulse Timing (2.048 Mbps H-MVIP Mode) RMVCK[n] / \ / Sepp Pt Reps RFPB[n] M tSep emvip PT ted omvip Figure 44 - Receive Data & Frame Pulse Timing (8.192 Mbps H-MVIP Mode) RMV8FPC / ' / #tSprpsp > A RD[m] (m=8n,8nt1...8n+7) M thHeepgp RFP8B > Pave RMV8DC / \ / M tSep smvip then suvip \ RDjn] / PROPRIETARY AND CONFIDENTIAL 310i ai y/ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET | PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 45 Receive Data Timing (Non H-MVIP Mode) RCLK[n] \ / \ tSrp +e tHe RD[n] Figure 46 - BERT Input Timing TBCLK \ V \ Stapp tH rep TBD Table 36 FREEDM-32P672 Link Output (Figure 47 to Figure 50) Symbol Description Min Max Units TCLK[31:0] Frequency (See Note 4) 1.542 | 1.546 | MHz TCLK[31:0] Frequency (See Note 5) 2.046 | 2.050 | MHz TCLK[2:0] Frequency (See Note 6) 51.84 | MHz TCLK[31:3] Frequency (See Note 6) 10 MHz TCLK[31:0] Duty Cycle 40 60 % TMVCK[3:0] Frequency (See Note 7) 4.092 | 4.100 | MHz TMVCK[3:0] Duty Cycle 40 60 % TMV8DC Frequency (See Note 8) 16.368 | 16.400 MHz TMV8DC Duty Cycle 40 60 % TMV8FPC Frequency (See Note 9) 4.092 | 4.100 | MHz PROPRIETARY AND CONFIDENTIAL 311r [\ v/ PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Symbol Description Min Max Units TMV8FPC Duty Cycle 40 60 % tPmvc TMV8DC to TMV8FPC skew -10 10 ns tStTepB TFPB[3:0] Set-Up Time 50 ns tHTEPB TFPB[3:0] Hold Time 50 ns TStepsB TFP8B Set-Up Time 50 ns THTFspB TFP8B Hold Time 50 ns tPtp TCLK[2:0] Low to TD[2:0] Valid 3 12 ns tPtp TCLK[31:3] Low to TD[31:3] Valid 4 25 ns tPtp omvip | TMVCK[3:0] Low to TD[31:0] Valid 4 25 ns ~ (2.048 Mbps H-MVIP Mode) tPtp suvip | TMV8DC Low to TD[31:0] Valid 4 25 ns ~ (8.192 Mbps H-MVIP Mode) tPrep RBCLK Low to RBD Valid -5 5 ns Notes on Output Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs, except for the TD[2:0] outputs, which are measured with a 20pF load, and the PCI outputs/bidirs, which are measured with a 10pF load. Maximum propagation delay for TD[2:0] increases by typically 1 ns for each 10 pF of extra load. 3. Output propagation delays of signal outputs that are specified in relation to a reference output are measured with a 50 pF load on both the signal output and the reference output. 4. Applicable only to channelised T1/J1 links and measured between framing bits. 5. Applicable only to channelised E1 links and measured between framing bytes. 6. Applicable only to unchannelised links of any format and measured between any two TCLK rising edges. PROPRIETARY AND CONFIDENTIAL 312i 2 [\ I q PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 7. Applicable only to 2.048 Mbps H-MVIP links and measured between any two TMVCK{[n] falling edges. 8. Applicable only to 8.192 Mbps H-MVIP links and measured between any two TMV8DC falling edges. 9. Applicable only to H-MVIP links and measured between any two TMV8FPC falling edges. 10. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. Figure 47 Transmit Data & Frame Pulse Timing (2.048 Mbps H-MVIP Mode) TMVCK[n}] / \ / Stepp Pt tHtrpp TFPB[n] @- tPrD omvip TD[m] (m=8n,8n+1...8n+7) PROPRIETARY AND CONFIDENTIAL 313rl fA PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 48 Transmit Data & Frame Pulse Timing (8.192 Mbps H-MVIP Mode) TMV8FPC f/ \ / tStepsp >< Hr epee TFP8B > + tPrive TMV8DC f \, / Mt tPtp smvip TD[n] Figure 49 Transmit Data Timing (Non H-MVIP Mode) TCLK(n] / \ / le tPtp TDIn] PROPRIETARY AND CONFIDENTIAL 314r > [\ /\ PMC-Sierra, inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 50 - BERT Output Timing RBCLK / \ / e tPrep RBD Table 37 PCI Interface (Figure 51) Symbol Description Min Max Units PCICLK Frequency (See Note 1) 25 66 MHz PCICLK Duty Cycle 40 60 % tSpc, All PCI Input and Bi-directional Set- | 4 ns | up time to PCICLK tHpc All PCI Input and Bi-directional Hold | 0.5 ns | time to PCICLK tPpc| PCICLK to all PC! Outputs Valid 2 8.5 ns | tZp, PCI Output active from PCICLK to 14 ns Tristate tZNec) All PCI Outputs Tristate from 2 ns PCICLK to active Notes on PCI Timing: 1. PCICLK cannot change frequency without resetting the FREEDM-32P672 device. 2. The phrase ali PCI Outputs in the above table excludes PCIINTB and PCICLKO. PROPRIETARY AND CONFIDENTIAL 318DATASHEET PMC-1990262 ri fi Cc" PMC-Sierra, Inc. ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 PM7380 FREEDM-32P672 Figure 51 PCI Interface Timing PCICLK \ j oN tS tH PC] ->y+ PCI PCI INPUT 1 tP i+ PCI PC! OUTPUT ! tZ j-_ PCI PCI TRISTATE Data Valid OUTPUT ere PC! TRISTATE Data Valid OUTPUT Table 38 JTAG Port Interface (Figure 52) 2a vel Symbol Description Min Max Units TCK Frequency 1 MHz TCK Duty Cycle 40 60 % tStms TMS Set-up time to TCK 50 ns tHruis TMS Hold time to TCK 50 ns tStp) TDI Set-up time to TCK 50 ns tHtp; TDI Hold time to TCK 50 ns tPrpo TCK Low to TDO Valid 2 60 ns PROPRIETARY AND CONFIDENTIAL 316r? [\ /\ PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 Figure 52 JTAG Port Interface Timing 10x \ !\ le tStyseee TH Tvs ms K le tS tp) eee HH TD) > TDI x |. _'P too TDO PROPRIETARY AND CONFIDENTIAL 317DATASHEET PMC-1990262 r-i\ A Cc" PMC-Sierra, Inc. PM7380 FREEDM-32P672 FRAME ENGINE AND DATA LINK MANAGER 32P672 18 ORDERING AND THERMAL INFORMATION Table 39 FREEDM-32P672 Ordering Information PART NO. DESCRIPTION PM7380-PI 329 Plastic Ball Grid Array (PBGA) Table 40 FREEDM-32P672 Thermal Information PART NO. AMBIENT TEMPERATURE Theta Ja PM7380-PI -40C to +85C 25 C/W PROPRIETARY AND CONFIDENTIAL 318r- Mi Y PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET aS PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 19 MECHANICAL INFORMATION Figure 53 329 Pin Plastic Ball Grid Array (PBGA) Note The FREEDM-32P672 is manufactured using the 4-layer variant of the package shown in the drawing below. >fa]} D Oy[e-20) (2x) Di : Bl CORNER Ar BALL 9 BOE Ce Px IN io 010 MIC | 22 20 18 18 14:12 10 8 6 4 2 A 2302499 97:95 1944 364 1 J o.20] (2x) b E Ooo pA : pe gece | 86 6000 | O 6 oo00]r es gage |: AIBALL 7] oo ooag i INDICATOR | 00 90900 0000 | * i 60 90000 0000 |: | i Ea E co 90000 ooo0|m Py 0 90600 o000|N pe See8b Beet eo oood|t e888 ages: Oooo Sece | # A fe : 2399 | . en i oo as J 8 a ac 45 CHAMFER YA 4 PLACES da? DIA. _ | 3 PLACES TOP VIEW BOTTOM VIEW A Ae "\ wet +4 | //[epe [c} f ft , Errers b c At \ NL SEATING PLANE SIDE VIEW NOTES: 1} ALL DIMENSIONS IN MILLIMETER. 2) DIMENSION aaa DENOTES COPLANARITY. 3) DIMENSION bbb DENOTES PARALLEL. PACKAGE TYPE : 329 PLASTIC BALL GRID ARRAY - PBGA BODY SIZE : 31 x 31 x 2.33 MM (4 layer) . c Dim. ladeoleden| At | A2| 0 [ort e fer! 11 J | b [eSeleSenl d | e [Px | Py [aaa |bbb Min. | 2.12 |] 2.12 10.50 | 1.12 730.80}25.50 30.80} 25.50 - - 0.60 - - . - 27.84 (27.84 - - Nom | 2.33 | 2.33 | 0.60 } 1.17 [31.00 [26.00 }31.00}26.00/1.53 | 1.53 }0.76 | 0.56 ]0.56 | 1.0 |1.27 427.94/27.94| - Max. | 2.54 | 2.56[0.70 | 1.22 [31.20126.70 |31.20|26.70 - - 0.90 - - - - 28.04[28.04}0.15 | 0.15 PROPRIETARY AND CONFIDENTIAL 319r> [\ /| PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET a PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 NOTES PROPRIETARY AND CONFIDENTIAL 320i 2 [\ Y/| PMC-Sierra, Inc. PM7380 FREEDM-32P672 DATASHEET PMC-1990262 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER 32P672 CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Application Information: apps@pmc-sierra.com Web Site: http:/Avww.pmc-sierra.com None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. 2000 PMC-Sierra, Inc PMC-1990262 (14) ref PMC-1980531 (r6) Issue date: July 2000 PMC-Sierra, inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604.415.6000