MT9M131C12STCH ES - ON SEMICONDUCTOR

Products and specifications discussed herein are subject to change by Aptina without notice.

MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Features

PDF:6163688301/Source:7457997359 Aptina reserves the right to change products or specifications without notice.

1/6-Inch SOC VGA CMOS Digital Image Sensor

MT9V112I2ASTC

For the latest data sheet, refer to Aptina’s Web site: www.aptina.com

Features

•Aptina

® DigitalClarity™ CMOS Imaging technology

• System-On-a-Chip (SOC)—Completely integrated

camera system

• Ultra-low power, low cost, progressive scan CMOS

image sensor

• Superior low-light performance

• On-chip image flow processor (IFP) performs

sophisticated processing:

• Color recovery and correction

•Sharpening

• Gamma

• Lens shading correction,

• On-the-fly defect correction

• Filtered image downscaling to arbitrary size with

smooth, continuous zoom and pan

• Automatic Features:

• Auto exposure (AE)

• Auto white balance (AWB)

• Auto black reference (ABR)

•Auto flicker avoidance

• Auto color saturation

• Auto defect identification and correction

• Fully automatic Xenon and LED-type flash support,

fast exposure adaptation

• Multiple parameter contexts, easy/fast mode

switching

• Camera control sequencer automates:

•Snapshots

• Snapshots with flash

• Video clips

•Simple two-wire serial programming interface

• ITU-R BT.656 (YCbCr), 565RGB, 555RGB, or 444RGB

formats (progressive scan)

• Raw and processed Bayer formats

Applications

• Cellular phones

•PDAs

•Toys

• Other battery-powered products

Notes:1.Measured at 1.0 lux*sec and 100% stauration

Ordering Information

Table 1: Key Performance Parameters

Parameter typical Value

Optical Format 1/6-inch (4:3)

Active Imager Size 2.30mm(H) x 1.73mm(V)

2.88mm Diagonal

Active Pixels 640H x 480V

Pixel Size 3.6μm x 3.6μm

Color Filter Array RGB Bayer Pattern

Shutter type Electronic Rolling Shutter

(ERS)

Maximum Data Rate/

Master Clock

12 MPS–13.5 MPS/

24 MHz–27 MHz

Frame Rate (VGA 640H x 480V) 30 fps at 27 MHz

ADC Resolution 10-bit, on-chip

Responsivity 1.0V/lux-sec (550nm)

Dynamic Range 71dB

SNRMAX 44dB1

Supply Voltage I/O Digital 1.7V–3.1V

(VDD nominal)

Core Digital 1.7V–1.9V or 2.5V–3.1V

(1.8V or 2.8V nominal)

Analog 2.5V–3.1V

(2.8V nominal)

Power Consumption 76mW at 1.8V, 15 fps

Operating temperature –30°C to +70°C

Packaging 36-Ball ICSP, wafer or die

Table 2: Available Part Numbers

Part Number Description

MT9V112I2ASTC 36-Ball iCSP (standard)

MT9V112I9ASTC 36-Ball iCSP (lead-free)

MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Table of Contents

PDF:6163688301/Source:7457997359 Aptina eserves the right to change products or specifications without notice.

Table of Contents

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Register Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Typical Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Dout[7:0] Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Viewfinder/Preview and Full-Resolution/Snapshot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Preview Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Tuning Frame Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Typical Resolutions, Modes, and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

RESET, Clocks, and STANDBY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

STANDBY Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Bus Idle State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Two-Wire Serial Interface Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

16-Bit Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

8-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

36-Ball ICSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

PDF:6163688301/Source:7457997359 Aptina reserves the right to change products or specifications without notice.

MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

List of Figures

Figure 1: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 2: Internal Registers Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3: Typical Configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: 36-Ball ICSP Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5: Primary Sensor Core Clock Relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 6: Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 7: Horizontal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 8: AC Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 9: Typical Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 10: Write Timing to R0x09:0—Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 11: Read Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 12: Write Timing to R0x09:0—Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 13: Read Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 14: Two-wire Serial Bus Signal Timing at the Pins of the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 15: Two-wire Serial Bus Signal Timing at the Pins of the Sensor(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 16: 36-Ball ICSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

List of Tables

PDF:6163688301/Source:7457997359 Aptina eserves the right to change products or specifications without notice.

List of Tables

Table 1: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 3: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 4: Data Ordering in YCbCr Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 5: Output Data Ordering in Processed Bayer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 6: Output Data Ordering in RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 7: Output Data Ordering in (8 + 2) Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 9: Blanking Parameter Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 8: Register Address Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 10: User Blanking Minimum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 11: Blanking Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 12: STANDBY Effect on the Output State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 13: Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 14: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 15: DC Electrical Characteristics (Condition 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 16: DC Electrical Characteristics (Condition 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 17: I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 18: Operating Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 19: STANDBY Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 20: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 21: Two-Wire Interface ID Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 22: Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

General Description

PDF:6163688301/Source:7457997359 Aptina eserves the right to change products or specifications without notice.

General Description

The Aptina MT9V112 is a VGA-format, single-chip camera CMOS active-pixel digital

image sensor. this device combines the MT9V012 image sensor core with fourth-genera-

tion digital image flow processor technology from Aptina Imaging. It captures high-

quality color images at VGA resolution.

The VGA CMOS image sensor features DigitalClarity—the Aptina breakthrough low-

noise CMOS imaging technology that achieves CCD image quality (based on signal-to-

noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and inte-

gration advantages of CMOS.

The sensor is a complete camera-on-a-chip solution designed specifically to meet the

low-power, low-cost demands of battery-powered products such as cellular phones,

PDAs, and toys. It incorporates sophisticated camera functions on-chip and is program-

mable through a simple two-wire serial interface.

The MT9V112 performs sophisticated processing functions including color recovery,

color correction, sharpening, programmable gamma correction, auto black reference

clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens shading correc-

tion, auto white balance, and on-the-fly defect identification and correction. Additional

features include day/night mode configurations; special camera effects such as sepia

tone and solarization; and interpolation to arbitrary image size with continuous filtered

zoom and pan. The device supports both Xenon and LED-type flash light sources in

several snapshot modes.

The MT9V112 can be programmed to output progressive-scan images up to 30 frames

per second (fps). The image data can be output in any one of six 8-bit formats:

• ITU-R BT.656 (formerly CCIR656, progressive scan only) YCbCr

• 565RGB

• 555RGB

• 444RGB

• Raw Bayer

•Processed Bayer

The FRAME_VALID and LINE_VALID signals are output on dedicated balls, along with a

pixel clock that is synchronous with valid data.

Functional Overview

The MT9V112 is a fully-automatic, single-chip camera, requiring only a power supply,

lens, and clock source for basic operation. Output video is streamed via a parallel 8-bit

DOUT port, shown in Figure 1, Functional Block Diagram, on page 6. The output pixel

clock is used to latch data, while FRAME_VALID and LINE_VALID signals indicate the

active video. The MT9V112 internal registers are configured using a two-wire serial inter-

face.

MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Functional Overview

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Figure 1: Functional Block Diagram

The device can be put in a low-power sleep mode by asserting STANDBY and shutting

down the clock. Output signals can be tri-stated. Both tri-stating output signals and

entry in STANDBY mode also can be achieved via two-wire serial interface register

writes.

The MT9V112 accepts input clocks up to 27 MHz, delivering up to 30 fps for VGA resolu-

tion images.

Internal Architecture

Internally, the MT9V112 consists of a sensor core and an image flow processor. The IFP is

divided in two sections: the colorpipe (CP), and the camera controller .

The sensor core captures raw Bayer-encoded images that are then input to the IFP.

The CP section of the IFP processes the incoming stream to create interpolated, color-

corrected output, and the CC section controls the sensor core to maintain the desired

exposure and color balance, and to support snapshot modes.

The sensor core, CP, and CC registers are grouped in three separate address spaces,

shown in Figure 2, Internal Registers Grouping, on page 7.

SRAM

Line Buffers

Image Flow Processor

Colorpipe

Image Flow Processor

Camera Control

Image Data

Control Bus

(Two-Wire Serial

Interface Transactions)

Pixel Data

SCLK

SDATA

CLKIN

STANDBY

VDDQ/DGND

/DGND

VAA /AGND

VAAPIX

Lens shading correction

Color interpolation

Filtered resize and zoom

Defect correction

Color correction

Gamma correction

Color conversion + formatting

Auto exposure

Auto white balance

Flicker detect/avoid

Camera control:

Snapshots, flash, video clip

OUT [7:0]

PIXCLK

FRAME_ V ALI D

LINE_ V ALI D

STROBE

Control Bus

(Two-Wire Serial Interface Transactions)

+ Sensor control (gains, shutter, etc.)

Sensor Core

. 640H x 480V

. 1/6-inch optical format

. Auto black compensation

. Programmable analog gain

. Programmable exposure

. 10-bit ADC

. H/W context switch to/from preview

. Bayer RGB output

Control Bus

(Two-Wire Serial

Interface

Transactions)

VDD

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Functional Overview

Figure 2: Internal Registers Grouping

Notes:

Internal registers are grouped in three address spaces. Program R240 selects the desired address space.

The register notation is defined in the section below. When accessing internal registers

via the two-wire serial interface, select the desired address space by programming the

R240 register.

The sensor registers are summarized in Table 12, “Sensor Registers – Address Page 0,” on

page 70. The colorpipe registers are summarized in Table 8, “Colorpipe Registers –

Address Page 1,” on page 20. The camera control registers are summarized in Table 9,

“Camera Control Registers – Address Page 2,” on page 23.

The following register address notations are used:

• R<decimal address>:<address page>

Example: R9:0—Shutter width register in sensor page (page 0). Used to uniquely

specify a register.

• R<decimal address>

Example: R240—Page address register. Used when the register address is global

in all three pages or when by context the address page is understood.

• 0x<2 digit hex address>

Example: 0xF0—Page address register. Used when the register address is global

in all three pages, or when by context the address page is understood.

• 0x<3 digit hex address>

Example: 0x105— Page 1, Aperture Correction register (0x05). Same as 0x<2 digit

hex address> notation; leading digit signifies page number.

When accessing internal registers via the two-wire serial interface, select the desired

address space by programming the R240 register.

The MT9V112 accelerates mode-switching with hardware-assisted context switching,

and supports taking snapshots, flash snapshots, and video clips using a configurable

sequencer.

Image Flow Processor

Sensor Core

Registers

R0:0–

R255:0

Page 0

Color Pipeline

Registers

Page 1

Camera Control

Registers

R0:2–

R255:2

Page 2

R0:1–

R255:1

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Typical Connections

The MT9V112 supports a range of color formats derived from four primary color repre-

sentations: YCbCr, RGB, raw Bayer (unprocessed, directly from the sensor), and pro-

cessed Bayer (Bayer format data regenerated from processed RGB). The device also

supports a variety of output signaling/timing options:

• Standard FRAME_VALID/LINE_VALID video interface with gated pixel clocks

• ITU-R BT.656 marker-embedded video interface with either gated or uniform pixel

clocking

Typical Connections

Figure 3, Typical Configuration (connection), on page 8 shows typical MT9V112 device

connections. For low-noise operation, the MT9V112 requires separate power supplies

for analog and digital. Incoming digital and analog ground conductors can be tied

together next to the die. Both power supply rails should be decoupled to ground using

capacitors. The use of inductance filters is not recommended.

The MT9V112 also supports different digital core (VDD/DGND) and I/O power (VDDQ/

DGND) power domains that can be at different voltages.

Figure 3: Typical Configuration (connection)

Notes: 1. MT9V112 STANDBY can be connected to customer’s ASIC controller directly or to

Digital GND, depending on the capability of the controller.

2. A 1.5KΩ resistor value is recommended, but may be greater for slower two-wire speed.

3. The bus connecting the sensor to the camera port is called the pixel bus.

GND

0.1µF

GND

1µF

0.1µF

GND

1µF

Q VAAPIX

1µF

GND

0.1µF 1µF

Power

VAAPIX

Power

1.5kW

DATA

SCLK

RESET#

TEST_ENABLE

FRAME_VALID

PIXCLK

LINE_VALID

OUT

[7:0]

CLKIN

ADDR

STANDBY

GND

Q D

GND

Power

VAAPIX

To CMOS

Camera

Port

To Xenon

or LED

Flash Driver

Two-Wire

Serial Interface

Master Clock

STROBE

STANDBY from

Controller

or Digital GND

RESET#

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Typical Connections

Figure 4: 36-Ball ICSP Assignment

Top View

(Ball Down)

DOUT3

DGND

DOUT2

DOUT

VDDQ

PIXCLK

DOUT5

DOUT4

DGND

STROBE

SCLK

VDD

DOUT0

DOUT1

DOUT

SADDR

VDD

DOUT7

DOUT6

DGND

STAND

VDD

LINE

VDD

VAA

AGND

VAAPIX

CLKIN

VDDQ

FRAME

DGND

SDATA

_LSB0 _LSB1

RESET#

_VALID

TEST_

ENABLE

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Typical Connections

Notes: 1. A proper reset sequence requires an active CLKIN signal after the RESET# signal has been driven low. For

more details about the reset sequence refer to the MT9V112 Developer Guide.

Table 3: Ball Descriptions

Ball Assignment Name Type Description

A5 CLKIN Input Master clock in sensor.

E4 RESET# Input Active LOW: RESET1.

E1 SADDR Input Two-Wire Serial Interface Device ID selection 1:0xBA, 0:0x90.

D5 TEST_ENABLE Input Tie to DGND for normal operation. (Manufacturing use only.)

F3 SCLK Input Two-Wire Serial Interface Clock.

F4 STANDBY Input Multifunctional signal to control device addressing, power-down, and state

functions (covering output enable function).

F5 SDATA Input/Output Two-Wire Serial Interface Data I/O.

B1, C1, C2, A2, B3,

A3, B4, A4 DOUT[7:0]2Output Pixel Data Output bit 0, DOUT[7] (most significant bit (MSB)), DOUT[0] (least

significant bit (LSB)).

D1 DOUT_LSB0 Output Sensor bypass mode output 0—typically left unconnected for normal SOC

operation.

D2 DOUT_LSB1 Output Sensor bypass mode output 1—typically left unconnected for normal SOC

operation.

C5 FRAME_VALID Output Active HIGH: FRAME_VALID; indicates active frame.

B6 LINE_VALID Output Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel.

F2 PIXCLK Output Pixel clock output.

E3 STROBE Output Active HIGH: STROBE (Xenon) or turn on (LED) flash.

E6 AGND Supply Analog ground.

B2, C3, C4, D3,

D4, E5

DGND Supply Core digital ground.

D6 VAA Supply Analog power: 2.5V–3.1V (2.8V nominal).

F6 VAAPIX Supply Pixel array analog power supply: 2.5V–3.1V (2.8V nominal).

A1, A6, C6, F1 VDD Supply Core digital power: 1.7V–1.9V or 2.5V–3.1V (1.8V or 2.8V nominal).

B5, E2 VDDQ Supply I/O digital power: 1.7V–3.1V (VDD nominal).

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Typical Connections

DOUT[7:0] Output Data Ordering

Data ordering formats are defined in the following tables.

Table 4: Data Ordering in YCbCr Mode

Mode Byte Byte + 1 Byte + Byte + 3

Default Cbi Yi Cri Yi+1

Swap CrCb Cri Yi Cbi Yi+1

SwapYC Yi Cbi Yi+1 Cri

Swap CrCb, SwapYC Yi Cri Yi+1 Cbi

Table 5: Output Data Ordering in Processed Bayer Mode

Mode Line Byte Byte + 1 Byte + 2 Byte + 3

Default First Gi Ri+1 Gi+2 Ri+3

Second Bi Gi+1 Bi+2 Gi+3

Flip Bayer Col First Ri Gi+1 Ri+2 Gi+3

Second Gi Bi+1 Gi+2 Bi+3

Flip Bayer Row First Bi Gi+1 Bi+2 Gi+3

Second Gi Ri+1 Gi+2 Ri+3

Flip Bayer Col,

Flip Bayer Row

First Gi Bi+1 Gi+2 Bi+3

Second Ri Gi+1 Ri+2 Gi+3

Table 6: Output Data Ordering in RGB Mode

Mode

(Swap disabled) Byte D7 D6 D5 D4 D3 D2 D1 D0

RGB565 First R7 R6 R5 R4 R3 G7 G6 G5

Second G4 G3 G2 B7 B6 B5 B4 B3

RGB555 First 0R7R6R5R4R3G7G6

Second G5 G4 G3 B7 B6 B5 B4 B3

RGB444x First R7R6 R5R4G7G6G5G4

SecondB7B6B5B40000

RGBx444 First 0 0 0 0 R7 R6 R5 R4

Second G7 G6 G5 G4 B7 B6 B5 B4

Table 7: Output Data Ordering in (8 + 2) Bypass Mode

Mode Byte D7 D6 D5 D4 D3 D2 D1 D0

8 + 2 bypassFirstB9B8B7B6B5B4B3B2

Second000000B1B0

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Modes and Timing

This section provides .an overview of typical usage modes for the MT9V112.

Contexts

The MT9V112 supports hardware-accelerated context switching. A number of parame-

ters have two copies of their setup registers; this allows two “contexts” to be loaded at

any given time. These are referred to as context A and context B. Context selection for

any single parameter is determined by the global context control register (GCCR, see

R200:2).

There are copies of this register in each address page. A write to any one of them has the

identical effect. However, a read from address page 0 only returns the subset bits of R200

that are specific to the sensor core.

Contexts are generically named because they can be utilized for a variety of purposes.

One typical usage model is to define context A as viewfinder or preview mode and

context B as snapshot mode. The device defaults are configured with this in mind. this

mechanism enables the user to have settings for viewfinder and snapshot modes loaded

at the same time, and then switch between them with a single write to a register (e.g.,

R200:2).

Viewfinder/Preview and Full-Resolution/Snapshot Modes

No context switching is necessary in the sensor core because this is a single ADC device.

Context switching occurs in the colorpipe stage.

Preview Mode

QVGA (320 x 240) images are generated at up to 30 fps. The reduced-size images are gener-

ated by a scaling down operation. The sensor always outputs a VGA size image to the

colorpipe in both context A and context B.

Snapshot Mode

VGA (640 x 480) images are generated at up to 30 fps. this is typically selected by setting

R200:n[10] = 1 selecting resize/zoom context B.

Switching Modes

Typically, switching to snapshot mode is achieved by writing R200:2 = 0x9F0B. this

restarts the sensor and sets most contexts to context B. Following this write, a read from

R200:1 or R200:2 results in 0x1F0B being read.

The MSB is cleared automatically by the sensor. A read from R200:0 results in 0x000B, as

only the lower 4 bits and the restart MSB are implemented in the sensor core.

Clocks

The sensor core is a master in the system. The sensor core frame rate defines the overall

image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced

by the sensor configuration, and are also a function of certain image flow pipeline func-

tions—particularly resize. The relationship of the primary clocks are depicted in Figure 5

on page 13.

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Modes and Timing

The image flow pipeline typically generates up to 16-bits per pixel—for example, YCbCr

or RGB565—but has only an 8-bit port through which to communicate this pixel data.

There is no phase-locked loop (PLL), so the primary input clock (CLKIN) must be twice

the fundamental pixel rate (defined by the sensor pixel clock).

To generate VGA images at 30 fps, the sensor core requires a clock in the 24 MHz–

27 MHz range. The device defaults assume a 24 MHz clock, and minimum clock

frequency is 2 MHz.

Figure 5: Primary Sensor Core Clock Relationships

Note: If R13:0[12] = 0 then the Master Clock will be equal to the frequency of CLKIN.

If R13:0[12] = 1 then the Master Clock will be 1/2 of the frequency of CLKIN.

Frequency of Master Clock = 2*Frequency of Pixel Clock

Tuning Frame Rates

Actual frame rates can be tuned by adjusting various sensor parameters. The sensor

registers are in address page 0, some of which are shown in Table 8.

10 bits/pixel

1 pixel/clock

16 bits/pixel

1 pixel/clock

16 bits/pixel (typical)

0.5 pixel/clock

Output Interface

Pixel Clock

Master Clock

Sensor Core

CLKIN

R13:0[12]

Colorpipe

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Modes and Timing

Default Blanking Calculations

the MT9V112 default blanking calculations are shown in Table 9.

In the MT9V112, the sensor core adds four border pixels all the way around the image,

taking the active image size to 648 x 488 in full power mode. this is achieved through the

default settings:

• Oversize and show border bits are set by default

• Oversize and show border bits are not context switchable, and therefore, their loca-

tion is only in read mode context B.

Table 8: Register Address Functions

R0x04:0 Column width, typically 640 in the MT9V112

R0x03:0 Row width, typically 480 in the MT9V112

R0x07:0, R0x05:0 Horizontal blanking, default is 203 (units of sensor pixel clocks)

R0x08:0, R0x06:0 Vertical blanking, default is 11

(rows including black rows)

Table 9: Blanking Parameter Calculations

Parameter Calculation

PC_PERIOD Sensor Pixel Clock Period (2/24)μs = 0.083μs

A: Active Data time (per line): R0 x 04:0 + 8 (border) * PC_PERIOD 648 x (2/24) = 54μs

Q: Horizontal Blanking: [R0 x 05:0 | R0 x 07:0] * PC_PERIOD 154 x (2/24) = 12.83μs

Row time = Q + A 66.83μs

P: Frame Start / End Blanking: 6 * PC_PERIOD 6 x (2/24) = 0.5μs

V: Vertical Blanking: [R0 x 06:0 | R0 x 08:0] * (Q + A) + (Q - 2 * P) (11 x 66.83) + (12.83 - 1.0) = 747μs

F: Total Frame time: (R0 x 03:0 + [R0 x 06:0 | R00 x 08:0]) * (Q + A) (488 + 11) x 66.83μs = 33349.83 ?s ≥ 30 fps

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Modes and Timing

User Blanking Calculations

When calculating blanking for different clock rates, minimum values for horizontal

blanking and vertical blanking must be taken into account. Table 10 shows minimum

values for each register.

Output Timing

Figure 6: Vertical Timing

Figure 7: Horizontal Timing

Table 10: User Blanking Minimum Values

Parameter Minimum

Horizontal Blanking 132 (sensor pixel clocks)

Vertical Blanking 6 + Reg0x22:0[2:0] rows

Line 0 Line 1 LineN-3 LineN-2 LineN-1

Line 0

RAME_VALID

LINE_VALID

D[7:0]

DBCA

NO DATA

10 FF 00 00 80 CB0 Y0 CR1 Y1 CB3 Y3 CRn

-1 Yn FF 00 00 9D

PIXCLK

INE_VALID

D[7:0]

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Modes and Timing

Typical Resolutions, Modes, and Timing

The parameters listed in Table 11 are illustrated in a waveform diagram, Figure 6,

Vertical Timing, on page 15. Figure 20, AC Electrical Characteristics, on page 23 provides

values for these parameters in some common resolutions and operating modes.

Table 11: Blanking Definitions

Designation Definition

(A) FRAME_VALID (rising edge) to LINE_VALID (rising edge) delay

(B) LINE_VALID (falling edge) to FRAME_VALID (falling edge) delay

(D) LINE_VALID (LOW/horizontal blanking) time

(E) FRAME_VALID (HIGH/valid) time

(F) FRAME_VALID (LOW/vertical blanking) time

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Modes and Timing

RESET, Clocks, and STANDBY

RESET

Power-up reset is asserted/de-asserted on RESET#. It is active LOW. In this reset state, all

control registers have the default values.

Soft reset is asserted/de-asserted by the two-wire serial interface program. In soft-reset

mode, the two-wire serial interface and register ring bus are still running. All control

registers are reset using default values. See R13:0.

Clocks

The MT9V112 has two primary clocks; a master clock coming from the CLKIN signal,

and a pixel clock via a clock-gated operation running at half frequency of the master

clock. All device clocks are turned off in power-down mode. When the MT9V112 oper-

ates in sensor stand-alone mode, the image flow pipeline clocks can be shut off to

conserve power. See R13:0.

When the MT9V112 is operated with the MT9M111 in a dual-camera application, the

MT9V112 employs a divide-by-two clock option, allowing a 54 MHz input to the master

clock. For more information about this feature, see the R13:0 register description on

page 74 in Table 13.

STANDBY

STANDBY is a multifunctional signal that controls power-down, device addressing, and

tri-state functions. Table 12 shows how STANDBY affects the output signal state. When

the sensor is in standby mode (hard or soft) CLKIN must be active (toggling) for

commands and data to be received by the two-wire serial interface bus.

Hard standby is asserted/de-asserted on STANDBY. It is active HIGH. In this hard

standby state, all internal clocks are turned off and the analog block is in STANDBY

mode to save power consumption. The signal state is High-Z when R13:0[4] = 0 and

R13:0[6] = 0.

Two-wire interface ID addressing is based on the result of SADDR XOR R13:0[10]. (The

R13:0[10] default is “0”.) the R13:0[10] bit is not writable when STANDBY is asserted “1.”

Soft standby is asserted/de-asserted by a two-wire serial interface to R13:0[2]. In soft

standby, all internal clocks are turned off, the analog block is in standby mode, but the

signal state is not affected. Following the assertion of either hard or soft STANDBY, the

analog circuitry completes reading the current row and then enters the standby state. It

is necessary to keep clocking the sensor for an entire row time to ensure proper entry

into the standby state.

Table 12: STANDBY Effect on the Output State

Output

Disable

R13:0[4] Drive Signal

R13:0[6] STANDBY Output State

000Driven

001High-Z

01xDriven

1xxHigh-Z

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Electrical Specifications

Operating Conditions

Note: Recommended die operating temperature range is from Ta = –20°C to 40°C. The sensor image quality may

degrade above 40°C.

Notes: 1. Stresses above those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions above those indicated in the product specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliabil-

ity.

Table 13: Operating Conditions

Symbol Definition MIN Typical MAX Units

VDDQ I/O Digital Voltage 1.7 VDD 3.1 V

VDD Core Digital Voltage (condition 1) 2.5 2.8 3.1 V

Core Digital Voltage (condition 2) 1.7 1.8 1.9 V

VAA Analog Voltage 2.5 2.8 3.1 V

VAAPIX Pixel Supply Voltage 2.5 2.8 3.1 V

TCOperating temperature ( At Junction) –30 30 70 °C

Table 14: Absolute Maximum Ratings

Symbol Parameter Condition

Rating

UnitMIN MAX

VDD Digital power (2.8V) -0.3 4.0 V

VDDQ I/O power -0.3 4.0 V

VAA Analog power (2.8V) -0.3 4.0 V

VAAPIX Pixel array power -0.3 4.0 V

VIN DC Input Voltage -0.3 VDDQ+0.3 V

VOUT DC Output Voltage -0.3 VDDQ+0.3 V

TSTG1Storage temperature -40 85 °C

ILZ High Impedance Output

Leakage Current

VIN = VDDQ or DGND -10 10 μA

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Electrical Specifications

DC Electrical Characteristics

Table 15: DC Electrical Characteristics (Condition 1)

VDD = 2.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30°C, Light Condition = Dark

Symbol Definition MIN Typical MAX Units

VIH Voltage Input High 2.5 2.8 3.1 V

VIL Voltage Input Low –0.3 0 0.3 V

IIL Current Input leakage Low –5 5 μA

IIH Current Input leakage High –5 5 μA

VOH Voltage Output High VDDQ-0.3 VDDQ V

VOL Voltage Output Low 000.3V

IOH Current Output High 12 15 mA

IOL Current Output Low 14 17 mA

Table 16: DC Electrical Characteristics (Condition 2)

VDD = 1.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 1.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30°C, Light Condition = Dark

Symbol Definition MIN Typical MAX Units

VIH Voltage Input High 1.7 1.8 1.9 V

VIL Voltage Input Low –0.3 0 0.3 V

IIL Current Input leakage Low –5 5 μA

IIH Current Input leakage High –5 5 μA

VOH Voltage Output High VDDQ-0.3 VDDQ V

VOL Voltage Output Low 0 0 0.3 V

IOH Current Output High 8 10 mA

IOL Current Output Low 10 12 mA

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Electrical Specifications

I/O Parameters

Note: I/O pins exhibit the characteristics of either the input signals or the output signals as defined in this

table depending on the mode of the pin.

Table 17: I/O Parameters

VAA = 2.8V, VAAPIX = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30°C, Light Condition = Dark

Signal Parameter Definitions Condition Min Typical Max Units

All

Outputs

Load capacitance 30 pF

Output signal slew VDD = VDDQ = 2.8V, 30pF load 0.25 1.25 V/ns

VDD = VDDQ = 1.8V, 30pF load 0.1 0.6 V/ns

All Inputs Signal CAP Input signal capacitance 5 pF

CLKIN freq Master clock frequency Absolute minimum 2 MHz

VGA at 30 fps 24 27 MHz

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Electrical Specifications

Power Consumption

STANDBY Power Consumption

Table 18: Operating Power Consumption

VAA = 2.8V, VAAPIX = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30 °C,Light Condition = 90 lux

Mode fps Definition (VDD,VDDQ = 2.8V) (VDD,VDDQ = 1.8V) Units

TYP MAX TYP MAX

VGA 30 fps Operating IDD 15 25 9 16 mA

Operating IAA 19 22 19 22 mA

Operating IDDQ 11 30 5 17 mA

Operating IAAPIX 1111mA

VGA 30 fps Total power consumption w/o IDDQ 98 136 72 94 mW

VGA 15 fps Operating IDD 15 20 9 12 mA

Operating IAA 19 22 19 22 mA

Operating IDDQ 10 19 5 11 mA

Operating IAAPIX 1111mA

VGA 15 fps Total power consumption w/o IDDQ 98 122 72 88 mW

QVGA 30 fps Operating IDD 15 25 9 15 mA

Operating IAA 19 22 19 22 mA

Operating IDDQ 9144 8mA

Operating IAAPIX 1212mA

QVGA 30 fps Total power consumption w/o IDDQ 98 136 72 94 mW

QVGA 15 fps Operating IDD 15 20 9 12 mA

Operating IAA 19 22 19 22 mA

Operating IDDQ 8114 7mA

Operating IAAPIX 1111mA

QVGA 15 fps Total power consumption w/o IDDQ 98 121 72 88 mW

Table 19: STANDBY Power Consumption

VAA = 2.8V, VAAPIX = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30 °C

Definition MAX

(VDD,VDDQ = 2.8V) MAX

(VDD,VDDQ = 1.8V) Units

Hard STANDBY IDD (without clock) 1 1 μA

Hard STANDBY IDDQ (without clock) 4 2 μA

Hard STANDBY IAA (without clock) 1 1 μA

Hard STANDBY IAAPIX (without clock) 1 1 μA

Total Power Consumption (without clock) 20 11 μW

Hard STANDBY IDD (with clock) 821 487 μA

Hard STANDBY IDDQ (with clock) 22 8 μA

Hard STANDBY IAA (with clock) 1 1 μA

Hard STANDBY IAAPIX (with clock) 1 1 μA

Total Power Consumption (with clock) 2366 897 μW

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Electrical Specifications

I/O Timing

By default, the MT9V112 launches pixel data, FRAME_VALID, and LINE_VALID synchro-

nously with the falling edge of PIXCLK. The expectation is that the user captures data,

FRAME_VALID, and LINE_VALID using the rising edge of PIXCLK. The timing diagram is

shown in Figure 8. As an option, the polarity of the PIXCLK can be inverted from the

default. this is achieved by programming R58:1[9] or R155:1[9] to “0.”

Figure 8: AC Output Timing Diagram

PHLp

PLHp

FVSETUP

LVSETUP

DSETUP

DHOLD

CLKIN _ HIGH

CLKIN _ LOW

PIXCLK _ HIGH

PIXCLK _ LOW

CLK

PIXCLK

OUT

[7:0]

OUT

[7:0] D

OUT

[7:0]

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Electrical Specifications

AC Electrical Characteristics

Table 20: AC Electrical Characteristics

VDD = 2.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30°C,

Light Condition = Dark

Symbol Definition MIN Typical MAX Units

fCLKIN Input clock frequency 13.5 27 MHz

tRPixel clock rise time 10 ns

tFPixel clock fall time 10 ns

tPLHP CLKIN to PIXCLK propagation delay (L–H) 48 ns

tPHLP CLKIN to PIXCLK propagation delay (H–L) 48 ns

tLVSETUP Setup time for LINE_VALID before rising edge of

PIXCLK

1/2 PIXCLK

Period

tFVSETUP Setup time for FRAME_VALID before rising edge

of PIXCLK

1/2 PIXCLK

Period

tDSETUP Setup time for DOUT before rising edge of

PIXCLK

1/2 PIXCLK

Period

tDHOLD Hold time for DOUT after rising edge of PIXCLK 1/2 PIXCLK

Period

tCLKIN_HIGH Master clock duty cycle (High time) 40 50 60 %

tCLKIN_LOW Master clock duty cycle (Low time) 40 50 60 %

tPIXCLK_HIGH Pixel clock duty cycle (High time) 40 50 60 %

tPIXCLK_LOW Pixel clock duty cycle (Low time) 40 50 60 %

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Electrical Specifications

Spectral Characteristics

Figure 9: Typical Spectral Characteristics

Quantum Efficiency

350 450 550 650 750 850 950 1050

Quantum Efficiency (%)

Wavelength (nm)

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Appendix A

Serial Bus Description

Registers are written to and read from the MT9V112 through the two-wire serial inter-

face bus. The sensor is a serial interface slave controlled by the serial clock (SCLK),

which is driven by the serial interface master. Data is transferred in and out of the

MT9V112 through the serial data (SDATA) line. The SDATA line is pulled up to VDDQ off-

chip by a 1.5KΩ resistor. Either the slave or the master device can pull the SDATA line

down—the serial interface protocol determines which device is allowed to pull the SDATA

line down at any given time.

Protocol

The two-wire serial interface defines several different transmission codes, as follows:

•Start bit

• (No) Acknowledge bit

•8-bit message

•Stop bit

• Slave device 8-bit address

SADDR and R13:0[10] are used to select between two different addresses in case of

conflict with another device. If SADDR XOR R13:0[10] is LOW, the slave address is 0x90; if

SADDR XOR R13:0[10] is HIGH, the slave address is 0xBA. See Table 21.

Sequence

A typical read or write sequence begins with the master sending a start bit. After the start

bit, the master sends the 8-bit slave device address. The last bit of the address determines

if the request is a read or a write, where a “0” indicates a write and a “1” indicates a read.

The slave device acknowledges its address by sending an acknowledge bit back to the

master.

If the request was a write, the master transfers the 8-bit register address for where a write

should take place. The slave sends an acknowledge bit to indicate that the register

address has been received. The master then transfers the data, eight bits at a time, with

the slave sending an acknowledge bit after each eight bits.

The MT9V112 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers

to write to one register. After 16 bits are transferred, the register address is automatically

incremented, so that the next 16 bits are written to the next register address. The master

stops writing by sending a start or stop bit.

A typical read sequence is executed as follows. The master sends the write mode slave

address and 8-bit register address, just as in the write request. The master then sends a

start bit and the read mode slave address. The master clocks out the register data, eight

Table 21: Two-Wire Interface ID Switching

SADDR R13:0[10] Two-Wire Interface ID

0 0 0x90

0 1 0xBA

1 0 0xBA

1 1 0x90

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Two-Wire Serial Interface Sample

bits at a time, and sends an acknowledge bit after each 8-bit transfer. The register

address is auto-incremented after every 16 bits is transferred. The data transfer is

stopped when the master sends a no-acknowledge bit.

Bus Idle State

The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-

ated with a start bit, and the bus is released with a stop bit. Only the master can generate

the start and stop bits.

Start Bit

The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line

is HIGH.

Stop Bit

The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line

is HIGH.

Slave Address

The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit

of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates

read mode. The write address of the sensor is 0xBA; the read address is 0xBB. This

applies only when the SADDR is set HIGH.

Data Bit Transfer

One data bit is transferred during each clock pulse. The serial interface clock pulse is

provided by the master. The data must be stable during the HIGH period of the two-wire

serial interface clock—it can only change when the serial clock is LOW. Data is trans-

ferred eight bits at a time, followed by an acknowledge bit.

Acknowledge Bit

The master generates the acknowledge clock pulse. The transmitter (which is the master

when writing, or the slave when reading) releases the data line, and the receiver signals

an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse.

No-Acknowledge Bit

The no-acknowledge bit is generated when the data line is not pulled down by the

receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate

a read sequence.

Two-Wire Serial Interface Sample

Write and read sequences (SADDR = 1).

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Two-Wire Serial Interface Sample

16-Bit Write Sequence

A typical write sequence for writing 16 bits to a register is shown in Figure 10. A start bit

sent by the master starts the sequence, followed by the write address. The image sensor

sends an acknowledge bit and expects the register address to come first, followed by the

16-bit data. After each 8-bit transfer, the image sensor sends an acknowledge bit.

All 16 bits must be written before the register is updated. After 16 bits are transferred, the

next register. The master stops writing by sending a start or stop bit.

Figure 10: Write Timing to R0x09:0—Value 0x0284

16-Bit Read Sequence

A typical read sequence is shown in Figure 11. The master writes the register address, as

in a write sequence. Then a start bit and the read address specify that a read is about to

occur from the register. The master then clocks out the register data, 8 bits at a time. The

master sends an acknowledge bit after each 8-bit transfer.

The register address should be incremented after every 16 bits is transferred. The data

transfer is stopped when the master sends a no-acknowledge bit.

Figure 11: Read Timing from R0x09:0; Returned Value 0x0284

SCLK

DATA

0xBA Address

Start Sto

ACK ACK ACK ACK

Reg 0x09 0000 0010 1000 0100

SCLK

SDATA

0xBA Address

Start Start Stop

ACK ACK ACK ACK NACK

Reg0x09 0xBB Address 0000 0010 1000 0100

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Two-Wire Serial Interface Sample

8-Bit Write Sequence

To be able to write one byte at a time to the register, a special register address is added.

The 8-bit write is started by writing the upper eight bits to the desired register, then

writing the lower eight bits to the special register address (R0xF1:0). The register is not

updated until all 16 bits have been written. It is not possible to update just half of a

written to the special register (R0xF1:0).

Figure 12: Write Timing to R0x09:0—Value 0x0284

8-Bit Read Sequence

To read one byte at a time, the same special register address is used for the lower byte.

The upper eight bits are read from the desired register. By following this with a read from

the special register (R0xF1:0), the lower eight bits are accessed (Figure 13). The master

sets the no-acknowledge bits.

Figure 13: Read Timing from R0x09:0; Returned Value 0x0284

SCLK

DATA

0xBA Address

Start Sto

ACK

ACK ACK

ACK

Reg0x09 0xBA Address

Start ACKACK

Reg0xF10000 0010 1000 0100

SCLK

DATA

0xBA Address

Start Start

ACK ACK ACK NACK

Reg0x09 0xBB Address 0000 0010

SCLK

DATA

0xBA Address

Start Start Stop

ACK ACK ACK NACK

Reg0xF1 0xBB Address 1000 0100

• • •

(

continued)

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Two-Wire Serial Interface Sample

Two-wire Serial Bus Timing

The two-wire serial interface operation requires a certain minimum of master clock

cycles between transitions. These are specified in the table below in master clock cycles.

Note: T = one master clock cycle

Figure 14: Two-wire Serial Bus Signal Timing at the Pins of the Sensor

Table 22: Two-wire Serial Bus Timing

VDD = 2.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 1.8V Ta = 55°C

Symbol Definition MIN TYP MAX Units

fic Two_Wire Serial Bus Input Clock Frequency 400 KHz

tic Two-Wire Serial Bus Input Clock period 2500 – – ns

ticl Two-Wire Serial Bus Clock Low 1000 1250 1500 ns

tich Two-Wire Serial Bus Clock High 1000 1250 1500 ns

tiss Setup time for start condition 600 – – ns

tihs Hold time for start condition 600 – – ns

tisd Setup time for input data 600 – – ns

tihd Hold time for input data 600 – – ns

toaa Output data delay time – – 600 ns

toda Output data hold time 600 – – ns

tisp Setup time of stop condition 600 – – ns

tihp Hold time for stop condition 600 – – ns

cIN Input pin capacitance – 3.5 – pF

cLOAD SDATA max load capacitance – – 30 pF

RSD SDATA pull-up resistor – 1.5 – KΩ

tic

ticl tich

tiss tihdtisd

toaa toda

tisp

SCLK

SDATA

(Sensor Receiving

Data from the Master)

SDATA

(Sensor Sending

Data to the Master)

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Two-Wire Serial Interface Sample

Figure 15: Two-wire Serial Bus Signal Timing at the Pins of the Sensor(2)

SCLK

ihs

ihp

SDATA

(Input to Sensor)

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Two-Wire Serial Interface Sample

36-Ball ICSP Package

Figure 16: 36-Ball ICSP Package

Note: All dimensions in millimeters.

SEATING PLANE

5.80 ±0.075

2.90 ±0.051.875

2.90 ±0.05

ENCAPSULANT: EPOXY

IMAGE SENSOR DIE

LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS

OPTICAL AREA

OPTICAL CENTER

PACKAGE CENTER

1.17 ±0.10

0.22

(FOR REFERENCE ONLY)

0.95 (FOR REFERENCE ONLY)

4.00

CTR

2.304 CTR

3.75

4.00

CTR

1.728

CTR

1.875

0.75 TYP

5.80 ±0.075

0.375 ±0.075

0.575 ±0.050

0.175

(FOR REFERENCE ONLY)

3.75

SUBSTRATE MATERIAL: PLASTIC LAMINATE

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR

96.5% Sn, 3% Ag, 0.5% Cu

BALL PADS Ø 0.27 SOLDER MASK DEFINED

0.10 A

BALL A1

BALL A1 ID

BALL A6

36X Ø0.35

DIMENSIONS APPLY TO

SOLDER BALLS POST

REFLOW. THE PRE-REFLOW

DIAMETER IS Ø0.33

BALL A1

CORNER

2.714 ±0.075

0.186

(FOR REFERENCE ONLY)

MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1º

MAXIMUM TILT OF OPTICAL AREA RELATIVE TO 0.3º.

MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3º.

PIXEL

(0,0)

2.900 ±0.075

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MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Revision History

Rev. L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/2/10

• Updated to non-confidential

Rev. K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/5/2010

• Updated to Aptina template

• Transfered registers to a seperate document

Rev. J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/30/2006

• Added note to Table 1 on page 1 and updated Figure 15 on page 6.

Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/10/2006

• Updated Note 2 in Table 3 on page 10.

Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/2/2006

• Updated Table 22 on page 5 for output delay time from 3T to 4T and hold time for

output data from 4T to 3T.

Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/2/2006

• Moved Value of Output Delay Time (3T) from Min column to Max column in Table 22

on page 5.

• Updated descriptions of SDATA in Table 14 on page 5.

Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/19/2006

• Figure 5 on page 13 added more detail and Figure 7: Horizontal Timing on page 15

updated last data out value to 9D (was 90).

• Table 3 definition of RESET changed from async to sync, Table 13 R0x00D Reset Bit 12

definition expanded, Table 12 columns swapped, and Table 17 note added, Table 19

column headings changed from Typical to MAX.

Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/3/2005

• New outline drawing (36_ICSP(5_8x5_8)SMD_MTG-341.eps) per PCN1543-

K12A_PHC, Figure 16 on page 7.

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/29/2005

• R161 changed to R161:1, new description and bits definition

• R161 changed to R164:1, new description

• R13:0[4] new description

• R32:0[10] is now reserved

• R33:0[10] is now reserved

• R40:2[12] new description

•IFP Block Diagram Edit

•Table 1 Edit

• Conversion to 1 column template

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/15/2004

• Operating Conditions

• DC Electrical Characteristics (two conditions)

• Operating Power Consumption

•STANDBY Power Consumption

•Two-Wire Serial Bus Timing

• Two-Wire Serial Bus Signal Timing (two figures)

10 Eunos Road 8 13-40, Singapore Post Center, Singapore 408600 prodmktg@aptina.com www.aptina.com

Aptina, Aptina Imaging, DigitalClarity, and the Aptina logo are the property of Aptina Imaging Corporation

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final,

these specifications are subject to change, as further product development and data characterization sometimes occur.

MT9V112 - SOC VGA DIGITAL IMAGE SENSOR

Revision History

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• AC Electrical Characteristics

•AC Timing Diagram

• Register Summary 0x format

• Register Description - standardized bit value definitions and register format

Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/6/2004

•Initial release