MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Features 1/6-Inch SOC VGA CMOS Digital Image Sensor MT9V112I2ASTC For the latest data sheet, refer to Aptina's Web site: www.aptina.com Features Table 1: * Aptina(R) DigitalClarityTM CMOS Imaging technology * System-On-a-Chip (SOC)--Completely integrated camera system * Ultra-low power, low cost, progressive scan CMOS image sensor * Superior low-light performance * On-chip image flow processor (IFP) performs sophisticated processing: * Color recovery and correction * Sharpening * Gamma * Lens shading correction, * On-the-fly defect correction * Filtered image downscaling to arbitrary size with smooth, continuous zoom and pan * Automatic Features: * Auto exposure (AE) * Auto white balance (AWB) * Auto black reference (ABR) * Auto flicker avoidance * Auto color saturation * Auto defect identification and correction * Fully automatic Xenon and LED-type flash support, fast exposure adaptation * Multiple parameter contexts, easy/fast mode switching * Camera control sequencer automates: * Snapshots * Snapshots with flash * Video clips * Simple two-wire serial programming interface * ITU-R BT.656 (YCbCr), 565RGB, 555RGB, or 444RGB formats (progressive scan) * Raw and processed Bayer formats Parameter typical Value Optical Format Active Imager Size 1/6-inch (4:3) 2.30mm(H) x 1.73mm(V) 2.88mm Diagonal 640H x 480V 3.6m x 3.6m RGB Bayer Pattern Electronic Rolling Shutter (ERS) 12 MPS-13.5 MPS/ 24 MHz-27 MHz 30 fps at 27 MHz 10-bit, on-chip 1.0V/lux-sec (550nm) 71dB 44dB1 1.7V-3.1V (VDD nominal) 1.7V-1.9V or 2.5V-3.1V (1.8V or 2.8V nominal) 2.5V-3.1V (2.8V nominal) 76mW at 1.8V, 15 fps -30C to +70C 36-Ball ICSP, wafer or die Active Pixels Pixel Size Color Filter Array Shutter type Maximum Data Rate/ Master Clock Frame Rate (VGA 640H x 480V) ADC Resolution Responsivity Dynamic Range SNRMAX Supply Voltage I/O Digital Core Digital Analog Power Consumption Operating temperature Packaging Notes:1.Measured at 1.0 lux*sec and 100% stauration Ordering Information Table 2: Available Part Numbers Part Number MT9V112I2ASTC MT9V112I9ASTC Applications * * * * Key Performance Parameters Description 36-Ball iCSP (standard) 36-Ball iCSP (lead-free) Cellular phones PDAs Toys Other battery-powered products PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 1 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation All rights reserved. Products and specifications discussed herein are subject to change by Aptina without notice. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Table of Contents Table of Contents Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Register Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Dout[7:0] Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contexts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Viewfinder/Preview and Full-Resolution/Snapshot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Preview Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Tuning Frame Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Typical Resolutions, Modes, and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 RESET, Clocks, and STANDBY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 STANDBY Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Two-Wire Serial Interface Sample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 8-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 36-Ball ICSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 2 Aptina eserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Internal Registers Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 36-Ball ICSP Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Primary Sensor Core Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Horizontal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 AC Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Typical Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Write Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Read Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Write Timing to R0x09:0--Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Read Timing from R0x09:0; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Two-wire Serial Bus Signal Timing at the Pins of the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Two-wire Serial Bus Signal Timing at the Pins of the Sensor(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 36-Ball ICSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 3 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 9: Table 8: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Data Ordering in YCbCr Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Data Ordering in Processed Bayer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Data Ordering in RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Data Ordering in (8 + 2) Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Blanking Parameter Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Register Address Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 User Blanking Minimum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Blanking Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 STANDBY Effect on the Output State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DC Electrical Characteristics (Condition 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 DC Electrical Characteristics (Condition 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Operating Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 STANDBY Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Two-Wire Interface ID Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 4 Aptina eserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR General Description General Description The Aptina MT9V112 is a VGA-format, single-chip camera CMOS active-pixel digital image sensor. this device combines the MT9V012 image sensor core with fourth-generation digital image flow processor technology from Aptina Imaging. It captures highquality color images at VGA resolution. The VGA CMOS image sensor features DigitalClarity--the Aptina breakthrough lownoise CMOS imaging technology that achieves CCD image quality (based on signal-tonoise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The sensor is a complete camera-on-a-chip solution designed specifically to meet the low-power, low-cost demands of battery-powered products such as cellular phones, PDAs, and toys. It incorporates sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface. The MT9V112 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens shading correction, auto white balance, and on-the-fly defect identification and correction. Additional features include day/night mode configurations; special camera effects such as sepia tone and solarization; and interpolation to arbitrary image size with continuous filtered zoom and pan. The device supports both Xenon and LED-type flash light sources in several snapshot modes. The MT9V112 can be programmed to output progressive-scan images up to 30 frames per second (fps). The image data can be output in any one of six 8-bit formats: * ITU-R BT.656 (formerly CCIR656, progressive scan only) YCbCr * 565RGB * 555RGB * 444RGB * Raw Bayer * Processed Bayer The FRAME_VALID and LINE_VALID signals are output on dedicated balls, along with a pixel clock that is synchronous with valid data. Functional Overview The MT9V112 is a fully-automatic, single-chip camera, requiring only a power supply, lens, and clock source for basic operation. Output video is streamed via a parallel 8-bit DOUT port, shown in Figure 1, Functional Block Diagram, on page 6. The output pixel clock is used to latch data, while FRAME_VALID and LINE_VALID signals indicate the active video. The MT9V112 internal registers are configured using a two-wire serial interface. PDF:6163688301/Source:7457997359 MT9V1112_DS - Rev. L 6/10 EN 5 Aptina eserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Functional Overview Figure 1: Functional Block Diagram SCLK SDATA CLKIN STANDBY Sensor Core SRAM Line Buffers Pixel Data . 640H x 480V . 1/6-inch optical format . Auto black compensation . Programmable analog gain . Programmable exposure . 10-bit ADC . H/W context switch to/from preview . Bayer RGB output Control Bus Control Bus (Two-Wire Serial Interface Transactions) (Two-Wire Serial Interface Transactions) + Sensor control (gains, shutter, etc.) Image Flow Processor Camera Control VDDQ/DGND VDD /DGND VAA /AGND VAAPIX Auto exposure Auto white balance Flicker detect/avoid Camera control: Snapshots, flash, video clip Control Bus (Two-Wire Serial Interface Transactions) Image Data Image Flow Processor Colorpipe Lens shading correction Color interpolation Filtered resize and zoom Defect correction Color correction Gamma correction Color conversion + formatting DOUT [7:0] PIXCLK FRAME_VALID LINE_ VALID STROBE The device can be put in a low-power sleep mode by asserting STANDBY and shutting down the clock. Output signals can be tri-stated. Both tri-stating output signals and entry in STANDBY mode also can be achieved via two-wire serial interface register writes. The MT9V112 accepts input clocks up to 27 MHz, delivering up to 30 fps for VGA resolution images. Internal Architecture Internally, the MT9V112 consists of a sensor core and an image flow processor. The IFP is divided in two sections: the colorpipe (CP), and the camera controller . The sensor core captures raw Bayer-encoded images that are then input to the IFP. The CP section of the IFP processes the incoming stream to create interpolated, colorcorrected output, and the CC section controls the sensor core to maintain the desired exposure and color balance, and to support snapshot modes. Register Overview The sensor core, CP, and CC registers are grouped in three separate address spaces, shown in Figure 2, Internal Registers Grouping, on page 7. PDF:6163688301/Source:7457997359 MT9V1112_DS - Rev. L 6/10 EN 6 Aptina eserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Functional Overview Figure 2: Internal Registers Grouping Image Flow Processor Sensor Core Registers R0:0- R255:0 Color Pipeline Registers R0:1- R255:1 Camera Control Registers R0:2- R255:2 Page 0 Page 1 Page 2 Notes: Internal registers are grouped in three address spaces. Program R240 selects the desired address space. The register notation is defined in the section below. When accessing internal registers via the two-wire serial interface, select the desired address space by programming the R240 register. The sensor registers are summarized in Table 12, "Sensor Registers - Address Page 0," on page 70. The colorpipe registers are summarized in Table 8, "Colorpipe Registers - Address Page 1," on page 20. The camera control registers are summarized in Table 9, "Camera Control Registers - Address Page 2," on page 23. Register Notation The following register address notations are used: * R<decimal address>:<address page> Example: R9:0--Shutter width register in sensor page (page 0). Used to uniquely specify a register. * R<decimal address> Example: R240--Page address register. Used when the register address is global in all three pages or when by context the address page is understood. * 0x<2 digit hex address> Example: 0xF0--Page address register. Used when the register address is global in all three pages, or when by context the address page is understood. * 0x<3 digit hex address> Example: 0x105-- Page 1, Aperture Correction register (0x05). Same as 0x<2 digit hex address> notation; leading digit signifies page number. When accessing internal registers via the two-wire serial interface, select the desired address space by programming the R240 register. The MT9V112 accelerates mode-switching with hardware-assisted context switching, and supports taking snapshots, flash snapshots, and video clips using a configurable sequencer. PDF:6163688301/Source:7457997359 MT9V1112_DS - Rev. L 6/10 EN 7 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Typical Connections The MT9V112 supports a range of color formats derived from four primary color representations: YCbCr, RGB, raw Bayer (unprocessed, directly from the sensor), and processed Bayer (Bayer format data regenerated from processed RGB). The device also supports a variety of output signaling/timing options: * Standard FRAME_VALID/LINE_VALID video interface with gated pixel clocks * ITU-R BT.656 marker-embedded video interface with either gated or uniform pixel clocking Typical Connections Figure 3, Typical Configuration (connection), on page 8 shows typical MT9V112 device connections. For low-noise operation, the MT9V112 requires separate power supplies for analog and digital. Incoming digital and analog ground conductors can be tied together next to the die. Both power supply rails should be decoupled to ground using capacitors. The use of inductance filters is not recommended. The MT9V112 also supports different digital core (VDD/DGND) and I/O power (VDDQ/ DGND) power domains that can be at different voltages. 1.5kW2 Typical Configuration (connection) 1.5kW2 Figure 3: VDDQ Power VDD Power VDDQ VDD VAA VAAPIX Power Power VAA VAAPIX 8 DOUT[7:0] SADDR STANDBY from Controller 1 or Digital GND STANDBY Master Clock To CMOS Camera Port3 PIXCLK LINE_VALID FRAME_VALID CLKIN Two-Wire Serial Interface STROBE SDATA SCLK To Xenon or LED Flash Driver TEST_ENABLE RESET# RESET# DGNDQ VDDQ 0.1F DGND Notes: 0.1F 1F DGND AGND DGND AGND VAAPIX VDD 1F DGND 0.1F VAA 1F AGND 0.1F 1F AGND 1. MT9V112 STANDBY can be connected to customer's ASIC controller directly or to Digital GND, depending on the capability of the controller. 2. A 1.5K resistor value is recommended, but may be greater for slower two-wire speed. 3. The bus connecting the sensor to the camera port is called the pixel bus. PDF:6163688301/Source:7457997359 MT9V1112_DS - Rev. L 6/10 EN 8 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Typical Connections Figure 4: 36-Ball ICSP Assignment 1 2 3 4 5 6 A VDD DOUT3 DOUT5 DOUT7 CLKIN VDD B DOUT0 DGND DOUT4 DOUT6 VDDQ LINE _VALID C DOUT1 DOUT2 DGND DGND FRAME _VALID VDD D DOUT _LSB0 DOUT _LSB1 DGND DGND TEST_ ENABLE VAA E SADDR VDDQ STROBE RESET# DGND AGND F VDD PIXCLK SCLK STAND BY SDATA VAAPIX Top View (Ball Down) PDF:6163688301/Source:7457997359 MT9V1112_DS - Rev. L 6/10 EN 9 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Typical Connections Table 3: Ball Descriptions Ball Assignment Name Type A5 E4 E1 D5 F3 F4 CLKIN RESET# SADDR TEST_ENABLE SCLK STANDBY Input Input Input Input Input Input F5 B1, C1, C2, A2, B3, A3, B4, A4 D1 SDATA Input/Output Output DOUT_LSB0 Output D2 DOUT_LSB1 Output C5 B6 F2 E3 E6 B2, C3, C4, D3, D4, E5 D6 F6 A1, A6, C6, F1 B5, E2 FRAME_VALID LINE_VALID PIXCLK STROBE AGND DGND Output Output Output Output Supply Supply Master clock in sensor. Active LOW: RESET1. Two-Wire Serial Interface Device ID selection 1:0xBA, 0:0x90. Tie to DGND for normal operation. (Manufacturing use only.) Two-Wire Serial Interface Clock. Multifunctional signal to control device addressing, power-down, and state functions (covering output enable function). Two-Wire Serial Interface Data I/O. Pixel Data Output bit 0, DOUT[7] (most significant bit (MSB)), DOUT[0] (least significant bit (LSB)). Sensor bypass mode output 0--typically left unconnected for normal SOC operation. Sensor bypass mode output 1--typically left unconnected for normal SOC operation. Active HIGH: FRAME_VALID; indicates active frame. Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel. Pixel clock output. Active HIGH: STROBE (Xenon) or turn on (LED) flash. Analog ground. Core digital ground. VAA VAAPIX VDD VDDQ Supply Supply Supply Supply Analog power: 2.5V-3.1V (2.8V nominal). Pixel array analog power supply: 2.5V-3.1V (2.8V nominal). Core digital power: 1.7V-1.9V or 2.5V-3.1V (1.8V or 2.8V nominal). I/O digital power: 1.7V-3.1V (VDD nominal). DOUT[7:0]2 Notes: PDF:6163688301/Source:7457997359 MT9V1112_DS - Rev. L 6/10 EN Description 1. A proper reset sequence requires an active CLKIN signal after the RESET# signal has been driven low. For more details about the reset sequence refer to the MT9V112 Developer Guide. 10 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Typical Connections DOUT[7:0] Output Data Ordering Data ordering formats are defined in the following tables. Table 4: Data Ordering in YCbCr Mode Mode Byte Byte + 1 Byte + Byte + 3 Cbi Cri Yi Yi Yi Yi Cbi Cri Cri Cbi Yi+1 Yi+1 Yi+1 Yi+1 Cri Cbi Default Swap CrCb SwapYC Swap CrCb, SwapYC Table 5: Output Data Ordering in Processed Bayer Mode Mode Default Flip Bayer Col Flip Bayer Row Flip Bayer Col, Flip Bayer Row Table 6: Byte Byte + 1 Byte + 2 Byte + 3 Gi Bi Ri Gi Bi Gi Gi Ri Ri+1 Gi+1 Gi+1 Bi+1 Gi+1 Ri+1 Bi+1 Gi+1 Gi+2 Bi+2 Ri+2 Gi+2 Bi+2 Gi+2 Gi+2 Ri+2 Ri+3 Gi+3 Gi+3 Bi+3 Gi+3 Ri+3 Bi+3 Gi+3 Output Data Ordering in RGB Mode Mode (Swap disabled) RGB565 RGB555 RGB444x RGBx444 Table 7: Line First Second First Second First Second First Second Byte D7 D6 D5 D4 D3 D2 D1 D0 First Second First Second First Second First Second R7 G4 0 G5 R7 B7 0 G7 R6 G3 R7 G4 R6 B6 0 G6 R5 G2 R6 G3 R5 B5 0 G5 R4 B7 R5 B7 R4 B4 0 G4 R3 B6 R4 B6 G7 0 R7 B7 G7 B5 R3 B5 G6 0 R6 B6 G6 B4 G7 B4 G5 0 R5 B5 G5 B3 G6 B3 G4 0 R4 B4 Output Data Ordering in (8 + 2) Bypass Mode Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 8 + 2 bypass First Second B9 0 B8 0 B7 0 B6 0 B5 0 B4 0 B3 B1 B2 B0 PDF:6163688301/Source:7457997359 MT9V1112_DS - Rev. L 6/10 EN 11 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Modes and Timing Modes and Timing This section provides .an overview of typical usage modes for the MT9V112. Contexts The MT9V112 supports hardware-accelerated context switching. A number of parameters have two copies of their setup registers; this allows two "contexts" to be loaded at any given time. These are referred to as context A and context B. Context selection for any single parameter is determined by the global context control register (GCCR, see R200:2). There are copies of this register in each address page. A write to any one of them has the identical effect. However, a read from address page 0 only returns the subset bits of R200 that are specific to the sensor core. Contexts are generically named because they can be utilized for a variety of purposes. One typical usage model is to define context A as viewfinder or preview mode and context B as snapshot mode. The device defaults are configured with this in mind. this mechanism enables the user to have settings for viewfinder and snapshot modes loaded at the same time, and then switch between them with a single write to a register (e.g., R200:2). Viewfinder/Preview and Full-Resolution/Snapshot Modes No context switching is necessary in the sensor core because this is a single ADC device. Context switching occurs in the colorpipe stage. Preview Mode QVGA (320 x 240) images are generated at up to 30 fps. The reduced-size images are generated by a scaling down operation. The sensor always outputs a VGA size image to the colorpipe in both context A and context B. Snapshot Mode VGA (640 x 480) images are generated at up to 30 fps. this is typically selected by setting R200:n[10] = 1 selecting resize/zoom context B. Switching Modes Typically, switching to snapshot mode is achieved by writing R200:2 = 0x9F0B. this restarts the sensor and sets most contexts to context B. Following this write, a read from R200:1 or R200:2 results in 0x1F0B being read. The MSB is cleared automatically by the sensor. A read from R200:0 results in 0x000B, as only the lower 4 bits and the restart MSB are implemented in the sensor core. Clocks The sensor core is a master in the system. The sensor core frame rate defines the overall image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced by the sensor configuration, and are also a function of certain image flow pipeline functions--particularly resize. The relationship of the primary clocks are depicted in Figure 5 on page 13. PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 12 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Modes and Timing The image flow pipeline typically generates up to 16-bits per pixel--for example, YCbCr or RGB565--but has only an 8-bit port through which to communicate this pixel data. There is no phase-locked loop (PLL), so the primary input clock (CLKIN) must be twice the fundamental pixel rate (defined by the sensor pixel clock). To generate VGA images at 30 fps, the sensor core requires a clock in the 24 MHz- 27 MHz range. The device defaults assume a 24 MHz clock, and minimum clock frequency is 2 MHz. Figure 5: Primary Sensor Core Clock Relationships 0 CLKIN Master Clock 1 2 Pixel Clock Sensor Core 10 R13:0[12] 10 bits/pixel 1 pixel/clock Colorpipe 16 16 bits/pixel 1 pixel/clock Output Interface 8 Note: 16 bits/pixel (typical) 0.5 pixel/clock If R13:0[12] = 0 then the Master Clock will be equal to the frequency of CLKIN. If R13:0[12] = 1 then the Master Clock will be 1/2 of the frequency of CLKIN. Frequency of Master Clock = 2*Frequency of Pixel Clock Tuning Frame Rates Actual frame rates can be tuned by adjusting various sensor parameters. The sensor registers are in address page 0, some of which are shown in Table 8. PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 13 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Modes and Timing Table 8: Register Address Functions Register Function R0x04:0 R0x03:0 R0x07:0, R0x05:0 R0x08:0, R0x06:0 Column width, typically 640 in the MT9V112 Row width, typically 480 in the MT9V112 Horizontal blanking, default is 203 (units of sensor pixel clocks) Vertical blanking, default is 11 (rows including black rows) Default Blanking Calculations Table 9: the MT9V112 default blanking calculations are shown in Table 9. Blanking Parameter Calculations Parameter Calculation PC_PERIOD Sensor Pixel Clock Period A: Active Data time (per line): R0 x 04:0 + 8 (border) * PC_PERIOD Q: Horizontal Blanking: [R0 x 05:0 | R0 x 07:0] * PC_PERIOD Row time = Q + A P: Frame Start / End Blanking: 6 * PC_PERIOD V: Vertical Blanking: [R0 x 06:0 | R0 x 08:0] * (Q + A) + (Q - 2 * P) F: Total Frame time: (R0 x 03:0 + [R0 x 06:0 | R00 x 08:0]) * (Q + A) (2/24)s = 0.083s 648 x (2/24) = 54s 154 x (2/24) = 12.83s 66.83s 6 x (2/24) = 0.5s (11 x 66.83) + (12.83 - 1.0) = 747s (488 + 11) x 66.83s = 33349.83 ?s 30 fps In the MT9V112, the sensor core adds four border pixels all the way around the image, taking the active image size to 648 x 488 in full power mode. this is achieved through the default settings: * Oversize and show border bits are set by default * Oversize and show border bits are not context switchable, and therefore, their location is only in read mode context B. PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 14 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Modes and Timing User Blanking Calculations When calculating blanking for different clock rates, minimum values for horizontal blanking and vertical blanking must be taken into account. Table 10 shows minimum values for each register. . Table 10: User Blanking Minimum Values Parameter Minimum Horizontal Blanking Vertical Blanking 132 (sensor pixel clocks) 6 + Reg0x22:0[2:0] rows Output Timing Figure 6: Vertical Timing E F FRAME_VALID A C D B LINE_VALID D[7:0] Line 0 Line 1 LineN-3 LineN-2 Line 0 LineN-1 NO DATA Figure 7: Horizontal Timing PIXCLK LINE_VALID D[7:0] PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 10 FF 00 15 00 80 CB0 Y0 CR1 Y1 CB3 Y3 CRn -1 Yn FF 00 00 9D Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Modes and Timing Typical Resolutions, Modes, and Timing Table 11: The parameters listed in Table 11 are illustrated in a waveform diagram, Figure 6, Vertical Timing, on page 15. Figure 20, AC Electrical Characteristics, on page 23 provides values for these parameters in some common resolutions and operating modes. Blanking Definitions Designation (A) (B) (C) (D) (E) (F) PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN Definition FRAME_VALID (rising edge) to LINE_VALID (rising edge) delay LINE_VALID (falling edge) to FRAME_VALID (falling edge) delay LINE_VALID (HIGH/valid) time LINE_VALID (LOW/horizontal blanking) time FRAME_VALID (HIGH/valid) time FRAME_VALID (LOW/vertical blanking) time 16 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Modes and Timing RESET, Clocks, and STANDBY RESET Power-up reset is asserted/de-asserted on RESET#. It is active LOW. In this reset state, all control registers have the default values. Soft reset is asserted/de-asserted by the two-wire serial interface program. In soft-reset mode, the two-wire serial interface and register ring bus are still running. All control registers are reset using default values. See R13:0. Clocks The MT9V112 has two primary clocks; a master clock coming from the CLKIN signal, and a pixel clock via a clock-gated operation running at half frequency of the master clock. All device clocks are turned off in power-down mode. When the MT9V112 operates in sensor stand-alone mode, the image flow pipeline clocks can be shut off to conserve power. See R13:0. When the MT9V112 is operated with the MT9M111 in a dual-camera application, the MT9V112 employs a divide-by-two clock option, allowing a 54 MHz input to the master clock. For more information about this feature, see the R13:0 register description on page 74 in Table 13. STANDBY STANDBY is a multifunctional signal that controls power-down, device addressing, and tri-state functions. Table 12 shows how STANDBY affects the output signal state. When the sensor is in standby mode (hard or soft) CLKIN must be active (toggling) for commands and data to be received by the two-wire serial interface bus. Hard standby is asserted/de-asserted on STANDBY. It is active HIGH. In this hard standby state, all internal clocks are turned off and the analog block is in STANDBY mode to save power consumption. The signal state is High-Z when R13:0[4] = 0 and R13:0[6] = 0. Two-wire interface ID addressing is based on the result of SADDR XOR R13:0[10]. (The R13:0[10] default is "0".) the R13:0[10] bit is not writable when STANDBY is asserted "1." Soft standby is asserted/de-asserted by a two-wire serial interface to R13:0[2]. In soft standby, all internal clocks are turned off, the analog block is in standby mode, but the signal state is not affected. Following the assertion of either hard or soft STANDBY, the analog circuitry completes reading the current row and then enters the standby state. It is necessary to keep clocking the sensor for an entire row time to ensure proper entry into the standby state. Table 12: STANDBY Effect on the Output State PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN Output Disable R13:0[4] Drive Signal R13:0[6] STANDBY Output State 0 0 0 1 0 0 1 x 0 1 x x Driven High-Z Driven High-Z 17 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications Electrical Specifications Operating Conditions Table 13: Operating Conditions Symbol Definition I/O Digital Voltage Core Digital Voltage (condition 1) Core Digital Voltage (condition 2) Analog Voltage Pixel Supply Voltage Operating temperature ( At Junction) VDDQ VDD VAA VAAPIX TC MIN Typical MAX Units 1.7 2.5 1.7 2.5 2.5 -30 VDD 2.8 1.8 2.8 2.8 30 3.1 3.1 1.9 3.1 3.1 70 V V V V V C Note: Recommended die operating temperature range is from Ta = -20C to 40C. The sensor image quality may degrade above 40C. Table 14: Absolute Maximum Ratings Rating Symbol VDD VDDQ VAA VAAPIX VIN VOUT TSTG1 ILZ Parameter Digital power (2.8V) I/O power Analog power (2.8V) Pixel array power DC Input Voltage DC Output Voltage Storage temperature High Impedance Output Leakage Current Notes: PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN Condition VIN = VDDQ or DGND MIN MAX Unit -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 -10 4.0 4.0 4.0 4.0 VDDQ+0.3 VDDQ+0.3 85 10 V V V V V V C A 1. Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the product specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 18 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications DC Electrical Characteristics Table 15: DC Electrical Characteristics (Condition 1) VDD = 2.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30C, Light Condition = Dark Symbol Definition MIN Typical MAX Units VIH Voltage Input High 2.5 2.8 3.1 V VIL Voltage Input Low -0.3 0 0.3 V IIL Current Input leakage Low -5 5 A IIH Current Input leakage High -5 5 A VDDQ-0.3 VDDQ V VOH Voltage Output High VOL Voltage Output Low 0 0.3 V IOH Current Output High 12 15 mA IOL Current Output Low 14 17 mA Table 16: 0 DC Electrical Characteristics (Condition 2) VDD = 1.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 1.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30C, Light Condition = Dark Symbol MIN Typical MAX Units VIH Voltage Input High Definition 1.7 1.8 1.9 V VIL Voltage Input Low -0.3 0 0.3 V IIL Current Input leakage Low 5 A IIH Current Input leakage High -5 -5 5 VOH Voltage Output High VDDQ-0.3 VDDQ A V VOL Voltage Output Low 0 0.3 V IOH Current Output High 8 10 mA IOL Current Output Low 10 12 mA PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 19 0 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications I/O Parameters Table 17: I/O Parameters VAA = 2.8V, VAAPIX = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30C, Light Condition = Dark Signal Parameter Definitions All Outputs All Inputs CLKIN Load capacitance Output signal slew Signal CAP freq Input signal capacitance Master clock frequency Note: PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN Condition Min VDD = VDDQ = 2.8V, 30pF load VDD = VDDQ = 1.8V, 30pF load 0.25 0.1 Absolute minimum VGA at 30 fps 2 24 Typical Max Units 30 1.25 0.6 5 pF V/ns V/ns pF MHz MHz 27 I/O pins exhibit the characteristics of either the input signals or the output signals as defined in this table depending on the mode of the pin. 20 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications Power Consumption Table 18: Operating Power Consumption VAA = 2.8V, VAAPIX = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30 C,Light Condition = 90 lux Mode fps VGA 30 fps VGA VGA 30 fps 15 fps VGA QVGA 15 fps 30 fps QVGA QVGA 30 fps 15 fps QVGA 15 fps Definition Operating IDD Operating IAA Operating IDDQ Operating IAAPIX Total power consumption w/o IDDQ Operating IDD Operating IAA Operating IDDQ Operating IAAPIX Total power consumption w/o IDDQ Operating IDD Operating IAA Operating IDDQ Operating IAAPIX Total power consumption w/o IDDQ Operating IDD Operating IAA Operating IDDQ Operating IAAPIX Total power consumption w/o IDDQ (VDD,VDDQ = 2.8V) (VDD,VDDQ = 1.8V) TYP MAX TYP MAX 15 19 11 1 98 15 19 10 1 98 15 19 9 1 98 15 19 8 1 98 25 22 30 1 136 20 22 19 1 122 25 22 14 2 136 20 22 11 1 121 9 19 5 1 72 9 19 5 1 72 9 19 4 1 72 9 19 4 1 72 16 22 17 1 94 12 22 11 1 88 15 22 8 2 94 12 22 7 1 88 Units mA mA mA mA mW mA mA mA mA mW mA mA mA mA mW mA mA mA mA mW STANDBY Power Consumption Table 19: STANDBY Power Consumption VAA = 2.8V, VAAPIX = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30 C MAX (VDD,VDDQ = 2.8V) MAX (VDD,VDDQ = 1.8V) Hard STANDBY IDD (without clock) 1 1 A Hard STANDBY IDDQ (without clock) 4 2 A Hard STANDBY IAA (without clock) 1 1 A Definition Units Hard STANDBY IAAPIX (without clock) 1 1 Total Power Consumption (without clock) Hard STANDBY IDD (with clock) 20 11 A W 821 487 A Hard STANDBY IDDQ (with clock) 22 8 A Hard STANDBY IAA (with clock) 1 1 A Hard STANDBY IAAPIX (with clock) 1 1 2366 897 A W Total Power Consumption (with clock) PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 21 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications I/O Timing By default, the MT9V112 launches pixel data, FRAME_VALID, and LINE_VALID synchronously with the falling edge of PIXCLK. The expectation is that the user captures data, FRAME_VALID, and LINE_VALID using the rising edge of PIXCLK. The timing diagram is shown in Figure 8. As an option, the polarity of the PIXCLK can be inverted from the default. this is achieved by programming R58:1[9] or R155:1[9] to "0." Figure 8: AC Output Timing Diagram CLK tPHLp tR tPLHp tF tCLKIN _ HIGH tCLKIN _ LOW PIXCLK tPIXCLK _ HIGH t PIXCLK _ LOW tFVSETUP FV tLVSETUP LV tDSETUP tDHOLD DOUT[7:0] DOUT[7:0] PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 22 DOUT[7:0] Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications AC Electrical Characteristics Table 20: AC Electrical Characteristics VDD = 2.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 2.8V, fCLKIN = 27 MHz (50% duty cycle), Ta = 30C, Light Condition = Dark Symbol Definition tDHOLD Input clock frequency Pixel clock rise time Pixel clock fall time CLKIN to PIXCLK propagation delay (L-H) CLKIN to PIXCLK propagation delay (H-L) Setup time for LINE_VALID before rising edge of PIXCLK Setup time for FRAME_VALID before rising edge of PIXCLK Setup time for DOUT before rising edge of PIXCLK Hold time for DOUT after rising edge of PIXCLK tCLKIN_HIGH tCLKIN_LOW tPIXCLK_HIGH tPIXCLK_LOW Master clock duty cycle (High time) Master clock duty cycle (Low time) Pixel clock duty cycle (High time) Pixel clock duty cycle (Low time) fCLKIN tR tF tPLHP tPHLP tLVSETUP tFVSETUP tDSETUP PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 23 MIN Typical MAX Units 27 MHz ns ns ns ns ns 40 40 40 40 13.5 10 10 48 48 1/2 PIXCLK Period 1/2 PIXCLK Period 1/2 PIXCLK Period 1/2 PIXCLK Period 50 50 50 50 ns ns ns 60 60 60 60 % % % % Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Electrical Specifications Spectral Characteristics Figure 9: Typical Spectral Characteristics Quantum Efficiency 40 G 35 R Quantum Efficiency (%) B 30 25 20 15 10 5 0 350 450 550 650 750 850 950 1050 Wavelength (nm) PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 24 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Appendix A Appendix A Serial Bus Description Registers are written to and read from the MT9V112 through the two-wire serial interface bus. The sensor is a serial interface slave controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred in and out of the MT9V112 through the serial data (SDATA) line. The SDATA line is pulled up to VDDQ offchip by a 1.5K resistor. Either the slave or the master device can pull the SDATA line down--the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. Protocol The two-wire serial interface defines several different transmission codes, as follows: * Start bit * (No) Acknowledge bit * 8-bit message * Stop bit * Slave device 8-bit address SADDR and R13:0[10] are used to select between two different addresses in case of conflict with another device. If SADDR XOR R13:0[10] is LOW, the slave address is 0x90; if SADDR XOR R13:0[10] is HIGH, the slave address is 0xBA. See Table 21. Table 21: . Two-Wire Interface ID Switching SADDR R13:0[10] Two-Wire Interface ID 0 0 1 1 0 1 0 1 0x90 0xBA 0xBA 0x90 Sequence A typical read or write sequence begins with the master sending a start bit. After the start bit, the master sends the 8-bit slave device address. The last bit of the address determines if the request is a read or a write, where a "0" indicates a write and a "1" indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master transfers the 8-bit register address for where a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data, eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9V112 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. The master sends the write mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read mode slave address. The master clocks out the register data, eight PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 1 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Two-Wire Serial Interface Sample bits at a time, and sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A "0" in the LSB of the address indicates write mode, and a "1" indicates read mode. The write address of the sensor is 0xBA; the read address is 0xBB. This applies only when the SADDR is set HIGH. Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock--it can only change when the serial clock is LOW. Data is transferred eight bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver signals an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. Two-Wire Serial Interface Sample Write and read sequences (SADDR = 1). PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 2 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Two-Wire Serial Interface Sample 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 10. A start bit sent by the master starts the sequence, followed by the write address. The image sensor sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit transfer, the image sensor sends an acknowledge bit. All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit. Figure 10: Write Timing to R0x09:0--Value 0x0284 SCLK SDATA 0xBA Address Start Reg 0x09 0000 0010 1000 0100 Stop ACK ACK ACK ACK 16-Bit Read Sequence A typical read sequence is shown in Figure 11. The master writes the register address, as in a write sequence. Then a start bit and the read address specify that a read is about to occur from the register. The master then clocks out the register data, 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Figure 11: Read Timing from R0x09:0; Returned Value 0x0284 SCLK SDATA 0xBA Address Reg0x09 0xBB Address Start ACK PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 0000 0010 1000 0100 Start Stop ACK ACK 3 ACK NACK Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Two-Wire Serial Interface Sample 8-Bit Write Sequence To be able to write one byte at a time to the register, a special register address is added. The 8-bit write is started by writing the upper eight bits to the desired register, then writing the lower eight bits to the special register address (R0xF1:0). The register is not updated until all 16 bits have been written. It is not possible to update just half of a register. In Figure 12, a typical sequence for an 8-bit write is shown. The second byte is written to the special register (R0xF1:0). Figure 12: Write Timing to R0x09:0--Value 0x0284 SCLK SDATA Reg0x09 0xBA Address Start ACK 0000 0010 0xBA Address Start ACK ACK Reg0xF1 1000 0100 Stop ACK ACK ACK 8-Bit Read Sequence To read one byte at a time, the same special register address is used for the lower byte. The upper eight bits are read from the desired register. By following this with a read from the special register (R0xF1:0), the lower eight bits are accessed (Figure 13). The master sets the no-acknowledge bits. Figure 13: Read Timing from R0x09:0; Returned Value 0x0284 SCLK SDATA 0xBA Address Reg0x09 0xBB Address Start *** 0000 0010 Start ACK ACK ACK NACK SCLK SDATA 0xBA Address *** (continued) Reg0xF1 0xBB Address Start ACK PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 1000 0100 Start ACK 4 ACK Stop NACK Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Two-Wire Serial Interface Sample Two-wire Serial Bus Timing The two-wire serial interface operation requires a certain minimum of master clock cycles between transitions. These are specified in the table below in master clock cycles. Table 22: Two-wire Serial Bus Timing VDD = 2.8V, VAA = 2.8V, VAAPIX = 2.8V, VDDQ = 1.8V Ta = 55C Symbol fic t ic t icl t ich tiss tihs t isd tihd toaa toda tisp tihp cIN cLOAD RSD Definition Two_Wire Serial Bus Input Clock Frequency Two-Wire Serial Bus Input Clock period Two-Wire Serial Bus Clock Low Two-Wire Serial Bus Clock High Setup time for start condition Hold time for start condition Setup time for input data Hold time for input data Output data delay time Output data hold time Setup time of stop condition Hold time for stop condition Input pin capacitance SDATA max load capacitance SDATA pull-up resistor Note: Figure 14: MIN TYP MAX Units 2500 1000 1000 600 600 600 600 - 600 600 600 - - - - 1250 1250 - - - - - - - - 3.5 - 1.5 400 - 1500 1500 - - - - 600 - - - - 30 - KHz ns ns ns ns ns ns ns ns ns ns ns pF pF K T = one master clock cycle Two-wire Serial Bus Signal Timing at the Pins of the Sensor tic ticl SCLK tich tiss tisd tihd tisp SDATA (Sensor Receiving Data from the Master) toaa toda SDATA (Sensor Sending Data to the Master) PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 5 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Two-Wire Serial Interface Sample Figure 15: Two-wire Serial Bus Signal Timing at the Pins of the Sensor(2) SCLK t ihs t ihp SDATA (Input to Sensor) PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 6 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Two-Wire Serial Interface Sample 36-Ball ICSP Package Figure 16: 36-Ball ICSP Package 0.95 (FOR REFERENCE ONLY) 1.17 0.10 B SEATING PLANE A 0.10 0.22 (FOR REFERENCE ONLY) 0.175 (FOR REFERENCE ONLY) 0.575 0.050 0.75 TYP 36X O0.35 4.00 CTR 0.375 0.075 3.75 BALL A1 BALL A1 ID CL PIXEL (0,0) 2.714 0.075 2.90 0.05 3.75 2.900 0.075 BALL A1 CORNER BALL A6 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE-REFLOW DIAMETER IS O0.33 1.728 CTR 4.00 CTR 5.80 0.075 1.875 0.186 (FOR REFERENCE ONLY) 0.75 TYP OPTICAL CENTER PACKAGE CENTER CL 1.875 2.90 0.05 2.304 CTR OPTICAL AREA MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1 5.80 0.075 MAXIMUM TILT OF OPTICAL AREA RELATIVE TO B 0.3. MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3. SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag, 0.5% Cu BALL PADS O 0.27 SOLDER MASK DEFINED SUBSTRATE MATERIAL: PLASTIC LAMINATE ENCAPSULANT: EPOXY Note: PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS IMAGE SENSOR DIE All dimensions in millimeters. 7 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Revision History Revision History Rev. L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/2/10 * Updated to non-confidential Rev. K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/5/2010 * Updated to Aptina template * Transfered registers to a seperate document Rev. J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/30/2006 * Added note to Table 1 on page 1 and updated Figure 15 on page 6. Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/10/2006 * Updated Note 2 in Table 3 on page 10. Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/2/2006 * Updated Table 22 on page 5 for output delay time from 3T to 4T and hold time for output data from 4T to 3T. Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/2/2006 * Moved Value of Output Delay Time (3T) from Min column to Max column in Table 22 on page 5. * Updated descriptions of SDATA in Table 14 on page 5. Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/19/2006 * Figure 5 on page 13 added more detail and Figure 7: Horizontal Timing on page 15 updated last data out value to 9D (was 90). * Table 3 definition of RESET changed from async to sync, Table 13 R0x00D Reset Bit 12 definition expanded, Table 12 columns swapped, and Table 17 note added, Table 19 column headings changed from Typical to MAX. Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/3/2005 * New outline drawing (36_ICSP(5_8x5_8)SMD_MTG-341.eps) per PCN1543K12A_PHC, Figure 16 on page 7. Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/29/2005 * R161 changed to R161:1, new description and bits definition * R161 changed to R164:1, new description * R13:0[4] new description * R32:0[10] is now reserved * R33:0[10] is now reserved * R40:2[12] new description * IFP Block Diagram Edit * Table 1 Edit * Conversion to 1 column template Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/15/2004 * Operating Conditions * DC Electrical Characteristics (two conditions) * Operating Power Consumption * STANDBY Power Consumption * Two-Wire Serial Bus Timing * Two-Wire Serial Bus Signal Timing (two figures) PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 8 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation. All rights reserved. MT9V112 - SOC VGA DIGITAL IMAGE SENSOR Revision History * * * * AC Electrical Characteristics AC Timing Diagram Register Summary 0x format Register Description - standardized bit value definitions and register format Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/6/2004 * Initial release 10 Eunos Road 8 13-40, Singapore Post Center, Singapore 408600 prodmktg@aptina.com www.aptina.com Aptina, Aptina Imaging, DigitalClarity, and the Aptina logo are the property of Aptina Imaging Corporation All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF:6163688301/Source:7457997359 MT9V112_DS - Rev. L 6/10 EN 9 Aptina reserves the right to change products or specifications without notice. (c)2005 Aptina Imaging Corporation All rights reserved.