LTC3615IUF-1#TRPBF - Linear Technology

LTC3615/LTC3615-1

3615fa

TYPICAL APPLICATION

DESCRIPTION

Dual 4MHz, 3A Synchronous

Step-Down DC/DC Converter

The LTC

3615/LTC3615-1 are dual 3A synchronous step-

down regulators using a current mode, constant-frequency

architecture. The DC supply current is only 130μA (Burst

Mode operation at no-load) while maintaining the output

voltages, dropping to zero current in shutdown. The 2.25V

to 5.5V input supply range makes the parts ideally suited

for single Li-Ion applications. 100% duty cycle capability

provides low dropout operation, which extends operating

time in battery-operated systems.

The operating frequency is externally programmable up to

4MHz, allowing the use of small surface mount inductors.

0°, 90°, or 180° (LTC3615) or 140°/180° (LTC3615-1) of

phase shift between the two channels can be selected to

minimize input current ripple and output voltage ripple in a

dual 3A or single 6A output conﬁ guration. Programmable

slew rate limiting reduces EMI, and external synchronization

can be applied up to 4MHz.

The internal synchronous switches increase efﬁ ciency

and eliminate the need for external catch diodes, saving

external components and board space.

The LTC3615/LTC3615-1 are offered in leadless 24-pin

4mm × 4mm QFN and thermally enhanced 24-pin eTSSOP

packages.

Efﬁ ciency and Power Loss vs Load Current

FEATURES

APPLICATIONS

n High Efﬁ ciency: Up to 94%

n Dual Outputs with 2 × 3A Output Current Capability

n Low Output Ripple Burst Mode

Operation: IQ = 130μA

n 2.25V to 5.5V Input Voltage Range

n ±1% Output Voltage Accuracy

n Output Voltages Down to 0.6V

n Programmable Slew Rate at Switch Pins

n Low Dropout Operation: 100% Duty Cycle

n Shutdown Current ≤1μA

n Adjustable Switching Frequency Up to 4MHz

n Internal or External Compensation

n Selectable Pulse-Skipping/Forced Continuous/

Burst Mode Operation with Adjustable Burst Clamp

n Optional Active Voltage Positioning (AVP) with

Internal Compensation

n Selectable 0°/90°/180° (LTC3615) or selectable

140°/180° (LTC3615-1) Phase Shift Between Channels

n Fixed Internal and Programmable External Soft-Start

n Accurate Start-Up Tracking Capability

n DDR Memory Mode IOUT = ±1.5A

n Available in 4mm × 4mm QFN-24 and eTSSOP-24 Packages

n Point-of-Load Supplies

n Distributed Power Supplies

n Portable Computer Systems

n DDR Memory Termination

n Handheld Devices

SW1

FB1

LTC3615

3615 TA01a

SGND PGND

RUN1

TRACK/SS1

ITH1

PHASE

RUN2

TRACK/SS2

PGOOD2

ITH2

PGOOD1

SRLIM

RT/SYNC

MODE

VIN

SVIN PVIN1 PVIN2

100μF

SW2

FB2

0.47μH

47μF

VOUT2

2.5V/3A

665k

210k

0.47μH

47μF

VOUT1

1.8V/3A

422k

210k

L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents, including 5481178, 5994885, 6304066, 6498466, 6580258,

6611131.

OUTPUT CURRENT (A)

EFFICIENCY (%)

POWER LOSS (W)

100

0.001 0.1 1

3615 TA01b

0.001

0.0001

0.1

0.01

VIN = 3.3V

VIN = 4V

VIN = 5V

2.25MHz

VOUT = 2.5V

LTC3615/LTC3615-1

3615fa

ABSOLUTE MAXIMUM RATINGS

PVIN1, PVIN2 Voltages .....................–0.3V to SVIN + 0.3V

SVIN Voltage ................................................. –0.3V to 6V

SW1 Voltage .............................–0.3V to (PVIN1 + 0.3V)

SW2 Voltage ..............................–0.3V to (PVIN2 + 0.3V)

PGOOD1, PGOOD2 Voltages ........................ –0.3V to 6V

All Other Pins .............................. –0.3V to (SVIN + 0.3V)

(Notes 1, 11)

TOP VIEW

FE PACKAGE

24-LEAD PLASTIC eTSSOP

PHASE

FB2

ITH2

TRACK/SS2

SGND

PVIN2

SW2

RUN2

RUN1

RT/SYNC

MODE

FB1

ITH1

TRACK/SS1

SVIN

PVIN1

SW1

PGOOD1

SRLIM

PGOOD2

PGND

TJMAX = 125°C, θJA = 33°C/W

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

24 23 22 21 20 19

7 8 9

TOP VIEW

UF PACKAGE

24-LEAD (4mm s 4mm) PLASTIC QFN

10 11 12

ITH1

FB1

MODE

PHASE

FB2

ITH2

PGOOD1

SRLIM

PGOOD2

RT/SYNC

RUN1

RUN2

TRACK/SS1

SVIN

PVIN1

SW1

TRACK/SS2

SGND

PVIN2

SW2

PGND

TJMAX = 125°C, θJA = 37°C/W

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3615EFE#PBF LTC3615EFE#TRPBF LTC3615FE 24-Lead Plastic eTSSOP –40°C to 125°C

LTC3615IFE#PBF LTC3615IFE#TRPBF LTC3615FE 24-Lead Plastic eTSSOP –40°C to 125°C

LTC3615EUF#PBF LTC3615EUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

LTC3615IUF#PBF LTC3615IUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

LTC3615EFE-1#PBF LTC3615EFE-1#TRPBF LTC3615FE-1 24-Lead Plastic eTSSOP –40°C to 125°C

LTC3615IFE-1#PBF LTC3615IFE-1#TRPBF LTC3615FE-1 24-Lead Plastic eTSSOP –40°C to 125°C

LTC3615EUF-1#PBF LTC3615EUF-1#TRPBF 36151 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

LTC3615IUF-1#PBF LTC3615IUF-1#TRPBF 36151 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ

cations, go to: http://www.linear.com/tapeandreel/

Operating Junction Temperature

Range (Note 2) .......................................–40°C to 125°C

Storage Temperature ..............................–65°C to 150°C

Lead Soldering Temperature (eTSSOP) ................. 300°C

Reﬂ ow Peak Body Temperature (QFN) .................. 260°C

LTC3615/LTC3615-1

3615fa

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Operating Voltage Range l2.25 5.5 V

VUVLO Undervoltage Lockout Threshold SVIN Ramping Down l1.7 V

SVIN Ramping Up 2.25 V

VFB Feedback Voltage Internal Reference (Note 3) VTRACK = SVIN, VSRLIM = 0V

0°C < TJ < 85°C

–40°C < TJ < 125°C l

0.592

0.590

0.6 0.608

0.610

Feedback Voltage External Reference

(Note 7)

(Note 3) VTRACK = 0.3V, VSRLIM = SVIN 0.289 0.3 0.311 V

(Note 3) VTRACK = 0.5V, VSRLIM = SVIN 0.489 0.5 0.511 V

IFB Feedback Input Current VFBx = 0.6V l0 ±30 nA

ΔVLINEREG Line Regulation SVIN = PVINx = 2.25V to 5.5V (Note 4) l0.2 %/ V

ΔVLOADREG Load Regulation VITHx from 0.5V to 0.9V (Note 4)

VITHx = SVIN, VFBx = 0.6V (Note 5)

0.2

ISActive Mode VFB1 = 0.5V, VMODE = SVIN, VRUN2 = 0V (Note 6) 1100 μA

VFBx = 0.5V, VMODE = SVIN, VRUNx = SVIN (Note 6) 1900 μA

Sleep Mode VFB1 = 0.7V, VRUN1 = SVIN, VRUN2 = 0V,

VMODE = 0V, VITH1 = SVIN (Note 5)

95 130 μA

VFBx = 0.7V, VRUN1 = SVIN, VRUN2 = 0V,

VMODE = 0V (Note 4)

145 220 μA

VFBx = 0.7V, VRUNx = SVIN, VMODE =0V,

VITHx = SVIN (Note 5)

130 200 μA

VFBx = 0.7V, VRUNx = SVIN, VMODE =0V,

ITH = (Note 4)

240 360 μA

Shutdown SVIN = PVIN = 5.5V, VRUNx = 0V 0.1 1 μA

RDS(ON) Top Switch On-Resistance PVINx = 3.3V (Note 10) 75 mΩ

Bottom Switch On-Resistance PVINx = 3.3V (Note 10) 55 mΩ

ILIM Top Switch Current Limit Sourcing (Note 8), VFB = 0.5V

Duty Cycle <35%

Duty Cycle = 100%

4.5

3.6

6 7.5 A

Bottom Switch Current Limit Sinking (Note 8), VFB = 0.7V,

Forced Continuous Mode

–2.5 –3.5 –5 A

ISW(LKG) Switch Leakage Current SVIN = PVIN = 5.5V, VRUNx = 0V 0.01 1 μA

gm(EA) Error Ampliﬁ er Transconductance –5μA < ITH < 5μA 240 μmho

IEAO Error Ampliﬁ er Output Current (Note 4) ±30 μA

tSOFT-START Internal Soft-Start Time VFBx from 0.06V to 0.54V, TRACK/SSx = SVIN 0.65 1.1 1.7 ms

RON(TRACK/SS_DIS) TRACK/SS Pull-Down Resistance at

Start-Up

200 Ω

tTRACK/SS_DIS Soft-Start Discharge Time at Start-Up 70 μs

fOSC Internal Oscillator Frequency RRT/SYNC = 178k l1.85 2.25 2.65 MHz

VRT/SYNC = SVIN l1.8 2.25 2.7 MHz

fSYNC Synchronization Frequency tLOW, tHIGH > 30ns 0.4 4 MHz

VRT/SYNC SYNC Level High 1.2 V

SYNC Level Low 0.3 V

The l denotes the speciﬁ cations which apply over the full operating

junction temperature range, otherwise speciﬁ cations are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, RSRLIM = 40.2k, unless

otherwise speciﬁ ed (Note 2).

LTC3615/LTC3615-1

3615fa

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ϕSW1–SW2 Output Phase Shift Between SW1

and SW2 (LTC3615)

VPHASE < 0.15 • SVIN 0Deg

0.35 • SVIN < VPHASE < 0.65 • SVIN 90 Deg

VPHASE > 0.85 • SVIN 180 Deg

Output Phase Shift Between SW1

and SW2 (LTC3615-1)

VPHASE < 0.65 • SVIN 140 Deg

VPHASE > 0.85 • SVIN 180 Deg

VSRLIM Voltage at SRLIM to Enable DDR

Mode

(Note 9) SVIN – 0.3 V

VMODE

(Note 9)

Internal Burst Mode Operation 0.3 V

Pulse-Skipping Mode SVIN – 0.3 V

Forced Continuous Mode 1.1 SVIN • 0.58 V

External Burst Mode Operation 0.5 0.85 V

PGOOD Power Good Voltage Windows TRACK/SSx = SVIN, Entering Window

VFBx Ramping Up

VFBx Ramping Down

–3.5

3.5

–6

TRACK/SSx = SVIN, Leaving Window

VFBx Ramping Up

VFBx Ramping Down

–9

–11

tPGOOD Power Good Blanking Time Entering/Leaving Window 70 105 140 μs

RPGOOD Power Good Pull-Down On-Resistance I = 10mA 8 12 30 Ω

VRUN Enable Pin Input High

Input Low

0.4

Pull-Down Resistance 4 MΩ

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3615/LTC3615-1 are tested under pulsed load conditions

such that TJ

≈

TA. The LTC3615E/LTC3615E-1 are guaranteed to meet

performance speciﬁ cations over the 0°C to 85°C operating junction

temperature range. Speciﬁ cations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3615I/LTC3615I-1 are

guaranteed to meet speciﬁ cations over the full –40°C to 125°C operating

junction temperature range. Note that the maximum ambient temperature

is determined by speciﬁ c operating conditions in conjunction with board

layout, the rated package thermal resistance and other environmental

factors. Note that the maximum ambient temperature consistent with

these speciﬁ cations is determined by speciﬁ c operating conditions in

conjunction with board layout, the rated package thermal impedance

and other environmental factors. The junction temperature (TJ, in °C) is

calculated from the ambient temperature

(TA, in °C) and power dissipation (PD, in watts) according to the formula:

J = TA + (PD • θJA)

where θJA (in °C/W) is the package thermal impedence.

Note 3: This parameter is tested in a feedback loop which servos VFB1,2 to

the midpoint for the error ampliﬁ er (VITH1,2 = 0.75V).

Note 4: External compensation on ITH pin.

Note 5: Tying the ITH pin to SVIN enables internal compensation and AVP

mode for the selected channel.

Note 6: Dynamic supply current is higher due to the internal gate charge

being delivered at the switching frequency.

Note 7: See description of the TRACK/SS pin in the Pin Functions section.

Note 8: When sourcing current, the average output current is deﬁ ned

as ﬂ owing out of the SW pin. When sinking current, the average output

current is deﬁ ned as ﬂ owing into the SW pin. Sinking mode requires the

use of forced continuous mode.

Note 9: See description of the MODE pin in the Pin Functions section.

Note 10: Guaranteed by design and correlation to wafer level

measurements for QFN packages.

Note 11: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the speciﬁ ed maximum operating junction

temperature may impair device reliability or permanently damage the

device.

The l denotes the speciﬁ cations which apply over the full operating

junction temperature range, otherwise speciﬁ cations are at TA = 25°C (Note 2), SVIN = PVINx = 3.3V, RT = 178k, RSRLIM = 40.2k, unless

otherwise speciﬁ ed (Note 2).

LTC3615/LTC3615-1

3615fa

TYPICAL PERFORMANCE CHARACTERISTICS

Load Regulation Line Regulation

Efﬁ ciency vs Load Current

(VMODE = 0V)

Efﬁ ciency vs Load Current

(VMODE = 0V)

Efﬁ ciency vs Load Current

(VMODE = 0V)

VIN = 3.3V, RT/ SYNC = SVIN, unless otherwise noted.

Efﬁ ciency vs Load Current

(VMODE = 0.55 • SVIN)

Efﬁ ciency vs Load Current

(VMODE = 0.55 • SVIN)

Efﬁ ciency vs Input Voltage

(VMODE = 0V)

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

3615 G01

VOUT = 1.8V

VIN = 2.5V

VIN = 3.3V

VIN = 5V

0.001 0.1 10.01

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

3615 G02

VOUT = 1.2V

VIN = 2.5V

VIN = 3.3V

VIN = 5V

0.001 0.1 10.01

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

3615 G03

VOUT = 2.5V

VIN = 3.3V

VIN = 4V

VIN = 5V

0.001 0.1 10.01

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

3615 G04

VOUT = 1.8V

VIN = 2.25V

VIN = 3.3V

VIN = 5V

0.001 0.1 10.01

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

3615 G05

VIN = 2.25V

VIN = 3.3V

VIN = 5V

VOUT = 1.2V

0.001 0.1 10.01

INPUT VOLTAGE (V)

2.25

EFFICIENCY (%)

3615 G06

3.75

3.25 5.25

2.75 4.25 4.75

IOUT = 3A

IOUT = 2A

IOUT = 1A

IOUT = 0.3A

IOUT = 0.2A

VOUT = 1.8V

OUTPUT CURRENT (A)

VOUT ERROR (%)

0.2

0.3

0.4

0.1

0.5 1.51 2 2.5 3

–0.3

–0.4

–0.1

0.5

–0.2

3615 G07

INTERNAL

COMPENSATION

(ITH = SVIN )

VMODE = 1.5V

EXTERNAL

COMPENSATION

INPUT VOLTAGE (V)

2.25

VOUT ERROR (%)

0.05

0.10

0.15

2.75 3.753.25 4.25 4.75 5.25

–0.15

–0.20

–0.05

0.20

–0.10

3615 G08

LTC3615/LTC3615-1

3615fa

Load Step Transient in FCM

with AVP Mode

Load Step Transient in

FCM External Compensation

Load Step Transient

in Pulse-Skipping Mode

Load Step Transient in

Burst Mode Operation

VOUT

200mV/DIV

1A/DIV

50μs/DIV 3615 G12

VOUT = 1.8V

ILOAD = 100mA TO 3A

VMODE = 1.5V

COMPENSATION FIGURE 1

VOUT

200mV/DIV

1A/DIV

50μs/DIV 3615 G13

VOUT = 1.8V

ILOAD = 100mA TO 3A

VMODE = 3.3V

COMPENSATION FIGURE 1

VOUT

200mV/DIV

1A/DIV

50μs/DIV 3615 G14

VOUT = 1.8V

ILOAD = 100mA TO 3A

VMODE = 0V

COMPENSATION FIGURE 1

VOUT

100mV/DIV

1A/DIV

50μs/DIV 3615 G15

VOUT = 1.8V

ILOAD = 100mA TO 3A

VMODE = 1.5V

VITH = 3.3V

OUTPUT CAPACITOR VALUE FIGURE 1

Pulse-Skipping Mode Operation

Forced Continuous Mode

Operation (FCM) Burst Mode Operation

VOUT

20mV/DIV

200mA/DIV

1μs/DIV 3615 G09

VOUT = 1.8V

IOUT = 100mA

VMODE = 1.5V

VOUT

20mV/DIV

500mA/DIV

20μs/DIV 3615 G10

VOUT = 1.8V

IOUT = 75mA

VMODE = 3.3V

VOUT

20mV/DIV

500mA/DIV

20μs/DIV 3615 G11

VOUT = 1.8V

IOUT = 75mA

VMODE = 0V

Load Step Transient in Forced

Continuous Mode Sourcing and

Sinking Current

VOUT

200mV/DIV

2A/DIV 0A

50μs/DIV 3615 G16

VOUT = 1.8V

ILOAD = –1.5A TO 3A

VMODE = 1.5V

COMPENSATION FIGURE 1

Internal Start-Up in Forced

Continuous Mode

VOUT

500mV/DIV

RUN

1V/DIV

1A/DIV

PGOOD

2V/DIV

500μs/DIV 3615 G17

VOUT = 1.8V

IOUT = 3A

VMODE = 1.5V

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.3V, RT/ SYNC = SVIN, unless otherwise noted.

LTC3615/LTC3615-1

3615fa

TYPICAL PERFORMANCE CHARACTERISTICS

Switch On-Resistance

vs Input Voltage

Reference Voltage

vs Temperature

TEMPERATURE (°C)

–50

0.594

REFERENCE VOLTAGE (V)

0.596

0.600

0.602

0.604

–10 30 50 130

3615 G18

0.598

–30 10 70 90 110

0.606

Frequency vs Input Voltage

Frequency vs RT/SYNC

Frequency vs Temperature

VIN = 3.3V, RT/ SYNC = SVIN, unless otherwise noted.

RT/SYNC (kΩ)

100

fOSC (MHz)

3.6

0.8

1.2

1.6

4.0

2.4

300 500 600 1000

3615 G22

0.4

2.8

3.2

2.0

200 400 700 800 900

TEMPERATURE (°C)

1.8

fOSC (MHz)

1.9

2.1

2.2

2.3

2.7

2.6

2.5

3615 G23

2.0

2.4

–40 –10 20 50

–25 580

35 65 110 12595

RT/SYNC = SVIN

RT= 178k

VIN (V)

2.25

1.60

fOSC (MHz)

1.80

1.90

2.00

2.10

2.60

2.50

2.40

2.30

3615 G24

1.70

2.20

4.503.75 5.25

3.00

RT/SYNC = SVIN

RT/SYNC = 200k

VIN (V)

2.25

RDS(ON) (Ω)

0.01

0.03

0.04

0.05

0.10

0.09

0.08

0.07

3615 G19

0.02

0.06

4.253.25 5.25

MAIN SWITCH

SYNCHRONOUS SWITCH

Switch On-Resistance

vs Temperature

TEMPERATURE (°C)

–40

RDS(ON) (μA)

100

–10 20 50

–25 580

35 65 110 12595

3615 G20

SYNCHRONOUS SWITCH

MAIN SWITCH

LTC3615/LTC3615-1

3615fa

TYPICAL PERFORMANCE CHARACTERISTICS

Switch Leakage vs Temperature

No Load Supply Current

vs Input Voltage

No Load Supply Current

vs Temperature

Slew Rate of Falling Edge at

SW1/2 vs SRLIM Resistor

Slew Rate of Rising Edge at

SW1/2 vs SRLIM Resistor Sinking Current

VOUT

20mV/DIV

2V/DIV

500mA/DIV

1μs/DIV 3615 G30

VOUT = 1.2V

IOUT = –1A

VMODE = 1.5V

Tracking Up/Down in

Forced Continuous Mode,

SRLIM Pin Tied to 0V

VOUT1

1V/DIV

VTRACK/SS

500mV/DIV

PGOOD

2V/DIV

2ms/DIV 3615 G31

VOUT = 0V TO 1.8V

IOUT = 3A

VTRACK/SS = 0V TO 0.7V

VMODE = 1.5V

VSRLIM = 0V

Tracking Up/Down in

Forced Continuous Mode,

SRLIM Pin Tied to SVIN

VTRACK/SS

200mV/DIV

VOUT1

500mV/DIV

PGOOD

2V/DIV

2ms/DIV 3615 G32

VOUT = 0V TO 1.2V

IOUT = 3A

VTRACK/SS = 0V TO 0.4V

VMODE = 1.5V

VSRLIM = 3.3V

VIN = 3.3V, RT/ SYNC = SVIN, unless otherwise noted.

2ns/DIV 3615 G28

SRLIM =

SGND OR SVIN

VIN = 3.3V

VOUT = 1.8V

IOUT = 1A

OPEN

100k

1V/DIV

40.2k

1V/DIV

2ns/DIV 3615 G29

SRLIM =

SGND OR SVIN

VIN = 3.3V

VOUT = 1.8V

IOUT = 1A

OPEN

100k

40.2k

TEMPERATURE (°C)

–40

SWITCH LEAKAGE (μA)

0.8

1.8

2.0

–10 20 50

0.4

1.4

0.6

1.6

0.2

1.2

1.0

–25 580

35 65 110 12595

3615 G25

SYNCHRONOUS SWITCH

MAIN SWITCH

VIN = 5.5V

VIN (V)

2.25

SUPPLY CURRENT (μA)

3615 G26

3.25 3.75

2.75 5.25

4.25 4.75

180

140

160

120

100

MODE = 0V

RUNx = ITHx = SVIN

–40 –10 20 50

–25 580

35 65 110 12595

TEMPERATURE (°C)

SUPPLY CURRENT (μA)

3615 G27

180

140

160

120

100

MODE = 0V

RUNx = ITHx = SVIN

LTC3615/LTC3615-1

3615fa

PIN FUNCTIONS

PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied

to SGND, the phase between SW1 and SW2 will be 0°

(LTC3615) or 140° (LTC3615-1). With the PHASE pin

tied to half of the SVIN voltage, 90° (LTC3615) or 140°

(LTC3615-1) of phase shift will be selected. Tying PHASE

to SVIN will select 180° (LTC3615 and LTC3615-1).

VFB2 (Pin 2/Pin 5): Voltage Feedback Input Pin for Chan-

nel 2. See VFB1.

ITH2 (Pin 3/Pin 6): Error Ampliﬁ er Compensation of

Channel 2. See ITH1.

TRACK/SS2 (Pin 4 /Pin 7): Internal, External Soft-Start,

External Reference Input for Channel 2. See TRACK/SS1.

SGND (Pin 5/Pin 8): Signal Ground. All small-signal and

compensation components should connect to this ground

pin which, in turn, should be connected to PGND at one

point.

PVIN2 (Pins 6, 7/Pins 9, 10) Channel 2 Power Supply

Input. See PVIN1.

SW2 (Pins 8, 9/Pins 11, 12): Channel 2 Switching Node.

See SW1.

RUN2 (Pin 10/Pin 13): Enable Pin for Channel 2. See

RUN1.

RUN1 (Pin 11/Pin 14): Enable Pin for Channel 1. Forcing

RUN1 above the input threshold enables the output SW1 of

channel 1. Forcing both RUNx pins to ground shuts down

the LTC3615. In shutdown, all functions are disabled and

the LTC3615 draws <1μA of supply current.

RT/SYNC (Pin 12/Pin 15): Oscillator Frequency. This

pin provides three modes of setting the switching

frequency.

1. Connecting a resistor from RT/SYNC to ground will set

the switching frequency based on the resistor value.

2. Driving RT/SYNC with an external clock signal will

synchronize the switcher to the applied frequency. The

slope compensation is automatically adapted to the

external clock frequency.

3. Tying this pin to SVIN enables the internal 2.25MHz

oscillator frequency.

PGOOD2 (Pin 13/Pin 16): Power Good Output for

Channel 2. See PGOOD1.

SRLIM (Pin 14 /Pin 17): Slew Rate Limit. Slew rate on the

switch pins is programmed with the SRLIM pin:

1. Tying this pin to SGND selects maximum slew rate.

2. Minimum slew rate is selected when the pin is open.

3. Connecting a resistor from SRLIM to SGND allows the

slew rate to be continuously adjusted.

4. If SRLIM is tied to SVIN the slew rate is set to maximum

and DDR mode is enabled (see the Applications

Information section).

PGOOD1 (Pin 15/Pin 18): Power Good Output Pin for

Channel 1. The open-drain output will be pulled down to

ground when the FB1 voltage of the channel is not within

the power good voltage window. The PGOOD1 will also be

pulled down if the channel is not enabled with the RUN1

pin or an undervoltage at SVIN is detected. In DDR mode

(SRLIM = SVIN), the power good window moves in relation

to the actual TRACK/SS pin voltage.

SW1 (Pins 17, 16/Pins 19, 20): Channel 1 Switching Node.

Connection to the external inductor. This pin connects to

the drains of the internal synchronous power MOSFET

switches.

PVIN1 (Pins 18, 19/Pins 21, 22): Channel 1 Power Supply

Inputs. These pins connect to the source of the internal

power P-channel MOSFET of channel 1. PVIN1 and PVIN2

are independent of each other. They may connect to equal

or lower supplies than SVIN.

SVIN (Pin 20/Pin 23) Signal Input Supply. This pin powers

the internal control circuitry and is monitored by the

undervoltage lockout comparator.

(FE/UF)

LTC3615/LTC3615-1

3615fa

TRACK/SS1 (Pin 21/Pin 24): Internal, External Soft-

Start, External Reference Input for Channel 1. The type

of start-up behavior for channel 1 is programmable with

the TRACK/SS1 pin:

1. Internal soft-start with a ﬁ xed timing can be programmed

by tying TRACK/SS1 to SVIN.

2. External soft-start can be programmed with the timing

set by a capacitor to ground and a resistor to SVIN.

3. Tracking the start-up behavior of another supply is

programmable (see the Applications Information

section).

4. The pin can be used as external reference input.

ITH1 (Pin 22/Pin 1): Error Ampliﬁ er Compensation.

Connection for external compensation from ITH to SGND.

The current comparator’s threshold increases with this

control voltage. Tying this pin to SVIN enables AVP mode

with internal compensation.

VFB1 (Pin 23/Pin 2): Voltage Feedback Input Pin for

Channel 1. Receives the feedback voltage for channel 1

from the external resistive divider across the output.

PIN FUNCTIONS

(FE/UF)

MODE (Pin 24/Pin 3): Mode Selection.

1. Tying the MODE pin to SVIN or SGND enables pulse-

skipping mode or Burst Mode operation (with an internal

Burst Mode clamp), respectively.

2. If this pin is held at slightly higher than half of SVIN,

forced continuous mode will be selected.

3. Connecting this pin to an external voltage will select

Burst Mode operation with the burst clamp set to the

pin voltage.

PGND (Exposed Pad Pin 25/ Exposed Pad Pin 25): Power

Ground. The exposed pad connects to the sources of the

power N-channel MOSFETs. The PGND pin is common

for both channels. The exposed pad must be soldered

to the PCB.

For electrical connection and rated thermal performance,

refer to the Operation and Applications Information sec-

tions for more information.

LTC3615/LTC3615-1

3615fa

FUNCTIONAL BLOCK DIAGRAM

IDEAL

DIODE

TRACK/SS1 SOFT-START

VREF

INTERNAL/

EXTERNAL

COMPENSATION

ITH-VOLTAGE

LIMIT

MODE

FB1

PGOOD1

RT/SYNC

RUN2

RUN1

PHASE

FB2

PGOOD2

TRACK/SS2

SW2

PVIN2

PVIN1

SW1

PGND

SVIN

SGND UNDERVOLTAGE

LOCKOUT

SLOPE

COMPENSATION

NMOS

CURRENT SENSE

PMOS

CURRENT SENSE

CONTROLLER LOGIC

GATE DRIVER

–

SHUTDOWN

CLK2

CLK1

MODE

ITH1

SRLIM

BURST

COMPARATOR

PGOOD

WINDOW-

COMPARATOR

CHANNEL 1

ERROR

AMPLIFIER

DUPLICATE FOR CHANNEL 2

REVERSE

CURRENT

COMPARATOR

PMOS

CURRENT

COMPARATOR

DELAY

PLL

OSCILLATOR

AND PHASE

SELECTOR

ITH2

–

3615 FD

LTC3615/LTC3615-1

3615fa

Figure 1. Mode Selection Voltage

OPERATION

Main Control Loop

The LTC3615 is a dual monolithic step-down DC/DC

converter featuring current-mode, constant-frequency

operation. Both channels are identical and share common

clock and reference circuits to improve channel-to-chan-

nel matching.

During normal operation, the internal top power switch

(P-channel MOSFET) of each channel is turned on at the

beginning of its clock cycle. Current in the inductor in-

creases until the current comparator trips and turns off the

top power MOSFET. The peak inductor current at which the

current comparator shuts off is controlled by the voltage

on the ITH pin. The error ampliﬁ er adjusts the voltage on

the ITH pin by comparing the feedback signals derived

from an external resistor divider on the VFBx pin with an

internal 0.6V reference. When the load current increases,

it causes a reduction in the feedback voltage relative to

the reference. The error ampliﬁ er raises the ITH voltage

until the average inductor current matches the new load

current. Typical voltage range for the ITH pin is from 0.45V

to 1.05V with 0.45V corresponding to zero current.

When the top power MOSFET shuts off, the synchronous

power switch (N-channel MOSFET) turns on until either

the current limit is reached or the next clock cycle begins.

The bottom current limit is typically set at –4A for forced

continuous mode and 0A for Burst Mode operation and

pulse-skipping mode.

The operating frequency defaults to 2.25MHz when

RT/SYNC is connected to SVIN, or can be set by an ex-

ternal resistor connected between the RT/SYNC pin and

ground, or by a clock signal applied to the RT/SYNC pin.

The switching frequency can be set from 400kHz to 4MHz

(see the Applications Information section).

Overvoltage and undervoltage comparators pull the PGOOD

output low if the output voltage varies more than ±7.5%

from the set point.

MODE SELECTION

The MODE pin is used to select one of four different

operating modes for both channels together (see Figures

1 and 3):

Burst Mode Operation—Internal Clamp

Connecting the MODE pin to the SGND pin enables Burst

Mode operation with its peak current set internally. In

Burst Mode operation the internal power MOSFETs operate

intermittently at light loads. This increases efﬁ ciency by

minimizing switching losses. During the intervals when the

MOSFETs are not switching, the LTC3615 enters a sleep

state where many of the internal circuits are disabled to

save power. During Burst Mode operation, the ITH volt-

age is monitored by the burst comparator to determine

when the sleep state is entered or exited again. When the

average inductor current is greater than the load current,

the voltage on the ITH pin drops. As the ITH voltage falls

below the internal threshold, the LTC3615 enters the sleep

state. In the sleep state, the power MOSFETs are held

off and the load current is solely supplied by the output

capacitor. When the output voltage drops, the top power

MOSFET is switched back on and the internal circuits are

reenabled. This process repeats at a rate that is dependent

on the load current.

PS PULSE-SKIPPING MODE ENABLE

FORCED CONTINUOUS MODE ENABLE

Burst Mode ENABLE—INTERNAL CLAMP

3615 F01

Burst Mode ENABLE—EXTERNAL CLAMP,

CONTROLLED BY VOLTAGE APPLIED AT

MODE PIN

SVIN

SVIN – 0.3V

SVIN • 0.58

1.1V

0.8V

0.5V

0.3V

SGND

EXT

LTC3615/LTC3615-1

3615fa

Burst Mode Operation—External Clamp

Connecting the MODE pin to a voltage in the range of 0.5V

to 0.8V enables Burst Mode operation with external clamp.

During this mode of operation, the minimum voltage on the

ITH pin is externally set by the voltage on the MODE pin.

It is recommended to use Burst Mode operation with the

internal clamp for ambient temperatures above 85°C.

Pulse-Skipping Mode Operation

Pulse-skipping mode is similar to Burst Mode operation,

but the LTC3615 does not disable power to the internal

circuitry during sleep mode. This improves output voltage

ripple but uses more quiescent current compromising

light load efﬁ ciency.

Connecting the MODE pin to SVIN enables pulse-skipping

mode. As the load current decreases, the peak inductor

current will be determined by the voltage on the ITH pin

until the ITH voltage drops below 450mV, corresponding

to 0A. At this point switching cycles will be skipped to

keep the output voltage in regulation.

Forced Continuous Mode Operation

In forced continuous mode the inductor current is con-

stantly cycled which creates a minimum output voltage

ripple at all output current levels.

Connecting the MODE pin, to a voltage in the range of

1.1V to SVIN • 0.58 will select the forced continuous mode

operation.

The forced continuous mode must be used if the output

is required to sink current.

Dropout Operation

As the input supply voltage approaches the output voltage,

the duty cycle increases toward the maximum on-time.

Further reduction of the supply voltage forces the main

switch to remain on for more than one cycle, eventually

reaching 100% duty cycle. The output voltage will then be

determined by the input voltage minus the voltage drop

across the internal P-channel MOSFET and the inductor.

OPERATION

Figure 2. Modes of Operation

LTC3615

SVIN

VIN

MODE

SGND

2a. Burst Mode Operation

Internally Controlled

LTC3615

SVIN

VIN

MODE

SGND

2c. Pulse-Skipping Mode

LTC3615

SVIN

VIN

MODE

SGND

RM1

RM2

3615 F02

2d. Forced Continuous Mode

2b. Burst Mode Operation

Externally Controlled

LTC3615

SVIN

VIN

MODE

SW1

FB1

SGND

VOUT1

RM1

RM2

LTC3615/LTC3615-1

3615fa

Low Supply Operation

The LTC3615 is designed to operate down to an input supply

voltage of 2.25V. An important consideration at low input

supply voltages is that the RDS(ON) of the P-channel and

N-channel power switches increases by 50% compared to

5V. The user should calculate the power dissipation when

the LTC3615 is used at 100% duty cycle with low input

voltages to ensure that thermal limits are not exceeded.

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in current mode

constant-frequency architectures by preventing subhar-

monic oscillations at duty cycles greater than 50%. The

LTC3615 implements slope compensation by adding a

compensation ramp to the inductor current signal.

Short-Circuit Protection

The peak inductor current at which the current comparator

shuts off the top power switch is controlled by the voltage

on the ITH pin.

If the output current increases, the error ampliﬁ er raises

the ITH pin voltage until the average inductor current

matches the new load current. In normal operation,

the LTC3615 clamps the maximum ITH pin voltage at

approximately 1.05V which corresponds to about 5A peak

inductor current.

When the output is shorted to ground, the inductor current

decays very slowly during a single switching cycle. The

LTC3615 uses two techniques to prevent current runaway

from occurring:

1. If the output voltage drops below 50% of its nominal

value, the clamp voltage at pin ITH is lowered, causing

the maximum peak inductor current to lower gradu-

ally with the output voltage. When the output voltage

reaches 0V, the clamp voltage at the ITH pin drops to

40% of the clamp voltage during normal operation. The

short-circuit peak inductor current is determined by the

minimum on-time of the LTC3615, the input voltage

and the inductor value. This foldback behavior helps

in limiting the peak inductor current when the output

is shorted to ground. It is disabled during internal or

external soft-start and tracking up/down operation (see

the Applications Information section).

2. If the inductor current of the bottom MOSFET increases

beyond 6A typical, the top power MOSFET will be held

off and switching cycles will be skipped until the induc-

tor current reduces.

OPERATION

LTC3615/LTC3615-1

3615fa

Operating Frequency

Selection of the operating frequency is a trade-off between

efﬁ ciency and component size. High frequency operation

allows the use of smaller inductor and capacitor values.

Operation at lower frequencies improves efﬁ ciency by

reducing internal gate charge losses but requires larger

inductance values and/or capacitance to maintain low

output ripple voltage.

The operating frequency of the LTC3615 is determined by

an external resistor that is connected between pin RT/SYNC

and ground. The value of the resistor sets the ramp current

that is used to charge and discharge an internal timing

capacitor within the oscillator and can be calculated by

using the following equation:

RHz

TOSC

=410

•Ω

Although frequencies as high as 4MHz are possible, the

minimum on-time of the LTC3615 imposes a minimum

limit on the operating duty cycle. The minimum on-time

APPLICATIONS INFORMATION

is typically 60ns, therefore, the minimum duty cycle is

equal to 60ns • 100% • fOSC(Hz)

Tying the RT/SYNC pin to SVIN sets the default internal

operating frequency to 2.25MHz ±20%.

Frequency Synchronization

The LTC3615’s internal oscillator can be synchronized to

an external frequency by applying a square wave clock

signal to the RT/SYNC pin. During synchronization, the

top MOSFET turn-on of channel 1 is locked to the rising

edge of the external frequency source. The synchronization

frequency range is 400kHz to 4MHz. The internal slope

compensation is automatically adapted to the external

clock frequency.

In the signal path from the RT/SYNC clock input to the

SW output, the LTC3615 is processing the external clock

frequency through an internal PLL.

After detecting an external clock on the ﬁ rst rising edge

of RT/SYNC the PLL starts up with the internal default of

2.25MHz. The internal PLL then requires a certain number

Figure 3. Soft-Start and Compensation for Channel 1 Externally Programmed,

Soft-Start and Compensation for Channel 2 Internally Programmed

(2s) SW1

FB1

MODELTC3615

3615 F03

SGND PGND

RUN1

TRACK/SS1

RT, 200k

ITH1

PHASE

RUN2

TRACK/SS2

PGOOD2

ITH2

PGOOD1

RT/SYNC

SRLIM

VIN

3.3V

SVIN (2s) PVIN1 (2s) PVIN2

1μF47μF47μF

0.47μH

47μF

VOUT1

1.8V/3A

422k

29.4k

178k

RSS

4.7M

CSS

10nF

15k

1000pF (2s) SW2

FB2

0.47μH

47μF

VOUT2

2.5V/3A

665k

210k

10pF

RSRLIM

40.2k

LTC3615/LTC3615-1

3615fa

LTC3615

SVIN

VIN

RT/SYNC

LTC3615

SVIN

VIN

0.4V RT/SYNC

ROSC SGND

fSW

2.25MHz fSW t1/ROSC

3615 F04

LTC3615

SVIN fSW

1/TP

VIN

RT/SYNC

SGND

1.2V

0.3V

fSW

1/TP

1.2V

0.3V

LTC3615

SVIN

VIN

RT/SYNC

SGND

15pF

on the duty cycle of the two channels, choose the phase

difference between the channels to keep edges as far away

from each other as possible.

For example, for duty cycles of less than 40% for one

channel and more than 60% for the other channel, the

SW node edges will not coincide for 0° or 180° phase

shifts. If both channels have a duty cycle of around 50%,

a 90° phase difference would be a better choice. In cases

where the duty cycles are ~25% and ~50%, a 140° phase

shift (LTC3615-1 only) is preferable to the other phase

selections.

Inductor Selection

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ΔIL increases with higher VIN and decreases

with higher inductance.

ΔIV

LOUT

OUT

IN MAX

=⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟

••–

()

Having a lower ripple current reduces the core losses

in the inductor, the ESR losses in the output capacitors

and the output voltage ripple. A reasonable starting point

for selecting the ripple current is ΔIL = 0.3(IOUT(MAX)).

The largest ripple current occurs at the highest VIN. To

guarantee that the ripple current stays below a speciﬁ ed

maximum, the inductor value should be chosen according

to the following equation:

OUT

SW L MAX

OUT

IN MAX

=⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

••–

() ()

Δ1

⎠⎠

⎟

The inductor value will also have an effect on Burst Mode

operation. The transition to low current operation begins

when the peak inductor current falls below a level set by

Figure 4. Setting the Switching Frequency

APPLICATIONS INFORMATION

of periods to settle until the frequency at SW matches the

frequency and phase of RT/SYNC.

When the external clock signal is removed, the LTC3615

needs approximately 5μs to detect the absence of the

external clock. During this time, the PLL will continue

to provide clock cycles before it is switched back to the

default frequency or selected frequency (set via the external

RT resistor).

A safe way of driving the RT/SYNC input is with an AC

coupling to the clock generator via a 15pF capacitor. The AC

coupling avoids complications if the external clock generator

cannot provide a continuous clock signal at the time of

start-up, operation and shut down of the LTC3615.

In general, any abrupt clock frequency change of the

regulator will have an effect on the SW pin timing and

may cause equally sudden output voltage changes. This

must be taken into account in particular if the external

clock frequency is signiﬁ cantly different from the internal

default of 2.25MHz.

Phase Selection

Channel 2 of the LTC3615 will operate in-phase, 180° out-

of-phase (anti-phase) or shifted by 90° from channel 1

depending on the state of the PHASE pin—low, midrail and

high, respectively. Channel 2 of LTC3615-1 will operate 180°

out-of-phase (anti-phase) with PHASE pin high or shifted

by 140° with PHASE midrail or low. Antiphase generally

reduces input voltage and current ripple. Crosstalk between

switch nodes SW1, SW2 and components or sensitive

lines connected to FBx, ITHx, RT/SYNC or SRLIM can

cause unstable switching waveforms and unexpectedly

large input and output voltage ripple.

The situation improves if rising and falling edges of the

switch nodes are timed carefully not to coincide. Depending

LTC3615/LTC3615-1

3615fa

the burst clamp. Lower inductor values result in higher

ripple current which causes this to occur at lower DC

load currents. This causes a dip in efﬁ ciency in the upper

range of low current operation. In Burst Mode operation,

lower inductance values will cause the burst frequency

to increase.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. Actual core loss is independent of core size

for ﬁ xed inductor value, but it is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance

requires more turns of wire, and therefore, copper losses

will increase.

Ferrite designs have very low core losses and are preferred

at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates hard, which means that

inductance collapses abruptly when the peak design current

is exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow a ferrite core to saturate!

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

Toroid or shielded pot cores in ferrite or permalloy materials

are small and do not radiate much energy, but generally

cost more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price versus size requirements

and any radiated ﬁ eld/EMI requirements. Table 1 shows

some typical surface mount inductors that work well in

LTC3615 applications.

Input Capacitor CIN Selection

In continuous mode, the source current of the top P-channel

MOSFET is a square wave of duty cycle VOUT/VIN. To prevent

large voltage transients, a low ESR capacitor sized for the

maximum RMS current must be used for CIN.

The maximum RMS capacitor current is given by:

II V

RMS OUT MAX OUT

OUT

=⎛

⎝

⎜

⎞

⎠

⎟

()

•• –1

This formula has a maximum at VIN = 2VOUT, where IRMS =

IOUT/2. This simple worst-case condition is commonly used

for design because even signiﬁ cant deviations do not offer

much relief. Note that ripple current ratings from capacitor

manufacturers are often based on only 2000 hours of life

which makes it advisable to further derate the capacitor,

or choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to meet

size or height requirements in the design.

APPLICATIONS INFORMATION

Table 1. Representative Surface Mount Inductors

INDUCTANCE

(μH)

DCR

(mΩ)

MAX

CURRENT (A)

DIMENSIONS

(mm)

HEIGHT

(mm)

Vishay IHLP-2020BZ-01

0.33 7.6 25 5.18 × 5.49 2

0.47 8.9 21 5.18 × 5.49 2

0.68 11.2 15 5.18 × 5.49 2

1 18.9 16 5.18 × 5.49 2

Toko DE3518C Series

0.22 8 24 4.3 × 4.7 2

Sumida CDMC6D28 Series

0.3 3.2 15.4 6.7 × 7.25 3

0.47 4.2 13.6 6.7 × 7.25 3

0.68 5.4 11.3 6.7 × 7.25 3

1 8.8 8.8 6.7 × 7.25 3

NEC/Tokin MPLC0730L Series

0.47 4.5 16.6 6.9 × 7.7 3.0

0.75 7.5 12.2 6.9 × 7.7 3.0

1.0 9.0 10.6 6.9 × 7.7 3.0

Coilcraft DO1813H Series

0.33 4 10 8.9 × 6.1 5

0.56 10 7.7 8.9 × 6.1 5

Coilcraft SLC7530 Series

0.27 0.1 14 7.5 × 6.7 3

0.35 0.1 11 7.5 × 6.7 3

0.4 0.1 8 7.5 × 6.7 3

LTC3615/LTC3615-1

3615fa

Output Capacitor COUT Selection

The selection of COUT is typically driven by the required

ESR to minimize voltage ripple and load step transients

(low-ESR ceramic capacitors are discussed in the next

section). Typically, once the ESR requirement is satisﬁ ed,

the capacitance is adequate for ﬁ ltering. The output ripple

ΔVOUT is determined by:

ΔΔVIESR

OUT L SW OUT

≤+

⎛

⎝

⎜

⎞

⎠

⎟

•••

where fSW = operating frequency, COUT = output capacitance

and ΔIL = ripple current in the inductor. The output ripple

is highest at maximum input voltage since ΔIL increases

with input voltage.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the capacitance, ESR or RMS

current handling requirement of the application. Aluminum

electrolytic, special polymer, ceramic and dry tantalum

capacitors are all available in surface mount packages.

Tantalum capacitors have the highest capacitance density,

but can have higher ESR and must be surge tested for

use in switching power supplies. Aluminum electrolytic

capacitors have signiﬁ cantly higher ESR, but can often

be used in extremely cost-sensitive applications provided

that consideration is given to ripple current ratings and

long term reliability.

Ceramic Input and Output Capacitors

Ceramic capacitors have the lowest ESR and can be cost

effective, but also have the lowest capacitance density,

high voltage and temperature coefﬁ cients, and exhibit

audible piezoelectric effects. In addition, the high-Q of

ceramic capacitors along with trace inductance can lead

to signiﬁ cant ringing.

Capacitors are tempting for switching regulator use

because of their very low ESR. Great care must be taken

when using only ceramic input and output capacitors.

Ceramic caps are prone to temperature effects which re-

quire the designer to check loop stability over the operating

temperature range. To minimize their large temperature and

voltage coefﬁ cients, only X5R or X7R ceramic capacitors

should be used.

When a ceramic capacitor is used at the input, and the

power is being supplied through long wires, such as from

a wall adapter, a load step at the output can induce ringing

at the VIN pin. At best, this ringing can couple to the output

and be mistaken as loop instability. At worst, the ringing

at the input can be large enough to damage the part.

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulﬁ ll a charge storage

requirement. During a load step, the output capacitor must

instantaneously supply the current to support the load

until the feedback loop raises the switch current enough

to support the load. The time required for the feedback

loop to respond is dependent on the compensation com-

ponents and the output capacitor size. Typically, three to

four cycles are required to respond to a load step, but only

in the ﬁ rst cycle does the output drop linearly. The output

droop, VDROOP, is usually about two to three times the

linear drop of the ﬁ rst cycle. Thus, a good place to start

is with the output capacitor size of approximately:

OUT OUT

SW DROOP

≈25.•

•

More capacitance may be required depending on the duty

cycle and load step requirements. In most applications,

the input capacitor is merely required to supply high

frequency bypassing, since the impedance to the supply

is very low.

APPLICATIONS INFORMATION

LTC3615/LTC3615-1

3615fa

Output Voltage Programming

The output voltages are set by external resistive dividers.

For example, VOUT2 can be set according to the following

equation:

OUT2 06 1 5

⎛

⎝

⎜

⎞

⎠

⎟

.•

The resistive divider allows pin VFB to sense a fraction of

the output voltage as shown in Figure 3.

Burst Clamp Programming

If the voltage on the MODE pin is less than 0.8V, Burst

Mode operation is enabled. If the voltage on the MODE pin

is less than 0.3V, the internal default burst clamp level is

selected. The minimum voltage on the ITH pin is typically

525mV (internal clamp).

If the voltage is between 0.45V and 0.8V, the voltage on

the MODE pin (VBURST) is equal to the minimum voltage

on the ITH pin (external clamp) and determines the burst

clamp level IBURST (typically from 1A to 3.5A).

When the ITH voltage falls below the internal (or external)

clamp voltage, the sleep state is entered. As the output

load current drops, the peak inductor current decreases

to keep the output voltage in regulation. When the output

load current demands a peak inductor current that is less

than IBURST, the burst clamp will force the peak inductor

current to remain equal to IBURST regardless of further

reductions in the load current.

Since the average inductor current is greater than the

output load current, the voltage on the ITH pin will

decrease. When the ITH voltage drops, sleep mode is

enabled in which both power switches are shut off along

with most of the circuitry to minimize power consumption.

All circuitry is turned back on and the power switches

resume operation when the output voltage drops out of

regulation. The value for IBURST is determined by the

desired amount of output voltage ripple. As the value of

IBURST increases, the sleep period between pulses and

the output voltage ripple increase. It is recommend to

use Burst Mode operation with internal clamp for tem-

peratures above 85°C ambient.

Pulse-Skipping Mode

Pulse-skipping mode, which is a compromise between low

output voltage ripple and efﬁ ciency, can be implemented

by connecting the MODE pin to SVIN. This sets IBURST to

0A. In this condition, the peak inductor current is limited

by the minimum on-time of the current comparator. The

lowest output voltage ripple is achieved while still operating

discontinuously. During very light output loads, pulse-

skipping allows only a few switching cycles to skip while

maintaining the output voltage in regulation.

Internal and External Compensation

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC load current.

When a load step occurs, like the one shown in Figure 5,

VOUT shifts by an amount equal to ΔILOAD • ESR, where

ESR is the effective series resistance of COUT. ΔILOAD

also begins to charge or discharge COUT, generating the

feedback error signal that forces the regulator to adapt

to the current change and return VOUT to its steady-state

value. During this recovery time, VOUT can be monitored

for excessive overshoot or ringing, which would indicate

a stability problem. The availability of the ITH pin allows

the transient response to be optimized over a wide range

of output capacitance.

The ITH1 external components (15k and 100pF) shown

in Figure 3 will provide an adequate compensation as

well as a starting point for most applications. The values

can be modiﬁ ed slightly to optimize transient response

once the ﬁ nal PCB layout is complete and the particular

output capacitor type and value have been determined.

The output capacitors need to be selected because the

various types and values determine the loop gain and

phase. The gain of the loop will be increased by increas-

ing RC and the bandwidth of the loop will be increased

by decreasing CC. If RC is increased by the same factor

that CC is decreased, the zero frequency will be kept the

same, thereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

output voltage settling behavior is related to the stabil-

ity of the closed-loop system. The external compensa-

tion, forced continuous operation circuit in the Typical

APPLICATIONS INFORMATION

LTC3615/LTC3615-1

3615fa

50μs/DIV 3615 F05

VOUT

200mV/DIV

1A/DIV

100mA

VOUT = 1.8V

ILOAD = 100mA TO 3A

VMODE = 1.5V

COMPENSATION AND OUTPUT CAPACITOR

VALUES OF FIGURE 3

VOUT

100mV/DIV

1A/DIV

50μs/DIV 3615 F06

VOUT = 1.8V

ILOAD = 100mA TO 3A

VMODE = 1.5V

VIN = VITH = 3.3V

OUTPUT CAPACITOR VALUE FIGURE 3

Figure 6. Load Step Transient in FCM in AVP ModeFigure 5. Load Step Transient in FCM with External Compensation

Applications section uses faster compensation to improve

load step response.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. More output

capacitance may be required depending on the duty cycle

and load step requirements.

If the ITH pin is tied to SVIN, the active voltage positioning

(AVP) mode and the internal compensation is selected.

In AVP mode, the load regulation performance is inten-

tionally reduced, setting the output voltage at a point that

is dependent on the load current. When the load current

suddenly increases, the output voltage starts from a level

slightly higher than nominal so the output voltage can

droop more and stay within the speciﬁ ed voltage range.

When the load current suddenly decreases, the output

voltage starts at a level lower than nominal so the output

voltage can have more overshoot and stay within the

speciﬁ ed voltage range. This behavior is demonstrated

in Figure 6.

The beneﬁ t is a lower peak-to-peak output voltage devia-

tion for a given load step without having to increase the

output ﬁ lter capacitance. Alternatively, the output voltage

ﬁ lter capacitance can be reduced while maintaining the

same peak-to-peak transient response. For this operation

mode, the loop gain is reduced and no external compensa-

tion is required.

Programmable Switch Pin Slew Rate

As switching frequencies rise, it is desirable to minimize the

transition time required when switching to minimize power

losses and blanking time for the switch to settle. However,

fast slewing of the switch node results in relatively high

external radiated EMI and high on-chip supply transients,

which can cause problems for some applications.

APPLICATIONS INFORMATION

LTC3615/LTC3615-1

3615fa

(7a) Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor

The LTC3615 allows the user to control the slew rate of

the switching node SW by using the SRLIM pin. Tying this

pin to ground selects the fastest slew rate. The slowest

slew rate is selected when the pin is open. Connecting a

resistor (between 10k to 100k) from SRLIM pin to ground

adjusts the slew rate between the maximum and minimum

values. The reduced dV/dt of the switch node results in a

signiﬁ cant reduction of the supply and ground ringing, as

well as lower radiated EMI. See Figure 7a and the Typical

Performance Characteristics section for examples.

Reducing the slew rate causes a trade-off between ef-

ﬁ ciency and low EMI (see Figure 7b).

Particular attention should be used with very high switching

frequencies. Using the slowest slew rate (SRLIM open)

can reduce the minimum duty cycle capability.

Soft-Start

The RUNx pins provide a means to shut down each chan-

nel of the LTC3615. Pulling both pins below 0.3V places

the LTC3615 in a low quiescent current shutdown state

(IQ < 1μA).

After enabling the LTC3615 by bringing either one or both

RUNx pins above the threshold, the enabled channels enter

a soft-start-up state. The type of soft-start behavior is set

by the TRACK/SSx pins. The soft-start cycle begins with

an initial discharge pulse pulling down the TRACK/SSx

pin to SGND and discharging the external capacitor CSS

(see Figure 3).

The initial discharge is adequate to discharge capacitors

up to 33nF. If a larger capacitor is required, connect the

external soft-start resistor RSS to the RUN pin to fully

discharge the capacitor.

1. Tying this pin to SVIN selects the internal soft-start

circuit. This circuit ramps the output voltage to the ﬁ nal

value within 1ms.

2. If a longer soft-start period is desired, it can be set ex-

ternally with a resistor and capacitor on the TRACK/SSx

pins as shown in Figure 3. The voltage applied at the

TRACK/SSx pins sets the value of the internal refer-

ence at VFB until TRACK/SSx is pulled above 0.6V. The

external soft-start duration can be calculated by using

the following equation:

tRCIn SV

SV V

SS SS SS IN

=⎛

⎝

⎜

⎞

⎠

⎟

•• –.06

3. The TRACK/SSx pin can be used to track the output

voltage of another supply.

Regardless of either the internal or external soft-start

state, the MODE pin is ignored during start-up and the

regulator defaults to pulse-skipping mode. In addition,

the PGOODx pin is kept low, and the frequency foldback

function is disabled.

APPLICATIONS INFORMATION

(7b) Efﬁ ciency vs SRLIM Resistor Programming

Figure 7. Slew Rate and the SRLIM Resistor

1V/DIV

2ns/DIV 3615 F07a

SRLIM =

SGND OR SVIN

VIN = 3.3V

VOUT = 1.8V

IOUT = 1A

OPEN

40.2k

100k

VIN (V)

2.25

EFFICIENCY (%)

3.06 3.88 4.69

5.50

3615 07b

VOUT = 1.8V

IOUT = 1A

FCM

GND OR SVIN

OPEN

40.2k 20k

LTC3615/LTC3615-1

3615fa

Output Voltage Tracking Input

If SRLIM is low, once VTRACK/SS reaches or exceeds 0.6V

the run state is entered, and the MODE selection, power

good and current foldback circuits are enabled.

In the run state, the TRACK/SS pin can be used to track

down/up the output voltage of another supply. If the

VTRACK/SS again drops below 0.6V, the LTC3615 enters

the down-tracking state and the VOUT is referenced to

the TRACK/SS voltage. If VTRACK/SS reaches 0.1V value

the switching frequency is reduced by 4x to ensure that

the minimum duty cycle limit does not prevent the out-

put from following the TRACK/SS pin. The run state will

resume if the VTRACK/SS again exceeds 0.6V and the VOUT

is referenced to the internal reference.

Through the TRACK/SS pin, the output voltage can be set

up to either coincidental or ratiometric tracking, as shown

in Figures 8 and 9.

To implement the coincidental tracking waveform in

Figure 8, connect an extra resistive divider to the output

of the master channel and connect its midpoint to the

TRACK/SS pin for the slave channel. The ratio of this

divider should be selected the same as that of the slave

channel’s feedback divider (Figure 10).

In this tracking mode, the master channel’s output must

be set higher than slave channel’s output. To implement

the ratiometric start-up in Figure 9, no extra divider is

needed; simply connect the TRACK/SS pin to the other

channel’s VFB pin (Figure 12).

APPLICATIONS INFORMATION

Figure 8. Coincident Start-Up Tracking Figure 9. Ratiometric Start-Up Tracking

Figure 10. Set for Coincidentally

Tracking (R3 = R5, R4 = R6)

Figure 11. Alternative Set-Up for Coincident

Start-Up Tracking (R1 = R3, R2 = R3 = R5)

Figure 12. Set-Up for

Ratiometric Tracking

TIME

VOUT1

VOUT2

OUTPUT VOLTAGE

3615 F08 TIME 3615 F09

VOUT1

VOUT2

OUTPUT VOLTAGE

VOUT1

FB1

LTC3615

TRACK/SS2

FB2

VOUT2

3615 F10

VOUT1

FB1

LTC3615

TRACK/SS2

FB2

VOUT2

3615 F11

VOUT1

FB1

LTC3615

TRACK/SS2

FB2

VOUT2

3615 F12

LTC3615/LTC3615-1

3615fa

APPLICATIONS INFORMATION

External Reference Input (DDR Mode)

If SRLIM is tied to SVIN, the TRACK/SS pin can be used

as an external reference input between 0.3V and 0.5V, if

desired (see Figure 13).

In DDR mode, the maximum slew rate is selected. If

VTRACK/SS is within 0.3V and 0.5V, the PGOOD function

is enabled. If VTRACK/SS is less than 0.3V, the output cur-

rent foldback is disabled and the PGOOD pin is always

pulled down.

Figure 13. Tracking if VSRLIM Is Low

Figure 14. Tracking if VSRLIM Is Tied to SVIN

SOFT-START

STATE

tSS > 1ms

SHUTDOWN

STATE

0.6V

0.1V

VIN

VFB PIN

VOLTAGE

TRACK/SS

PIN VOLTAGE

RUN PIN

VOLTAGE

SVIN PIN

VOLTAGE

RUN STATE RUN STATE

TIME

3615 F13

REDUCED

SWITCHING

FREQUENCY

DOWN-

TRACKING

STATE

UP-

TRACKING

STATE

SOFT-START

STATE

tSS > 1ms

SHUTDOWN

STATE

0.3V

0.45V

0.3V

0.1V

VIN

VFB PIN

VOLTAGE

EXTERNAL

VOLTAGE

REFERENCE 0.45V

TRACK/SS

PIN VOLTAGE

RUN PIN

VOLTAGE

SVIN PIN

VOLTAGE

RUN STATE RUN STATE

TIME

3615 F14

REDUCED

SWITCHING

FREQUENCY

DOWN-

TRACKING

STATE

UP-

TRACKING

STATE

LTC3615/LTC3615-1

3615fa

DDR Application

The LTC3615 can be used in DDR memory power supply

applications by tying the SRLIM pin to SVIN. In DDR

mode, the maximum slew rate is selected. The output can

both source and sink current. Current sinking is typically

limited to 1.5A, for 1MHz frequency and 1μH inductance,

but can be lower at higher frequencies and low output

voltages. If higher ripple current can be tolerated, smaller

inductor values can increase the sink current limit. See

the Typical Performance Characteristics curves for more

information. In addition, in DDR mode, lower external

reference voltages and tracking output voltages between

channels are possible. See the Output Voltage Tracking

Input section.

Single, Low Ripple 6A Output Application

The LT3615 can generate a single, low ripple 6A output if

the outputs of the two switching regulators are tied together

and share a single output capacitor (see Figure 15 on back

of data sheet). In order to evenly share the current between

the two regulators, it is needed to connect pins FB1 to

FB2, ITH1 to ITH2 and to select forced continuous mode

at the MODE pin. To achieve lowest ripple, 90°, or better,

180°, antiphase is selected by connecting the PHASE pin

to midrail or SVIN. There are several advantages to this

2-phase buck regulator. Ripple currents at the input and

output are reduced, reducing voltage ripple and allowing

the use of smaller, less expensive capacitors. Although

two inductors are required, each will be smaller than the

inductor required for a single-phase regulator. This may

be important when there are tight height restrictions on

the circuit.

Efﬁ ciency Considerations

The efﬁ ciency of a switching regulator is equal to the output

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efﬁ ciency and which change would produce

the most improvement. Efﬁ ciency can be expressed as:

Efﬁ ciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

APPLICATIONS INFORMATION

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of

the losses: VIN quiescent current and I2R losses. The VIN

quiescent current loss dominates the efﬁ ciency loss at

very low load currents whereas the I2R loss dominates

the efﬁ ciency loss at medium to high load currents. In a

typical efﬁ ciency plot, the efﬁ ciency curve at very low load

currents can be misleading since the actual power lost is

of little consequence.

1. The VIN quiescent current is due to two components: the

DC bias current as given in the Electrical Characteristics

and the internal main switch and synchronous switch

gate charge currents. The gate charge current results

from switching the gate capacitance of the internal power

MOSFET switches. Each time the gate is switched from

high to low to high again, a packet of charge dQ moves

from VIN to ground. The resulting dQ/dt is the current

out of VIN due to gate charge, and it is typically larger

than the DC bias current. Both the DC bias and gate

charge losses are proportional to VIN, thus, their effects

will be more pronounced at higher supply voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In

continuous mode the average output current ﬂ owing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

top and bottom MOSFET RDS(ON) and the duty cycle

(DC), as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteristics

curves. To obtain I2R losses, simply add RSW to RL and

multiply the result by the square of the average output

current.

Other losses, including CIN and COUT ESR dissipative losses

and inductor core losses, generally account for less than

2% of the total loss.

Thermal Considerations

In most applications, the LTC3615 does not dissipate much

heat due to its high efﬁ ciency. However, in applications

LTC3615/LTC3615-1

3615fa

Design Example

As a design example, consider using the LTC3615 in an

application with the following speciﬁ cations:

VIN = 3.3V to 5.5V

VOUT1 = 2.5V

VOUT2 = 1.2V

IOUT1(MAX) = 1A

IOUT2(MAX) = 3A

IOUT(MIN) = 100mA

f = 2.25MHz

Because efﬁ ciency is important at both high and low

load current, Burst Mode operation will be selected by

connecting the MODE pin to SGND.

First, calculate the timing resistor:

REHz

MHz k

RT SYNC/

•

411

225 178

Next, calculate the inductor values for about 1A ripple

current at maximum VIN:

MHz A

125

225 1 125

55 0=⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

⎟=

.•

•–

..66

212

225 1 112

μH

MHz A

=⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

⎞

⎠

.•

•–

.⎟⎟ =042.μH

Using a standard value of 0.56μH and 0.47μH inductors

results in maximum ripple currents of:

ΔIV

MHz μH

225 056 125

=⎛

⎝

⎜

⎞

⎠

⎟

⎛

⎝

⎜

.•.•–

⎞⎞

⎠

⎟=

=⎛

⎝

⎜

⎞

⎠

⎟

108

225 047 11

.•.•–

MHz μH

Δ..

55 089

⎛

⎝

⎜

⎞

⎠

⎟=

COUT will be selected based on the ESR that is required

to satisfy the output voltage ripple requirement and the

bulk capacitance needed for loop stability. For this design,

47μF ceramic capacitors will be used with X5R or X7R

dielectric.

CIN should be sized for a maximum current rating of:

III A

RMS MAX OUT OUT RMS()

=+ =

APPLICATIONS INFORMATION

where the LTC3615 is running at high ambient temperature

with low supply voltage and high duty cycles, such as in

dropout, the heat dissipated may exceed the maximum

junction temperature of the part. If the junction temperature

reaches approximately 160°C, all four power switches

will be turned off and the SW node will become high

impedance.

To prevent the LTC3615 from exceeding the maximum

junction temperature, the user will need to do some thermal

analysis. To determine whether the power dissipated

exceeds the maximum junction temperature of the part.

The temperature rise is given by:

RISE = PD • θJA

where PD is the power dissipated by the regulator, and

θJA is the thermal resistance from the junction of the die

to the ambient temperature. The junction temperature,

TJ, is given by:

J = TA + TRISE

where TA is the ambient temperature.

As an example, consider this case: the LTC3615 is in

dropout at an input voltage of 3.3V with a load current for

each channel of 2A at an ambient temperature of 70°C.

Assuming a 20°C rise in junction temperature, to 90°C,

results in an RDS(ON) of 0.086mΩ (see the graph in the

Typical Performance Characteristics section). Therefore,

the power dissipated by the part is:

D = (I12 + I22) • RDS(ON) = 0.69W

For the QFN package, the θJA is 37°C/W.

Therefore, the junction temperature of the regulator operating

at 70°C ambient temperature is approximately:

J = 0.69W • 37°C/W + 70°C = 95°C

Note that for very low input voltage, the junction temperature

will be higher due to increased switch resistance RDS(ON).

It is not recommended to use full load current at high

ambient temperature and low input voltage.

To maximize the thermal performance of the LTC3615, the

Exposed Pad should be soldered to a ground plane. See

the PC Board Layout Checklist.

LTC3615/LTC3615-1

3615fa

Decoupling the PVIN with two 47μF capacitors is adequate

for most applications.

Finally, it is possible to deﬁ ne the soft-start up time

choosing the proper value for the capacitor and the resistor

connected to TRACK/SS pin. If one sets minimum TSS =

5ms and a resistor of 4.7M, the following equation can

be solved with the maximum SVIN = 5.5V:

Cms

MIn V

SS =⎛

⎝

⎜

⎞

⎠

⎟

47 55

55 06

.• .

.–.

The standard value of 10nF and 4.7M guarantees the

minimum soft-start time of 5ms. In Figure 3, channel 1

shows the schematic for this design example.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3615:

1. A ground plane is recommended. If a ground plane

layer is not used, the signal and power grounds should be

segregated with all small signal components returning to

the SGND pin at one point which is then connected to the

PGND node at the exposed pad close to the LTC3615

2. Connect the (+) terminal of the input capacitors, CIN, as

close as possible to the PVINx pins, and the (–) terminal

as close as possible to the exposed pad PGND. This

capacitor provides the AC current into the internal

power MOSFETs.

3. Keep the switching nodes, SWx, away from all sensitive

small signal nodes FBx, ITHx, RTSYNC, SRLIM.

4. Flood all unused areas on all layers with copper. Flooding

with copper will reduce the temperature rise of power

components. Connect the copper areas to PGND

(exposed pad) for best performance.

5. Connect the VFBx pins directly to the feedback resistors.

The resistor divider must be connected between VOUTx

and SGND.

APPLICATIONS INFORMATION

DDR Memory Termination

FB1

MODE

LTC3615

3615 TA03a

SGND PGND

RUN1

TRACK/SS1

ITH1

PHASE

RUN2

TRACK/SS2

PGOOD2

ITH2

PGOOD1

RT/SYNC

SRLIM

VIN

3.3V

SVIN

CIN1

47μF

CIN2

47μF

CIN3

1μF L1

0.47μH

COUT1

47μF

VDDQ

1.8V/3A

121k

60.4k

15k

1000pF

R10

15k

1000pF

150k

49.9k

FB2

0.47μH

COUT2

47μF

49.9k

10pF

226k

174k

VTT

0.9V

3A/–1.5A

(2s) SW1

(2s) PVIN1 (2s) PVIN2

(2s) SW2

Ratiometric Start-Up

3615 TA03b

500mV/

DIV

500μs/DIV

VDD

VTT

TYPICAL APPLICATIONS

LTC3615/LTC3615-1

3615fa

External Compensation, Forced Continuous Operation, In-Phase Switching, Slew Rate Limit, Common PGOOD Output

(2s) SW1

FB1

MODE

LTC3615

3615 TA02

SGND

RUN1

TRACK/SS1

178k

ITH1

PHASE

RUN2

TRACK/SS2

PGOOD2

ITH2

PGOOD1

RT/SYNC

SRLIM

MODE

VIN

3.3V

RUN

PGOOD

SVIN (2s) PVIN1 (2s) PVIN2 0.47μH

47μF

VOUT1

1.8V/3A

412k

205k

RC2

43k

CC2

220pF

RC1

43k

CC1

220pF

(2s) SW2

FB2

0.47μH

47μF

VOUT2

2.5V/3A

665k

210k

10pF

40.2k

100k

PGND

1μF47μF47μF

226k

174k

TYPICAL APPLICATIONS

VOUT1 Waveform VOUT2 Waveform

3615 TA02b

VOUT1

100mV/DIV

IOUT1

1A/DIV

20μs/DIV 3615 TA02c

VOUT2

100mV/DIV

IOUT2

1A/DIV

20μs/DIV

LTC3615/LTC3615-1

3615fa

TYPICAL APPLICATIONS

Coincident Start-Up Coincident Tracking Up/Down

3615 TA04b

500mV/

DIV

2ms/DIV

VOUT1

VOUT2

3615 TA04c

500mV/

DIV

200ms/DIV

VOUT1

VOUT2

FB1

MODE

LTC3615-1

3615 TA04a

SGND PGND

RUN1

TRACK/SS1

ITH1

PHASE

RUN2

TRACK/SS2

PGOOD2

ITH2

PGOOD1

RT/SYNC

SRLIM

VIN

3.3V

SVIN

47μF

47μF L1

0.47μH

CO11

47μF

VOUT1

1.8V/3A

CO12

22μF

715k

357k

RC2

15k

CC3

470pF

RC1

15k

CC1

1000pF

453k

FB2

0.47μH

CO21

47μF

294k

CC2

10pF

CC4

10pF

CO22

22μF

VOUT2

1.2V/3A

CF1

1μF

RF1

24Ω

4.7M

10nF

100k

200k

100k

CSYNC

15pF

2MHz

CLOCK

PGOOD2

PGOOD1

22pF

(2s) SW1

(2s) SW2

(2s) PVIN1 (2s) PVIN2

174k

226k

Master and Slave for Coincident Tracking Outputs Using a 2MHz External Clock

LTC3615/LTC3615-1

3615fa

PACKAGE DESCRIPTION

FE24 (AA) eTSSOP REV A 0510

0.09 – 0.20

(.0035 – .0079)

0o – 8o

0.25

REF

RECOMMENDED SOLDER PAD LAYOUT

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

134

5678 9 10 11 12

14 13

7.70 – 7.90*

(.303 – .311)

3.25

(.128)

2.74

(.108)

2021222324 19 18 17 16 15

1.20

(.047)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC 0.195 – 0.30

(.0077 – .0118)

TYP

2.74

(.108)

0.45 p0.05

0.65 BSC

4.50 p0.10

6.60 p0.10

1.05 p0.10

3.25

(.128)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

FE Package

24-Lead Plastic eTSSOP (4.4mm)

(Reference LTC DWG # 05-08-1771 Rev A)

Exposed Pad Variation AA

LTC3615/LTC3615-1

3615fa

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697)

PACKAGE DESCRIPTION

4.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

2423

BOTTOM VIEW—EXPOSED PAD

2.45 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.45 ± 0.05

(4 SIDES)

3.10 ± 0.05

4.50 ± 0.05

PACKAGE OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 × 45° CHAMFER

LTC3615/LTC3615-1

3615fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 7/10 LTC3615-1 added. Reﬂ ected throughout the data sheet 1 to 32

LTC3615/LTC3615-1

3615fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0710 REV A • PRINTED IN USA

200ns/DIV 3615 F16

VSW1

2V/DIV,

1A/DIV

VSW2

IL1 + IL2

IL2

IL1

MODE = FCM

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

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LTC3546 5.5V, Dual 3A/1A, 4MHz, Synchronous Step-Down

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95% Efﬁ ciency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 160μA, ISD < 1μA,

4mm × 5mm QFN-28 Package

LTC3417A-2 5.5V, Dual 1.5A/1A, 4MHz, Synchronous Step-Down

DC/DC Converter

95% Efﬁ ciency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 125μA, ISD < 1μA,

TSSOP-16E and 3mm × 5mm DFN-16 Packages

LTC3612 5.5V, 3A, 4MHz, Synchronous Step-Down DC/DC

Converter

95% Efﬁ ciency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75μA, ISD < 1μA,

3mm × 4mm QFN-20 and TSSOP-20E Packages

LTC3614 5.5V, 4A, 4MHz, Synchronous Step-Down DC/DC

Converter

95% Efﬁ ciency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75μA, ISD < 1μA,

3mm × 4mm QFN-20 and TSSOP-20E Packages

LTC3616 5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC

Converter

95% Efﬁ ciency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.6V, IQ = 75μA, ISD < 1μA,

3mm × 5mm QFN-24 Package

Figure 15. Single, Low Ripple 6A Output

(2s)

SW1

FB1

LTC3615

3615 F15

SGND PGND

RUN1

TRACK/SS1

ITH1

PHASE

RUN2

TRACK/SS2

PGOOD2

ITH2

PGOOD1

RT/SYNC

MODE

SRLIM

VIN

3.3V

SVIN (2s)

PVIN1

(2s)

PVIN2

47μF 1μF

0.47μH

VOUT

1.2V/6A

47μF

102k

7.5k

2000pF

(2s) SW2

FB2

20pF

226k

174k

Figure 16. Reduced Ripple Current

(Waveform IL1 + IL2) and Ripple Voltage

(Not Shown) Through 180° Phase Shift

Between SW1 and SW2

Figure 17. Efﬁ ciency vs Load Current

for VOUT = 1.2V and IOUT Up to 6A

OUTPUT CURRENT (A)

0.01

EFFICIENCY (%)

0.1 1 10

100

3615 F17

VOUT = 1.2V

MODE = FCM

VIN = 2.5V

VIN = 3.3V

VIN = 5V