IRDC3871
1
USER GUIDE FOR IRDC3871 EVALUATION BOARD
The IR3871 SupIRBuckTM
is an easy-to-use,
fully integrated and highly efficient DC/DC
voltage regulator. The onboard constant on
time hysteretic controller and MOSFETs make
IR3871 a space-efficient solution that delivers
up to 8A of precisely controlled output voltage
at 60°C ambient temperature without airflow.
IR3871 is housed in a 20-lead 5mmx6mm QFN
package.
Key features offered by IR3871 include:
programmable switching frequency, soft start,
and over current protection allowing a very
flexible solution suitable for many different
applications and an ideal choice for battery
powered applications.
Additional features include pre-bias startup, a
very precise 0.5V reference, over/under voltage
protection, power good output, and enable input
with voltage monitoring capability.
This user guide contains the schematic, bill of
materials, and operating instructions of the
IRDC3871 evaluation board. Detailed product
specifications, application information and
performance curves at different operating
conditions are available in the IR3871 data
sheet.
BOARD FEATURES
SupIRBuckTM
DESCRIPTION
•VIN
= +12V
•VCC = +5V
•VOUT
= +1.05V
•IOUT
= 0 to 8A
•FS
= 300kHz @ CCM
•L = 1.5µH
•CIN
= 22µF
(ceramic 1210) + 68µF (electrolytic)
•COUT
= 47µF (ceramic 0805) + 330µF (PC-CON)
IRDC3871
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CONNECTIONS and OPERATING INSTRUCTIONS
LAYOUT
The PCB is a 4-layer board. All layers are 2 oz. copper.
IR3871 and other components are
mounted
on the top and bottom layers of the board.
The power supply decoupling capacitors, bootstrap capacitor and feedback components are located
close to IR3871. To improve efficiency, the circuit board is designed to minimize the length of the on-
board power ground current path.
Table 1. Connections
A well regulated +12V input supply should be connected to VIN and PGND. A maximum load of 8A
may be connected to VOUT
and PGND. The connection diagram is shown in Fig. 1
and inputs and
outputs of the board are listed in Table 1.
IRDC3871 has two input supplies, one for biasing (VCC) and the other for input voltage (VIN).
Separate supplies should be applied to these inputs. VCC
input should be a well regulated 4.5V to
5.5V supply connected to VCC and PGND. Enable (EN) is controlled
by the first switch of SW1. The
absolute maximum voltage of the external signal applied to EN (TP4) is +8V.
Connection Signal Name
VIN (TP2) VIN (+12V)
PGND (TP5) Ground for VIN
VCC (TP16) VCC Input (+5.0V)
PGND (TP17) Ground for VCC Input
VOUT (TP7) VOUT
(+1.05V)
PGND (TP10) Ground for VOUT
EN (TP4) Enable Input
AGND (TP26) Ground for Enable
IRDC3871
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CONNECTION DIAGRAM
Fig. 1: Connection Diagram of IRDC3871 Evaluation Board
VIN= +12V
GROUND
VOUT = +1.05V
GROUND
VCC = +5.0V
EN
GROUND
IRDC3871
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Fig. 2: Board Layout, Top Components
PCB Board Layout
Fig. 3: Board Layout, Bottom Components
Single point
connection
between analog
and power
ground.
IRDC3871
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Fig. 4: Board Layout, Top Layer
PCB Board Layout
Fig. 5: Board Layout, Bottom Layer
IRDC3871
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PCB Board Layout
Fig. 6: Board Layout, Mid-layer I
Fig. 7: Board Layout, Mid-layer II
IRDC3871
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Fig. 8: Schematic of the IRDC3871 Evaluation Board
VOUT TP7
TP10
EN
R9
0
VCC
TP23
+Vsws
TP24
+Vsws
+Vins
R12
open
C26
open
TP8
VOUTS
1
3
4
52
TP21
-Vsws
TP25
-Vin1s
C27
open
TP12
VSWS
1
3
4
52
TP22
+Vsws
VIN
C7
open
C8
open
C9
330uF
C10
47uF
-Vout1s
C11
open
-Vdd2s
-Vdd1s
C1
1uF
R7
2.80K
R8
2.55K
C12
0.1uF
C24
open
ISET
-Vout1s
+Vdd2s
Vout
+Vdd1s
+3.3V
+Vin1s
TP6
PGNDS
TP14
+3.3V
IR3871
U1
IR3871
3V3BP
8
NC
1
SS
6
PGOOD
3
FF 15
GND1
4
FB
5
GND 17
NC1
7
ISET
2
BOOT 14
VIN 13
VCC
10
NC2
9
PGND
11
PHASE 12
EN 16
C4
0.22uF
VCC
TP4
EN
SW1
EN / FCCM
1
2
4
3
TP17
PGND
C20
0.1uF
TP26
AGND
C5
open
VSW
C21
1uF
TP11
PGOOD
L1
1.5uH
R6
open
C22
open
TP1
VINS
R4
10.5K
R3
200K
C13
open
C2
22uF
C16
open
+
C3
68uF
TP2
VIN
TP5
PGND
C14
open
C17
open
C18
open
TP16
VCC
R10
open
FB
R5
10K
C15
open
C6
open
TP1 8
VOLTAGE SENSE
+Vins
1
+Vdd1s
2
+Vdd2s
3
+Vout1s
4
+Vout2s
5-Vout2s 10
-Vdd2s 8
-Vout1s 9
-Vins 6
-Vdd1s 7
-Vout1s
TP9
+Vout1s
R1
open
FCCM
PGOOD
+Vin1s TP20
+Vin1s
+3.3V
C25
1uF
+Vdd1s
-Vdd1s
R13
open
+3.3V TP15
-Vout1s
R14
open
TP19
FB
R11
open
TP13
SS
VSW
+Vdd2s
TP3
FCCM
SS
-Vdd2s
R2
10K
C19
open
-Vins
PGND
VOUT
C23
open
IRDC3871
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Bill of Materials
Quantity Reference Value Description Manufacturer Part-Number
1 C4 0.22uF CAP,CER,0.22uF,50V,10%,X7R,0603 Murata Electronics GRM188R71H224KA64D
3 C1, C21, C25 1uF CAP,CER,1.0uF,25V,X7R,0603 Murata Electronics GRM188R71E105KA12D
1 C2 22uF CAP,22uF,25V,CERAMIC,X5R,1210 Panasonic ECJ-4YB1E226M
1 C3 68uF CAP,68uF,25V,ELECT,FK,SMD Panasonic EEV-FK1E680P
1 C9 330uF POSCAP, 330uF, 2.5V, SMD Sanyo 2R5TPE330M9
1 C10 47uF CAP,CER,47uF,6.3V,X5R,0805 TDK C2012X5R0J476M
2 C12, C20 0.1uF CAP,CER,0.1uF,50V,10%,X7R,0603 TDK C1608X7R1H104K
1 L1 1.5uH INDUCTOR, 1.5uH, 11A, 6.7mOhm,SMD CYNTEC PCMB065T-1R5MS
2 R2, R5 10K RES,10.0K,OHM,1/10W,1%,0603,SMD Vishay/Dale CRCW060310K0FKEA
1 R9 0 RES,0.0,OHM,1/10W,1%,0603,SMD Vishay/Dale CRCW06030000Z0EAHP
1 R3 200K RES,200K,OHM,1/10W,1%,0603,SMD Vishay/Dale CRCW0603200KFKEA
1 R4 10.5K RES,10.5K,OHM,1/10W,1%,0603,SMD Vishay/Dale CRCW060310K5FKEA
1 R7 2.8K RES,2.8K,OHM,1/10W,1%,0603,SMD Vishay/Dale CRCW06032K80FKEA
1 R8 2.55K RES,2.55K,OHM,1/10W,1%,0603,SMD Vishay/Dale CRCW06032K55FKEA
1 SW1 SPST SWITCH, DIP, SPST, SMT C&K Components SD02H0SK
1 U1 IR3871 5mm x 6mm QFN IR IR3871MPBF
IRDC3871
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Fig. 9: Startup1Fig. 10: Shutdown1
Note1: Enable is pulled up to VCC after VIN = 12V and VCC = 5V are applied.
Note2: VOUT ripple is measured across the 47µF output capacitor.
TYPICAL OPERATING WAVEFORMS
Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT
= 1.05V, Fs = 300kHz, TA
= 25oC, no airflow,
unless otherwise specified
EN
PGOOD
SS
VOUT
EN
PGOOD
SS
VOUT
5V/div 5V/div 1V/div 500mV/div 5ms/div 5V/div 5V/div 1V/div 500mV/div 200µs/div
Fig. 11: DCM (IOUT
= 0.1A)2Fig. 12: CCM (IOUT
= 6A)2
VOUT
PHASE
iL
VOUT
PHASE
iL
20mV/div 5V/div 2A/div 10µs/div 20mV/div 5V/div 5A/div 2µs/div
PGOOD
VOUT
IOUT
PGOOD
FB
VOUT
iL
5V/div 1V/div 500mV/div 2A/div 50µs/div5V/div 1V/div 1V/div 10A/div 1ms/div
SS
Fig. 13: Over Current Protection (tested by
shorting VOUT to PGND on demoboard)
Fig. 14: Over Voltage Protection
(tested by shorting FB to VOUT)
IRDC3871
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TYPICAL OPERATING WAVEFORMS
Tested with demoboard shown in Fig. 8, VIN = 12V, VCC = 5V, VOUT
= 1.05V, Fs = 300kHz, TA
= 25oC, no airflow,
unless otherwise specified
Fig. 15: Load Transient 0-4A Fig. 16: Load Transient 4-8A
VOUT
PHASE
iL
VOUT
PHASE
iL
50mV/div 10V/div 2A/div 20µs/div50mV/div 10V/div 2A/div 20µs/div
TYPICAL PERFORMANCE
VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 8A, TA = 25oC, no airflow
Fig. 17: Thermal Image (IR3871: 66oC, Inductor: 58oC, PCB: 40oC)
IRDC3871
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Fig. 18: Efficiency vs. Output Current
TYPICAL OPERATING DATA
VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, IOUT = 0 ~ 8A, TA = 25oC, no airflow,
unless otherwise specified
35%
45%
55%
65%
75%
85%
95%
0.01 0.1 1 10
Output Current (A)
Efficiency
1.048
1.049
1.050
1.051
1.052
6 8 10 12 14 16 18 20
Input Voltage (V)
Output Voltage (V)
1.048
1.049
1.050
1.051
1.052
012345678
Output Current (A)
Output Voltage (V)
0
50
100
150
200
250
300
350
012345678
Output Current (A)
Frequency (kHz)
Fig. 19: Switching Frequency vs. Output
Current
Fig. 20: Load Regulation Fig. 21: Line Regulation at 8A Load
IRDC3871
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PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing
should be ≥0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard
extension ensures a large toe fillet that can be easily inspected.
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be no less than 0.17mm for
2 oz. Copper, or no less than 0.1mm for 1 oz.
Copper, or no less than 0.23mm for 3 oz. Copper.
IRDC3871
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Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled
away from the metal lead lands by a minimum of 0.025mm to ensure
NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum
overlap of the solder resist onto the copper of
0.05mm to accommodate solder resist misalignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥0.15mm due to the high aspect ratio of
the solder resist strip separating the lead lands from the pad land.
IRDC3871
Stencil Design
The Stencil apertures for the lead lands should be approximately
80% of the area of the lead lads. Reducing the
amount of solder deposited will minimize the occurrences of lead
shorts. If too much solder is deposited on the
center pad, the part will float and the lead lands will open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus
an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part
is pushed into the solder paste.
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IRDC3871
IR WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 06/2011
MIN MAX MIN MAX MIN MAX MIN MAX
A 0.8 1 0.0315 0.0394 L 0.35 0.45 0.0138 0.0177
A1 0 0.05 0 0.002 M 2.441 2.541 0.0962 0.1001
b 0.375 0.475 0.1477 0.1871 N 0.703 0.803 0.0277 0.0314
b1 0.25 0.35 0.0098 0.1379 O 2.079 2.179 0.0819 0.0858
c P 3.242 3.342 0.1276 0.1316
D Q 1.265 1.365 0.0498 0.05374
E R 2.644 2.744 0.1042 0.1081
e S 1.5 1.6 0.0591 0.063
e1 t1, t2, t3
e2 t4
t5
DIM
MILIMITERS INCHES
DIM
MILIMITERS INCHES
0.203 REF. 0.008 REF.
5.000 BASIC 1.970 BASIC
6.000 BASIC 2.364 BASIC
1.033 BASIC 0.0407 BASIC
0.650 BASIC 0.0256 BASIC
0.852 BASIC 0.0259 BASIC 1.153 BASIC 0.045 BASIC
0.727 BASIC 0.0286 BASIC
0.401 BASIC 0.016 BACIS
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