Numonyx(R) AxcellTM M29EW Datasheet 128-Mbit, 64-Mbit, 32-Mbit (x8 / x16, page read) 3 V supply flash memory Features Supply voltage -- VCC = 2.7 to 3.6 V for Program, Erase and Read -- VCCQ = 1.65 to 3.6 V for I/O buffers Asynchronous Random/Page Read -- Page size: 8 words or 16 bytes -- Page access: 25 ns -- Random access: 60 ns (BGA); 70 ns (TSOP) Buffer Program -- 256-word program buffer Programming time -- 0.56s per byte (1.8MB/s) typical when using 256-word buffer size in buffer program without VPPH -- 0.31s per byte (3.2MB/s) typical when using 256-word buffer size in buffer program with VPPH Memory organization -- 128Mbit: 128 main blocks, 128 Kbytes each -- 64Mbit: 128 main blocks, 64 Kbytes each or eight 8-Kbyte boot blocks (top or bottom) and 127 main blocks, 64 Kbytes each -- 32Mbit: 64 main blocks, 64 Kbytes each or eight 8-Kbyte boot blocks (top or bottom) and 63 main blocks, 64 Kbytes each Program/Erase controller -- Embedded byte/word program algorithms Program/ Erase Suspend and Resume -- Read from any block during Program Suspend -- Read and Program another block during Erase Suspend Blank Check to verify an erased block April 2011 208031-05 Unlock Bypass/Block Erase/Chip Erase/Write to Buffer -- Faster Buffered/Batch Programming -- Faster Block and Chip Erase VPP/WP# pin protection -- VPPH voltage on VPP to accelerate programming performance -- Protects highest/lowest block (H/L uniform) or top/bottom two blocks (T/B boot) Software protection -- Volatile Protection -- Non-Volatile Protection -- Password Protection -- Password Access Extended Memory block -- 128-word/256-byte block for permanent, secure identification. -- Programmable and lockable by Numonyx factory or customer. Low power consumption -- Standby Minimum 100,000 Program/Erase cycles per block 65 nm technology Density and Packaging -- 56-Lead TSOP (128-Mbit, 64-Mbit) -- 48-Lead TSOP (64-Mbit, 32-Mbit) -- 64-Ball Fortified BGA (128-Mbit, 64-Mbit) -- 48-Ball BGA (64-Mbit, 32-Mbit) JESD47E compliant Green packages available -- RoHS Compliant -- Halogen Free 1 Numonyx(R) AxcellTM M29EW Table of Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Data input/output or address input (DQ15/A-1) . . . . . . . . . . . . . . . . . . . . 15 2.5 Chip Enable (CE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Output Enable (OE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 Write Enable (WE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8 VPP/Write Protect (VPP/WP#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9 Reset (RST#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10 Ready/Busy output (RY/BY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11 Byte/Word organization select (BYTE#) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.12 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.13 VCCQ input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Auto Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6.1 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6.2 Verify Extended Memory Block protection indicator . . . . . . . . . . . . . . . . 20 3.6.3 Verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6.4 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Volatile Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 Non-Volatile Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 208031-05 Numonyx(R) AxcellTM M29EW 5.3 6 6.1 6.2 6.3 Table of Contents 5.2.1 Non-Volatile Protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.2 Non-Volatile Protection Bit Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Password Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.4 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1.6 Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1.7 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.8 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.9 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.10 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.11 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 Double Byte/Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.2 Quadruple Byte/Word Program command . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.3 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.4 Write to Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2.5 Enhanced Buffer Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2.6 Buffered Program Abort and Reset command . . . . . . . . . . . . . . . . . . . . 43 6.2.7 Write to Buffer Program Confirm command . . . . . . . . . . . . . . . . . . . . . . 44 6.2.8 Enhanced Buffer Program Confirm command . . . . . . . . . . . . . . . . . . . . 44 6.2.9 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2.10 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.2.11 Unlock Bypass Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2.12 Unlock Bypass Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2.13 Unlock Bypass Write to Buffer Program command . . . . . . . . . . . . . . . . 45 6.2.14 Unlock Bypass Enhanced Buffer Program command . . . . . . . . . . . . . . 45 6.2.15 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.1 Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.2 Exit Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.3 Lock Register command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 208031-05 3 Numonyx(R) AxcellTM M29EW Table of Contents 7 7.1 7.2 6.3.4 Password Protection mode command set . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.5 Non-Volatile Protection mode command set . . . . . . . . . . . . . . . . . . . . . 50 6.3.6 NVPB Lock Bit command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.7 Volatile Protection mode command set . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.8 Exit Protection command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.1.1 Password Protection Mode Lock bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . 57 7.1.2 Non-Volatile Protection Mode Lock bit (DQ1) . . . . . . . . . . . . . . . . . . . . . 57 7.1.3 Extended Memory Block Protection bit (DQ0) . . . . . . . . . . . . . . . . . . . . 57 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.2.1 Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.2.2 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.2.3 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.2.4 Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2.5 Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.2.6 Buffered Program Abort bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9 DC and AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10 Programming and Erase Performance . . . . . . . . . . . . . . . . . . . . . . . . . 81 11 Package Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Appendix A 128-Mbit Memory Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 C.1 Numonyx pre-locked Extended Memory Block . . . . . . . . . . . . . . . . . . . . . 96 C.2 Customer-lockable Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . 97 Appendix D Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4 208031-05 Numonyx(R) AxcellTM M29EW Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. List of Tables Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VPP/WP# functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus operations, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Bus operations, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read electronic signature - auto select mode - programmer method (8-bit mode) . . . . . . 23 Read electronic signature - auto select mode - programmer method (16-bit mode) . . . . . 23 Block protection - auto select mode - programmer method (8-bit mode) . . . . . . . . . . . . . . 24 Block protection - auto select mode - programmer method (16-bit mode) . . . . . . . . . . . . . 24 Standard commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Standard commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Fast Program commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Fast Program commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Block Protection commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Block Protection commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Lock Register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Block Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Power-up wait timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Read AC characteristics (Sheet of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Write AC characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Write AC characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Accelerated Program and Data Polling/Data Toggle AC characteristics . . . . . . . . . . . . . . 80 Programming and Erase Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TSOP56 - 56 lead thin small-outline package, 14 x 20 mm, package mechanical data . . 82 TSOP48 - 48 lead thin small-outline package, 12 x 20 mm, package mechanical data . . 83 BGA48 6 x 8 mm - 6 x 8 active ball array, package mechanical data. . . . . . . . . . . . . . . . . 84 Fortified BGA64 11 x 13 mm - 8 x 8 active ball array, package mechanical data. . . . . . . . 85 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Valid Combinations of SBC M29EW Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Block Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Extended Memory Block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 208031-05 5 Numonyx(R) AxcellTM M29EW List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. 6 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 56-Lead TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 48-Lead TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 48B BGA connections (top and bottom views) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 64B Fortified BGA connections (top and bottom views) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 128-Mbit Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 64-Mbit and 32-Mbit Uniform Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 64-Mbit and 32-Mbit Boot Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Boundary condition of program buffer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Write to Buffer Program fletcher and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 NVPB Program/Erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Lock Register program flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Data polling flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Toggle flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Status Register polling flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Power-up wait timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Random Read AC waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Random Read AC waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Byte Transition AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Page Read AC waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Write Enable Controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 72 Write Enable Controlled Program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . 73 Chip Enable Controlled Program waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . 75 Chip Enable Controlled Program waveforms (16-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . 76 Chip/Block Erase waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Reset AC waveforms (no program/erase in progress) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Reset AC waveforms (during program/erase operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Data polling AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Toggle/Alternative Toggle bit polling AC waveforms (8-bit mode) . . . . . . . . . . . . . . . . . . . 79 TSOP56 - 56 lead thin small-outline package,14 x 20 mm, package outline. . . . . . . . . . . 82 TSOP48 - 48 lead thin small-outline package, 12 x 20 mm, package outline . . . . . . . . . . 83 BGA48 6 x 8 mm - 6 x 8 active ball array, package outline . . . . . . . . . . . . . . . . . . . . . . . . 84 Fortified BGA64 11 x 13 mm - 8 x 8 active ball array, package outline . . . . . . . . . . . . . . . 85 208031-05 Numonyx(R) AxcellTM M29EW 1 Description Description The Numonyx(R) AxcellTM 128-Mbit, 64-Mbit and 32-Mbit M29EW flash memories, based on 65nm SBC (Single Bit per Cell) technology is the world's leading line of parallel NOR flash for embedded applications. They can be read, erased and reprogrammed; and these operations can be performed using a single low voltage (2.7 to 3.6 V) supply. Upon powerup, these memories default to their array read mode. The main memory array is divided into 64-Kword/128-Kbyte blocks or 32-Kword/64-Kbyte blocks that can be erased independently so that valid data can be preserved while old data is purged. Program and Erase commands are written to the command interface of the memory. An on-chip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error condition can be identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The M29EW supports Asynchronous Random Read and Page Read from all blocks of the memory array. It also features an internal program buffer which improves throughput by programming up to 256 words via one command sequence. The M29EW contains a 128-word Extended Memory Block which overlaps addresses with array block 0. The user can program this additional space; then protect it to permanently secure its contents. The device features different levels of hardware and software protection to secure blocks from unwanted modification (program or erase): l Hardware protection: - l VPP/WP# provides hardware protection for the highest (M29EWH), lowest (M29EWL), top two (M29EWT) or bottom two (M29EWB) blocks of the main memory array. Software protection: - Volatile Protection - Non-Volatile Protection - Password Protection - Password Access The M29EW is offered in TSOP56 (14 x 20 mm), TSOP48 (12 x 20 mm), Fortified BGA64 (11 x 13 mm, 1 mm pitch) and BGA48 (6 x 8 mm, 0.8 mm pitch) packages. The memories are delivered with all bits erased (set to `1'). 208031-05 7 Numonyx(R) AxcellTM M29EW Description Table 1. Signal descriptions Name Description Direction A0-Amax Address inputs Inputs DQ0-DQ7 Data inputs/outputs I/O DQ8-DQ14 Data inputs/outputs I/O DQ15/A-1 Data input/output or address input I/O or input CE# Chip Enable Input OE# Output Enable Input WE# Write Enable Input RST# Reset Input RY/BY# Ready/Busy output BYTE# Byte/word organization select VCCQ VCC VPP/WP#(1) Output Input Input/output buffer supply voltage Supply Supply voltage Supply VPP/Write Protect Input VSS Ground - NC Not connected - 1. VPP/WP# may be left unconnected as it is internally connected to a pull-up resistor, which enables Program/Erase operations. Figure 1. Logic diagram VCC VCCQ VPP/WP# 15 A0 - Amax DQ0 - DQ14 WE# CE# DQ15 / A-1 M29EW OE # RY/BY# RST# BYTE# VSS 1. 8 A22, A21 and A20 are maximum address pins for 128-Mbit, 64-Mbit and 32-Mbit density respectively. 208031-05 Numonyx(R) AxcellTM M29EW Figure 2. RFU A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 VPP/WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 RFU RFU Description 56-Lead TSOP connections 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56-Lead TSOP Pinout 14 mm x 20 mm Top View 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RFU RFU A16 BYTE# VSS DQ15 / A -1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 RFU VCCQ 1. A-1 is the least significant address bit in x8 mode. 2. A21 is valid for 64-Mbit density and above; otherwise, it is RFU. 3. A22 is valid for 128-Mbit density; otherwise, it is RFU. 4. RFU stands for Reserved for Future Use. 208031-05 9 Numonyx(R) AxcellTM M29EW Description Figure 3. A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 VPP/WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 48-Lead TSOP connections 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-Lead TSOP Pinout 12 mm x 20 mm Top View 1. A-1 is the least significant address bit in x8 mode. 2. A21 is valid for 64-Mbit density; otherwise, it is RFU. 3. RFU stands for Reserved for Future Use. 10 208031-05 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 Numonyx(R) AxcellTM M29EW Figure 4. Description 48B BGA connections (top and bottom views) 1 2 3 4 5 6 6 5 4 3 2 1 A A A3 A7 RY/BY# WE# A9 A13 A13 A9 WE# RY/BY# A7 A3 A4 A17 Vpp/ RST# A8 WP# A12 A12 A8 RST# Vpp/ A17 A4 B B WP# C C A2 A6 A18 A21 A10 A14 A14 A10 A21 A18 A6 A2 D D A1 A5 A20 A19 A11 A15 A15 A11 A19 A20 A5 A1 A0 D0 D2 D5 D7 A16 D7 D5 D2 D0 A0 CE# D8 D10 BYTE# D14 D12 D10 D8 CE# E E A16 F F D12 D14 BYTE# G G OE# D9 D11 Vcc D13 D15/ A-1 D15 /A-1 D13 Vcc D11 D9 OE# H H Vss D1 D3 D4 D6 Vss Vss BGA Top View- Ball side down D6 D4 D3 D1 Vss BGA Bottom View- Ball side up 1. A-1 is the least significant address bit in x8 mode. 2. A21 is valid for 64-Mbit density; otherwise, it is RFU. 3. RFU stands for Reserved for Future Use. 208031-05 11 Numonyx(R) AxcellTM M29EW Description Figure 5. 1 64B Fortified BGA connections (top and bottom views) 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A A RFU A3 A7 RY/BY# WE# A9 A4 / A17 Vpp WP# RST# A13 RFU RFU A13 A9 WE# RY/BY# A7 A 22 A12 A8 RST# Vpp/ WP# A17 A3 RFU B B RFU A8 A12 A22 A4 RFU C C RFU A2 A6 A18 A21 A10 A14 RFU RFU A14 A10 A21 A18 A6 A2 RFU D D RFU A1 A5 A20 RFU A0 D0 D2 A19 A 11 A15 Vccq Vccq A15 A11 A19 A20 A5 A1 RFU D5 Vss A16 D2 D0 A0 RFU E E D7 A16 Vss D7 D5 F F Vccq CE# D8 D10 D12 D14 BYTE#RFU RFU OE# D9 D11 Vcc RFU D1 D3 D4 RFU BYTE# D14 D12 D10 D8 CE# Vccq RFU D15/ D13 A-1 Vcc D11 D9 OE# RFU RFU Vss D4 D1 Vss RFU G G D13 D15/ RFU A-1 H H Vss D6 Vss RFU Fortified BGA Top View - Ball side down D6 Fortified BGA Bottom View- Ball side up 1. A-1 is the least significant address bit in x8 mode. 2. A21 is valid for 64-Mbit density and above; otherwise, it is RFU. 3. A22 is valid for 128-Mbit density; otherwise, it is RFU. 4. RFU stands for Reserved for Future Use. 12 D3 208031-05 Numonyx(R) AxcellTM M29EW 128-Mbit Block addresses A<22:0> 128 Mbit A<22:-1> 128 Mbit 0FFFFFF 0FE0000 7FFFFF 128-Kbyte Block 127 128-Kbyte Block 63 07FFFFF 07E 0000 003 FFFF 0020000 001 FFFF 7F0000 3FFFFF 01FFFF 128-Kbyte Block 1 128-Kbyte Block 0 010000 00FFFF 64-Kbyte Block 127 1 64-Kword Block 0 Word Wide (x16) Mode 3FFFFF 32-Kword Block 127 32-Kword Block 63 32-Kword Block 1 32-Kword Block 0 3F0000 1FFFFF 64-Kbyte Block 63 64-Kbyte Block 1 64-Kbyte Block 0 1F0000 001FFFF 32-Mbit 03FFFFF 0000000 64-Kword Block A<21:0> 64 Mbit A<20:0> 32 Mbit 07FFFFF 0010000 000FFFF 63 64-Mbit and 32-Mbit Uniform Block addresses A<21:-1> 64 Mbit A<20:-1> 32 Mbit 03E0000 64-Kword Block 000000 Byte-Wide (x8) Mode 07E0000 127 3F0000 0000000 Figure 7. 64-Kword Block 00FFFF 008000 007FFF 000000 Byte-Wide (x8) Mode 64-Mbit Figure 6. Description Word Wide (x16) Mode 208031-05 13 Numonyx(R) AxcellTM M29EW Description 64-Mbit and 32-Mbit Boot Block addresses A<21:-1> 64 Mbit A<20:-1> 32 Mbit A<21:0> 64 Mbit A<20:0> 32 Mbit 7F0000 - 7FFFFF 64KB/32KW Block 134 3F8000 - 3FFFFF 3F0000 - 3FFFFF 64KB/32KW Block 70 1F8000 - 1FFFFF 010000 - 01FFFF 64KB/32KW Block 8 008000 - 00FFFF 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 7 007000 - 007 FFF 6 006000 - 006 FFF 5 005000 - 005 FFF 4 004000 - 004 FFF 3 003000 - 003 FFF 2 002000 - 002 FFF 1 001000 - 001 FFF 0 000000 - 000 FFF 00E000 - 00FFFF 00C000 - 00DFFF 00A000 - 00BFFF 008000 - 09FFFF 006000 - 007 FFF 004000 - 005 FFF 002000 - 003 FFF 000000 - 001 FFF Bottom Boot Byte Wide (x8) Mode A<21:-1> 64 Mbit A<20:-1> 32 Mbit 70 1FF000 - 1FFFFF 69 1FE000 - 1FEFFF 68 1FD000 - 1FDFFF 67 1FC000 - 1FCFFF 66 1FB000 - 1FBFFF 65 1FA000 - 1FAFFF 64 1F9000 - 1F9FFF 3F0000 - 3F1FFF 63 1F8000 - 1F8FFF 3F0000 - 3F7FFF 3E0000 - 3EFFFF 64KB/32KW Block 62 1F0000 - 1F7FFF 1 008000 - 00FFFF 010000 - 01FFFF 64KB/32KW Block 1 008000 - 00FFFF 0 000000 - 007FFF 000000 - 00FFFF 64KB/32KW Block 0 000000 - 007 FFF 7F0000 - 7F1FFF 3FF000 - 3FFFFF 3FE000 - 3FFFFF 3FE000 - 3FEFFF 3FC000 - 3FDFFF 132 3FD000 - 3FDFFF 3FA000 - 3FBFFF 131 3FC000 - 3FCFFF 3F8000 - 3F9FFF 130 3FB000 - 3FBFFF 3F6000 - 3F7FFF 3FA000 - 3FAFFF 3F4000 - 3F5FFF 128 3F9000 - 3F9FFF 3F2000 - 337FFF 127 3F8000 - 3F8FFF 7E0000 - 7EFFFF 64KB/32KW Block 126 010000 - 01FFFF 64KB/32KW Block 000000 - 00FFFF 64KB/32KW Block 7FA000 - 7FBFFF 7F8000 - 7F9FFF 7F6000 - 7F7FFF 7F4000 - 7F5FFF 7F2000 - 7F3FFF Top Boot 64Mbit Byte Wide (x8) Mode A<20:0> 32 Mbit 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 134 7FC000 - 7FDFFF 14 Bottom Boot Word Wide (x16) Mode A<21:0> 64 Mbit 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 8KB/4KW Block 7FE000 - 7FFFFF 32-Mbit 64-Mbit Figure 8. 133 129 Top Boot 64Mbit Word Wide (x16) Mode Top Boot 32Mbit Byte Wide (x8) Mode 208031-05 Top Boot 32Mbit Word Wide (x16) Mode Numonyx(R) AxcellTM M29EW 2 Signal Descriptions Signal Descriptions See Figure 1: Logic diagram, and Table 1: Signal descriptions, for a brief overview of device signals. 2.1 Address inputs (A0-A22) The Address inputs select the cells in the memory array, CFI space to access during Bus Read operations. During Bus Write operations they direct the commands sent to the command interface of the Program/Erase controller. 2.2 Data inputs/outputs (DQ0-DQ7) During Bus Read operations, the data lines output the data stored at the selected address or register. During Bus Write operations, the data lines are used to input data or commands. 2.3 Data inputs/outputs (DQ8-DQ14) During Bus Read operations, the data lines output the data stored at the selected address when BYTE# is High, VIH. When BYTE# is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. Ignore these bits when reading the Status Register . 2.4 Data input/output or address input (DQ15/A-1) When the device operates in x16 bus mode, this pin behaves as a Data input/output pin, together with DQ8-DQ14. When the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. Throughout this document, when both references occur, consider the DQ15 function adding to the other data lines when in X16 mode and the A-1 function adding to the others addresses when in X8 mode, except when explicitly stated otherwise. 2.5 Chip Enable (CE#) The Chip Enable pin, CE#, activates the memory when it's low, VIL, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, the memory is deselected and power is reduced to standby level. 2.6 Output Enable (OE#) The Output Enable pin, OE#, controls the Bus Read operation of the memory. 208031-05 15 Numonyx(R) AxcellTM M29EW Signal Descriptions 2.7 Write Enable (WE#) The Write Enable pin, WE#, controls the Bus Write operation of the memory's command interface. 2.8 VPP/Write Protect (VPP/WP#) The VPP/WP# pin provides three functions: write protect function, programming acceleration, and the unlock bypass mode entry. When VPP/WP# is low, the write protect function provides hardware protection for the highest M29EWH block, the lowest M29EWL block, the top two M29EWT blocks, or the bottom two M29EW blocks (see Section 1: Description). Program and Erase operations on this block are ignored while VPP/Write Protect is Low. When VPP/WP# pin is High, VIH, the memory reverts to the previous protection status of the highest, lowest, top two or bottom two blocks . Program and Erase operations can now modify the data in this block unless the block is protected using other block protection method. When VPP/WP# pin is raised to VPPH in read mode, the memory automatically enters the Unlock Bypass mode (see Section 6.2.9). When VPP/WP# returns to VIH or VIL normal operation resumes. See the description of the Unlock Bypass command in the command interface section. When VPP/WP# pin is raised to VPPH during programming, it will accelerate the programming speed. The transitions from VIH to VPPH and from VPPH to VIH must be slower than tVHVPP (see Figure 31: Accelerated program timing waveforms). Never raise VPP/WP# to VPPH from any mode except in read mode or during programming, otherwise the memory may be left in an indeterminate state. A 0.1 F capacitor should be connected between the VPP/Write Protect pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during programming (see IPP1, IPP2, IPP3, IPP4 in Table 22: DC characteristics). The VPP/WP# pin may be left unconnected because it features an internal pull-up resistor. Refer to Table 2 for a summary of VPP/WP# functions. Table 2. VPP/WP# functions VPP/WP# 16 Function VIL Highest block protected or lowest block protected. VIH Highest and lowest block unprotected unless software protection is activated (see Section 4: Hardware Protection). VPPH Unlock bypass mode. VPPH Programming speed acceleration. 208031-05 Numonyx(R) AxcellTM M29EW 2.9 Signal Descriptions Reset (RST#) The Reset pin can be used to apply a Hardware Reset to the memory. A hardware reset is achieved by holding Reset Low, VIL, for at least tPLPX. After Reset goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL (or tPHGL or tRHGL), whichever occurs last. See Section 2.10: Ready/Busy output (RY/BY#), Table 26: Reset AC characteristics, Figure 29 and Figure 30 for more details. 2.10 Ready/Busy output (RY/BY#) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. During program or erase operations Ready/Busy is Low, VOL (see Table 17: Status Register bits). Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 26: Reset AC characteristics, Figure 29 and Figure 30. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A low value will then indicate that one, or more, of the memories is busy. The 10K ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1V VOL. 2.11 Byte/Word organization select (BYTE#) The BYTE# pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word organization select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode. 2.12 VCC supply voltage VCC provides the power supply for all operations (Read, Program and Erase). The command interface is disabled when VCC is Lockout voltage, VLKO. This prevents Bus Write operations from accidentally corrupting the data during power-up, power-down and power surges. The operation will abort, and the memory contents being altered will thus be invalid, if the VCC drops below VLKO while the Program/Erase controller is running. A 0.1 F capacitor should be connected between the VCC supply voltage pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations (see ICC1, ICC2, ICC3 in Table 22: DC characteristics). 2.13 VCCQ input/output supply voltage VCCQ provides the power supply to the I/O pins; it enables the I/Os to be powered independently from VCC. 208031-05 17 Numonyx(R) AxcellTM M29EW Signal Descriptions 2.14 VSS ground VSS is the reference for all voltage measurements. The device features two VSS pins; both of which must be connected to the system ground. 18 208031-05 Numonyx(R) AxcellTM M29EW 3 Bus Operations Bus Operations There are four standard bus operations that control the device. These are Bus Read (Random and Page modes), Bus Write, Output Disable, Standby. See Table 3: Bus operations, 8-bit mode and Table 4: Bus operations, 16-bit mode for a summary. Typical glitches of less than 3ns on Chip Enable, Write Enable, and Reset pins are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, registers or CFI space. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The page has a size of 8 words (or 16 bytes) and is addressed by the address inputs A2-A0 in x16 bus mode and A2-A0 plus DQ15/A-1 in x8 bus mode. The Extended Memory Blocks and CFI area do not support Page Read mode. A valid Bus Read operation involves setting the desired address on the Address inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data inputs/outputs will output the value, see Figure 20: Random Read AC waveforms (8-bit mode), Figure 23: Page Read AC waveforms (16-bit mode), and Table 23: Read AC characteristics (Sheet of 2), for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write to the command interface. A valid Bus Write operation begins by setting the desired address on the Address inputs. The Address inputs are latched by the command interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data inputs/outputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the entire Bus Write operation. See Figure 24, and Figure 25, Write AC waveforms, and Table 24 and Table 25, Write AC characteristics, for details of the timing requirements. 3.3 Output Disable The Data inputs/outputs are in the high impedance state when Output Enable is High, VIH. 3.4 Standby Driving Chip Enable High in Read mode, causes the memory to enter Standby mode and the data inputs/outputs pins are placed in the high-impedance state. To reduce the Supply current to the Standby Supply current, ICC2, Chip Enable should be held within VCC 0.3 V. For the Standby current level see Table 22: DC characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply current, ICC3, for Program or Erase operations until the operation completes. 208031-05 19 Numonyx(R) AxcellTM M29EW Bus Operations 3.5 Reset During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when RST# is at VIL. The power consumption is reduced to the standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. 3.6 Auto Select mode The Auto Select mode allows the system or the programming equipment to read the electronic signature, verify the protection status of the Extended Memory Block, and apply/remove Block protection. For example, this mode can be used by programming equipment to automatically match a device and the application code to be programmed. At power-up, the device is in Read mode, and can then be put in Auto Select mode by issuing the Auto Select command (see Section 6.1.2). The device cannot enter Auto Select mode when a program or erase operation is in progress (RY/BY# Low). However, Auto Select mode can be entered if the program or erase operation has been suspended by issuing a Program Suspend or Erase Suspend command (see Section 6.1.7). The Auto Select mode is exited by performing a reset. The device is returned to Read mode, except if the Auto Select mode was entered after an Erase Suspend or a Program Suspend command. In this case, it returns to the Erase or Program Suspend mode. 3.6.1 Read electronic signature The memory has two codes, the manufacturer code and the device code used to identify the memory. These codes can be accessed by performing read operations with control signals and addresses set as shown in Table 5: Read electronic signature - auto select mode programmer method (8-bit mode) and Table 6: Read electronic signature - auto select mode - programmer method (16-bit mode). These codes can also be accessed by issuing an Auto Select command (see Section 6.1.2: Auto Select command). 3.6.2 Verify Extended Memory Block protection indicator The Extended Memory Block is either Numonyx pre-locked or customer-lockable. The protection status of the Extended Memory Block (pre-locked or customer-lockable) can be accessed by reading the Extended Memory Block protection indicator. It can be read in Auto Select mode using either the programmer (see Table 7 and Table 8) or the in-system method (see Table 9 and Table 10). The protection status of the Extended Memory Block is then output on bit DQ7 of the Data input/outputs (see Table 3 and Table 4, Bus operations in 8-bit and 16-bit mode). 3.6.3 Verify block protection status The protection status of a block can be determined by performing a read operation with control signals and addresses set as shown in Table 7 and Table 8. If the block is protected, then 01h (in x 8 mode) is output on Data input/outputs DQ0-DQ7, otherwise 00h is output. 20 208031-05 Numonyx(R) AxcellTM M29EW 3.6.4 Bus Operations Hardware Block Protect Hardware protection of certain memory blocks is supported via the VPP/WP# write protection function. When VPP/WP# is VIL, the highest (M29EWH), lowest (M29EWL), top two (M29EWT), or bottom two (M29EWB) blocks are protected ; these, and other blocks, may also be enabled with software protection. 208031-05 21 Numonyx(R) AxcellTM M29EW Bus Operations Table 3. Bus operations, 8-bit mode Operation(1) Bus Read Address Inputs Data Inputs/Outputs CE# OE# WE# RST# VPP/WP# VIL VIL VIH VIH A[max:-1] DQ[14:8] DQ[7:0] Byte address Hi-Z Data output Command address Hi-Z Data input(3) X Bus Write VIL VIH VIL VIH Standby VIH X X VIH VIH X Hi-Z Hi-Z Output Disable VIL VIH VIH VIH X X Hi-Z Hi-Z X X X VIL X X Hi-Z Hi-Z Reset VIH (2) 1. X = VIL or VIH. 2. If WP# is Low, VIL, the highest, lowest, top two or bottom two blocks (depending on line item) remain protected. 3. Data input as required when issuing a command sequence, performing data polling or block protection. Table 4. Bus operations, 16-bit mode Operation(1) Bus Read Address Inputs Data Inputs/Outputs A[max:0] DQ[15:0] CE# OE# WE# RST# VPP/WP# VIL VIL VIH VIH X Word address Data output Command address Data input(3) Bus Write VIL VIH VIL VIH VIH(2) Standby VIH X X VIH VIH X Hi-Z Output Disable VIL VIH VIH VIH X X Hi-Z X X X VIL X X Hi-Z Reset 1. X = VIL or VIH. 2. If WP# is Low, VIL, the highest, lowest, top two or bottom two blocks (depending on line item) remain protected. 3. Data input as required when issuing a command sequence, performing data polling or block protection. 22 208031-05 Numonyx(R) AxcellTM M29EW Table 5. Read cycle(1) Bus Operations Read electronic signature - auto select mode - programmer method (8-bit mode) Address inputs Data inputs/outputs CE# OE# WE# Amax-A11 A10-A4 A3 A2 A1 A0 A-1 DQ[14:8] DQ[7:0] Manufacture r code VIL VIL VIL VIL X X 89h Device code (cycle 1) VIL VIL VIL VIH X X 7Eh 21h (128-Mbit) 10h (64-Mbit, boot) Device code VIL (cycle 2) VIL VIH X VIL VIH VIH VIH VIL X X 0Ch (64-Mbit, uniform) 1Ah (32-Mbit, boot) 1Dh (32-Mbit, uniform) Device code (cycle 3) VIH VIH VIH VIH X X 01h (128- and 64-Mbit uniform, 64- and 32-Mbit top) 00h (64- and 32-Mbit bottom, 32-Mbit uniform) 1. X = VIL or VIH. Table 6. Read electronic signature - auto select mode - programmer method (16-bit mode) Read cycle(1) Address inputs Data inputs/outputs CE# OE# WE# Amax-A11 A10-A4 A3 A2 A1 A0 DQ[15:0] Manufacturer code VIL VIL VIL VIL 0089h Device code (cycle 1) VIL VIL VIL VIH 227Eh 2221h (128-Mbit) 2210h (64-Mbit, boot) Device code (cycle 2) VIL VIL VIH X VIL VIH VIH VIH VIL 220Ch (64-Mbit, uniform) 221Ah (32-Mbit, boot) 221Dh (32-Mbit, uniform) Device code (cycle 3) VIH VIH VIH VIH 2201h (128- and 64-Mbit uniform, 64- and 32-Mbit top) 2200h (64- and 32-Mbit bottom, 32-Mbit uniform) 1. X = VIL or VIH. 208031-05 23 Numonyx(R) AxcellTM M29EW Bus Operations Table 7. Block protection - auto select mode - programmer method (8-bit mode) Address inputs Operation(1) Amax-A15 Verify Extended Memory Block protection indicator (bit DQ7) Data inputs/outputs CE# OE# WE# A14-A11 A10-A2 A1 A0 A-1 DQ[14:8] DQ[7:0] M29EWL 128-Mbit 89h (Numonyx prelocked) 09h (customerlockable) M29EWH 128-Mbit 99h (Numonyx prelocked) 19h (customerlockable) X M29EWL/B VIL 64-Mbit 32-Mbit VIL VIH VIH X VIL VIH X X 8Ah (Numonyx prelocked) 0Ah (customerlockable) 9Ah (Numonyx prelocked) 1Ah (customerlockable) M29EWH/T 64-Mbit 32-Mbit Verify block protection status BBA(2) 01h (protected) 00h (unprotected) VIL 1. X = VIL or VIH. 2. BBA = Block Base Address. For 128-Mbit, BBA should be Amax-A16 and A15 is X. Table 8. Block protection - auto select mode - programmer method (16-bit mode) Address inputs Operation(1) Data inputs/outputs CE# OE# WE# Amax-A15 A14-A11 A10-A2 A1 A0 M29EWL 128-Mbit 0089h (Numonyx prelocked) 0009h (customer-lockable) M29EWH 128-Mbit 0099h (Numonyx prelocked) 0019h (customer-lockable) Verify Extended Memory M29EWL/B Block 64-Mbit indicator 32-Mbit (bit DQ7) X VIL VIL VIH VIH X VIL VIH Verify block protection status 008Ah (Numonyx prelocked) 000Ah (customer-lockable) 009Ah (Numonyx prelocked) 001Ah (customer-lockable) M29EWH/T 64-Mbit 32-Mbit BBA(2) VIL 1. X = VIL or VIH. BBA = Block Base Address. 2. BBA = Block Base Address. For 128-Mbit, BBA should be Amax-A16 and A15 is X. 24 DQ[15:0] 208031-05 0001h (protected) 0000h (unprotected) Numonyx(R) AxcellTM M29EW 4 Hardware Protection Hardware Protection The M29EW features a VPP/WP# pin that protects the highest, lowest, top two or bottom two blocks. Refer to Section 2: Signal Descriptions for a detailed description of the signal. 5 Software Protection The M29EW has four different software protection modes: - Volatile Protection - Non-Volatile Protection - Password Protection - Password Access On first use all parts default to operate in non-volatile Protection mode and the customer is free to activate the non-volatile or the password protection mode. The desired protection mode is activated by setting either the one-time programmable NonVolatile Protection Mode Lock bit, or the Password Protection Mode Lock bit of the Lock Register (see Section 7.1: Lock Register). Programming the Non-Volatile Protection Mode Lock bit or the Password Protection Mode Lock bit, to `0' will permanently activate the Nonvolatile or the Password Protection mode, respectively. These two bits are one-time programmable and non-volatile: once the protection mode has been programmed, it cannot be changed and the device will permanently operate in the selected protection mode. It is recommended to activate the desired software protection mode when first programming the device. The Non-volatile and Password Protection modes both provide non-volatile Protection. Volatilely protected blocks and non-volatilely protected blocks can co-exist within the memory array. However, the volatile Protection only control the protection scheme for blocks that are not protected using the non-volatile or password protection. If the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. The device is shipped with all blocks unprotected. The block protection status can be read either by performing a read electronic signature (see Table 5 and Table 6) or by issuing an Auto Select command (see Table 16: Block Protection Status). For the lowest and highest blocks, an even higher level of block protection can be achieved by locking the blocks using the non-volatile Protection and then by holding the VPP/WP# pin Low. Password Access is a security enhancement offered on the M29EW device. This feature protects information stored in the main-array blocks by preventing content alteration or reads until a valid 64-bit password is received. Password Access may be combined with NonVolatile and/or Volatile Protection to create a multi-tiered solution. Please contact your Numonyx Sales representative for further details concerning Password Access feature. 208031-05 25 Numonyx(R) AxcellTM M29EW Software Protection 5.1 Volatile Protection mode The volatile Protection allows the software application to easily protect blocks against inadvertent change. However, the protection can be easily disabled when changes are needed. Volatile Protection bits, VPBs, are volatile and unique for each block and can be individually modified. VPBs only control the protection scheme for unprotected blocks that have their non-volatile Protection bits, NVPBs, cleared (erased to `1') (see Section 5.2: NonVolatile Protection mode and Section 6.3.5: Non-Volatile Protection mode command set). By issuing the VPB Program or VPB Clear commands, the VPBs are set (programmed to `0') or cleared (erased to `1'), thus placing associated blocks in the protected or unprotected state respectively. The VPBs can be set (programmed to `0') or cleared (erased to `1') as often as needed. When the parts are first shipped, or after a power-up or hardware reset, the VPBs default to be cleared. Refer to Section 6.3.7 for a description of the volatile Protection mode command set. 5.2 Non-Volatile Protection mode 5.2.1 Non-Volatile Protection bits A non-volatile Protection bit (NVPB) is assigned to each block. When a NVPB is set to `0', the associated block is protected, preventing any program or erase operations in this block. The NVPB bits can be set individually by issuing a NVPB Program command. They are nonvolatile and will remain set through a hardware reset or a power-down/power-up sequence. The NVPBs cannot be cleared individually, they can only be all cleared at the same time by issuing a Clear all Non-Volatile Protection bits command. The NVPBs can be protected all at a time by setting a volatile bit, the NVPB Lock bit (see Section 5.2.2: Non-Volatile Protection Bit Lock bit). If one of the non-volatile protected blocks needs to be unprotected (corresponding NVPB set to `1'), a few more steps are required: Note: 1. First, the NVPB Lock bit must be `1' by either putting the device through a power cycle, or hardware reset. 2. The NVPBs can then be changed to reflect the desired settings. 3. The NVPB Lock bit must be set to `0' once again to lock the NVPBs by associated command. The device operates normally again. 1 To achieve the best protection, it is recommended to execute the NVPB Lock Bit Program command early in the boot code and to protect the boot code by holding VPP/WP# Low, VIL. 2 The NVPBs and VPBs have the same function when VPP/WP# pin is High, VIH, as they do when VPP /WP# pin is at the voltage for program acceleration (VPPH). Refer to Table 16: Block Protection Status and Figure 9: Software protection scheme for details on the block protection mechanism, and to Section 6.3.5 for a description of the NonVolatile Protection mode command set. 26 208031-05 Numonyx(R) AxcellTM M29EW 5.2.2 Software Protection Non-Volatile Protection Bit Lock bit The Non-Volatile Protection Bit Lock bit (NVPB Lock bit) is a global volatile bit for all NVPBs. When set (programmed to `0'), it prevents changing the state of the NVPBs. When reset to `1', the NVPBs can be set and reset using the NVPB Program command and Clear all NVPBs command, respectively. There is only one NVPB Lock bit per device. Refer to Section 6.3.6 for a description of the NVPB Lock bit command set. Note: 5.3 1 No software command unlocks this bit unless the device is in password protection mode; in standard non-volatile Protection mode, it can be cleared only by taking the device through a hardware reset or a power-up. 2 The NVPB Lock bit must be set (programmed to `0') only after all NVPBs are configured to the desired settings. Password Protection mode The password protection mode provides an even higher level of security than the NonVolatile Protection mode by requiring a 64-bit password for unlocking the device NVPB Lock bit. In addition to this password requirement, the NVPB Lock bit is set `0' after power-up and reset to maintain the device in password protection mode. Successful execution of the Password Unlock command by entering the correct password clears the NVPB Lock bit, allowing for block NVPBs to be modified. If the password provided is incorrect, the NVPB Lock bit remains locked and the state of the NVPBs cannot be modified. To place the device in password protection mode, the following steps are required: 1. Prior to activating the password protection mode, it is necessary to set a 64-bit password and to verify it (see Password Program command and Password Read command). Password verification is only allowed before the password protection mode is activated. 2. The password protection mode is then activated by programming the Password Protection Mode Lock bit to `0'. This operation is not reversible and once the bit is programmed it cannot be erased, the device permanently remains in password protection mode, and the 64-bit password can neither be retrieved nor reprogrammed. Moreover, all commands to the address where the password is stored, are disabled. Refer to Table 16: Block Protection Status and Figure 9: Software protection scheme for details on the block protection scheme. Refer to Section 6.3.4 for a description of the Password Protection mode command set. Note: There is no means to verify the password after Password Protection mode is enabled. If the password is lost after enabling the Password Protection mode, there is no way to clear the NVPB Lock bit. 208031-05 27 Numonyx(R) AxcellTM M29EW Software Protection Figure 9. Software protection scheme VPB(2) Array block NVPB(1) NVPB Lock bit (3) Volatile protection Non-volatile protection Non-volatile protection mode Password protection mode AI13676 1. NVPBs default to `1' (block unprotected) when shipped from Numonyx. A block is protected or unprotected when its NVPB is set to `0' and `1', respectively. NVPBs are programmed individually and cleared collectively. 2. VPB default status depends on ordering option. A block is protected or unprotected when its VPB is set to `0' and `1', respectively. VPBs can be programmed and cleared individually. 3. The NVPB Lock bit is volatile and default to `1' (NVPB bits unlocked) after power-up or hardware reset. NVPB bits are locked by setting the NVPB Lock bit to `0'. Once programmed to `0', the NVPB Lock bit can only be reset to `1' by taking the device through a power-up or hardware reset. 28 208031-05 Numonyx(R) AxcellTM M29EW 6 Command Interface Command Interface All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. 6.1 Standard commands See either Table 9, or Table 10, depending on the configuration that is being used, for a summary of the standard commands. 6.1.1 Read/Reset command The device enters read mode of main array memory after a reset or power-up sequence. The Read/Reset command returns the memory to Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to Read mode. If the Read/Reset command is issued during the time-out of a Block erase operation, the memory will take up to 10 s to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. 6.1.2 Auto Select command The Auto Select command puts the device in Auto Select mode, once in Auto Select mode, the system can read the manufacturer code, the device code, the protection status of each block (Block Protection status) and the Extended Memory Block protection indicator. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued Bus Read operations to specific addresses output the manufacturer code, the device code, the Extended Memory Block protection indicator and a block protection status (see Table 9 and Table 10 in conjunction with Table 5, Table 6, Table 7, and Table 8). The memory remains in Auto Select mode until a Read/Reset or CFI Query command is issued. 208031-05 29 Numonyx(R) AxcellTM M29EW Command Interface 6.1.3 Read CFI Query command The memory contains an information area, named CFI data structure, which contains a description of various electrical and timing parameters, density information and functions supported by the memory. See Appendix B, Table 36, Table 37, Table 38, Table 39 and Table 40 for details on the information contained in the Common Flash Interface (CFI) memory area. The Read CFI Query command is used to put the memory in Read CFI Query mode. Once in Read CFI Query mode, Bus Read operations to the memory will output data from the Common Flash Interface (CFI) memory area. One Bus Write cycle is required to issue the Read CFI Query command. This command is valid only when the device is in the Read Array or Auto Select mode. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/Reset command is required to put the device in Read Array mode from Auto Select mode. 6.1.4 Chip Erase command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase command and start the Program/Erase controller. If some block are protected, then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical Chip Erase times are given in Table 28. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data inputs/outputs. See Section 7.2: Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to `1'. All previous data is lost. The Chip Erase operation is aborted by performing a reset or powering down the device. In this case, data integrity cannot be ensured, and it is recommended to erase again the entire chip. 6.1.5 Block Erase command The Block Erase command can be used to erase a list of one or more blocks. It sets all of the bits in the unprotected selected blocks to `1'. All previous data in the selected blocks is lost. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. After the command sequence is written, a Block Erase time-out occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Once the Program/Erase controller has started, it is not possible to select 30 208031-05 Numonyx(R) AxcellTM M29EW Command Interface any more blocks. Each additional block must therefore be selected within the time-out period of the last block. The time-out timer restarts when an additional block is selected. After the sixth Bus Write operation, a Bus Read operation outputs the Status Register. See Figure 24: Write Enable Controlled Program waveforms (8-bit mode) and Figure 25: Write Enable Controlled Program waveforms (16-bit mode) for details on how to identify if the Program/Erase controller has started the Block Erase operation. After the Block Erase operation has completed, the memory returns to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory ignores all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the timeout period. Typical Block Erase time and Block Erase time-out are given in Table 28. The Block Erase operation is aborted by performing a reset or powering down the device. In this case, data integrity cannot be ensured, and it is recommended to erase again the blocks aborted. 6.1.6 Blank Check command The Blank Check operation determines whether a specified block is blank (i.e. completely erased). Without Blank Check, Block Erase would be the only other way to ensure a block is completely erased. Blank Check can be used to determine whether or not a prior erase operation was successful; this includes erase operations that may have been interrupted by power-loss. The Blank Check operation checks for cells that are programmed as well as cells that are over-erased. If any cells are programmed or over-erased, Blank Check will return a failure status, indicating that the block is not blank. If a Blank Check operation returns a passing status, the block is guaranteed blank (all 1's) and ready to program. The erase algorithm will do Blank Check for the target block firstly. If it's blank (all 1's) then the actual erase operation will be skipped. Otherwise, the actual erase operation will continue. This could benefit the overall cycle performance when erase happens on a blank block. Blank check can occur in only one block at a time, and no operations other than Status Register Reads are allowed during Blank Check (e.g. reading array data, program, erase etc). Blank Check is not supported during any suspended operations. The status register can be examined for Blank Check progress and errors by reading any address within the device. After the Blank Check operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations to the memory continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. 208031-05 31 Numonyx(R) AxcellTM M29EW Command Interface 6.1.7 Erase Suspend command The Erase Suspend command can be used to temporarily suspend a Block Erase operation. One Bus Write operation is required to issue the command together with the block address. After the command sequence is written, a minimum Block Erase time-out occurs (see Table 28). During the time-out period, additional block addresses and block erase commands can be written. The Program/Erase controller suspends the erase operation within the Erase Suspend Latency time of the Erase Suspend command being issued. However, when the Erase Suspend command is written during the Block Erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Once the Program/Erase controller has stopped, the memory operates in Read mode and the Erase is suspended. During Erase Suspend it is possible to read and execute Program or Write to Buffer Program operations in blocks that are not suspended; both read and program operations behave as normal on these blocks. Reading from blocks that are suspended will output the Status Register. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. In this case the Status Register is not read and no error condition is given. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. During Erase Suspend a Bus Read operation to the Extended Memory Block will output the Extended Memory Block data. Once in the Extended Memory Block mode, the Exit Extended Memory Block command must be issued before the erase operation can be resumed. The Erase Suspend command is ignored if written during Chip Erase operations. Refer to Table 28: Programming and Erase Performance for the values of Block Erase timeout and Block Erase Suspend latency time. If the Erase Suspend operation is aborted by performing a reset or powering down the device, data integrity cannot be ensured, and it is recommended to erase again the blocks suspended. 6.1.8 Erase Resume command The Erase Resume command is used to restart the Program/Erase controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. 32 208031-05 Numonyx(R) AxcellTM M29EW 6.1.9 Command Interface Program Suspend command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the program operation within the Program Suspend latency time (see Table 28: Programming and Erase Performance) and updates the Status Register bits. After the program operation has been suspended, the system can read array data from any address. However, data read from program-suspended addresses is not valid. The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Extended Memory Block area (one-time program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the Program Suspend mode. The system can read as many Auto Select codes as required. When the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information. If the Program Suspend operation is aborted by performing a reset or powering down the device, data integrity cannot be ensured, and it is recommended to program again the words or bytes aborted. 6.1.10 Program Resume command After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to Figure 24: Write Enable Controlled Program waveforms (8-bit mode) and Figure 25: Write Enable Controlled Program waveforms (16-bit mode) for details. The system must issue a Program Resume command, to exit the Program Suspend mode and to continue the programming operation. Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming. 6.1.11 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.9: Program Suspend command and Section 6.1.10: Program Resume command). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. After programming has started, Bus Read operations output the Status Register content. See Figure 24: Write Enable Controlled Program waveforms (8-bit mode) and Figure 25: 208031-05 33 Numonyx(R) AxcellTM M29EW Command Interface Write Enable Controlled Program waveforms (16-bit mode) for more details. Typical program times are given in Table 28: Programming and Erase Performance. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations to the memory continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase commands must be used to set all the bits in a block or in the whole memory from `0' to `1'. The Program operation is aborted by performing a reset or powering-down the device. In this case data integrity cannot be ensured, and it is recommended to reprogram the word or byte aborted. 34 208031-05 Numonyx(R) AxcellTM M29EW Table 9. Command Interface Standard commands, 8-bit mode Command Length Bus operations(1) 1st Add 2nd 3rd Data Add Data Add 4th 5th 6th Data Add Data Add Data Add Data 1 X F0 - - - - - - - - - - 3 AAA AA 555 55 X F0 - - - - - - 3 AAA AA 555 55 AAA 90 (2)(3) (2)(3) - - - - Program(4) 4 AAA AA 555 55 AAA A0 PA PD - - - - Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BAd 30 Erase/Program Suspend 1 X B0 - - - - - - - - - - Erase/Program Resume 1 X 30 - - - - - - - - - - Read CFI Query 1 AA 98 - - - - - - - - - - Blank Check setup 6 AAA AA 555 55 BAd EB BAd 76 BAd 00 BAd 00 Blank Check confirm and read 2 BAd 29 BAd (2) - - - - - - - - Read/Reset Manufacturer code Device code Auto Select Extended Memory Block protection indicator Block protection status 1. X = Don't care, PA = Program Address, PD = Program Data, BAd = Any address in the Block. All values in the table are in hexadecimal. 2. These cells represent Read cycles. The other cells are Write cycles. 3. The Auto Select addresses and data are given in Table 5: Read electronic signature - auto select mode - programmer method (8-bit mode), and Table 7: Block protection - auto select mode - programmer method (8-bit mode), except for A9 that is `Don't care'. 4. In Unlock Bypass, the first two unlock cycles are no more needed (see Table 11: Fast Program commands, 8-bit mode and Table 12: Fast Program commands, 16-bit mode). 208031-05 35 Numonyx(R) AxcellTM M29EW Command Interface Table 10. Standard commands, 16-bit mode Command Length Bus operations(1) 1st Add 2nd 3rd Data Add Data Add 4th 5th 6th Data Add Data Add Data Add Data 1 X F0 - - - - - - - - - - 3 555 AA 2AA 55 X F0 - - - - - - 3 555 AA 2AA 55 555 90 (2)(3) (2)(3) - - - - Program(4) 4 555 AA 2AA 55 555 A0 PA PD - - - - Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BAd 30 Erase/Program Suspend 1 X B0 - - - - - - - - - - Erase/Program Resume 1 X 30 - - - - - - - - - - Read CFI Query 1 55 98 - - - - - - - - - - Blank Check setup 6 555 AA 2AA 55 BAd EB BAd 76 BAd 00 BAd 00 Blank Check confirm and read 2 BAd 29 BAd (2) - - - - - - - - Read/Reset Manufacturer code Device code Extended Memory Auto Block protection Select indicator Block protection status 1. X = Don't care, PA = Program Address, PD = Program Data, BAd = any address in the Block. All values in the table are in hexadecimal. 2. These cells represent Read cycles. The other cells are Write cycles. 3. The Auto Select addresses and data are given in Table 6: Read electronic signature - auto select mode - programmer method (16-bit mode), and Table 8: Block protection - auto select mode - programmer method (16-bit mode), except for A9 that is `Don't care'. 4. In Unlock Bypass, the first two unlock cycles are no more needed (see Table 11 and Table 12 Fast Program commands, 8bit and 16-bit mode). 36 208031-05 Numonyx(R) AxcellTM M29EW 6.2 Command Interface Fast Program commands The M29EW offers a set of Fast Program commands to improve the programming throughput: - Double Byte/Word Program (for 32-Mbit and 64-Mbit devices) - Quadruple Byte/Word Program (for 32-Mbit and 64-Mbit devices) - Octuple Byte Program (for 32-Mbit and 64-Mbit devices) - Write to Buffer Program - Enhanced Buffer Program (x16 128-Mbit device only) - Unlock Bypass The Table 11: Fast Program commands, 8-bit mode on page 46 and the Table 12: Fast Program commands, 16-bit mode on page 47 show a summary of the Fast Program commands. When VPPH is applied to the VPP/WP# pin during Write to Buffer Program and Enhanced Buffer Program, it will accelerate the programming speed. (see Figure 31: Accelerated program timing waveforms) When VPPH is applied to the VPP/WP# pin in read mode, the memory automatically enters Unlock Bypass mode (see Section 6.2.9: Unlock Bypass command). Note: For double byte/word program, quadruple byte/word program and octuple byte program, only VPPL could be applied to the VPP/WP# pin. After programming has started, Bus Read operations in the memory output the Status Register content. Write to Buffer Program command can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.9: Program Suspend command and Section 6.1.10: Program Resume command). After the fast program operation has completed, the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase commands must be used to set all the bits in a block or in the whole memory from `0' to `1'. Typical program times are given in Table 28: Programming and Erase Performance. 6.2.1 Double Byte/Word Program command The Double Byte/Word Program command for 32-Mbit and 64-Mbit devices is used to write a page of two adjacent bytes/words in parallel. The two bytes/words must differ only for the address A-1 or A0, respectively. Three bus write cycles are necessary to issue the Double Byte/Word Program command: 1. The first bus cycle sets up the Double Byte/Word Program command. 2. The second bus cycle latches the Address and the Data of the first byte/word to be programmed. 3. The third bus cycle latches the Address and the Data of the second byte/word to be programmed and starts the Program/Erase Controller. See Table 11: Fast Program commands, 8-bit mode and Table 12: Fast Program commands, 16-bit mode for command details. 208031-05 37 Numonyx(R) AxcellTM M29EW Command Interface 6.2.2 Quadruple Byte/Word Program command The Quadruple Byte/Word Program command for 32-Mbit and 64-Mbit devices is used to write a page of four adjacent bytes/words in parallel. The four bytes/words must differ for addresses A0, DQ15/A-1 in x8 mode or addresses A1, A0 in x16 mode. Five bus write cycles are necessary to issue the Quadruple Byte/Word Program command: 1. The first bus cycle sets up the Quadruple Byte/Word Program command. 2. The second bus cycle latches the Address and the Data of the first byte/word to be programmed. 3. The third bus cycle latches the Address and the Data of the second byte/word to be programmed. 4. The fourth bus cycle latches the Address and the Data of the third byte/word to be programmed. 5. The fifth bus cycle latches the Address and the Data of the fourth byte/word to be programmed and starts the Program/Erase Controller. See Table 11: Fast Program commands, 8-bit mode and Table 12: Fast Program commands, 16-bit mode for command details. 6.2.3 Octuple Byte Program command The Octuple Byte Program command for 32-Mbit and 64-Mbit devices is used to write a page of eight adjacent bytes in parallel. The eight bytes must differ for addresses A1, A0, DQ15/A-1 in x8 mode only. Nine bus write cycles are necessary to issue the Octuple Byte Program command: 1. The first bus cycle sets up the Octuple Byte Program command. 2. The second bus cycle latches the Address and the Data of the first byte to be programmed. 3. The third bus cycle latches the Address and the Data of the second byte to be programmed. 4. The fourth bus cycle latches the Address and the Data of the third byte to be programmed. 5. The fifth bus cycle latches the Address and the Data of the fourth byte to be programmed. 6. The sixth bus cycle latches the Address and the Data of the fifth byte to be programmed. 7. The seventh bus cycle latches the Address and the Data of the sixth byte/word to be programmed. 8. The eighth bus cycle latches the Address and the Data of the seventh byte/word to be programmed. 9. The ninth bus cycle latches the Address and the Data of the eighth byte/word to be programmed and starts the Program/Erase Controller. See Table 11: Fast Program commands, 8-bit mode and Table 12: Fast Program commands, 16-bit mode for command details. 38 208031-05 Numonyx(R) AxcellTM M29EW 6.2.4 Command Interface Write to Buffer Program command The Write to Buffer Program command makes use of the device's 256-word program buffer to speed up programming. A maximum of 256 words can be loaded into the program buffer in word mode. In byte mode, the maximum buffer size is 256-byte (128-word) due to the limitation of 8 pins. The Write to Buffer Program command dramatically reduces system programming time compared to the standard non-buffered Program command. Note: The maximum number of bytes in write buffer in CFI region (refer to offset 2Ah, Table 39: Device geometry definition on page 93) is set to 08h (256 bytes) for backward compatible reasons. No software change is required on the existing applications in both x8 and x16 mode. However, the system performance can be optimized by implement the maximum 256word buffer size, contact your sales representatives for questions. When issuing a Write to Buffer Program command, the VPP/WP# pin can be either held High, VIH, or raised to VPPH (programming acceleration). See Table 28 for details on typical Write to Buffer Program times in both cases. Five successive steps are required to issue the Write to Buffer Program command: 1. The Write to Buffer Program command starts with two unlock cycles. 2. The third bus write cycle sets up the Write to Buffer Program command. The set-up code can be addressed to any location within the targeted block. 3. The fourth bus write cycle sets up the number of words/bytes to be programmed. Value N is written to the same block address, where N+1 is the number of words/bytes to be programmed. N+1 must not exceed the size of the program buffer, otherwise the operation will abort. In x8 mode, the maximum N should be no more than 256. 4. The fifth cycle loads the first address and data to be programmed. 5. Use N bus write cycles to load the address and data for each word/byte into the program buffer. Addresses must lie within the range from the start address+1 to the start address + N-1. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 256-word boundary (A[7:0] = 000h). All the addresses used in the Write to Buffer Program operation must lie within the 256-word boundary. Any crossing boundary buffer program will result in a program abort. See Figure 10 for details of the available program buffer size. To program the content of the program buffer, this command must be followed by a Write to Buffer Program Confirm command. If an address is written several times during a Write to Buffer Program operation, the address/data counter will be decremented at each data load operation and the data will be programmed to the last word loaded into the buffer. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will abort the Write to Buffer Program. The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a Write to Buffer Program operation. It is possible to detect Program operation fails when changing programmed data from `0' to `1', that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. See Figure 11: Write to Buffer Program fletcher and pseudo code, for a suggested flow chart on using the Write to Buffer Program command. 208031-05 39 Numonyx(R) AxcellTM M29EW Command Interface 6.2.5 Enhanced Buffer Program The Enhanced Buffer Program command, available only on x16 mode 128-Mbit device, makes use of the device's 256-word write buffer to speed up programming. 256 words can be loaded into the write buffer. Each write buffer has the same A22-A8 addresses. The Enhanced Buffer Program command dramatically reduces system programming time. When issuing a Enhanced Buffer Program command, the VPP/WP# pin can be either held High, VIH, or raised to VPPH (programming acceleration). The Enhanced Buffer Program has the same programming speed as a 256-word write to buffer program speed. See Table 28 for details. Three successive steps are required to issue the Enhanced Buffer Program command: - The Enhanced Buffered Program command starts with two unlock cycles. - The third bus write cycle sets up the Enhanced Buffered Program command. The setup code can be addressed to any location within the targeted block. - The fourth bus write cycle loads the first address and data to be programmed. There a total of 256 address and data loading cycles. To program the content of the write buffer, the Enhanced Buffer Program command must be followed by an Enhanced Buffer Program Confirm command. The command ends with an internal Enhanced Buffer Program confirm cycle. Note that address/data cycles must be loaded in an increasing address order (A[7:0] from 00h to FFh) and completely (all 256 words). Invalid address combinations or failing to follow the correct sequence of bus write cycles will result in Enhanced Buffer Program abort. The status register bits DQ1, DQ5, DQ6, and DQ7 can be used to monitor the device status during an Enhanced Buffer Program operation. An external supply (12 V) can be used to improve programming efficiency. It is possible to detect program operation fails when changing programmed data from "0" to "1". Note: 40 Enhanced Buffered Program commands are available for x 16 mode only. 208031-05 Numonyx(R) AxcellTM M29EW Command Interface Figure 10. Boundary condition of program buffer size 0000h 256 Words 256 Words program buffer is allowed 0100h 256 Words 256 Words program buffer is allowed Any buffer program attempt is not allowed 255 Words or less program buffer is allowed 0200h 208031-05 41 Numonyx(R) AxcellTM M29EW Command Interface Figure 11. Write to Buffer Program fletcher and pseudo code Start Write to Buffer command, block address (1) Write n , block address First three cycles of the Write to Buffer and Program command Write Buffer Data, start address X=n YES X=0 NO YES Abort Write to Buffer Write to a different block address NO Write Next Data,(3) Program Address Pair Write to Buffer and (2) Program Aborted X = X-1 Write to Buffer Program Confirm, block address Read Status Register (DQ1, DQ5, DQ7) at last loaded address YES DQ7 = Data NO NO DQ1 = 1 NO DQ5 = 1 YES YES Check Status Register (DQ5, DQ7) at last loaded address DQ7 = Data YES (4) NO (5) FAIL OR ABORT END AI08968b 1. n+1 is the number of addresses to be programmed. 2. A Write to Buffer Program Abort and Reset must be issued to return the device in Read mode. 3. When the block address is specified, any address in the selected block address space is acceptable. However when 42 208031-05 Numonyx(R) AxcellTM M29EW Command Interface loading program buffer address with data, all addresses must fall within the selected program buffer page. 4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously. 5. If this flow chart location is reached because DQ5='1', then the Write to Buffer Program command failed. If this flow chart location is reached because DQ1='1', then the Write to Buffer Program command aborted. In both cases, the appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a Write to Buffer Program Abort and Reset command if the operation aborted. 6. See Table 9 and Table 10, for details on Write to Buffer Program command sequence. 6.2.6 Buffered Program Abort and Reset command A Buffered Program Abort and Reset command must be issued to abort the Buffer Program operation and reset the device in Read mode. The buffer programming sequence can be aborted in the following ways: - Load a value that is greater than the page buffer size during the number of locations to program step in the Write to Buffer Program command. - Write to an address in a block different than the one specified during the writebuffer-load command. - Write an address/data pair to a different write-buffer-page than the one selected by the starting address during the program buffer data loading stage of the operation. - Write data other than the Confirm command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DQ7 (for the last address location loaded), DQ6 = toggle, and DQ5 = 0 (all of which are Status Register bits). A Buffered Program Abort and Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Buffered Program Abort and Reset command sequence is required when using Buffer Programming features in Unlock Bypass mode. 208031-05 43 Numonyx(R) AxcellTM M29EW Command Interface 6.2.7 Write to Buffer Program Confirm command The Write to Buffer Program Confirm command is used to confirm a Write to Buffer Program command and to program the N+1 words/bytes loaded in the program buffer by this command. 6.2.8 Enhanced Buffer Program Confirm command The Enhanced Buffer Program Confirm command is used to confirm an Enhanced Buffer Program command and to program the 256 words loaded in the buffer. 6.2.9 Unlock Bypass command The Unlock Bypass command is used to place the device in Unlock Bypass mode. When the device enters the Unlock Bypass mode, the two initial unlock cycles required in the standard program command sequence are no more needed, and only two write cycles are required to program data, instead of the normal four cycles (see Note 4 below Table 9 and Table 10). This results in a faster total programming time. Unlock Bypass command is consequently used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. When in Unlock Bypass mode, only the Unlock Bypass Program, Unlock Bypass Block Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are valid: - The Unlock Bypass Program command can be issued to program addresses within the memory. - The Unlock Bypass Block Erase command can then be issued to erase one or more memory blocks. - The Unlock Bypass Chip Erase command can be issued to erase the whole memory array. - The Unlock Bypass Write to Buffer Program command can be issued to speed up programming operation. - The Unlock Bypass Reset command can be issued to return the memory to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode. 6.2.10 Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data and starts the Program/Erase controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted, a Bus Read operation to the memory outputs the Status Register. See the program command in Table 11.: Fast Program commands, 8-bit mode and Table 12.: Fast Program commands, 16-bit mode for more details. 44 208031-05 Numonyx(R) AxcellTM M29EW 6.2.11 Command Interface Unlock Bypass Block Erase command The Unlock Bypass Block Erase command can be used to Erase one or more memory blocks at a time. The command requires two Bus Write operations instead of six using the standard Block Erase command. The final Bus Write operation latches the address of the block and starts the Program/Erase controller. To erase multiple block (after the first two Bus Write operations have selected the first block in the list), each additional block in the list can be selected by repeating the second Bus Write operation using the address of the additional block. The Unlock Bypass Block Erase command behaves in the same way as the Block Erase command: the operation cannot be aborted, and a Bus Read operation to the memory outputs the Status Register (see Section 6.1.5: Block Erase command for details). 6.2.12 Unlock Bypass Chip Erase command The Unlock Bypass Chip Erase command can be used to erase all memory blocks at a time. The command requires two Bus Write operations only instead of six using the standard Chip Erase command. The final Bus Write operation starts the Program/Erase controller. The Unlock Bypass Chip Erase command behaves in the same way as the Chip Erase command: the operation cannot be aborted, and a Bus Read operation to the memory outputs the Status Register (see Section 6.1.4: Chip Erase command for details). 6.2.13 Unlock Bypass Write to Buffer Program command The Unlock Bypass Write to Buffer command can be used to program the memory in Fast Program mode. The command requires two Bus Write operations less than the standard Write to Buffer Program command. The Unlock Bypass Write to Buffer Program command behaves in the same way as the Write to Buffer Program command: the operation cannot be aborted and a Bus Read operation to the memory outputs the Status Register (see Section 6.2.4: Write to Buffer Program command for details). The Write to Buffer Program Confirm command is used to confirm an Unlock Bypass Write to Buffer Program command and to program the N+1 words/bytes loaded in the program buffer by this command. 6.2.14 Unlock Bypass Enhanced Buffer Program command The Unlock Bypass Enhanced Buffer Program command can be used to program the memory in fast program mode. The command requires two address/data loading cycles less than the regular Enhanced Buffer Program command (see Table 12: Fast Program commands, 16-bit mode for the details). The Unlock Bypass Enhanced Buffer Program command behaves identically to the Enhanced Buffer Program operation using the Enhanced Buffer Program command. The operation cannot be aborted and a bus read operation to the memory outputs the status register (see Chapter 6.2.8: Enhanced Buffer Program Confirm command for the behavior details). The Enhanced Buffer Program Confirm command is used to confirm an Unlock Bypass Enhanced Buffer Program command and to program the 256 words loaded in the buffer. 208031-05 45 Numonyx(R) AxcellTM M29EW Command Interface 6.2.15 Unlock Bypass Reset command Table 11. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass mode. Fast Program commands, 8-bit mode Command Length Bus Write operations(1) 1st 2nd 3rd 4th 5th Add Data Add Data Add Data Add Data Add Data Double Byte Program 3 AAA 50 PA2(2) PD - - - - - - Quadruple Byte Program 5 AAA 56 PA4(3) PD - - - - - - Octuple byte Program 9 AAA 8B PA8(4) PD - - - - - - N+5 AAA AA 555 55 BAd 25 BAd N(5) PA(6) PD Write to Buffer Program Confirm 1 BAd(7) 29 - - - - - - - - Buffered Program Abort and Reset 3 AAA AA 555 55 AAA F0 - - - - Unlock Bypass mode entry 3 AAA AA 555 55 AAA 20 - - - - Unlock Bypass Program 2 X A0 PA PD - - - - - - Unlock Bypass Block Erase 2+ X 80 BAd 30 - - - - - - Unlock Bypass Chip Erase 2 X 80 X 10 - - - - - - Unlock Bypass Write to Buffer Program N+3 BAd 25 BAd N(5) PA(6) PD - - - - Unlock Bypass Reset 2 X 90 X 00 - - - - - - Write to Buffer Program 1. X = Don't care, PA = Program Address, PD = Program Data, BAd = Any address in the Block. All values in the table are in hexadecimal. 2. Amax-A0 address pins should remian unchanged. Address A-1 selects between adjacent bytes. 3. Amax-A1 address pin should remain unchanged. A0 and A-1 pins are used to select four adjacent bytes. This address should be used four times. 4. Amax-A2 address pin should remain unchanged. A1, A0 and A-1 pins are used to select eight adjacent bytes. This address should be used eight times. 5. The maximum number of cycles in the buffer program command sequence is 261. The maximum number of cycles in the unlock bypass buffer program command sequence is 259. N+1 is the number of bytes to be programmed during the Write to Buffer Program operation. 6. Amax-A7 address pins should be consistently unchanged. Addresses A[6:-1] select a byte within the N+1 byte page. 7. BAd must be identical to the address loaded during the Write to Buffer Program 3rd and 4th cycles. 46 208031-05 Numonyx(R) AxcellTM M29EW Table 12. Command Interface Fast Program commands, 16-bit mode Command Length Bus Write operations(1) 1st 2nd 3rd 4th 5th Add Data Add Data Add Data Add Data Add Data Double Word Program 3 555 50 PA2(2) PD - - - - - - Quadruple Word Program 5 555 56 PA4(3) PD - - - - - - N+5 555 AA 2AA 55 BAd 25 BAd N(4) PA(5) PD Write to Buffer Program Confirm 1 BAd(6) 29 - - - - - - - - Enhanced Buffer Program N+5 555 AA 2AA 55 BAd 33 BAd N(4) PA(5) PD Enhanced Buffer Program Confirm 1 BAd(6) 29 - - - - - - - - Buffered Program Abort and Reset 3 555 AA 2AA 55 555 F0 - - - - Unlock Bypass mode entry 3 555 AA 2AA 55 555 20 - - - - Unlock Bypass Program 2 X A0 PA PD - - - - - - Unlock Bypass Block Erase 2+ X 80 BAd 30 - - - - - - Unlock Bypass Chip Erase 2 X 80 X 10 - - - - - - Unlock Bypass Write to Buffer Program N+3 BAd 25 BAd N(4) PA(5) PD - - - - Unlock Bypass Enhanced Buffer Program N+3 BAd 33 BAd N(4) PA(5) PD - - - - 2 X 90 X 00 - - - - - - Write to Buffer Program Unlock Bypass Reset 1. X = Don't care, PA = Program Address, PD = Program Data, BAd = Any address in the Block. All values in the table are in hexadecimal. 2. Amax-A1 address pin should remain unchanged. A0 pin is used to select two adjacent words. 3. Amax-A2 address pin should remian unchanged. A1 and A0 pins are used to select four adjacent words. This address should be used four times. 4. The maximum number of cycles in the buffer program command sequence is 261. The maximum number of cycles in the unlock bypass buffer program command sequence is 259. N+1 is the number of bytes to be programmed during the Write to Buffer Program operation. 5. Amax-A9 address pins should be consistently unchanged. A0-A8 pins are used to select a word within the N+1 word page. 6. BAd must be identical to the address loaded during the Write to Buffer Program 3rd and 4th cycles. 208031-05 47 Numonyx(R) AxcellTM M29EW Command Interface 6.3 Protection commands Blocks can be protected individually against accidental program, erase or read operations. The device block protection scheme is shown in Figure 9: Software protection scheme. See either Table 13, or Table 14, depending on the configuration that is being used, for a summary of the Block Protection commands. Block protection commands are available both in 8-bit and 16-bit configuration. The protections of both memory blocks and Extended Memory Block protection are configured through the Lock register (see Section 7.1: Lock Register). 6.3.1 Enter Extended Memory Block command The M29EW has one extra 128-word Extended Memory Block that can only be accessed using the Enter Extended Memory Block command. Three Bus Write cycles are required to issue the Enter Extended Memory Block command. Once the command has been issued the device enters the Extended Memory Block mode where all Bus Read or Program operations are conducted on the Extended Memory Block. Once the device is in the Extended Memory Block mode, the Extended Memory Block is addressed by using the addresses occupied by block 0 in the other operating modes (see Figure 8: 64-Mbit and 32-Mbit Boot Block addresses on page 14). The device remains in Extended Memory Block mode until the Exit Extended Memory Block command is issued or power is removed from the device. After a power-up sequence or hardware reset, the device will revert to reading from memory blocks in the main array. The Extended Memory Block cannot be erased, and each bit of the Extended Memory Block can only be programmed once. In Extended Memory Block mode, Erase, Chip Erase, Erase Suspend and Erase Resume commands are not allowed. To exit from the Extended Memory Block mode the Exit Extended Memory Block command must be issued. The Extended Memory Block is protected from further modification by programming Lock Register bit 0 (see Section 7.1: Lock Register). Once invoked, this protection cannot be undone. 6.3.2 Exit Extended Memory Block command The Exit Extended Memory Block command is used to exit from the Extended Memory Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. 48 208031-05 Numonyx(R) AxcellTM M29EW 6.3.3 Command Interface Lock Register command set The M29EW offers a set of commands to access the Lock Register and to configure and verify its content. See the following sections in conjunction with Section 7.1: Lock Register, Table 13 and Table 14. Enter Lock Register Command Set command Three Bus Write cycles are required to issue the Enter Lock Register Command Set command. Once the command has been issued, all Bus Read or Program operations are issued to the Lock Register. Lock Register Program and Lock Register Read command The Lock Register Program command allows to configure the Lock Register. The programmed data can then be checked by issuing a Lock Register Read command. An Exit Protection Command Set command must then be issued to return the device to Read mode (see Section 6.3.8: Exit Protection command set). 6.3.4 Password Protection mode command set Enter Password Protection Command Set command Three Bus Write cycles are required to issue the Enter Password Protection Command Set command. Once the command has been issued, the commands related to the Password Protection mode can be issued to the device. Password Program command The Password Program command is used to program the 64-bit password used in the Password Protection mode. To program the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by A1-A0 plus DQ15/A-1 in 8-bit mode, or four times at four consecutive addresses selected by A1-A0 in 16-bit mode. The password can be checked by issuing a Password Read command. Once Password Program operation has completed, an Exit Protection Command Set command must be issued to return the device to Read mode. The Password Protection mode can then be selected. By default, all Password bits are set to `1'. Password Read command The Password Read command is used to verify the Password used in Password Protection mode. To verify the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by A1-A0 plus DQ15/A-1 in 8-bit mode, or four times at four consecutive addresses selected by A1-A0 in 16-bit mode. If the Password Mode Lock bit is programmed and the user attempts to read the password, the device will output FFh onto the I/O data bus. An Exit Protection Command Set command must be issued to return the device to Read mode. 208031-05 49 Numonyx(R) AxcellTM M29EW Command Interface Password Unlock command The Password Unlock command is used to clear the NVPB Lock bit allowing to modify the NVPBs. The Password Unlock command must be issued along with the correct password. There must be a 1 s delay between successive Password Unlock commands in order to prevent hackers from cracking the password by trying all possible 64-bit combinations. If this delay is not respected, the latest command will be ignored. Approximately 1 s is required for unlocking the device after the valid 64-bit password has been provided. 6.3.5 Non-Volatile Protection mode command set Enter Non-Volatile Protection Command Set command Three Bus Write cycles are required to issue the Enter Non-Volatile Protection Command Set command. Once the command has been issued, the commands related to the NonVolatile Protection mode can be issued to the device. Non-Volatile Protection Bit Program command (NVPB Program) A block can be protected from program or erase by issuing a Non-Volatile Protection Bit command along with the block address. This command sets the NVPB to `1' for a given block. Read Non-Volatile Protection Bit Status command (Read NVPB Status) The status of a NVPB for a given block or group of blocks can be read by issuing a Read Non-Volatile Modify Protection Bit command along with the block address. Clear all Non-Volatile Protection Bits command (Clear all NVPBs) The NVPBs are erased simultaneously by issuing a Clear all Non-Volatile Protection Bits command. No specific block address is required. If the NVPB Lock bit is set to `0', the command fails. 50 208031-05 Numonyx(R) AxcellTM M29EW Command Interface Figure 12. NVPB Program/Erase algorithm Enter NVPB command set. Program NVPB Addr = BAd Read Byte twice Addr = BAd DQ6= Toggle NO YES NO DQ5=1 Wait 500 s YES Read Byte twice Addr = BAd DQ6= Toggle NO Read Byte twice Addr = BAd YES NO DQ0= '1'(Erase) '0'(Program) YES Fail Reset Pass Exit NVPB command set AI14242 208031-05 51 Numonyx(R) AxcellTM M29EW Command Interface 6.3.6 NVPB Lock Bit command set Enter NVPB Lock Bit Command Set command Three bus Write cycles are required to issue the Enter NVPB Lock Bit Command Set command. Once the command has been issued, the commands allowing to set the NVPB Lock bit can be issued to the device. NVPB Lock Bit Program command This command is used to set the NVPB Lock bit to `0' thus locking the NVPBs, and preventing them from being modified. Read NVPB Lock Bit Status command This command is used to read the status of the NVPB Lock bit. 6.3.7 Volatile Protection mode command set Enter Volatile Protection Command Set command Three bus Write cycles are required to issue the Enter Volatile Protection Command Set command. Once the command has been issued, the commands related to the Volatile Protection mode can be issued to the device. Volatile Protection Bit Program command (VPB Program) The VPB Program command individually sets a VPB to `0' for a given block. If the NVPB for the same block is set, the block is locked regardless of the value of the VPB bit. (see Table 16: Block Protection Status). Read VPB Status command The status of a VPB for a given block can be read by issuing a Read VPB Status command along with the block address. VPB Clear command The VPB Clear command individually clears (sets to `1') the VPB for a given block. If the NVPB for the same block is set, the block is locked regardless of the value of the VPB bit. (see Table 16: Block Protection Status). 6.3.8 Exit Protection command set The Exit Protection Command Set command is used to exit from the Lock Register, Password Protection, Non-Volatile Protection, Volatile Protection, and NVPB Lock Bit Command Set mode. It return the device to Read mode. 52 208031-05 Numonyx(R) AxcellTM M29EW Table 13. Command Interface Block Protection commands, 8-bit mode(1)(2)(3) NVPB Lock bit Non-Volatile Protection Password Protection Lock Register Command Length Bus operations 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data 55 AAA 40 - - - - - - - - - - - - - - - - (5) - - - - - - - - - - - - - - - - - - Enter Lock Register Command Set(4) 3 AAA AA 555 Lock Register Program 2 X A0 X Lock Register Read 1 X Enter Password Protection Command Set(4) 3 DATA DATA (5) - - - - - - - - - - - - - - - - - - - - AAA AA 555 55 AAA 60 - - - - - - - - - - - - - - - - 2 X A0 PWA n PWD n - - - - - - - - - - - - - - - - - - Password Read 8 00 PWD 0 01 PWD 1 02 PW D2 03 PW D3 04 PW D4 05 PW D5 06 PW D6 07 PW D7 - - - - - - Password Unlock(7) 11 00 25 00 03 00 PW D0 01 PW D1 02 PW D2 03 PW D3 04 PW D4 05 PW D5 06 PW D6 07 PW D7 00 29 Enter NonVolatile Protection Command Set(4) 3 AAA AA 555 55 AAA C0 - - - - - - - - - - - - - - - - NVPB Program(8) 2 X A0 BAd 00 - - - - - - - - - - - - - - - - - - Clear all NVPBs(9) 2 X 80 00 30 - - - - - - - - - - - - - - - - - - Read NVPB Status (8) 1 BAd RD(0) - - - - - - - - - - - - - - - - - - - - Enter NVPB Lock Bit Command Set 3 AAA AA 555 55 AAA 50 - - - - - - - - - - - - - - - - NVPB Lock Bit Program(8) 2 X A0 X 00 - - - - - - - - - - - - - - - - - - 1 X RD(0) - - - - - - - - - - - - - - - - - - - - Enter Volatile Protection Command Set 3 AAA AA 555 55 AAA E0 - - - - - - - - - - - - - - - - VPB Program(8) 2 X A0 BAd 00 - - - - - - - - - - - - - - - - - - Read VPB Status 1 BAd RD(0) - - - - - - - - - - - - - - - - - - - - VPB Clear(8) 2 X A0 BAd 01 - - - - - - - - - - - - - - - - - - 2 X 90 X 00 - - - - - - - - - - - - - - - - - - 3 AAA AA 555 55 AAA 88 - - - - - - - - - - - - - - - - Password Program (6)(7) Read NVPB Lock Bit Status Volatile Protection (8) Exit Protection Command Set (10) Enter Extended Memory Block(4) 208031-05 53 Numonyx(R) AxcellTM M29EW Command Interface 1. Ad = address; Dat = data; BAd = Any address in the Block; RD = Read data; PWDn = Password byte 0 to 7; PWAn = Password Address (n = 0 to 7); X = Don't care. All values in the table are in hexadecimal. 2. Grey cells represent Read cycles. The other cells are Write cycles. 3. DQ15 to DQ8 are `Don't care' during unlock and command cycles. Amax to A16 are `Don't care' during unlock and command cycles unless an address is required. 4. An Enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any other block are allowed. 5. DATA = Lock Register content. 6. Only one portion of password can be programmed or read by each Password Program command. 7. The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 8. Protected and unprotected states correspond to 00 and 01, respectively. 9. The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared Non Volatile Modify Protection bits. 10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to Read mode. 54 208031-05 Numonyx(R) AxcellTM M29EW Table 14. Command Interface Block Protection commands, 16-bit mode(1)(2)(3) Command Length Bus operations 1st 2nd 3rd 4th 5th 6th 7th Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data Ad Data 3 555 AA 2AA 55 555 40 - - - - - - - - Lock Register Program 2 X A0 X DATA(5) - - - - - - - - - - Lock Register Read 1 X (5) - - - - - - - - - - - - Enter Password Protection Command Set(4) 3 555 AA 2AA 55 555 60 - - - - - - - - Password Program (6)(7) 2 X A0 PWAn PWDn - - - - - - - - - - Password Read 4 00 PWD0 01 PWD1 02 PWD2 03 PWD3 - - - - - - Password Unlock(7) 7 00 25 00 03 00 PWD0 01 PWD1 02 PWD2 03 PWD3 00 29 Enter NonVolatile Protection Command Set(4) 3 555 AA 2AA 55 555 C0 - - - - - - - - NVPB Program(8) 2 X A0 BAd 00 - - - - - - - - - - Clear all NVPBs(9) 2 X 80 00 30 - - - - - - - - - - Read NVPB Status 1 BAd RD(0) - - - - - - - - - - - - Enter NVPB Lock Bit Command Set 3 555 AA 2AA 55 555 50 - - - - - - - - NVPB Lock Bit Program 2 X A0 X 00 - - - - - - - - - - Read NVPB Lock Bit Status 1 X RD(0) - - - - - - - - - - - - Enter Volatile Protection Command Set 3 555 AA 2AA 55 555 E0 - - - - - - - - VPB Program 2 X A0 BAd 00 - - - - - - - - - - Read VPB Status 1 BAd RD(0) - - - - - - - - - - - - VPB Clear 2 X A0 BAd 01 - - - - - - - - - - Exit Protection Command Set(10) 2 X 90 X 00 - - - - - - - - - - Enter Extended Memory Block(4) 3 555 AA 2AA 55 555 88 - - - - - - - - Exit Extended Memory Block 4 555 AA 2AA 55 555 90 X 00 - - - - - - Volatile Protection NVPB Lock bit Non-Volatile Protection Password Protection Lock register Enter Lock Register Command Set(4) DATA 208031-05 55 Numonyx(R) AxcellTM M29EW Command Interface 1. Ad = address; Dat = data; BAd = Any address in the Block; RD = Read data; PWDn = Password byte 0 to 3; PWAn = Password Address (n = 0 to 3); X = Don't care. All values in the table are in hexadecimal. 2. Grey cells represent Read cycles. The other cells are Write cycles. 3. DQ15 to DQ8 are `Don't care' during unlock and command cycles. Amax to A16 are `Don't care' during unlock and command cycles unless an address is required. 4. An Enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any other block are allowed. 5. DATA = Lock Register content. 6. Only one portion of password can be programmed or read by each Password Program command. 7. The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 8. Protected and unprotected states correspond to 00 and 01, respectively. 9. The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared Non-volatile Modify Protection bits. 10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to Read mode. 56 208031-05 Numonyx(R) AxcellTM M29EW 7 Registers Registers The device features two registers: 7.1 1. A Lock Register that allows to configure the memory blocks and Extended Memory Block protection (see Table 16: Block Protection Status) 2. A Status Register that provides information on the current or previous Program or Erase operations. Lock Register The Lock Register is a 16-bit one-time programmable register. The bits in the Lock Register are summarized in Table 15: Lock Register bits. See Section 6.3.3: Lock Register command set for a description of the commands allowing to read and program the Lock Register. 7.1.1 Password Protection Mode Lock bit (DQ2) The Password Protection Mode Lock bit, DQ0, is one-time programmable. Programming (setting to `0') this bit permanently places the device in Password Protection mode. Any attempt to program the Password Protection mode Lock bit when the Non-Volatile Protection Mode bit is programmed causes the operation to abort and the device to return to Read mode. 7.1.2 Non-Volatile Protection Mode Lock bit (DQ1) The Non-Volatile Protection Mode Lock bit, DQ1, is one-time programmable. Programming (setting to `0') this bit permanently places the device in Non-Volatile Protection mode. When shipped from Numonyx factory, all parts default to operate in Non-Volatile Protection mode. The memory blocks are unprotected (NVPBs set to `1'). Any attempt to program the Non-Volatile Protection mode Lock bit when the Password Protection Mode bit is programmed causes the operation to abort and the device to return to Read mode. 7.1.3 Extended Memory Block Protection bit (DQ0) If the device is shipped with the Extended Memory Block unlocked, the block can be protected by setting the Extended Memory Block Protection bit, DQ0, to `0'. However, this bit is one-time programmable and once protected the Extended Memory Block cannot be unprotected any more. The Extended Memory Block protection status can be read in Auto Select mode by issuing an Auto Select command (see Table 9 and Table 10). 208031-05 57 Numonyx(R) AxcellTM M29EW Registers Lock Register bits(1) Table 15. DQ15-3(2) DQ2 DQ1 DQ0 Reserved Password Protection Mode Lock bit Non-Volatile Protection Mode Lock bit Extended Memory Block Protection bit 1. DQ0, DQ1 and DQ2 Lock Register bits are set to `1' when shipped from the Numonyx. 2. DQ15 to DQ3 are reserved and default to `1'. Table 16. Block Protection Status NVPB Lock bit(1) Block NVPB(2) Block VPB(3) Block protection status 1 1 1 00h Block unprotected (NVPB changeable) 1 1 0 01h Block protected by VPB (NVPB changeable) 1 0 1 01h Block protected by NVPB (NVPB changeable) 1 0 0 01h Block protected by NVPB and VPB (NVPB changeable) 0 1 1 00h Block unprotected (NVPB unchangeable) 0 1 0 01h Block protected by VPB (NVPB unchangeable) 0 0 1 01h Block protected by NVPB (NVPB unchangeable) 0 0 0 01h Block protected by NVPB and VPB (NVPB unchangeable) Block Protection Status 1. If the NVPB Lock bit is set to `0', all NVPBs are locked. If the NVPB Lock bit is set to `1', all NVPBs are unlocked. 2. If the Block NVPB is set to `0', the block is protected, if set to `1', it is unprotected. 3. If the Block VPB is set to `0', the block is protected, if set to `1', it is unprotected. 58 208031-05 Numonyx(R) AxcellTM M29EW Registers Figure 13. Lock Register program flow chart START Write Unlock cycles: Add 555h, Data AAh Add 2AAh, Data 55h Unlock cycle 1 unlock cycle 2 Write Enter Lock Register command set: Add 555h, Data 40h Program Lock Register Data: Add Dont' care, Data A0h Add Dont' care(1), Data PDh Polling algorithm YES Done NO DQ5 = 1 NO YES Device returned to Read mode PASS: Write Lock Register Exit command: Add Dont' care, Data 90h Add Dont' care, Data 00h FAIL Reset to return the device to Read mode ai13677 1. PD is the programmed data (see Table 15: Lock Register bits). 2. Each bit of the Lock Register can only be programmed once. 208031-05 59 Numonyx(R) AxcellTM M29EW Registers 7.2 Status Register The M29EW device has one Status Register. The various bits convey information and errors on the current and previous program/erase operation. Bus Read operations from any address within the memory, always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 17: Status Register bits. 7.2.1 Data Polling bit (DQ7) The Data Polling bit can be used to identify whether the Program/Erase controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations, from the address just programmed, output DQ7, not its complement. During Erase or Blank Check operations the Data Polling bit outputs `0', the complement of the erased state of DQ7. When the algorithm is complete, Data Polling produces a '1' on DQ7. After successful completion of the Erase or Blank Check operation the memory returns to Read mode. In Erase Suspend mode the Data Polling bit will output a `1' during a Bus Read operation within a block being erased. The Data Polling bit will change from `0' to `1' when the Program/Erase controller has suspended the Erase operation. Figure 14: Data polling flow chart, gives an example of how to use the Data Polling bit. A Valid Address is the address being programmed or an address within the block being erased or blank checked. 7.2.2 Toggle bit (DQ6) The Toggle bit can be used to identify whether the Program/Erase controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle bit is output on DQ6 when the Status Register is read. During a Program/Erase operation the Toggle bit changes from `0' to `1' to `0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle bit will output when addressing a cell within a block being erased. The Toggle bit will stop toggling when the Program/Erase controller has suspended the Erase operation. Figure 15: Toggle flow chart, gives an example of how to use the Data Toggle bit. 7.2.3 Error bit (DQ5) The Error bit can be used to identify errors detected by the Program/Erase controller. The Error bit is set to `1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory, or a Blank Check operation fails. If the Error bit is set a 60 208031-05 Numonyx(R) AxcellTM M29EW Registers Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to `0' back to `1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from `0' to `1'. 7.2.4 Erase Timer bit (DQ3) The Erase Timer bit can be used to identify the start of Program/Erase controller operation during a Block Erase command. Once the Program/Erase controller starts erasing the Erase Timer bit is set to `1'. Before the Program/Erase controller starts the Erase Timer bit is set to `0' and additional blocks to be erased may be written to the command interface. The Erase Timer bit is output on DQ3 when the Status Register is read. 7.2.5 Alternative Toggle bit (DQ2) The Alternative Toggle bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle bit changes from `0' to `1' to `0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle bit changes from `0' to `1' to `0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory array data as if in Read mode. After an Erase operation that causes the Error bit to be set, the Alternative Toggle bit can be used to identify which block or blocks have caused the error. The Alternative Toggle bit changes from `0' to `1' to `0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle bit does not change if the addressed block has erased correctly. 7.2.6 Buffered Program Abort bit (DQ1) The Buffered Program Abort bit, DQ1, is set to `1' when a Buffer Program operation aborts. The Buffered Program Abort and Reset command must be issued to return the device to Read mode (see Write to Buffer Program in Section 6.1: Standard commands). For the complete polling flow chart, please refer to Figure 16.: Status Register polling flow chart. 208031-05 61 Numonyx(R) AxcellTM M29EW Registers Status Register bits(1) Table 17. Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# Any address DQ7 Toggle 0 - No Toggle 0 0 Any address DQ7 Toggle 0 - - - 0 Any address DQ7 Toggle 0 - - 1 0 Program Error Any address DQ7 Toggle 1 - - - Hi-Z Chip Erase Any address 0 Toggle 0 1 Toggle - 0 Erasing block 0 Toggle 0 0 Toggle - 0 Non-erasing block 0 Toggle 0 0 No toggle - 0 Erasing/Verifying block 0 Toggle 0 1 Toggle - 0 Nonerasing/Verifying block 0 Toggle 0 1 No toggle - 0 Erasing/Verifying block 1 No Toggle 0 - Toggle - Hi-Z - Hi-Z Program(2) Program During Erase Suspend Buffered Program Abort(2) Block Erase before timeout Block Erase/Blank Check Erase/Blank Check Suspend Nonerasing/Verifying block Data read as normal Good block address 0 Toggle 1 1 No toggle - Hi-Z Faulty Block address 0 Toggle 1 1 Toggle - Hi-Z Erase/Blank Check Error 1. Unspecified data bits should be ignored. 2. DQ7 for Buffer Program is related to the last address location loaded. 62 208031-05 Numonyx(R) AxcellTM M29EW Registers Figure 14. Data polling flow chart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA YES NO NO NO DQ = 1 DQ5 = 1 YES YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES PASS AI07760 208031-05 63 Numonyx(R) AxcellTM M29EW Registers Figure 15. Toggle flow chart START READ DQ6 at Valid Address READ DQ5 & DQ6 at Valid Address DQ6 = TOGGLE NO YES NO DQ5 =1 YES READ DQ6 TWICE at Valid Address DQ6 = TOGGLE NO YES FAIL PASS AI11530 64 208031-05 Numonyx(R) AxcellTM M29EW Registers Figure 16. Status Register polling flow chart Start Read 1 DQ7=Valid Data? Yes Read 2 Programming Operation? Read 3 Yes Read3 correct data? No No No DQ5=1? Yes Yes Programming Operation Complete Programming Operation Failed Read 2 Read2.DQ6 Read3.DQ6 DQ6 toggling ? Read 3 Yes DEVICE ERROR Yes Device in Erase / Suspend Mode Invalid state use RESET comand No Read2.DQ2 Read3.DQ2 DQ2 toggling ? No DQ6 toggling ? Yes Timeout failure No Read1.DQ6 Read2.DQ6 No Erase Complete Device Busy , RePoll Write Buffer Programming Yes DQ1=1? Yes Write Buffer Program Abort No No Device Busy , RePoll 208031-05 65 Numonyx(R) AxcellTM M29EW Maximum Ratings 8 Maximum Ratings Stressing the device above the rating listed in Table 18: Absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Refer also to the relevant quality documents from Numonyx. Table 18. Absolute maximum ratings Symbol Parameter Min Max Unit TBIAS Temperature under bias -40 85 C TSTG Storage temperature -65 125 C -0.6 VCC + 0.6 V -2 5.6 V -2 5.6 V -2 14.5 V VIO VCC VCCQ VPPH(3) Input or output Supply voltage(1)(2) voltage(1)(2) Input/output supply voltage(1)(2) Program voltage(1)(2) 1. Minimum voltage may undershoot to -2 V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC + 2 V during transition and for less than 20ns during transitions. 3. VPPH must not remain at 12 V for more than a cumulative total of 80hrs. 66 208031-05 Numonyx(R) AxcellTM M29EW 9 DC and AC Parameters DC and AC Parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 19: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 19. Operating and AC measurement conditions Parameter Min Max Unit VCC supply voltage 2.7 3.6 V VCCQ supply voltage (VCCQ VCC) 1.7 3.6 V VPP supply voltage -0.6 12.5 V Ambient operating temperature - 40 85 C Load capacitance (CL) 30 Input rise and fall times pF - Input pulse voltages Input and output timing ref. voltages 2.5 ns 0 to VCCQ V VCCQ/2 V Figure 17. AC measurement load circuit VPP VCC VCCQ 25 k DEVICE UNDER TEST CL 0.1 F 25 k 0.1 F CL includes JIG capacitance AI05558b Figure 18. AC measurement I/O waveform VCCQ VCCQ/2 0V AI05557b 208031-05 67 Numonyx(R) AxcellTM M29EW DC and AC Parameters Table 20. Power-up wait timings Symbol Alt. tVCHVCQH - tVCHPH(2) tVCQHPH (2) Parameter Limit Value Unit VCC(1) High to VCCQ(1) High Min 0 s tVCS VCC High to rising edge of RST# Min 60 s tVIOS VCCQ High to rising edge of RST# Min 0 s tPHEL tRH RST# High to Chip Enable Low Min 50 ns tPHWL - RST# High to Write Enable Low Min 150 ns 1. VCC and VCCQ ramps must be synchronized during power-up. 2. If RST# is not stable for tVCHRH or tVCQHRH, the device does not permit any Read and Write operations and a hardware reset is required. Figure 19. Power-up wait timings t VCHVCQH VCC VCCQ t PHEL CE# t VCQHPH RST# t VCHPH WE# t PHWL AI14247 68 208031-05 Numonyx(R) AxcellTM M29EW DC and AC Parameters Device capacitance(1) Table 21. Symbol CIN COUT Parameter Test condition Min Max VIN = 0 V 2 7 VOUT = 0 V 2 5 Input capacitance Output capacitance Unit pF 1. Sampled only, not 100% tested. Table 22. DC characteristics Symbol Parameter Min Typ Max Unit 0 V VIN VCC - - 1 A 0 V VOUT VCC - - 1 A Random Read CE# = VIL, OE# = VIH, f = 5 MHz - 20 25 mA Page Read CE# = VIL, OE# = VIH, f = 13 MHz - 12 16 mA - 50 120 - 35 120 - 35 120 VPP/WP# = VIL or VIH - 35 50 mA VPP/WP#=VPPH - 26 33 mA ILI(1) Input leakage current ILO Output leakage current ICC1 Read current Test condition 128-Mbit ICC2 Supply current (Standby) 64-Mbit 32-Mbit ICC3(2) Supply current (Program/Erase/Blank Check) IPP1 IPP2 IPP3 Vpp Current IPP4 CE# = VCCQ 0.2V RST# = VCCQ 0.2V Program/Erase controller active A Read VPP/WP# VCC - 2 15 A Standby VPP/WP# VCC - 0.2 5 A Reset RST# = VSS 0.2 V - 0.2 5 A Program operation ongoing VPP/WP# = 12 V 5% - 5 10 mA VPP/WP# = VCC - 0.05 0.10 mA Erase operation ongoing VPP/WP# = 12 V 5% - 5 10 mA VPP/WP# = VCC - 0.05 0.10 mA VIL Input Low voltage VCC 2.7 V -0.5 - 0.8 V VIH Input High voltage VCC 2.7 V 2 - VCCQ+0.5 V VOL Output Low voltage IOL = 100 A, VCC = VCC(min), VCCQ = VCCQ(min) - - 0.2 V VOH Output High voltage IOH = -100 A, VCC = VCC(min), VCCQ = VCCQ(min) VCCQ-0.2 - - V VPPLK VPP Lock-Out voltage - - - 0.4 V VPPH Voltage for VPP/WP# Program acceleration - 11.5 - 12.5 V VPPL VPP logic level 2.7 - 3.6 V 2.3 - - V VLKO(2) Program/Erase lockout supply voltage - 1. The maximum input leakage current is 5 A on the VPP/WP# pin. 2. Sampled only, not 100% tested. 208031-05 69 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 20. Random Read AC waveforms (8-bit mode) tAVAV VALID A0-AMAX/A-1 tAVQV tAXQX CE# tELQV tEHQX tELQX tEHQZ OE# tGLQX tGHQX tGHQZ tGLQV DQ0-DQ7 VALID BYTE# tELBL tBLQZ AI13698 Figure 21. Random Read AC waveforms (16-bit mode) tAVAV A0-AMAX VALID tAVQV tAXQX CE# tELQV tEHQX tELQX tEHQZ OE# tGLQX tGHQX tGHQZ tGLQV DQ0-DQ15 VALID BYTE# tELBH AI08970 70 208031-05 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 22. Byte Transition AC waveform VALID A0-AMAX VALID A-1 tAXQX tAVQV BYTE# tBHQV DQ0-DQ7 DATA OUT tBLQX Hi-Z DQ8-DQ15 DATA OUT tBLQZ Byte_Transition_AC-Waveform 1. CE# and OE# are VIL. Figure 23. Page Read AC waveforms (16-bit mode) A4-Amax VALID VALID A0-A3 VALID VALID VALID VALID tAVQV CE# tELQV tEHQX tEHQZ OE# tGLQV tGHQX tAVQV1 DQ0-DQ15 VALID tGHQZ VALID VALID VALID VALID AI08971c Table 23. Read AC characteristics (Sheet 1 of 2) Test condition Limit BGA TSOP Unit CE# = VIL, OE# = VIL Min 60 70 ns tACC Address Valid to Output Valid CE# = VIL, OE# = VIL Max 60 70 ns Address Valid to Output Valid (Page) CE# = VIL, OE# = VIL Max 25 ns tLZ Chip Enable Low to Output Transition OE# = VIL Min 0 ns tELQV tE Chip Enable Low to Output Valid OE# = VIL Max tGLQX(1) tOLZ Output Enable Low to Output Transition CE# = VIL Min Symbol Alt. tAVAV tRC tAVQV tAVQV1 tPAGE tELQX(1) Parameter Address Valid to Next Address Valid 208031-05 60 70 0 ns ns 71 Numonyx(R) AxcellTM M29EW DC and AC Parameters Table 23. Read AC characteristics (Sheet 2 of 2) Symbol Alt. Parameter Test condition Limit tGLQV tOE Output Enable Low to Output Valid CE# = VIL Max 25 ns tEHQZ(1) tHZ Chip Enable High to Output Hi-Z OE# = VIL Max 20 ns tGHQZ(1) tDF Output Enable High to Output Hi-Z CE# = VIL Max 15 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition - Min 0 ns tELBL tELBH tELFL Chip Enable to BYTE# Low or tELFH High - Max 10 ns tBLQV tFLQV BYTE# Low to Output Valid - Max 1 s tBHQV tFHQV BYTE# High to Output Valid - Max 1 s tBLQZ tFLQZ BYTE# Low to Output in high Z - Max 1 s BGA TSOP Unit 1. Sampled only, not 100% tested. Figure 24. Write Enable Controlled Program waveforms (8-bit mode) 3rd cycle 4th cycle A0-Amax/A-1 Read cycle Data Polling tAVAV tAVAV AAAh PA PA tAVWL tWLAX tELQV tWHEH tELWL CE# tGHWL tGLQV OE# tWLWH tWHWL WE# tDVWH DQ0-DQ7 tGHQZ tWHWH1 AOh PD DQ7 DOUT tWHDX tAXQX DOUT AI13333 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. SeeTable 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings. 72 208031-05 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 25. Write Enable Controlled Program waveforms (16-bit mode) 3rd cycle 4th cycle A0-Amax Read cycle Data Polling tAVAV tAVAV 555h PA PA tAVWL tWLAX tELQV tWHEH tELWL CE# tGHWL tGLQV OE# tWLWH tWHWL WE# tDVWH DQ0-DQ15 tGHQZ AOh PD DQ7 DOUT tWHDX tAXQX DOUT AI13699 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous Program command. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. SeeTable 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings. 208031-05 73 Numonyx(R) AxcellTM M29EW DC and AC Parameters Table 24. M Write AC characteristics, Write Enable Controlled Symbol Alt tAVAV tWC tELWL Limit BGA TSOP Unit Address Valid to Next Address Valid Min 60 70 ns tCS Chip Enable Low to Write Enable Low Min 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 35 ns tDVWH tDS Input Valid to Write Enable High Min 30 ns tWHDX tDH Write Enable High to Input Transition Min 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 20 ns tAVWL tAS Address Valid to Write Enable Low Min 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 ns tGHWL - Output Enable High to Write Enable Low Min 0 ns tWHGL tOEH Write Enable High to Output Enable Low Min 0 ns tBUSY Program/Erase Valid to RY/BY# Low Max 90 ns tVCS VCC High to Chip Enable Low Min 60 s tWHRL (1) tVCHEL Parameter 1. Sampled only, not 100% tested. 74 208031-05 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 26. Chip Enable Controlled Program waveforms (8-bit mode) 3rd cycle 4th cycle Data Polling PA PA tAVAV A0-Amax/A-1 AAAh tAVEL tELAX tEHWH tWLEL WE# tGHEL OE# tELEH tEHEL1 CE# tDVEH DQ0-DQ7 tWHWH1 AOh PD DQ7 DOUT tEHDX AI13334 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. See Table 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings. 208031-05 75 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 27. Chip Enable Controlled Program waveforms (16-bit mode) 3rd cycle 4th cycle Data Polling PA PA tAVAV A0-Amax 555h tAVEL tELAX tEHWH tWLEL WE# tGHEL OE# tELEH tEHEL1 CE# tDVEH DQ0-DQ15 AOh PD DQ7 DOUT tEHDX AI14100 1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check of Status Register Data Polling bit. 2. PA is the address of the memory location to be programmed. PD is the data to be programmed. 3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 7.2.1: Data Polling bit (DQ7)). 4. See Table 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings. 76 208031-05 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 28. Chip/Block Erase waveforms (8-bit mode) tAVAV A0-Amax/A-1 555h 2AAh 555h 555h tAVWL 2AAh 555h/BAd (1) tWLAX tWHEH tELWL CE# tGHWL OE# tWLWH tWHWL WE# tDVWH DQ0-DQ7 AAh 55h AAh 80h 55h 10h/ 30h tWHDX AI13335 1. For a Chip Erase command, addresses and data are 555h and 10h, respectively, while they are BAd and 30h for a Block Erase command. 2. BAd is the block address. 3. See Table 24: Write AC characteristics, Write Enable Controlled, Table 25: Write AC characteristics, Chip Enable Controlled and Table 23: Read AC characteristics (Sheet of 2) for details on the timings. Table 25. Write AC characteristics, Chip Enable Controlled Symbol Alt. tAVAV tWC tWLEL Parameter Limit BGA TSOP Unit Address Valid to Next Address Valid Min 60 70 ns tWS Write Enable Low to Chip Enable Low Min 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 35 ns tDVEH tDS Input Valid to Chip Enable High Min 30 ns tEHDX tDH Chip Enable High to Input Transition Min 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 ns tGHEL - Output Enable High Chip Enable Low Min 0 ns 208031-05 77 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 29. Reset AC waveforms (no program/erase in progress) RY/BY# CE#, OE# tPHEL, tPHGL RST# tPLPH AI11300b Figure 30. Reset AC waveforms (during program/erase operation) tPLRH RY/BY# tRHEL, tRHGL CE#,OE# RST# tPLPH AI11301b Table 26. Reset AC characteristics Symbol Alt. tPLRH(1) tREADY RST# Low to Read mode, during Program or Erase tPLPH tPHEL, tPHGL Parameter (1) tRHWL, tRHEL, tRHGL(1) Min Max Unit - 25 s tRP RST# Pulse width 100 - ns tRH RST# High to Chip Enable Low, Output Enable Low 50 - ns RST# Low to Standby mode, during Read mode 10 - s RST# Low to Standby mode, during Program or Erase 50 - s RY/BY# High to Write Enable Low, Chip Enable Low, Output Enable Low 0 - ns tRPD tRB 1. Sampled only, not 100% tested. Figure 31. Accelerated program timing waveforms VPPH VPP/WP# VIL or VIH tVHVPP tVHVPP AI05563 78 208031-05 Numonyx(R) AxcellTM M29EW DC and AC Parameters Figure 32. Data polling AC waveforms tEHQZ tGHQZ tELQV tWHEH CE# tGLQV OE# tWHGL2 WE# DQ7 DATA DQ7 DQ7 Valid DQ7 Data DQ6-DQ0 DATA Output Flag Output Flag Valid DQ6-DQ0 Data tWHRL RY/BY# AI13336c 1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed. 2. See Table 27: Accelerated Program and Data Polling/Data Toggle AC characteristics and Table 23: Read AC characteristics (Sheet of 2) for details on the timings. Figure 33. Toggle/Alternative Toggle bit polling AC waveforms (8-bit mode) A0-Amax/A-1 tGHAX tAXGL CE# tWHGL2 tAVEL tEHAX WE# tEHEL2 tGHGL2 tGHGL2 OE# tGLQV tWHDX DQ6/DQ2 Data Toggle tELQV Toggle Toggle Stop toggling Output Valid tWHRL RY/BY# AI13337 1. DQ6 stops toggling when the ongoing Program or Erase command is completed. DQ2 stops toggling when the in-progress Chip Erase or Block Erase command is completed. 2. See Table 27: Accelerated Program and Data Polling/Data Toggle AC characteristics and Table 23: Read AC characteristics (Sheet of 2) for details on the timings. 208031-05 79 Numonyx(R) AxcellTM M29EW DC and AC Parameters Table 27. Accelerated Program and Data Polling/Data Toggle AC characteristics Symbol Alt tVHVPP - tVHHWH - tAXGL Min Max Unit VPP/WP# raising or falling time 250 - ns Valid VHH on VPP/WP# to WE# high 50 - ns tASO Address setup time to Output Enable Low during Toggle bit polling 15 - ns tGHAX, tEHAX tAHT Address hold time from Output Enable during Toggle bit polling 0 - ns tEHEL2 tEPH Chip Enable High during Toggle bit polling 20 - ns tWHGL2, tGHGL2 tOEH Output Hold time during Data and Toggle bit polling 20 - ns - 90 ns tWHRL 80 Parameter tBUSY Program/Erase Valid to RY/BY# Low 208031-05 Numonyx(R) AxcellTM M29EW Programming and Erase Performance 10 Programming and Erase Performance Table 28. Programming and Erase Performance Buffer Size Byte Word Min Typ(1)(2) Max(2) Unit Block Erase - - - - 0.5 4 s Erase Suspend latency - - - - 20 25 s Block Erase time-out - - - 50 - - s Single Byte Program - - - - 15 175 s Double / Quadruple / Octuple Byte Program - - - - 10 200 s 32 32 - - 70 200 64 64 - - 85 200 256 256 - - 160 710 32 1 - - 2.19 6.25 64 1 - - 1.33 3.125 256 1 - - 0.625 2.77 - - - - 15 175 16 - 16 - 70 200 32 - 32 - 85 200 128 - 128 - 160 710 256 - 256 - 284 1280 256 - 256 - 160 800 16 - 1 - 4.375 12.5 32 - 1 - 2.66 6.25 128 - 1 - 1.25 5.55 256 - 1 - 1.11 5 256 - 1 - 0.625 3.125 s Program Suspend latency - - - - 20 25 s Blank Check - - - - 3.2 - ms Program/Erase cycles (per block) - - - 100,000 - - Cycles Parameter Byte Program Byte Write to Buffer Program Effective Write to Buffer Program per Byte Single Word Program Word Write to Buffer Program Word Program Full Buffer Program With VPPH Effective Write to Buffer Program per Word Effective Full Buffer Program per Word With VPPH s s s s s s 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 208031-05 81 Numonyx(R) AxcellTM M29EW Package Mechanical Specifications 11 Package Mechanical Specifications Numonyx offers these devices in both lead-free and leaded packages. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 34. TSOP56 - 56 lead thin small-outline package,14 x 20 mm, package outline A2 1 N e E B N/2 A D1 CP D DIE C A1 TSOP-b L 1. Drawing is not to scale. Table 29. TSOP56 - 56 lead thin small-outline package, 14 x 20 mm, package mechanical data Millimeters Inches Symbol Typ Min Max Typ Min Max A - - 1.20 - - 0.047 A1 - 0.05 - - 0.002 - A2 0.995 0.965 1.025 0.039 0.038 0.040 B(1) 0.22 0.17 0.27 0.0087 0.0067 0.0106 C 0.125 0.115 0.135 0.0049 0.0045 0.0053 CP - - 0.10 - - 0.004 E 14.00 13.80 14.20 0.551 0.543 0.559 D 20.00 19.80 20.20 0.787 0.780 0.795 D1 18.40 18.20 18.60 0.724 0.717 0.732 e 0.50 - - 0.020 - - L 0.60 0.50 0.70 0.024 0.020 0.028 3o 0o 5o 3o 0o 5o 56 1. For legacy lead width, 0.15mm (Typ), 0.10mm (Min), 0.20mm (Max). 82 208031-05 Numonyx(R) AxcellTM M29EW Package Mechanical Specifications Figure 35. TSOP48 - 48 lead thin small-outline package, 12 x 20 mm, package outline A2 1 N e E B N/2 A D1 CP D DIE C A1 TSOP-b L 1. Drawing is not to scale. Table 30. TSOP48 - 48 lead thin small-outline package, 12 x 20 mm, package mechanical data millimeters Symbol Typ Min Max A - - 1.20 A1 0.10 0.05 0.15 A2 1.00 0.95 1.05 B 0.22 0.17 0.27 C - 0.10 0.21 CP - - 0.10 E 12.00 11.90 12.10 D 20.00 19.80 20.20 D1 18.40 18.30 18.50 e 0.50 - - L 0.60 0.50 0.70 0o 5o o 3 48 208031-05 83 Numonyx(R) AxcellTM M29EW Package Mechanical Specifications Figure 36. BGA48 6 x 8 mm - 6 x 8 active ball array, package outline 1. Drawing is not to scale. 2. Drawing is bottom view. Table 31. BGA48 6 x 8 mm - 6 x 8 active ball array, package mechanical data millimeters Symbol 84 Typ Min Max A - - 1.00 A1 - 0.20 - A2 0.64 - - b 0.35 0.30 0.40 D 6.00 5.90 6.10 D1 4.00 - - e 0.80 - - E 8.00 7.90 8.10 E1 5.60 - - FD 1.00 - - FE 1.20 - - SD 0.40 - - SE 0.40 - - ddd - - 0.10 208031-05 Numonyx(R) AxcellTM M29EW Package Mechanical Specifications Figure 37. Fortified BGA64 11 x 13 mm - 8 x 8 active ball array, package outline D D1 FD FE E SD SE E1 ddd BALL "A1" A e b A2 A1 BGA-Z23 1. Drawing is not to scale. 2. Drawing is bottom view. Table 32. Fortified BGA64 11 x 13 mm - 8 x 8 active ball array, package mechanical data millimeters Symbol Typ Min Max A - - 1.40 A1 0.49 0.40 - A2 0.80 - - b 0.60 0.55 0.65 D 11.00 10.90 11.10 D1 7.00 - - ddd - - 0.10 e 1.00 - - E 13.00 12.90 13.10 E1 7.00 - - FD 2.00 - - FE 3.00 - - SD 0.50 - - SE 0.50 - - 208031-05 85 Numonyx(R) AxcellTM M29EW Ordering Information 12 Ordering Information Table 33. Ordering information scheme Example: RC 28F 128 M29EW H ***** Package JS = TSOP56: 14 x 20 mm, lead free, RoHS compliant, halogen free PC = Fortified BGA64: 11 x 13 mm, lead free, RoHS compliant, halogen free RC = Fortified BGA64: 11 x 13 mm, leaded JR = TSOP48: 12 x 20 mm, lead free, RoHS compliant, halogen free PZ = BGA48: 6 x 8 mm, lead free, RoHS compliant, halogen free Product Line 28F= NOR Parallel Interface Device Density 128=128-Mbit 064=64-Mbit 032=32-Mbit Device Type M29EW = 3V core, page flash memory Device function H = uniform block, highest block protected by VPP/WP# L = uniform block, lowest block protected by VPP/WP# B = bottom boot, bottom two blocks protected by VPP/WP# T = top boot, top two blocks protected by VPP/WP# Device features *= The last digit is randomly assigned to cover packing media and/or features or other specific configuration. Note: This product is also available with the Extended Memory Block Numonyx pre-locked. For further details and ordering information contact your nearest Numonyx sales office. Devices are shipped from Numonyx factory with the memory content bits erased to `1'. For a list of available options (package, High/Low protect, etc.) or for further information on any aspect of the device, please contact your nearest Numonyx Sales Office. 86 208031-05 Numonyx(R) AxcellTM M29EW Table 34. Note: Ordering Information Valid Combinations of SBC M29EW Part Numbers 128-Mbit 64-Mbit 32-Mbit JS28F128M29EWH* JS28F064M29EWH* JR28F032M29EWH* JS28F128M29EWL* JS28F064M29EWL* JR28F032M29EWL* PC28F128M29EWH* JS28F064M29EWB* JR28F032M29EWB* PC28F128M29EWL* JS28F064M29EWT* JR28F032M29EWT* RC28F128M29EWH* JR28F064M29EWH* PZ28F032M29EWH* RC28F128M29EWL* JR28F064M29EWL* PZ28F032M29EWL* - JR28F064M29EWB* PZ28F032M29EWB* - JR28F064M29EWT* PZ28F032M29EWT* - PC28F064M29EWH* - - PC28F064M29EWL* - - PC28F064M29EWB* - - PC28F064M29EWT* - - PZ28F064M29EWH* - - PZ28F064M29EWL* - - PZ28F064M29EWB* - - PZ28F064M29EWT* - For further information on ordering products or for product part numbers, go to: http://www.numonyx.com/en-US/MemoryProducts/Pages/PartNumberLookup.aspx. 208031-05 87 Numonyx(R) AxcellTM M29EW 128-Mbit Memory Address Table Appendix A 128-Mbit Memory Address Table Block Address Table(1) Table 35. 88 Block Number Block Size (Kbytes / Kwords) x8 Address (HEX) x16 Address (HEX) 0 128 / 64 0000000-001FFFF 0000000-000FFFF 1 128 / 64 0020000-003FFFF 0010000-001FFFF 2 128 / 64 0040000-005FFFF 0020000-002FFFF 3 128 / 64 0060000-007FFFF 0030000-003FFFF 4 128 / 64 0080000-009FFFF 0040000-004FFFF 5 128 / 64 00A0000-00BFFFF 0050000-005FFFF 6 128 / 64 00C0000-00DFFFF 0060000-006FFFF 7 128 / 64 00E0000-00FFFFF 0070000-007FFFF 8 128 / 64 0100000-011FFFF 0080000-008FFFF 9 128 / 64 0120000-013FFFF 0090000-009FFFF 10 128 / 64 0140000-015FFFF 00A0000-00AFFFF 11 128 / 64 0160000-017FFFF 00B0000-00BFFFF 12 128 / 64 0180000-019FFFF 00C0000-00CFFFF 13 128 / 64 01A0000-01BFFFF 00D0000-00DFFFF 14 128 / 64 01C0000-01DFFFF 00E0000-00EFFFF 15 128 / 64 01E0000-01FFFFF 00F0000-00FFFFF 16 128 / 64 0200000-021FFFF 0100000-010FFFF 17 128 / 64 0220000-023FFFF 0110000-011FFFF 18 128 / 64 0240000-025FFFF 0120000-012FFFF 19 128 / 64 0260000-027FFFF 0130000-013FFFF 20 128 / 64 0280000-029FFFF 0140000-014FFFF 21 128 / 64 02A0000-02BFFFF 0150000-015FFFF 22 128 / 64 02C0000-02DFFFF 0160000-016FFFF 23 128 / 64 02E0000-02FFFFF 0170000-017FFFF 24 128 / 64 0300000-031FFFF 0180000-018FFFF 25 128 / 64 0320000-033FFFF 0190000-019FFFF 26 128 / 64 0340000-035FFFF 01A0000-01AFFFF 27 128 / 64 0360000-037FFFF 01B0000-01BFFFF 28 128 / 64 0380000-039FFFF 01C0000-01CFFFF 29 128 / 64 03A0000-03BFFFF 01D0000-01DFFFF 30 128 / 64 03C0000-03DFFFF 01E0000-01EFFFF 208031-05 Numonyx(R) AxcellTM M29EW 128-Mbit Memory Address Table Block Address Table(1) Table 35. Block Number Block Size (Kbytes / Kwords) x8 Address (HEX) x16 Address (HEX) 31 128 / 64 03E0000-03FFFFF 01F0000-01FFFFF 32 128 / 64 0400000-041FFFF 0200000-020FFFF 33 128 / 64 0420000-043FFFF 0210000-021FFFF 34 128 / 64 0440000-045FFFF 0220000-022FFFF 35 128 / 64 0460000-047FFFF 0230000-023FFFF 36 128 / 64 0480000-049FFFF 0240000-024FFFF 37 128 / 64 04A0000-04BFFFF 0250000-025FFFF 38 128 / 64 04C0000-04DFFFF 0260000-026FFFF 39 128 / 64 04E0000-04FFFFF 0270000-027FFFF 40 128 / 64 0500000-051FFFF 0280000-028FFFF 41 128 / 64 0520000-053FFFF 0290000-029FFFF 42 128 / 64 0540000-055FFFF 02A0000-02AFFFF 43 128 / 64 0560000-057FFFF 02B0000-02BFFFF 44 128 / 64 0580000-059FFFF 02C0000-02CFFFF 45 128 / 64 05A0000-05BFFFF 02D0000-02DFFFF 46 128 / 64 05C0000-05DFFFF 02E0000-02EFFFF 47 128 / 64 05E0000-05FFFFF 02F0000-02FFFFF 48 128 / 64 0600000-061FFFF 0300000-030FFFF 49 128 / 64 0620000-063FFFF 0310000-031FFFF 50 128 / 64 0640000-065FFFF 0320000-032FFFF 51 128 / 64 0660000-067FFFF 0330000-033FFFF 52 128 / 64 0680000-069FFFF 0340000-034FFFF 53 128 / 64 06A0000-06BFFFF 0350000-035FFFF 54 128 / 64 06C0000-06DFFFF 0360000-036FFFF 55 128 / 64 06E0000-06FFFFF 0370000-037FFFF 56 128 / 64 0700000-071FFFF 0380000-038FFFF 57 128 / 64 0720000-073FFFF 0390000-039FFFF 58 128 / 64 0740000-075FFFF 03A0000-03AFFFF 59 128 / 64 0760000-077FFFF 03B0000-03BFFFF 60 128 / 64 0780000-079FFFF 03C0000-03CFFFF 61 128 / 64 07A0000-07BFFFF 03D0000-03DFFFF 62 128 / 64 07C0000-07DFFFF 03E0000-03EFFFF 63 128 / 64 07E0000-07FFFFF 03F0000-03FFFFF 64 128 / 64 0800000-081FFFF 0400000-040FFFF 208031-05 89 Numonyx(R) AxcellTM M29EW 128-Mbit Memory Address Table Block Address Table(1) Table 35. 90 Block Number Block Size (Kbytes / Kwords) x8 Address (HEX) x16 Address (HEX) 65 128 / 64 0820000-083FFFF 0410000-041FFFF 66 128 / 64 0840000-085FFFF 0420000-042FFFF 67 128 / 64 0860000-087FFFF 0430000-043FFFF 68 128 / 64 0880000-089FFFF 0440000-044FFFF 69 128 / 64 08A0000-08BFFFF 0450000-045FFFF 70 128 / 64 08C0000-08DFFFF 0460000-046FFFF 71 128 / 64 08E0000-08FFFFF 0470000-047FFFF 72 128 / 64 0900000-091FFFF 0480000-048FFFF 73 128 / 64 0920000-093FFFF 0490000-049FFFF 74 128 / 64 0940000-095FFFF 04A0000-04AFFFF 75 128 / 64 0960000-097FFFF 04B0000-04BFFFF 76 128 / 64 0980000-099FFFF 04C0000-04CFFFF 77 128 / 64 09A0000-09BFFFF 04D0000-04DFFFF 78 128 / 64 09C0000-09DFFFF 04E0000-04EFFFF 79 128 / 64 09E0000-09FFFFF 04F0000-04FFFFF 80 128 / 64 0A00000-0A1FFFF 0500000-050FFFF 81 128 / 64 0A20000-0A3FFFF 0510000-051FFFF 82 128 / 64 0A40000-0A5FFFF 0520000-052FFFF 83 128 / 64 0A60000-0A7FFFF 0530000-053FFFF 84 128 / 64 0A80000-0A9FFFF 0540000-054FFFF 85 128 / 64 0AA0000-0ABFFFF 0550000-055FFFF 86 128 / 64 0AC0000-0ADFFFF 0560000-056FFFF 87 128 / 64 0AE0000-0AFFFFF 0570000-057FFFF 88 128 / 64 0B00000-0B1FFFF 0580000-058FFFF 89 128 / 64 0B20000-0B3FFFF 0590000-059FFFF 90 128 / 64 0B40000-0B5FFFF 05A0000-05AFFFF 91 128 / 64 0B60000-0B7FFFF 05B0000-05BFFFF 92 128 / 64 0B80000-0B9FFFF 05C0000-05CFFFF 93 128 / 64 0BA0000-0BBFFFF 05D0000-05DFFFF 94 128 / 64 0BC0000-0BDFFFF 05E0000-05EFFFF 95 128 / 64 0BE0000-0BFFFFF 05F0000-05FFFFF 96 128 / 64 0C00000-0C1FFFF 0600000-060FFFF 97 128 / 64 0C20000-0C3FFFF 0610000-061FFFF 98 128 / 64 0C40000-0C5FFFF 0620000-062FFFF 208031-05 Numonyx(R) AxcellTM M29EW 128-Mbit Memory Address Table Block Address Table(1) Table 35. Block Number Block Size (Kbytes / Kwords) x8 Address (HEX) x16 Address (HEX) 99 128 / 64 0C60000-0C7FFFF 0630000-063FFFF 100 128 / 64 0C80000-0C9FFFF 0640000-064FFFF 101 128 / 64 0CA0000-0CBFFFF 0650000-065FFFF 102 128 / 64 0CC0000-0CDFFFF 0660000-066FFFF 103 128 / 64 0CE0000-0CFFFFF 0670000-067FFFF 104 128 / 64 0D00000-0D1FFFF 0680000-068FFFF 105 128 / 64 0D20000-0D3FFFF 0690000-069FFFF 106 128 / 64 0D40000-0D5FFFF 06A0000-06AFFFF 107 128 / 64 0D60000-0D7FFFF 06B0000-06BFFFF 108 128 / 64 0D80000-0D9FFFF 06C0000-06CFFFF 109 128 / 64 0DA0000-0DBFFFF 06D0000-06DFFFF 110 128 / 64 0DC0000-0DDFFFF 06E0000-06EFFFF 111 128 / 64 0DE0000-0DFFFFF 06F0000-06FFFFF 112 128 / 64 0E00000-0E1FFFF 0700000-070FFFF 113 128 / 64 0E20000-0E3FFFF 0710000-071FFFF 114 128 / 64 0E40000-0E5FFFF 0720000-072FFFF 115 128 / 64 0E60000-0E7FFFF 0730000-073FFFF 116 128 / 64 0E80000-0E9FFFF 0740000-074FFFF 117 128 / 64 0EA0000-0EBFFFF 0750000-075FFFF 118 128 / 64 0EC0000-0EDFFFF 0760000-076FFFF 119 128 / 64 0EE0000-0EFFFFF 0770000-077FFFF 120 128 / 64 0F00000-0F1FFFF 0780000-078FFFF 121 128 / 64 0F20000-0F3FFFF 0790000-079FFFF 122 128 / 64 0F40000-0F5FFFF 07A0000-07AFFFF 123 128 / 64 0F60000-0F7FFFF 07B0000-07BFFFF 124 128 / 64 0F80000-0F9FFFF 07C0000-07CFFFF 125 128 / 64 0FA0000-0FBFFFF 07D0000-07DFFFF 126 128 / 64 0FC0000-0FDFFFF 07E0000-07EFFFF 127 128 / 64 0FE0000-0FFFFFF 07F0000-07FFFFF 1. The 128M-bit device consists of 128 blocks, from block 0 to block 127. 208031-05 91 Numonyx(R) AxcellTM M29EW Common Flash Interface (CFI) Appendix B Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query command is issued, the memory enters Read CFI Query mode and read operations output the CFI data. Table 36, Table 37, Table 38, Table 39 and Table 40 and show the addresses (A-1, A0-A7) used to retrieve the data. Query structure overview(1) Table 36. Address Sub-section name Description x16 x8 10h 20h CFI query identification string Command set ID and algorithm data offset 1Bh 36h System interface information Device timing & voltage information 27h 4Eh Device geometry definition Flash device layout 40h 80h Primary algorithm-specific extended query table Additional information specific to the primary algorithm (optional) 1. Query data are always presented on the lowest order data outputs. CFI query identification string(1) Table 37. Address Data x16 x8 10h 20h 0051h 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0040h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h 19h 32h 0000h 1Ah 34h 0000h Description `Q' Query Unique ASCII String `QRY' `R' `Y' Primary algorithm command set and control interface ID code 16 bit ID code defining a specific algorithm AMD compatible Address for primary algorithm extended query table (see Table 40) P = 40h Alternate vendor command set and control interface ID code second vendor - specified algorithm supported NA Address for alternate algorithm extended query table NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'. 92 Value 208031-05 Numonyx(R) AxcellTM M29EW Common Flash Interface (CFI) CFI query system interface information(1) Table 38. Address Data Description Value x16 x8 1Bh 36h 0027h VCC logic supply minimum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 2.7 V 1Ch 38h 0036h VCC logic supply maximum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 3.6 V 00B5h VPPH [programming] supply minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 11.5 V 12.5 V 16 s 1Dh 3Ah 1Eh 3Ch 00C5h VPPH [programming] supply maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 10 mV 1Fh 3Eh 0004h Typical time-out for single byte/word program = 2n s Typical time-out for maximum size buffer program = 2n 20h 40h 0009h 21h 42h 0009h Typical time-out for individual block erase = 2n ms 22h 44h 000Fh 0010h 0011h Typical time-out for full Chip Erase = 2n ms 23h 46h 0004h Maximum time-out for byte/word program = 2n times typical time-out 256 s 24h 48h 0002h Maximum time-out for buffer program = 2n times typical time-out 2048 s 25h 4Ah 0003h Maximum time-out per individual block erase = 2n times typical time-out 0002h Maximum time-out for Chip Erase = 2n times typical time-out 26h 4Ch s 512 s 0.5 s 32M 33 s 64M 66 s 128M 131 s 4s 32M 131 s 64M 262 s 128M 524 s 1. The values given in the above table are valid for all packages. Table 39. Device geometry definition Address Data x16 x8 27h 4Eh 0016h / 0017h / 0018h 28h 29h 50h 52h 0002h 0000h Description Device size = 2n in number of bytes Flash device interface code description 208031-05 Value 4 Mbytes 8 Mbytes 16 Mbytes x8, x16 Async. 93 Numonyx(R) AxcellTM M29EW Common Flash Interface (CFI) Table 39. Device geometry definition Address Data x16 x8 2Ah 2Bh 54h 56h Description 0008h(1) 0000h Value Maximum number of bytes in multiple-byte program or page= 2n 256 See below table Number of Erase block regions within device. It specifies the number of regions containing contiguous Erase blocks of the same size. 01h = uniform device 02h = boot device - See below table Erase block region 1 information bits 0-15 = y, y+1 = Number of Erase blocks of identical size. bits 16-31 = z, Block size in region1 is zx256 bytes. - Erase block region 2 information bits 0-15 = y, y+1 = Number of Erase blocks of identical size. bits 16-31 = z, Block size in region 2 is zx256 bytes. - 2Ch 58h 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 31h 32h 33h 34h 62h 64h 66h 68h See below table 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase block region 3 information 0 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase block region 4 information 0 1. The value at 2Ah in CFI region is purposely set to 08h (256 bytes) due to compatibility reasons. The maximum 256-word program buffer can be used to optimize system program performance. 32-Mbit 64-Mbit 128-Mbit Address Top Bottom Uniform Top Bottom Uniform Uniform 2Ch 02h 02h 01h 02h 02h 01h 01h 2Dh 07h 07h 3Fh 07h 07h 7Fh 7Fh 2Eh 00h 00h 00h 00h 00h 00h 00h 2Fh 20h 20h 00h 20h 20h 00h 00h 30h 00h 00h 01h 00h 00h 01h 02h 31h 3Eh 3Eh 00h 7Eh 7Eh 00h 00h 32h 00h 00h 00h 00h 00h 00h 00h 33h 00h 00h 00h 00h 00h 00h 00h 34h 01h 01h 00h 01h 01h 00h 00h 94 208031-05 Numonyx(R) AxcellTM M29EW Table 40. Common Flash Interface (CFI) Primary algorithm-specific extended query table (1) Address Data Description Value x16 x8 40h 80h 0050h 41h 82h 0052h 42h 84h 0049h 43h 86h 0031h Major version number, ASCII `1' 44h 88h 0033h Minor version number, ASCII `3' 45h 8Ah 0018h Address sensitive unlock (bits 1 to 0) 00 = required, 01= not required Silicon revision number (bits 7 to 2) 46h 8Ch 0002h Erase Suspend 00 = not supported, 01 = Read only, 02 = read and write 2 47h 8Eh 0001h Block protection 00 = not supported, x = number of blocks per group 1 48h 90h 0000h Temporary block unprotect 00 = not supported, 01 = supported 49h 92h 0008h Block protect / unprotect 08 = M29EWH/M29EWL 4Ah 94h 0000h Simultaneous operations: not supported 4Bh 96h 0000h Burst mode, 00 = not supported, 01 = supported 4Ch 98h 0002h Page mode, 00 = not supported, 01 = 8-word page 02 = 8-word page, 03 = 16-word page 8-word page 4Dh 9Ah 00B5h VPPH supply minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 11.5 V 4Eh 9Ch 00C5h VPPH supply maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 12.5 V `P' Primary algorithm extended query table unique ASCII string "PRI" `R' `I' 4Fh 9Eh 00xxh Top/bottom boot block flag xx = 02h: Bottom boot device, HW protection for bottom two blocks xx = 03h: Top boot device, HW protection for top two blocks xx = 04h: Uniform device, HW protection for lowest block xx = 05h: Uniform device, HW protection for highest block 50h A0h 0001h Program suspend, 00 = not supported, 01 = supported Required Not supported 8 NA Not supported device type (bottom boot, top boot, uniform) Supported 1. The values given in the above table are valid for all packages. 208031-05 95 Numonyx(R) AxcellTM M29EW Extended Memory Block Appendix C Extended Memory Block The M29EW has an extra block, the Extended Memory Block, that can be accessed using a dedicated command. This Extended Memory Block is 128 words in x16 mode and 256 bytes in x8 mode. It is used as a security block (to provide a permanent security identification number) or to store additional information. The device can be shipped either with the Extended Memory Block pre-locked by Numonyx, or unlocked. If the Extended Memory Block is not pre-locked by Numonyx, it can be customer-lockable. Its status is indicated by bit DQ7 of Extended Memory Block Verify Indicator in Auto Select mode. This bit is permanently set to either `1' or `0' at the Numonyx factory and cannot be changed. When set to `1', it indicates that the device is pre-locked by Numonyx and the Extended Memory Block is protected. When set to `0', it indicates that the device is customer-lockable. Bit DQ7 being permanently locked to either `1' or `0' is another security feature which ensures that a customer-lockable device cannot be used instead of a Numonyx pre-locked one. Bit DQ7 is the most significant bit in the Extended Memory Block Verify Indicator. It can be read in Auto Select mode using either the Programmer (see Table 7 and Table 8) or the Insystem method (see Table 9 and Table 10). The Extended Memory Block can only be accessed when the device is in Extended Memory Block mode. For details of how the Extended Memory Block mode is entered and exited, refer to the Section 6.3.1: Enter Extended Memory Block command and Section 6.3.2: Exit Extended Memory Block command, and to Table 13 and Table 9. C.1 Numonyx pre-locked Extended Memory Block If devices of which the Extended Memory Block is pre-locked upon customer request, the 128bits security identification number is written to the Extended Memory Block address space (see Table 41: Extended Memory Block address and data) in Numonyx factory. The contents in the Extended Memory Block cannot be changed any more. 96 208031-05 Numonyx(R) AxcellTM M29EW C.2 Extended Memory Block Customer-lockable Extended Memory Block A device where the Extended Memory Block is customer-lockable is delivered with the DQ7 bit set to `0' and the Extended Memory Block unprotected. It is up to the customer to program and protect the Extended Memory Block but care must be taken because the protection of the Extended Memory Block is not reversible. If the device has not been shipped with the Extended Memory Block pre-protected, the block can be protected by setting the Extended Memory Block Protection bit, DQ0, to `0'. However, this bit can only be programmed once; and once it is protected the Extended Memory Block cannot be unprotected. Once the Extended Memory Block is programmed, the Exit Extended Memory Block command must be issued to exit the Extended Memory Block mode and return the device to Read mode. Table 41. Extended Memory Block address and data Address(1) Data x8 x16 Numonyx pre-locked 000000h-00000Fh 000000h-000007h Secure identification number 000010h-0000FFh 000008h-00007Fh Protected and unavailable Customer-lockable Determined by customers (default) Secure identification number Determined by customers 1. 208031-05 97 Numonyx(R) AxcellTM M29EW Revision History Appendix D Table 42. Document revision history Date Version Jun 2009 01 Initial release 02 Added 48L TSOP and 48B BGA connection information. Added 64M and 32M memory map. Added 48L TSOP and 48B BGA package outline information. Updated program performance and suspend latency. Order information updated with device feature digit. Updated part number information in valid combination table. CFI updated to cover 64-Mbit and 32-Mbit device related information. Read electronic signature information updated to cover 64-Mbit and 32-Mbit device. Block protection information updated to cover 64-Mbit and 32-Mbit device. Updated the Random Read AC waveforms about BYTE# pin in Section 9: DC and AC Parameters. Added a note to state fast program (double program, quadruple program and octuple program) can only work with VPPL in Section 6.2: Fast Program commands on page 37. Updated typical time-out and maximum time-out for buffer program at CFI table. Updated the description of VPP/WP# pin in Section 2.8: VPP/Write Protect (VPP/WP#) on page 16. Added JESD47E compliant. Apr 2010 98 Revision History Changes 208031-05 Numonyx(R) AxcellTM M29EW Revision History Date Version May 2010 03 Updated the Random Read AC waveforms about BYTE# pin in Section 9: DC and AC Parameters. Put a link for product part numbers in Section 12: Ordering Information. 04 Aligned with device about the commands for double byte/quadruple byte/octuble byte program at Table 11: Fast Program commands, 8-bit mode on page 46 and double word/quadruple word program at Table 12: Fast Program commands, 16-bit mode on page 47. Corrected the CFI value for address 2Fh (x16) for 64-Mbit/32-Mbit Top/Bottom devices. Corrected the CFI value for address 22h (x16) for 32-Mbit devices. Removed the invalid automatic standby mode from front page and Section 3: Bus Operations on page 19. Removed the statement about unlock bypass fast program at note of Section 6.2: Fast Program commands on page 37 since it's not valid. Added JEDEC standard lead width for TSOP56 package at Table 29: TSOP56 - 56 lead thin small-outline package, 14 x 20 mm, package mechanical data on page 82 05 For read ID and read protection status, align with device about higher address pins input status at Table 5, Table 6, Table 7 and Table 8. Corrected the glitch filter from 5ns to 3ns Removed the invalid statement about applying VID to A9 to enter Auto Select mode at Section 7.1.3: Extended Memory Block Protection bit (DQ0) Add Blank Check related information Jan 2011 Apr 2011 Changes 208031-05 99 Numonyx(R) AxcellTM M29EW Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx Axcell is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2009, Numonyx, B.V., All Rights Reserved. 100