1
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
1
7
tab
D²-PAK7pin
Drain
Pin 4, tab
Gate
Pin 1
Source
Pin 2,3,5,6,7
MOSFET
OptiMOSª5Power-Transistor,100V
Features
•Idealforhighfrequencyswitchingandsync.rec.
•ExcellentgatechargexRDS(on)product(FOM)
•Verylowon-resistanceRDS(on)
•N-channel,normallevel
•100%avalanchetested
•Pb-freeplating;RoHScompliant
•QualifiedaccordingtoJEDEC1)fortargetapplications
•Halogen-freeaccordingtoIEC61249-2-21
Table1KeyPerformanceParameters
Parameter Value Unit
VDS 100 V
RDS(on),max 3.2 mΩ
ID166 A
Qoss 98 nC
QG(0V..10V) 76 nC
Type/OrderingCode Package Marking RelatedLinks
IPB032N10N5 PG-TO263-7 032N10N5 -
1) J-STD20 and JESD22
2
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
1Maximumratings
atTA=25°C,unlessotherwisespecified
Table2Maximumratings
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Continuous drain current ID-
-
-
-
166
118 ATC=25°C
TC=100°C
Pulsed drain current1) ID,pulse - - 664 A TC=25°C
Avalanche energy, single pulse EAS - - 233 mJ ID=100A,RGS=25Ω
Gate source voltage VGS -20 - 20 V -
Power dissipation Ptot - - 187 W TC=25°C
Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category;
DIN IEC 68-1: 55/175/56
2Thermalcharacteristics
Table3Thermalcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Thermal resistance, junction - case RthJC - 0.5 0.8 K/W -
Thermal resistance, junction - ambient,
minimal footprint RthJA - - 62 K/W -
Thermal resistance, junction - ambient,
6 cm2 cooling area2) RthJA - - 40 K/W -
Soldering temperature and
reflow soldering is allowed Tsold - - 260 °C reflow MSL1
1) see Diagram 3
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.
PCB is vertical in still air.
4
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
3Electricalcharacteristics
Table4Staticcharacteristics
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Drain-source breakdown voltage V(BR)DSS 100 - - V VGS=0V,ID=1mA
Gate threshold voltage VGS(th) 2.2 3.0 3.8 V VDS=VGS,ID=125µA
Zero gate voltage drain current IDSS -
-
0.1
10
1
100 µA VDS=100V,VGS=0V,Tj=25°C
VDS=100V,VGS=0V,Tj=125°C
Gate-source leakage current IGSS - 1 100 nA VGS=20V,VDS=0V
Drain-source on-state resistance RDS(on) -
-
2.8
3.4
3.2
4.2 mΩVGS=10V,ID=83A
VGS=6V,ID=42A
Gate resistance1) RG- 1.3 2 Ω-
Transconductance gfs 84 168 - S |VDS|>2|ID|RDS(on)max,ID=83A
Table5Dynamiccharacteristics1)
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Input capacitance Ciss - 5360 6970 pF VGS=0V,VDS=50V,f=1MHz
Output capacitance Coss - 829 1078 pF VGS=0V,VDS=50V,f=1MHz
Reverse transfer capacitance Crss - 37 65 pF VGS=0V,VDS=50V,f=1MHz
Turn-on delay time td(on) - 16.2 - ns VDD=50V,VGS=10V,ID=83A,
RG,ext=1.6Ω
Rise time tr- 9.7 - ns VDD=50V,VGS=10V,ID=83A,
RG,ext=1.6Ω
Turn-off delay time td(off) - 35 - ns VDD=50V,VGS=10V,ID=83A,
RG,ext=1.6Ω
Fall time tf- 9.8 - ns VDD=50V,VGS=10V,ID=83A,
RG,ext=1.6Ω
Table6Gatechargecharacteristics2)
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Gate to source charge Qgs - 25 - nC VDD=50V,ID=83A,VGS=0to10V
Gate to drain charge1) Qgd - 16 23 nC VDD=50V,ID=83A,VGS=0to10V
Switching charge Qsw - 25 - nC VDD=50V,ID=83A,VGS=0to10V
Gate charge total1) Qg- 76 95 nC VDD=50V,ID=83A,VGS=0to10V
Gate plateau voltage Vplateau - 4.7 - V VDD=50V,ID=83A,VGS=0to10V
Output charge1) Qoss - 98 130 nC VDD=50V,VGS=0V
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
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OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
Table7Reversediode
Values
Min. Typ. Max.
Parameter Symbol Unit Note/TestCondition
Diode continous forward current IS- - 156 A TC=25°C
Diode pulse current IS,pulse - - 624 A TC=25°C
Diode forward voltage VSD - 0.9 1.2 V VGS=0V,IF=83A,Tj=25°C
Reverse recovery time1) trr - 62 124 ns VR=50V,IF=83,diF/dt=100A/µs
Reverse recovery charge1) Qrr - 103 206 nC VR=50V,IF=83,diF/dt=100A/µs
1) Defined by design. Not subject to production test.
6
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
4Electricalcharacteristicsdiagrams
Diagram1:Powerdissipation
TC[°C]
Ptot[W]
0 25 50 75 100 125 150 175 200
0
40
80
120
160
200
Ptot=f(TC)
Diagram2:Draincurrent
TC[°C]
ID[A]
0 50 100 150 200
0
20
40
60
80
100
120
140
160
180
200
ID=f(TC);VGS10V
Diagram3:Safeoperatingarea
VDS[V]
ID[A]
10-1 100101102103
10-1
100
101
102
103
1 µs
10 µs
100 µs
1 ms
10 ms
DC
ID=f(VDS);TC=25°C;D=0;parameter:tp
Diagram4:Max.transientthermalimpedance
tp[s]
ZthJC[K/W]
10-5 10-4 10-3 10-2 10-1 100
10-2
10-1
100
0.5
0.2
0.1
0.05
0.02
0.01
single pulse
ZthJC=f(tp);parameter:D=tp/T
7
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
Diagram5:Typ.outputcharacteristics
VDS[V]
ID[A]
012345
0
100
200
300
400
500
600
700
8 V
10 V
6 V
5.5 V
5 V
4.5 V
ID=f(VDS);Tj=25°C;parameter:VGS
Diagram6:Typ.drain-sourceonresistance
ID[A]
RDS(on)[mΩ]
0 100 200 300 400 500 600 700
1
2
3
4
5
6
5 V 5.5 V
6 V
8 V
10 V
RDS(on)=f(ID);Tj=25°C;parameter:VGS
Diagram7:Typ.transfercharacteristics
VGS[V]
ID[A]
02468
0
50
100
150
200
250
300
350
400
450
500
175 °C 25 °C
ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj
Diagram8:Typ.forwardtransconductance
ID[A]
gfs[S]
0 40 80 120 160
0
40
80
120
160
200
240
gfs=f(ID);Tj=25°C
8
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
Diagram9:Drain-sourceon-stateresistance
Tj[°C]
RDS(on)[mΩ]
-60 -20 20 60 100 140 180
0
1
2
3
4
5
6
7
max
typ
RDS(on)=f(Tj);ID=83A;VGS=10V
Diagram10:Typ.gatethresholdvoltage
Tj[°C]
VGS(th)[V]
-60 -20 20 60 100 140 180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1250 µA
125 µA
VGS(th)=f(Tj);VGS=VDS;parameter:ID
Diagram11:Typ.capacitances
VDS[V]
C[pF]
0 20 40 60 80
101
102
103
104
105
Ciss
Coss
Crss
C=f(VDS);VGS=0V;f=1MHz
Diagram12:Forwardcharacteristicsofreversediode
VSD[V]
IF[A]
0.0 0.5 1.0 1.5 2.0
100
101
102
103
25 °C
175 °C
25 °C, max
175 °C, max
IF=f(VSD);parameter:Tj
9
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
Diagram13:Avalanchecharacteristics
tAV[µs]
IAS[A]
100101102103
100
101
102
103
25 °C
100 °C
150 °C
IAS=f(tAV);RGS=25Ω;parameter:Tj(start)
Diagram14:Typ.gatecharge
Qgate[nC]
VGS[V]
0 10 20 30 40 50 60 70 80
0
2
4
6
8
10
20 V
50 V
80 V
VGS=f(Qgate),ID=83Apulsed;parameter:VDD
Diagram15:Drain-sourcebreakdownvoltage
Tj[°C]
VBR(DSS)[V]
-60 -20 20 60 100 140 180
95
100
105
110
VBR(DSS)=f(Tj);ID=1mA
Gate charge waveforms
10
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
5PackageOutlines
Figure1OutlinePG-TO263-7,dimensionsinmm/inches
11
OptiMOSª5Power-Transistor,100V
IPB032N10N5
Rev.2.0,2016-12-12Final Data Sheet
RevisionHistory
IPB032N10N5
Revision:2016-12-12,Rev.2.0
Previous Revision
Revision Date Subjects (major changes since last revision)
2.0 2016-12-12 Release of final version
TrademarksofInfineonTechnologiesAG
AURIX™,C166™,CanPAK™,CIPOS™,CoolGaN™,CoolMOS™,CoolSET™,CoolSiC™,CORECONTROL™,CROSSAVE™,DAVE™,DI-POL™,DrBlade™,
EasyPIM™,EconoBRIDGE™,EconoDUAL™,EconoPACK™,EconoPIM™,EiceDRIVER™,eupec™,FCOS™,HITFET™,HybridPACK™,Infineon™,
ISOFACE™,IsoPACK™,i-Wafer™,MIPAQ™,ModSTACK™,my-d™,NovalithIC™,OmniTune™,OPTIGA™,OptiMOS™,ORIGA™,POWERCODE™,
PRIMARION™,PrimePACK™,PrimeSTACK™,PROFET™,PRO-SIL™,RASIC™,REAL3™,ReverSave™,SatRIC™,SIEGET™,SIPMOS™,SmartLEWIS™,
SOLIDFLASH™,SPOC™,TEMPFET™,thinQ™,TRENCHSTOP™,TriCore™.
TrademarksupdatedAugust2015
OtherTrademarks
Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners.
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Publishedby
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©2016InfineonTechnologiesAG
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(“Beschaffenheitsgarantie”).
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