X9259 (R) Single Supply/Low Power/256-Tap/2-Wire bus Data Sheet April 13, 2007 Quad Digitally-Controlled (XDCPTM) Potentiometers FN8169.5 Features * Four Separate Potentiometers in One Package The X9259 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. * 256 Resistor Taps-0.4% Resolution * 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. * Wiper Resistance: 100 typical @ VCC = 5V * 4 Non-volatile Data Registers for Each Potentiometer * Non-volatile Storage of Multiple Wiper Positions * Standby Current <5A Max * VCC: 2.7V to 5.5V Operation * 50k, 100k versions of Total Resistance * Endurance: 100,000 Data Changes per Bit per Register The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. * 100 year Data Retention * Single Supply Version of X9258 * 24 Ld SOIC, 24 Ld TSSOP * Low Power CMOS * Pb-Free Plus Anneal Available (RoHS Compliant) Functional Diagram A3 A2 2-Wire Interface A1 A0 RH1 RH0 VCC WCR0 DR00 DR01 DR02 DR03 POWER UP, INTERFACE CONTROL AND STATUS DCP0 WCR1 DR10 DR11 DR12 DR13 DCP1 RH3 RH2 WCR2 DR20 DR21 DR22 DR23 DCP2 WCR3 DR30 DR31 DR32 DR33 DCP3 SDA SCL VSS WP 1 RW0 RL0 RW1 RL1 RW2 RL2 RW3 RL3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9259 Ordering Information PART NUMBER VCC LIMITS PART MARKING (V) 5 10% RTOTAL (k) TEMPERATURE RANGE (C) 100 0 to +70 24 Ld SOIC M24.3 24 Ld SOIC (Pb-free) M24.3 PACKAGE PKG. DWG. # X9259TS24 X9259TS X9259TS24Z (Note) X9259TS Z 0 to +70 X9259TS24I X9259TS I -40 to +85 24 Ld SOIC M24.3 X9259TS24IZ (Note) X9259TS ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259TV24I X9259TV I -40 to +85 24 Ld TSSOP MDP0044 X9259TV24IZ (Note) X9259TV ZI -40 to +85 24 Ld TSSOP (Pb-free) MDP0044 X9259US24* X9259US 0 to +70 24 Ld SOIC M24.3 X9259US24Z* (Note) X9259US Z 0 to +70 24 Ld SOIC (Pb-free) M24.3 X9259US24I X9259US I -40 to +85 24 Ld SOIC M24.3 X9259US24IZ (Note) X9259US ZI -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259UV24I* X9259UV I -40 to +85 24 Ld TSSOP MDP0044 X9259UV24IZ* (Note) X9259UV Z I -40 to +85 24 Ld TSSOP (Pb-free) MDP0044 X9259TS24-2.7* X9259TS F 0 to +70 24 Ld SOIC M24.3 X9259TS24Z-2.7* (Note) X9259TS ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3 X9259TS24I-2.7 X9259TS G -40 to +85 24 Ld SOIC M24.3 X9259TS24IZ-2.7 (Note) X9259TS ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259TV24-2.7 X9259TV F 0 to +70 24 Ld TSSOP MDP0044 X9259TV24Z-2.7 (Note) X9259TV ZF 0 to +70 24 Ld TSSOP (Pb-free) MDP0044 X9259US24-2.7 X9259US F 0 to +70 24 Ld SOIC M24.3 X9259US24Z-2.7 (Note) X9259US ZF 0 to +70 24 Ld SOIC (Pb-free) M24.3 X9259US24I-2.7 X9259US G -40 to +85 24 Ld SOIC M24.3 X9259US24IZ-2.7 (Note) X9259US ZG -40 to +85 24 Ld SOIC (Pb-free) M24.3 X9259UV24-2.7* X9259UV F 0 to +70 24 Ld TSSOP MDP0044 X9259UV24Z-2.7 (Note) X9259UV ZF 0 to +70 24 Ld TSSOP (Pb-free) MDP0044 X9259UV24I-2.7* X9259UV G -40 to +85 24 Ld TSSOP MDP0044 X9259UV24IZ-2.7* (Note) X9259UV ZG -40 to +85 24 Ld TSSOP (Pb-free) MDP0044 50 2.7 to 5.5 100 50 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. 2 FN8169.5 April 13, 2007 X9259 Circuit Level Applications Pin Configuration * Vary the gain of a voltage amplifier SOIC/TSSOP * Provide programmable dc reference voltages for comparators and detectors DNC 1 24 A3 A0 2 23 SCL * Control the volume in audio circuits RW3 3 22 RL2 * Trim out the offset voltage error in a voltage amplifier circuit RH3 4 21 RH2 RL3 5 20 RW2 19 NC 18 VSS * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits NC 6 VCC 7 RL0 X9259 8 17 RW1 RH0 9 16 RH1 RW0 10 15 RL1 A2 11 14 A1 WP 12 13 SDA * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits Pin Assignments PIN (SOIC/ TSSOP) SYMBOL FUNCTION 2 A0 Device Address for 2-Wire bus. (See Note 1) 3 RW3 Wiper Terminal of DCP3 4 RH3 High Terminal of DCP3 * Set and regulate the DC biasing point in an RF power amplifier in wireless systems 5 RL3 Low Terminal of DCP3 6 NC1 Must be left unconnected * Control the gain in audio and home entertainment systems 7 VCC System Supply Voltage * Provide the variable DC bias for tuners in RF wireless systems 8 RL0 Low Terminal of DCP0 9 RH0 High Terminal of DCP0 * Set the operating points in temperature control systems 10 RW0 Wiper Terminal of DCP0 11 A2 Device Address for 2-Wire bus. (See Note 1) 12 WP Hardware Write Protect - Active Low 13 SDA Serial Data Input/Output for 2-Wire bus. 14 A1 Device Address for 2-Wire bus. (See Note 1) 15 RL1 Low Terminal of DCP1 16 RH1 High Terminal of DCP1 17 RW1 Wiper Terminal of DCP1 18 VSS System Ground 20 RW2 Wiper Terminal of DCP2 21 RH2 High Terminal of DCP2 22 RL2 Low Terminal of DCP2 23 SCL Serial Clock for 2-Wire bus. 24 A3 Device Address for 2-Wire bus. (See Note 1) 6, 19 NC No Connect 1 DNC System Level Applications * Adjust the contrast in LCD displays * Control the power level of LED transmitters in communication systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems Do Not Connect Note 1: A0 through A3 Device address pins must be tied to a logic level. 3 FN8169.5 April 13, 2007 X9259 Pin Descriptions Potentiometer Pins Bus Interface Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RH and RL such that RH0 and RL0 are the terminals of DCP0 and so on. SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RW such that RW0 is the terminal of DCP0 and so on. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. Bias Supply Pins SERIAL CLOCK (SCL) SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9259. The VCC pin is the system supply voltage. The VSS pin is the system ground. DEVICE ADDRESS (A3 THROUGH A0) Other Pins The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9259. A maximum of 16 devices may occupy the 2-Wire serial bus. Device pins A3 through A0 must be tied to a logic level which specifies the external address of the device, see Figures 3, 4, and 5. NO CONNECT No connect pins should be left open. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers. One of Four Potentiometers RH #: 0, 1, 2, or 3 SERIAL BUS INPUT SERIAL DATA PATH FROM INTERFACE CIRCUITRY DR#0 DR#1 8 DR#2 IF WCR = 00[H] then RW is closest to RL IF WCR = FF[H] then RW is closest to RH 8 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR#) DR#3 COUNTER --DECODE DCP CORE RW INC/DEC LOGIC UP/DN MODIFIED SCK UP/DN CLK RL FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM 4 FN8169.5 April 13, 2007 X9259 Principles of Operation The X9259 is an integrated circuit incorporating four DCPs and their associated registers and counters, and the serial interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR). written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (see Instruction section for more details). Finally, it is loaded with the contents of its data register zero (DR#0) upon power-up. (See Figure 1) The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9259 is powered-down. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR# (See Design Considerations Section). Data Registers (DR) Power Up and Down Recommendations There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate specification is always in effect. Wiper Counter Register (WCR) The X9259 contains four Wiper Counter Registers, one for each potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be Each of the four DCPs has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a non-volatile operation and takes a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit [7:0] are used to store one of the 256 wiper positions (0 ~ 255). TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile). WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 (MSB) WCR0 (LSB) TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]: Used to store wiper positions or data (Non-volatile). Bit 7 Bit 6 Bit 5 (MSB) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 5 FN8169.5 April 13, 2007 X9259 Serial Interface Acknowledge The X9259 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provide the clock for both transmit and receive operations. Therefore, the X9259 operates as a slave device in all applications. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. See Figure 3. All 2-wire interface operations must begin with a START, followed by an Identification Byte, that selects the X9259. All communication over the 2-wire interface is conducted by sending the MSB of each byte of data first. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions. See Figure 2. On power up of the X9259 the SDA pin is in the input mode. START Condition All commands to the X9259 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9259 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met. See Figure 2. The X9259 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Instruction Byte. The X9259 also responds with an ACK after receiving a Data Byte after a Write Instruction. A valid Identification Byte contains the Device Type Identifier 0101, as the four MSBs, and the Device Address bits matching the logic states of pins A3, A2, A1, and A0, as the four LSBs. See Figure 4. In the Read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. During the internal non-volatile Write operation, the X9259 ignores the inputs at SDA and SCL, and does not issue an ACK after Identification bytes. STOP Condition All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 2. The STOP condition is also used to place the device into the Standby Power mode after a Read sequence. A STOP condition can only be issued after the transmitting device has released the bus. 6 FN8169.5 April 13, 2007 X9259 SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START ACK FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER Identification Byte Data Register Selection The first byte sent to the X9259 from the host is called the Identification Byte. The most significant four bits are a Device Type Identifier, ID[3:0] bits, which must be 0101. Refer to Table 3. Only the device which Slave Address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I) The next byte sent to the X9259 contains the instruction and register pointer information. The four most significant bits are used provide the instruction opcode I [3:0]. The RB and RA bits point to one of the four data registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs. The format is shown in Table 4. 7 REGISTER RB RA DR#0 0 0 DR#1 0 1 DR#2 1 0 DR#3 1 1 #: 0, 1, 2, or 3 The least significant four bits of the Identification Byte are the Slave Address bits, AD[3:0]. To access the X9259, these four bits must match the logic values of pins A3, A2, A1, and A0. FN8169.5 April 13, 2007 X9259 TABLE 3. IDENTIFICATION BYTE FORMAT Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 A0 Logic value of pins A3, A2, A1, and A0 (MSB) (LSB) TABLE 4. INSTRUCTION BYTE FORMAT Instruction Opcode I3 I2 DCP Selection (WCR Selection) Register Selection I1 I0 RB RA P1 (MSB) P0 (LSB) TABLE 5. INSTRUCTION SET INSTRUCTION SET INSTRUCTION I3 I2 I1 I0 RB RA P1 P0 Read Wiper Counter Register 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by P1 - P0 and RB - RA Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by P1 - P0 and RB - RA XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by P1 - P0 and RB - RA to its associated Wiper Counter Register XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register pointed to by RB - RA Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to by RB - RA of all four pots to their respective Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB - RA of all four DCPs Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 1/0 1/0 Note: OPERATION Enable Increment/decrement of the Control Latch pointed to by P1 - P0 1/0 = data is one or zero 8 FN8169.5 April 13, 2007 X9259 Instructions or directly between the host and the Wiper Counter Register. These instructions are: Four of the nine instructions are three bytes in length. These instructions are: * XFR Data Register to Wiper Counter Register - This transfers the contents of one specified Data Register to the associated Wiper Counter Register. * Read Wiper Counter Register - read the current wiper position of the selected potentiometer, * XFR Wiper Counter Register to Data Register - This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. * Write Wiper Counter Register - change current wiper position of the selected potentiometer, * Read Data Register - read the contents of the selected Data Register; * Global XFR Data Register to Wiper Counter Register - This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. * Write Data Register - write a new value to the selected Data Register. * Global XFR Wiper Counter Register to Data Register - This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. The basic sequence of the three byte instructions is illustrated in Figure 5. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action is delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometer's WCR, and one of its associated registers, DRs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Increment/Decrement Command The final command is Increment/Decrement (Figure 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9259 has responded with an Acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper moves one wiper position towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper moves one resistor wiper position towards the RL terminal. Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9259; either between the host and one of the data registers See Instruction format for more details. SCL SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A External R Device ID Address T A I3 C K I2 I1 I0 Instruction Opcode RB RA P1 P0 A C K Register DCP/WCR Address Address S T O P FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE SCL SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 T A Device ID R T A2 A0 A I3 C K External Address A1 I2 I1 I0 Instruction Opcode RB RA P1 P0 A C K Register Pot/WCR Address Address D7 D6 D5 D4 D3 D2 D1 D0 Data for WCR[7:0] or DR[7:0] A C K S T O P FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE 2-WIRE INTERFACE 9 FN8169.5 April 13, 2007 X9259 SCL 0 SDA S T A R T 1 0 1 ID3 ID2 ID1 ID0 A3 A2 A1 A0 External Address Device ID A C K I3 I2 I1 Instruction Opcode I0 RB RA P1 P0 A C Register Pot/WCR K Address Address I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE 2-WIRE INTERFACE INC/DEC CMD Issued tWRID SCL SDA Voltage Out RW FIGURE 7. INCREMENT/DECREMENT TIMING SPEC 10 FN8169.5 April 13, 2007 X9259 Instruction Format Read Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 0 1 0 0 P1 P0 S A C K Wiper Position (Sent by X9259 on SDA) M W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P S A C K Wiper Position (Sent by Master on SDA) S W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P Write Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 0 0 0 P1 P0 Read Data Register (DR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 1 RB RA P1 P0 S A C K Wiper Position (Sent by X9259 on SDA) M W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 1 0 0 RB RA P1 P0 K S A C K Wiper Position (Sent by Master on SDA) S W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P HIGH-VOLTAGE WRITE CYCLE Write Data Register (DR) Global XFR Data Register (DR) to Wiper Counter Register (WCR) S T A R T Device Type Identifier 0 1 Notes: (1) (2) (3) (4) (5) 0 Device Addresses Instruction DR/WCR S Opcode Addresses A C 1 A3 A2 A1 A0 K 0 0 0 1 RB RA 0 0 S A C K S T O P "MACK"/"SACK": stands for the acknowledge sent by the Master/Slave. "A3 ~ A0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high). 11 FN8169.5 April 13, 2007 X9259 Global XFR Wiper Counter Register (WCR) to Data Register (DR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 0 0 0 RB RA 0 0 K S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Wiper Counter Register (WCR) to Data Register (DR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 1 1 0 RB RA P1 P0 S A C K S T O P S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 1 0 1 RB RA P1 P0 Increment/Decrement Wiper Counter Register (WCR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Notes: (1) (2) (3) (4) (5) Instruction DR/WCR S Opcode Addresses A C K 0 0 1 0 0 0 P1 P0 Increment/Decrement S (Sent by Master on SDA) A C K I/D I/D . . . . I/D I/D S T O P "MACK"/"SACK": stands for the acknowledge sent by the Master/Slave. "A3 ~ A0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high). 12 FN8169.5 April 13, 2007 X9259 Absolute Maximum Ratings Recommended Operating Conditions Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on SCL, SDA, any address input, VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V V = | (VH-VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300C IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0C to +70C Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC) (Note 4) Limits X9259. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10% X9259-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper current ...........................................................................3mA Power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Analog Specifications Over recommended industrial (2.7V) operating conditions unless otherwise stated. LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RTOTAL End to End Resistance T version 100 k RTOTAL End to End Resistance U version 50 k End to End Resistance Tolerance RW Wiper Resistance IW = IW = VTERM V(VCC) RTOTAL V(VCC) RTOTAL Voltage on any RH or RL Pin VSS = 0V Noise (Note 6) Ref: 1V % 300 220 VCC V @ VCC = 3V @ VCC = 5V VSS Resolution CH/CL/CW 20 Absolute Linearity (Note 1) Rw(n)(actual) - Rw(n)(expected) (Note 5) Relative Linearity (Note 2) Rw(n + 1) - [Rw(n) + MI] (Note 5) -120 dB/Hz 0.4 % -1 +1 MI (Note 3) -0.6 +0.6 MI (Note 3) Temperature Coefficient of RTOTAL (Note 6) 300 ppm/C Ratiometric Temp. Coefficient (Note 6) 20 ppm/C 10/10/25 pF Potentiometer Capacitances (Note 6) See Macro model NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT / 255 or (RH - RL) / 255, single pot 4. During power up VCC > VH, VL, and VW. 5. n = 0, 1, 2, ...,255; m =0, 1, 2, ..., 254. 13 FN8169.5 April 13, 2007 X9259 DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ICC1 VCC supply current (active) fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) 3 mA ICC2 VCC supply current (non-volatile write) fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Non-volatile Write State only) 5 mA ISB VCC current (standby) VCC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) 5 A ILI Input leakage current VIN = VSS to VCC 10 A VOUT = VSS to VCC 10 A ILO Output leakage current VIH Input HIGH voltage VCC x 0.7 V VIL Input LOW voltage VOL Output LOW voltage IOL = 3mA VCC x 0.3 V 0.4 V VOH Output HIGH voltage IOH = -1mA, VCC +3V VCC - 0.8 V VOH Output HIGH voltage IOH = -0.4mA, VCC +3V VCC - 0.4 V Endurance and Data Retention PARAMETER MIN UNITS Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Capacitance SYMBOL TEST MAX UNITS TEST CONDITIONS CIN/OUT (Note 6) Input / Output capacitance (SDA) 8 pF VOUT = 0V Input capacitance (SCL, WP, A2, A1 and A0) 6 pF VIN = 0V CIN (Note 6) Power-up Timing SYMBOL tr VCC (Note 6) PARAMETER MIN VCC Power-up rate 0.2 MAX UNITS V/ms tPUR (Note 7) Power-up to initiation of read operation 1 ms tPUW (Note 7) Power-up to initiation of write operation 50 ms A.C. Test Conditions Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 NOTES: 6. This parameter is not 100% tested 7. tPUR and tPUW are the delays required from the time the power supply (VCC) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. 14 FN8169.5 April 13, 2007 X9259 Equivalent A.C. Load Circuit 5V SPICE Macromodel 1533 RTOTAL RH SDA pin RL CW CL CL 10pF 100pF 25pF 10pF RW AC Timing SYMBOL PARAMETER MIN MAX UNITS 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 s tDH SDA Data Output Hold Time 0 ns Noise Suppression Time Constant at SCL and SDA inputs 50 ns 1200 ns TI tBUF Bus Free Time (Prior to Any Transmission) tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns High-Voltage Write Cycle Timing SYMBOL PARAMETER tWR High-voltage write cycle time (store instructions) TYP MAX UNITS 5 10 ms XDCP Timing SYMBOL tWRPO tWRL PARAMETER MIN MAX UNITS Wiper response time after the third (last) power supply is stable 5 10 s Wiper response time after instruction issued (all load instructions) 5 10 s 15 FN8169.5 April 13, 2007 X9259 Symbol Table . WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Timing Diagrams Start and Stop Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA 16 tDH FN8169.5 April 13, 2007 X9259 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx Write Protect and Device Address Pins Timing (START) SCL (STOP) ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 17 FN8169.5 April 13, 2007 X9259 Applications Information Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Non inverting Amplifier VS Voltage Regulator + VO - VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysteresis R2 VS VS - + 100k - VO + +12V 10k } 10k } TL072 10k VO R1 R2 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) -12V 18 FN8169.5 April 13, 2007 X9259 Application Circuits (continued) Attenuator Filter C VS R2 R1 VO - - VS + R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10k R1 GO = 1 + R2/R1 fc = 1/(2RC) VO = G VS -1/2 G +1/2 R1 R2 } VS } Inverting Amplifier Equivalent L-R Circuit R2 C1 - VS VO + + - R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 - + R1 - } RA + } RB frequency R1, R2, C amplitude RA, RB 19 FN8169.5 April 13, 2007 X9259 Small Outline Plastic Packages (SOIC) M24.3 (JEDEC MS-013-AD ISSUE C) N 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- A D h x 45 -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e B S 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N NOTES: MILLIMETERS 24 0 24 8 0 7 8 Rev. 1 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 20 FN8169.5 April 13, 2007 X9259 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 0.05 A2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL "X" 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0 - 8 DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8169.5 April 13, 2007