TC74HC390AP/AF
2014-03-01
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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC390AP, TC74HC390AF
Dual Decade Counter
The TC74HC390A is a high speed CMOS DUAL DECADE
COUNTER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It consists of two independent 4-bit counters, each composed of
a divide-by-two and a divide-by-five counter. The divide-by-two
counter is incremented on the negative going transition of clock A
(CKA ). The divided-by-five counter is incremented on the
negative going transition of clock B ( CKB ). The counter can be
cascaded to form decade, bi-quinary, or various combinations up
to a divide-by-100 counter. When the CLR input is set high, the
Q outputs are set to low independent of the clock inputs.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 84 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
• Balanced propagation delays: tpLH ∼
−
tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
• Pin and function compatible with 74LS390
Pin Assignment
TC74HC390AP
TC74HC390AF
Weight
DIP16-P-300-2.54A : 1.00 g (typ.)
SOP16-P-300-1.27A : 0.18 g (typ.)
Start of commercial production
1986-11
TC74HC390AP/AF
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IEC Logic Symbol
Block Diagram
Truth Table
Inputs Outputs
CKA CKB CLR QA QB QC QD
X X H L L L L
X L Binary Count Up
X L Quinary Count Up
X: Don’t care
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System Diagram (1/2 package)
Timing Chart
(1) BCD count sequence (Note)
Note: QA connected to
CKB
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(2) BI-quinary count sequence (Note)
Note: QD connected to CKA
Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7 V
DC input voltage VIN −0.5 to VCC + 0.5 V
DC output voltage VOUT −0.5 to VCC + 0.5 V
Input diode current IIK ±20 mA
Output diode current IOK ±20 mA
DC output current IOUT ±25 mA
DC VCC/ground current ICC ±50 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW
Storage temperature Tstg −65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be
applied until 300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 2 to 6 V
Input voltage VIN 0 to VCC V
Output voltage VOUT 0 to VCC V
Operating temperature Topr −40 to 85 °C
Input rise and fall time tr, tf
0 to 1000 (VCC = 2.0 V)
0 to 500 (VCC = 4.5 V)
0 to 400 (VCC = 6.0 V)
ns
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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Electrical Characteristics
DC Characteristics
Test Condition Ta = 25°C Ta = −40 to 85°C
Characteristics Symbol
VCC (V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH ⎯
2.0
4.5
6.0
1.50
3.15
4.20
⎯
⎯
⎯
⎯
⎯
⎯
1.50
3.15
4.20
⎯
⎯
⎯
V
Low-level input
voltage VIL ⎯
2.0
4.5
6.0
⎯
⎯
⎯
⎯
⎯
⎯
0.50
1.35
1.80
⎯
⎯
⎯
0.50
1.35
1.80
V
IOH = −20 μA
2.0
4.5
6.0
1.9
4.4
5.9
2.0
4.5
6.0
⎯
⎯
⎯
1.9
4.4
5.9
⎯
⎯
⎯
High-level output
voltage VOH VIN
= VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
4.5
6.0
4.18
5.68
4.31
5.80
⎯
⎯
4.13
5.63
⎯
⎯
V
IOL = 20 μA
2.0
4.5
6.0
⎯
⎯
⎯
0.0
0.0
0.0
0.1
0.1
0.1
⎯
⎯
⎯
0.1
0.1
0.1
Low-level output
voltage VOL VIN
= VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
4.5
6.0
⎯
⎯
0.17
0.18
0.26
0.26
⎯
⎯
0.33
0.33
V
Input leakage
current IIN VIN = VCC or GND 6.0 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA
Quiescent supply
current ICC VIN = VCC or GND 6.0 ⎯ ⎯ 4.0 ⎯ 40.0 μA
Timing Requirements (input: tr = tf = 6 ns)
Test Condition Ta = 25°C
Ta =
−40 to
85°C
Characteristics Symbol
VCC (V) Typ. Limit Limit
Unit
Minimum pulse width
(CK )
tW (H)
tW (L) ⎯
2.0
4.5
6.0
⎯
⎯
⎯
75
15
13
95
19
16
ns
Minimum pulse width
(CLR) tW (H) ⎯
2.0
4.5
6.0
⎯
⎯
⎯
75
15
13
95
19
16
ns
Minimum removal time trem ⎯
2.0
4.5
6.0
⎯
⎯
⎯
25
5
5
30
6
5
ns
Clock frequency
(CKA ) f ⎯
2.0
4.5
6.0
⎯
⎯
⎯
6
32
38
5
26
31
MHz
Clock frequency
(CKB ) f ⎯
2.0
4.5
6.0
⎯
⎯
⎯
6
31
36
5
25
29
MHz
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AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C input: tr = tf = 6 ns)
Characteristics Symbol Test Condition Min Typ. Max Unit
Output transition time tTLH
tTHL
⎯ ⎯ 4 8 ns
Propagation delay time
(CKA -QA)
tpLH
tpHL
⎯ ⎯ 10 20 ns
Propagation delay time
(CKA -QC)
tpLH
tpHL
QA connected to CKB ⎯ 29 51 ns
Propagation delay time
(CKB -QB, QD)
tpLH
tpHL
⎯ ⎯ 12 22 ns
Propagation delay time
(CKB -QC)
tpLH
tpHL
⎯ ⎯ 17 32 ns
Propagation delay time
(CLR-Qn) tpHL ⎯ ⎯ 12 26 ns
Maximum clock frequency
(CKA ) fmax ⎯ 35 84 ⎯ MHz
Maximum clock frequency
(CKB ) fmax ⎯ 33 65 ⎯ MHz
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AC Characteristics (CL = 50 pF, input: tr = tf = 6 ns)
Test Condition Ta = 25°C Ta = −40 to 85°C
Characteristics Symbol
VCC (V) Min Typ. Max Min Max
Unit
Output transition time tTLH
tTHL
⎯
2.0
4.5
6.0
⎯
⎯
⎯
30
8
7
75
15
13
⎯
⎯
⎯
95
19
16
ns
Propagation delay
time
(CKA -QA)
tpLH
tpHL
⎯
2.0
4.5
6.0
⎯
⎯
⎯
39
13
11
120
24
20
⎯
⎯
⎯
150
30
26
ns
Propagation delay
time
(CKA -QC)
tpLH
tpHL
QA connected to CKB
2.0
4.5
6.0
⎯
⎯
⎯
102
34
29
290
58
49
⎯
⎯
⎯
365
73
62
ns
Propagation delay
time
(CKB -QB, QD)
tpLH
tpHL
⎯
2.0
4.5
6.0
⎯
⎯
⎯
45
15
13
130
26
22
⎯
⎯
⎯
165
33
28
ns
Propagation delay
time
(CKB -QC)
tpLH
tpHL
⎯
2.0
4.5
6.0
⎯
⎯
⎯
63
21
18
185
37
31
⎯
⎯
⎯
230
46
39
ns
Propagation delay
time
(CLR-Qn)
tpHL ⎯
2.0
4.5
6.0
⎯
⎯
⎯
45
15
13
150
30
26
⎯
⎯
⎯
190
38
32
ns
Maximum clock
frequency
(CKA )
fmax ⎯
2.0
4.5
6.0
6
32
38
20
77
90
⎯
⎯
⎯
5
26
31
⎯
⎯
⎯
MHz
Maximum clock
frequency
(CKB )
fmax ⎯
2.0
4.5
6.0
6
32
36
15
60
70
⎯
⎯
⎯
5
25
29
⎯
⎯
⎯
MHz
Input capacitance CIN ⎯ ⎯ 5 10 ⎯ 10 pF
Power dissipation
capacitance
CPD
(Note) ⎯ ⎯ 44 ⎯ ⎯ ⎯ pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC/2 (per counter)
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Package Dimensions
Weight: 1.00 g (typ.)
TC74HC390AP/AF
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Package Dimensions
Weight: 0.18 g (typ.)
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