CY7C375i
Document #: 38-03029 Rev. ** Page 5 of 17
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH37 0i PLD s. Note that produc t term a lloca tion is han-
dled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin as sociated with it. T he in put to the m ac roc ell is t he sum of
betwee n 0 and 16 produc t terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and four
global clocks to trigger the register. The macrocell also fea-
tures a s ep arat e fe edback path to the PIM so that the reg is ter
can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with FLASH370i.”
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i e nsures compl iance with the PC I AC specificat ions
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O operation
The FLASH370i family can be configured to operate in both
3.3V and 5 .0V systems . All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V sourc e, the I/O volta ge levels a re
compat ible w ith 5.0 V syst ems. W hen VCCIO pins are connec t-
ed to a 3.3V source, the input voltage levels are compatible
with bot h 5.0V and 3.3V sys tems, while the ou tput voltage lev -
els are compatible with 3.3V systems. There will be an addi-
tional ti ming delay o n all output b uffers wh en operating i n 3.3V
I/O mode. The added flexibility of 3.3V I/O capability is avail-
able in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In additi on to ISR capa bility, a new feature ca lled bus-h old has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up re sisto r, is a wea k latch co nnect ed to the pin that doe s
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
addition ally al lows u nused d evice p ins to re main un conne cted
on the b oard, whi ch is partic ularly us eful during p rototy ping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
Design Tools
Devel opment so ftwar e for the C Y7C 375i is availab le f rom Cy-
press’s Warp™, Warp Professional™, an d Warp Enterprise™
software packages. Please refer to the data sheets on these
products for more details. Cypress also actively supports al-
most a ll third-party design tool s. Please refe r to third-part y tool
support for further information.
Maximum Ratings
(Above which the us efu l l ife ma y be impai red. For user guide-
lines, not tes ted .)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................ –55°C to +125°C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Program Voltage ....................................................12.5V
Output Current into Outputs........................................ 16 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature VCC
VCCINT VCCIO
Commercial 0°C to +70°C5V ± 0.25V 5V ± 0.25V
OR
3.3V ± 0.3V
Industrial −40°C to +85°C5V ± 0.5V 5V ± 0.5V
OR
3.3V ± 0.3V
Military[2] –55°C to +125°C5V ± 0.5V
Note:
2. TA is the “instant on” case temperature.