UltraLogic™ 128-Macrocell Flash CPLD
CY7C375i
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-03029 Rev. ** Revised September 4, 2001
75i
Features
128 macrocells in eight logic blocks
128 I/O pins
5 dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR™) Flash technology
—JTAG Interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—fMAX = 125 MHz
—tPD = 10 ns
—tS = 5.5 ns
—tCO = 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C375i is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic FLASH370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which si mp lifies both design and manu fac turi ng f low s the reby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
thro ugh the S DI and S DO pins. The ISR int erfac e is en abled
using the programming voltage pin (ISREN). Additionally, be-
cause of the s uperior ro utability of the FLASH370i d evices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
Logic Block Diagram
7C375i1
PIM
INPUT
MACROCELL
CLOCK
INPUTS
4 4
36
16 16
36
LOGIC
BLOCK 36
16 16
36
16 I/Os
36 36
36
16 16
36
16 16
64 64
41 INPUT/CLOCK
MACROCELLS
I/O0I/O15 A
INPUTS
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O16I/O31
I/O32I/O47
I/O48I/O63
I/O112I/O127
I/O96I/O111
I/O80I/O95
I/O64I/O79
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
Selection Guide
7C375i125 7C375i100 7C375i83 7C375iL83 7C375i66 7C375iL66
Maximu m Propagation Delay[1], tPD (ns) 10 12 15 15 20 20
Minimum Set-Up, tS (ns) 5.5 6 8 8 10 10
Maximum Clock to Output[1], tCO (ns) 6.5 7 8 8 10 10
Typical Supply Current, ICC (mA) 125 125 125 75 125 75
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V
CY7C375i
Document #: 38-03029 Rev. ** Page 2 of 17
Pin Configurati ons
I/O
2
124
3
123
4
122
5
121
6
120
7
119
8
118
9
117
10
116
11
115
12
114
13
113
14
112
15
111
16
110
17
109
18
108
19
107
20
106
21
105
22
104
23
103
24
102
25
101
26
100
27
99
28
98
29
97
30
96
31
95
32
94
33
93
34
92
35
91
36
90
37
89
38
88
39
87
40
86
41
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
TQFP
Top View
125
84
83
42
7C375i2
1
GND
I/O16
I/O17
I/O18
I/O19
I/O20/SCLK
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
GND
CLK0/I0
VCCIO
GND
CLK1/I1
GND
GND
48
GND
2
CCIO
GND
GND
VCCIO
I/O49
I/O
50
I/O
51
I/O
52
I/O 53
I/O
54
I/O55
I/O
56
I/O57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/OI
V
CCINT
V
64
I/O65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O71
I/O
72
I/O73
I/O
74
I/O
75
I/O
76
I/O
77
78
I/O
79
I/O
CCIO
V
GND
I/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
GND
I/O88
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
I/O98
I/O99
I/O100
I/O101
I/O102
I/O103
GND
GND
CLK2/I3
VCCIO
CLK3/I4
I/O104
I/O105
I/O106
I/O107
I/O108/SDI
I/O109
I/O110
I/O111
VCCIO
GND
GND
V
GND
I/O
GND
112
CCINT
VCCIO
VCCIO
I/O113
I/O114
I/O115
I/O116
I/O117
I/O118
I/O119
I/O120
I/O121
I/O122
I/O123
I/O124
I/O125
I/O126
I/O127
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
ISREN
/SMODE
/SDO
CY7C375i
Document #: 38-03029 Rev. ** Page 3 of 17
Pin Configurati ons (continued)
I/O
2
124
3
123
4
122
5
121
6
120
7
119
8
118
9
117
10
116
11
115
12
114
13
113
14
112
15
111
16
110
17
109
18
108
19
107
20
106
21
105
22
104
23
103
24
102
25
101
26
100
27
99
28
98
29
97
30
96
31
95
32
94
33
93
34
92
35
91
36
90
37
89
38
88
39
87
40
86
41
85
43
44
160
45
159
46
158
47
157
48
156
49
155
50
154
51
153
52
152
53
151
54
150
55
149
56
148
57
147
58
146
59
145
60
144
61
143
62
142
63
141
64
65
66
67
68
140
69
139
70
138
71
137
72
136
73
135
74
134
75
133
76
132
77
131
78
130
79
129
80
128
81
127
82
126
CQFP
Top View
125
84
83
42
7C375i3
1
GND
I/O16
I/O17
I/O18
I/O19
I/O20/SCLK
I/O21
I/O22
I/O23
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
I/O44
I/O45
I/O46
I/O47
GND
CLK0/I0
VCC
GND
CLK1/I1
GND
GND
48
GND
2
CC
GND
GND
VCC
I/O49
I/O
50
I/O
51
I/O
52
I/O 53
I/O
54
I/O55
I/O
56
I/O57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/OI
V
CC
V
64
I/O65
I/O
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O71
I/O
72
I/O73
I/O
74
I/O
75
I/O
76
I/O
77
78
I/O
79
I/O
CC
V
GND
I/O80
I/O81
I/O82
I/O83
I/O84
I/O85
I/O86
I/O87
GND
I/O88
I/O89
I/O90
I/O91
I/O92
I/O93
I/O94
I/O95
I/O96
I/O97
I/O98
I/O99
I/O100
I/O101
I/O102
I/O103
GND
GND
CLK2/I3
VCC
CLK3/I4
I/O104
I/O105
I/O106
I/O107
I/O108/SDI
I/O109
I/O110
I/O111
VCC
GND
GND
V
GND
I/O
GND
112
CC
VCC
VCC
I/O113
I/O114
I/O115
I/O116
I/O117
I/O118
I/O119
I/O120
I/O121
I/O122
I/O123
I/O124
I/O125
I/O126
I/O127
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
ISREN
/SMODE
/SDO
CY7C375i
Document #: 38-03029 Rev. ** Page 4 of 17
Functional Description (continued)
The 128 macrocells in the CY7C375i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resourcethe
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
Like all members of the FLASH370i family , the CY7C375i is rich
in I/O resources. Every macrocell in the device features an
assoc iated I/O pin, res ulting in 128 I/O pi ns on the CY7C375 i.
In addition, there is one dedicated input and four input/clock
pins.
Finally, the CY7C375i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the ty pe of applic ation, the tim ing paramete rs
on the CY7C375i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C375i includes eight logic blocks.
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i lo gic bl ock inc ludes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very c omplex fun ctions to be im plemented in single pas ses
through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms tha t are comm on to more than one ou tput ca n be imple-
Pin Configurati ons (continued)
PGA
Bottom View
12345 67891011
R
P
N
M
L
K
J
H
G
F
E
I/O109
D
C
B
A
12 13 14 15 7C375i4
I/O106
I/O105
I/O102
I/O100
I/O98
I/O96
I/O86
I/O89
I/O91
I/O94
I/O95
I/O83
I/O80
I/O78
I/O112
I/O110
I/O108
I/O104
I/O101
I/O99
I/O97
I/O84
I/O87
I/O90
I/O93
GND
I/O81
I/O79
I/O75
/SDI
I/O115
I/O113
I/O111
I/O107
I/O103
GND
CLK3
I/O82
I/O85
I/O88
I/O92
CLK2
GND
I/O77
I/O74
/I4
/I3
I/O118
I/O116
I/O114
VCC
VCC
GND
VCC
GND
I/O76
I/O73
I/O71
/SDO
I/O121
I/O119
I/O117
I/O72
I/O70
I/O69
I/O123
I/O122
I/O120
GND
I/O68
I/O67
I/O126
I/O125
I/O124
VCC
VCC
I/O66
I/O65
I/O64
I/O127
GND
ISREN
GND
GND
I2
GND
I/O63
I/O0
I/O1
I/O2
VCC
VCC
I/O60
I/O61
I/O62
I/O3
I/O4
GND
I/O56
I/O58
I/O59
I/O5
I/O6
I/O8
I/O53
I/O55
I/O57
I/O7
I/O9
I/O12
GND
VCC
VCC
VCC
GND
I/O52/
I/O50
I/O71
SMODE
I/O10
I/O13
GND
I/O18
I/O21
I/O24
CLK28
I/O43
I/O39
GND
CLK1
CLK0
I/O47
I/O49
I/O51
/I0
I/O11
I/O15
I/O17
I/O20
I/O23
I/O26
I/O29
I/O40
I/O37
I/O35
I/O33
GND
I/O44
I/O46
I/O48
I/O14
I/O16
I/O19
I/O22
I/O25
I/O27
I/O30
I/O38
I/O36
I/O34
I/O32
I/O31
I/O41
I/O42
I/O45
/I1
/SCLK
CY7C375i
Document #: 38-03029 Rev. ** Page 5 of 17
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH37 0i PLD s. Note that produc t term a lloca tion is han-
dled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin as sociated with it. T he in put to the m ac roc ell is t he sum of
betwee n 0 and 16 produc t terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and four
global clocks to trigger the register. The macrocell also fea-
tures a s ep arat e fe edback path to the PIM so that the reg is ter
can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, An In-
troduction to In System Reprogramming with FLASH370i.
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i e nsures compl iance with the PC I AC specificat ions
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
3.3V or 5.0V I/O operation
The FLASH370i family can be configured to operate in both
3.3V and 5 .0V systems . All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V sourc e, the I/O volta ge levels a re
compat ible w ith 5.0 V syst ems. W hen VCCIO pins are connec t-
ed to a 3.3V source, the input voltage levels are compatible
with bot h 5.0V and 3.3V sys tems, while the ou tput voltage lev -
els are compatible with 3.3V systems. There will be an addi-
tional ti ming delay o n all output b uffers wh en operating i n 3.3V
I/O mode. The added flexibility of 3.3V I/O capability is avail-
able in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In additi on to ISR capa bility, a new feature ca lled bus-h old has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up re sisto r, is a wea k latch co nnect ed to the pin that doe s
not degrade the devices performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
addition ally al lows u nused d evice p ins to re main un conne cted
on the b oard, whi ch is partic ularly us eful during p rototy ping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
Design Tools
Devel opment so ftwar e for the C Y7C 375i is availab le f rom Cy-
presss Warp, Warp Professional, an d Warp Enterprise
software packages. Please refer to the data sheets on these
products for more details. Cypress also actively supports al-
most a ll third-party design tool s. Please refe r to third-part y tool
support for further information.
Maximum Ratings
(Above which the us efu l l ife ma y be impai red. For user guide-
lines, not tes ted .)
Storage Temperature ................................. 65°C to +150°C
Ambient Temperature with
Power Applied............................................ 55°C to +125°C
Supply Voltage to Ground Potential ...............0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................0.5V to +7.0V
DC Input Voltage............................................ 0.5V to +7.0V
DC Program Voltage ....................................................12.5V
Output Current into Outputs........................................ 16 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature VCC
VCCINT VCCIO
Commercial 0°C to +70°C5V ± 0.25V 5V ± 0.25V
OR
3.3V ± 0.3V
Industrial 40°C to +85°C5V ± 0.5V 5V ± 0.5V
OR
3.3V ± 0.3V
Military[2] 55°C to +125°C5V ± 0.5V
Note:
2. TA is the instant on case temperature.
CY7C375i
Document #: 38-03029 Rev. ** Page 6 of 17
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.
5. IOH = 2 mA, IOL = 2 mA for SDO.
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note Understanding Bus Hold for addit ional
information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9. Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
11. CI/O for dedicated inputs, and for I/O pins with JTAG functionality is 12 pF,and for the ISREN pin is 15 pF Max.
Electrical Characteristics Ov er the Op erating Range[3, 4]
Parameter Description Test Conditions Min. Typ. Max. Unit
VOH Output HIGH Voltage VCC = Min. IOH = 3.2 mA (Coml/Ind)[5] 2.4 V
IOH = 2.0 mA (Mil) V
VOHZ Output HI GH Voltage
with Output Disabled[9] VCC = Max. IOH = 0 µA (Coml/Ind)[5, 6] 4.0 V
IOH = 50 µA (Coml/Ind)[5 , 6] 3.6 V
VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Coml/Ind)[5] 0.5 V
IOL = 12 mA (Mil) V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH voltage for all inputs[7] 2.0 7.0 V
VIL Input LOW Voltage Guarant eed Input Logical LOW voltage for all inputs[7] 0.5 0.8 V
IIX Input Load Current VI = Internal GND, VI = VCC 10 +10 µA
IOZ Output Leakage Current VCC = Max., VO = GND or VO = VCC, Outpu t Disabled 50 +50 µA
VCC = Max., VO = 3.3V, Output Disabl ed[6] 070 125 µA
IOS Output Short
Circuit Current[8, 9] VCC = Max., VOUT = 0.5V 30 160 mA
ICC Power Supply
Current[10] VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC Coml/Ind. 125 200 mA
Coml L 66 75 125 mA
Military 125 250 mA
IBHL Input Bus Hold LOW
Sustaining Current VCC = Min., VIL = 0.8V +75 µA
IBHH Input Bus Hold HIGH
Sustaining Current VCC = Min., VIH = 2.0V 75 µA
IBHLO Input Bus Hold LOW
Overdrive Current VCC = Max. +500 µA
IBHHO Input Bus Hold HIGH
Overdrive Current VCC = Max. 500 µA
Capacitance[9]
Parameter Description Test Conditions Min. Max. Unit
CI/O[11] Input/Output Capacitance VIN = 5.0V at f=1 MHz 8pF
CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz 512 pF
CY7C375i
Document #: 38-03029 Rev. ** Page 7 of 17
Note:
12. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Inductance[9]
Parameter Description Test Conditions 160-Lead
TQFP 160-Pin
CQFP 160-Pin
CPGA Unit
LMaximum Pin Inductance VIN = 5.0V at 5 = 1 MHz 9 6 10 nH
Endurance Characteri stics[9]
Parameter Description Test Conditions Max. Unit
NMaximum Reprogramming Cycles Normal Programming Conditions 100 Cycles
AC Test Loads and Waveforms
7C375i4
7C375i5
90%
10%
3.0V
GND
90%
10%
ALL INP UT PULSES
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2ns
OUTPUT
238(COML)
319(MIL)
170(COML)
236(MIL)
99(COML)
136(MIL)
Equivale nt to: THÉVENIN EQUIVALENT
2.08V(COM'L)
2.13V(MIL)
238(COM'L)
319(MIL)
170(COM'L)
236(MIL)
<2ns
Parameter[12] VXOutput Waveforms--Measurement Level
tER()1.5V
tER(+) 2.6V
tEA(+) 1.5V
tEA()Vthe
(d) Test Waveforms
VOH VX
0.5V 7C375i-6
VOL VX
0.5V
7c375i-7
VXVOH
0.5V
7c375i-8
VXVOL
0.5V 7c375i-9
CY7C375i
Document #: 38-03029 Rev. ** Page 8 of 17
Switching Characteristics Over the Operating Range[13]
7C375i125 7C375i100 7C375i83
7C374iL83 7C375i66
7C375iL66
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
tPD Input to Combinatorial Output[1] 10 12 15 20 ns
tPDL Input to Outp ut Through T ransparent Input
or Output Latch[1] 13 15 18 22 ns
tPDLL Input to Outp ut Through T ransparent Inpu t
and Output Latches[1] 15 16 19 24 ns
tEA Input to Output Enable[1] 14 16 19 24 ns
tER Input to Output Disable 14 16 19 24 ns
Input Registered/Latched Mode Parameters
tWL Clock or Latch Enable Input LOW Time[9] 3 3 4 5 ns
tWH Clock or Latch Enable Input HIGH Time[9] 3 3 4 5 ns
tIS Input Register or Latch Set-Up Time 2 2 3 4 ns
tIH Input Register or Latch Hold Time 2 2 3 4 ns
tICO Input Register Clock or Latch Enable to
Combinatorial Output[1] 14 16 19 24 ns
tICOL Input Register Clock or Latch Enable to
Output Through Transparent Output
Latch[1]
16 18 21 26 ns
Ouptut Registered/Latched Mode Parameters
tCO Clock or Latch Enable to Output[1] 6.5 7 8 10 ns
tSSet-Up Time from Input to Clock or Latch
Enable 5.5 6 8 10 ns
tHRegister or Latch Data Hold Time 0 0 0 0 ns
tCO2 Output Clock or Latch Enable to Output
Delay (Through Memory Array) [1] 14 16 19 24 ns
tSCS Output Clock or Latch Enable to Output
Clock or Latch Enable (Through Memory
Array)
810 12 15 ns
tSL Set-Up T im e from Input Throu gh T ranspar-
ent Latch to Output Register Clock or Latch
Enable
10 12 15 20 ns
tHL Hold Time for Input Through Transparent
Latch fro m Ou tput Reg ister C loc k or L atch
Enable
0 0 0 0 ns
fMAX1 Maximum Frequency with Internal Feed-
back (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[9] 125 100 83 66 MHz
fMAX2 Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL
+ tWH), 1/(tS + tH), or 1/tCO)
158.3 143 125 100 MHz
fMAX3 Maximum Frequency with External Feed-
back (Lesser of 1/(tCO + tS) and 1/(tWL +
tWH,
83.3 76.9 62.5 50 MHz
tOHtIH
37x Output Data Stable from Output Clock
Minus Input Register Hold Time for
7C37x[9, 14]
0 0 0 0 ns
Notes:
13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
CY7C375i
Document #: 38-03029 Rev. ** Page 9 of 17
Pipelined Mode Parameters
tICS Input Register Clock to Output Register
Clock 810 12 15 ns
fMAX4 Maximum Frequency in Pipelined Mode
(Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH),
1/(tIS + tIH), or 1/tSCS)
125 100 83.3 66.6 MHz
Reset/Preset Parameters
tRW Asynchro nou s Re se t Width[9] 10 12 15 20 ns
tRR Asyn chronous Reset Re covery Time[9] 12 14 17 22 ns
tRO Asynchronous Reset to Output[1] 16 18 21 26 ns
tPW Asynchro nou s Pres et Width [9] 10 12 15 20 ns
tPR Asynchronous Preset Recovery Time[9] 12 14 17 22 ns
tPO Asynchronous Preset to Output[1] 16 18 21 26 ns
Tap Controller Parameter
fTAP Tap Controller Frequency 500 500 500 500 kHz
3.3V I/O Mode Parameters
t3.3IO 3.3V I/O mode timing adder 1 1 1 1 ns
Switching Characteristics Over the Operating Range[13] (continued)
7C375i125 7C375i100 7C375i83
7C374iL83 7C375i66
7C375iL66
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Switching Waveforms
tPD
7C375i10
INPUT
COMBINATORIAL
OUTPUT
Combinatorial Output
Registered Output
tS
7C375i11
INPUT
CLOCK
tCO
REGISTERED
OUTPUT
tH
CLOCK
tWL
tWH
CY7C375i
Document #: 38-03029 Rev. ** Page 10 of 17
Switching Waveforms (continued)
Latched Output
tS
7C375i12
INPUT
LATCHENABLE
tCO
LATCHED
OUTPUT
tH
tPDL
Registered Input
tIS
7C375i13
REGISTERED
INPUT
INPU T R EGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tIH
CLOCK
tWL
tWH
Clock to Clock
7C375i14
REGISTERED
INPUT
INPU T R EGISTER
CLOCK tICS
OUTPUT
REGISTER CLOCK
tSCS
CY7C375i
Document #: 38-03029 Rev. ** Page 11 of 17
Switching Waveforms (continued)
Latched Input
tIS
7C375i15
LATCHED INPUT
LATCHENABLE
tICO
COMBINATORIAL
OUTPUT
tIH
tPDL
LATCH ENABLE
tWL
tWH
Latched Input and Output
tICS
7C375i16
LATCHED INPUT
OUTPUT LATCH
ENABLE
LATCHED
OUTPUT
tPDLL
LATCH ENABLE
tWL
tWH
tICOL
INPUT LATCH
ENABLE
tSL tHL
CY7C375i
Document #: 38-03029 Rev. ** Page 12 of 17
Switching Waveforms (continued)
Asynchronous Reset
7C375i17
INPUT
tRO
REGISTERED
OUTPUT
CLOCK
tRR
tRW
Asynchronous Preset
7C375i18
INPUT
tPO
REGISTERED
OUTPUT
CLOCK
tPR
tPW
OutputEnable/Disable
7C375i20
INPUT
tER
OUTPUTS
tEA
CY7C375i
Document #: 38-03029 Rev. ** Page 13 of 17
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Note:
15. Stan dar d prod uct s hips tri m and for med i n a car rier. This prod uct i s also avail ab le in a mo lded carr ier ri ng. Cont act local Cypress office for package information.
ISR, UltraLogic, FLASH370 and FLASH370i are trademarks of Cypress Semiconductor Corporation.
Wa rp, Warp Professional , and Warp Enterprise are registered trademarks of Cypress Semiconductor Corporation.
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
125 CY7C375i125AC A160 160-Lead Thin Quad Flatpack Commercial
100 CY7C375i100AC A160 160-Lead Thin Quad Flatpack Commercial
CY7C375i100AI A160 160-Lead Thin Quad Flatpack Industrial
83 CY7C375i83AC A160 160-Lead Thin Quad Flatpack Commercial
CY7C375i83AI A160 160-Lead Thin Quad Flatpack Industrial
CY7C375i83GMB G160 160-Pin Grid Array Military
CY7C375i83UMB U162 160-Pin Ceramic Quad Flatpack[15]
CY7C375iL83AC A160 160-Lead Thin Quad Flatpack Commercial
66 CY7C375i66AC A160 160-Lead Thin Quad Flatpack Commercial
CY7C375i66AI A160 160-Lead Thin Quad Flatpack Industrial
CY7C375i66GMB G160 160-Pin Grid Array Military
CY7C375i66UMB U162 160-Pin Ceramic Quad Flatpack[15]
CY7C375iL66AC A160 160-Lead Thin Quad Flatpack Commercial
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tPD 9, 10, 11
tCO 9, 10, 11
tICO 9, 10, 11
tS9, 10, 11
tH9, 10, 11
tIS 9, 10, 11
tIH 9, 10, 11
tICS 9, 10, 11
CY7C375i
Document #: 38-03029 Rev. ** Page 14 of 17
Package Diagrams
160-Pin Thin Plastic Quad Flat Pack (TQFP) A160
51-85049-A
CY7C375i
Document #: 38-03029 Rev. ** Page 15 of 17
Package Diagrams (continued)
160-Pin PGA G160
CY7C375i
Document #: 38-03029 Rev. ** Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
160-Lead Ceramic Quad Flatpack (Cavity Up) U162
CY7C375i
Document #: 38-03029 Rev. ** Page 17 of 17
Document Title: CY7C375i UltraLogic 128-Macrocell Flash CPLD
Document Number: 38-03029
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 106374 09/15/01 SZV Change from Spec number: 38-00494 to 38-03029