LTC2341-18
1
234118f
For more information www.linear.com/LTC2341-18
Typical applicaTion
FeaTures DescripTion
Dual, 18-Bit, 666ksps/ch
Differential SoftSpan ADC with
Wide Input Common Mode Range
The LTC
®
2341-18 is an 18-bit, low noise 2-channel simul-
taneous sampling successive approximation register (SAR)
ADC with differential, wide common mode range inputs.
Operating from a 5V supply and using the internal reference
and buffer, both channels of this SoftSpan
TM
ADC can be
independently configured on a conversion-by-conversion
basis to accept ±4.096V, 0V to 4.096V, ±2.048V, or 0V
to 2.048V signals. One channel may also be disabled to
increase throughput on the other channel.
The wide input common mode range and 105dB CMRR of
the LTC2341-18 analog inputs allow the ADC to directly
digitize a variety of signals, simplifying signal chain de-
sign. This input signal flexibility, combined with ±4LSB
INL, no missing codes at 18 bits, and 95dB SNR, makes
the LTC2341-18 an ideal choice for many applications
requiring wide dynamic range.
The LTC2341-18 supports pin-selectable SPI CMOS (1.8V
to 5V) and LVDS serial interfaces. Either one or two lanes
of data output may be employed in CMOS mode, allowing
the user to optimize bus width and throughput.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673,
9197235.
applicaTions
n 666ksps per Channel Throughput
n Two Simultaneous Sampling Channels
n ±4LSB INL (Maximum)
n Guaranteed 18-Bit, No Missing Codes
n Differential, Wide Common Mode Range Inputs
n Per-Channel SoftSpan Input Ranges:
±4.096V, 0V to 4.096V, ±2.048V, 0V to 2.048V
±5V, 0V to 5V, ±2.5V, 0V to 2.5V
n 95dB Single-Conversion SNR (Typical)
n −114dB THD (Typical) at fIN = 2kHz
n 105dB CMRR (Typical) at fIN = 200Hz
n Rail-to-Rail Input Overdrive Tolerance
n Guaranteed Operation to 125°C
n Integrated Reference and Buffer (4.096V)
n SPI CMOS (1.8V to 5V) and LVDS Serial I/O
n Internal Conversion Clock, No Cycle Latency
n 74mW Power Dissipation (Typical)
n 32-Lead (5mm × 5mm) QFN Package
n Programmable Logic Controllers
n Industrial Process Control
n Medical Imaging
n High Speed Data Acquisition
Integral Nonlinearity vs
Output Code and Channel
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
ALL CHANNELS
OUTPUT CODE
–131072
–65536
0
65536
131072
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL ERROR (LSB)
234118 TA01b
0.1µF2.2µF0.1µF
1.8V TO 5V5V
SAMPLE
CLOCK
234118 TA01a
S/H
S/H
MUX
VDD VDDLBYP OVDD
TWO SIMULTANEOUS
SAMPLING CHANNELS
DIFFERENTIAL INPUTS
IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
5V
0V
FULLY
DIFFERENTIAL
5V
0V
BIPOLAR
5V
0V
ARBITRARY
5V
0V
UNIPOLAR
SDO0
SDO1
SCKO
SCKI
SDI
CS
BUSY
CNV
LVDS/CMOS
PD
IN0+
IN0–
IN1+
IN1–
18-BIT
SAR ADC
CMOS OR LVDS
I/O INTERFACE
0.1µF
REFIN
47µF
GNDREFBUF
LTC2341-18
LTC2341-18
2
234118f
For more information www.linear.com/LTC2341-18
pin conFiguraTionabsoluTe MaxiMuM raTings
Supply Voltage (VDD) ..................................................6V
Supply Voltage (OVDD) ................................................6V
Internal Regulated Supply Bypass (VDDLBYP) ... (Note 3)
Analog Input Voltage
IN0+, IN1+,
IN0–, IN1– (Note 4) ..................... –0.3V to (VDD + 0.3V)
REFIN .................................................... –0.3V to 2.8V
REFBUF, CNV (Note 4) ............. –0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) .....–0.3V to (OVDD + 0.3V)
Digital Output Voltage (Note 4) .. –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2341C ................................................ 0°C to 70°C
LTC2341I ..............................................–40°C to 85°C
LTC2341H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
32
33
GND
31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1IN1–
IN1+
GND
GND
GND
GND
IN0–
IN0+
SDO+
SCKO–/SDO1
SCKO+/SCKO
OVDD
GND
SCKI–/SCKI
SCKI+/SDO0
SDI–
GND
GND
VDD
GND
VDDLBYP
CS
BUSY
SDO–/SDI
GND
REFIN
GND
REFBUF
PD
LVDS/CMOS
CNV
SDI+
TJMAX = 150°C, θJA = 44°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2341CUH-18#PBF LTC2341CUH-18#TRPBF 234118 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2341IUH-18#PBF LTC2341IUH-18#TRPBF 234118 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC2341HUH-18#PBF LTC2341HUH-18#TRPBF 234118 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC2341-18#orderinfo
LTC2341-18
3
234118f
For more information www.linear.com/LTC2341-18
elecTrical characTerisTics
converTer characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+ Absolute Input Range
(IN0+, IN1+)
(Note 6) l0 VDD V
VIN– Absolute Input Range
(IN0–, IN1–)
(Note 6) l0 VDD V
VIN+ – VIN– Input Differential Voltage
Range
SoftSpan 7: ±VREFBUF Range (Note 6)
SoftSpan 6: ±VREFBUF/1.024 Range (Note 6)
SoftSpan 5: 0V to VREFBUF Range (Note 6)
SoftSpan 4: 0V to VREFBUF/1.024 Range (Note 6)
SoftSpan 3: ±0.5 • VREFBUF Range (Note 6)
SoftSpan 2: ±0.5 • VREFBUF/1.024 Range (Note 6)
SoftSpan 1: 0V to 0.5 • VREFBUF Range (Note 6)
l
l
l
l
l
l
l
– VREFBUF
– VREFBUF/1.024
0
0
–0.5 • VREFBUF
–0.5 • VREFBUF/1.024
0
VREFBUF
VREFBUF/1.024
VREFBUF
VREFBUF/1.024
0.5 • VREFBUF
0.5 • VREFBUF/1.024
0.5 • VREFBUF
V
V
V
V
V
V
V
VCM Input Common Mode Voltage
Range
(Note 6) l0 VDD V
VIN+ – VIN– Input Differential Overdrive
Tolerance
(Note 7) l−VDD VDD V
IIN Analog Input Leakage Current l–1 1 µA
CIN Analog Input Capacitance Sample Mode
Hold Mode
90
10
pF
pF
CMRR Input Common Mode
Rejection Ratio
VIN+ = VIN− = 3.6VP-P 200Hz Sine l88 105 dB
VIHCNV CNV High Level Input Voltage l1.3 V
VILCNV CNV Low Level Input Voltage l0.5 V
IINCNV CNV Input Current VIN = 0V to VDD l–10 10 μA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l18 Bits
No Missing Codes l18 Bits
Transition Noise SoftSpans 7 and 6: ±4.096V and ±4V Ranges
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges
SoftSpans 3 and 2: ±2.048V and ±2V Ranges
SoftSpan 1: 0V to 2.048V Range
1.6
3.2
3.2
6.3
LSBRMS
LSBRMS
LSBRMS
LSBRMS
INL Integral Linearity Error (Note 9) l–4 ±1.5 4 LSB
DNL Differential Linearity Error (Note 10) l−0.9 ±0.5 0.9 LSB
ZSE Zero-Scale Error (Note 11) l−500 ±50 500 μV
Zero-Scale Error Drift ±2 μV/°C
FSE Full-Scale Error VREFBUF = 4.096V (REFBUF Overdriven) (Note 11) l−0.13 ±0.025 0.13 %FS
Full-Scale Error Drift ±2.5 ppm/°C
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
LTC2341-18
4
234118f
For more information www.linear.com/LTC2341-18
DynaMic accuracy
inTernal reFerence characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise +
Distortion) Ratio
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
91.0
85.0
85.1
79.3
95.0
89.1
89.1
83.3
dB
dB
dB
dB
SNR Signal-to-Noise Ratio SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
91.1
85.2
85.1
79.3
95.0
89.1
89.1
83.3
dB
dB
dB
dB
THD Total Harmonic Distortion SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048V and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
–114
–111
–110
–109
–99
–95
–95
–95
dB
dB
dB
dB
SFDR Spurious Free Dynamic
Range
SoftSpans 7 and 6: ±4.096V and ±4V Ranges, fIN = 2kHz
SoftSpans 5 and 4: 0V to 4.096V and 0V to 4V Ranges, fIN = 2kHz
SoftSpans 3 and 2: ±2.048 and ±2V Ranges, fIN = 2kHz
SoftSpan 1: 0V to 2.048V Range, fIN = 2kHz
l
l
l
l
99
95
95
95
115
112
111
110
dB
dB
dB
dB
Channel-to-Channel
Crosstalk
One Channel Converting 3.6VP-P 200Hz Sine in ±2.048V Range,
Crosstalk to Other Channel
–119 dB
–3dB Input Bandwidth 22 MHz
Aperture Delay 1 ns
Aperture Delay Matching 150 ps
Aperture Jitter 3 psRMS
Transient Response Full-Scale Step, 0.005% Settling 210 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFIN Internal Reference Output Voltage 2.043 2.048 2.053 V
Internal Reference Temperature Coefficient (Note 13) l5 20 ppm/°C
Internal Reference Line Regulation VDD = 4.75V to 5.25V 0.1 mV/V
Internal Reference Output Impedance 20 kΩ
VREFIN REFIN Voltage Range REFIN Overdriven (Note 6) 1.25 2.2 V
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Notes 8, 12)
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
LTC2341-18
5
234118f
For more information www.linear.com/LTC2341-18
reFerence buFFer characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFBUF Reference Buffer Output Voltage REFIN Overdriven, VREFIN = 2.048V l4.091 4.096 4.101 V
REFBUF Voltage Range REFBUF Overdriven (Notes 6, 14) l2.5 5 V
REFBUF Input Impedance VREFIN = 0V, Buffer Disabled 13 kΩ
IREFBUF REFBUF Load Current VREFBUF = 5V, 2 Channels Enabled (Notes 14, 15)
VREFBUF = 5V, Acquisition Mode (Note 14)
l1.3
0.35
1.6 mA
mA
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
DigiTal inpuTs anD DigiTal ouTpuTs
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMOS Digital Inputs and Outputs
VIH High Level Input Voltage l0.8•OVDD V
VIL Low Level Input Voltage l0.2•OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IOUT = –500μA lOVDD–0.2 V
VOL Low Level Output Voltage IOUT = 500μA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA
ISOURCE Output Source Current VOUT = 0V –50 mA
ISINK Output Sink Current VOUT = OVDD 50 mA
LVDS Digital Inputs and Outputs
VID Differential Input Voltage l200 350 600 mV
RID On-Chip Input Termination
Resistance
CS = 0V, VICM = 1.2V
CS = OVDD
l80 106
10
130 Ω
MΩ
VICM Common-Mode Input Voltage l0.3 1.2 2.2 V
IICM Common-Mode Input Current VIN+ = VIN– = 0V to OVDD l–10 10 μA
VOD Differential Output Voltage RL = 100Ω Differential Termination l275 350 425 mV
VOCM Common-Mode Output Voltage RL = 100Ω Differential Termination l1.1 1.2 1.3 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 μA
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8)
LTC2341-18
6
234118f
For more information www.linear.com/LTC2341-18
power requireMenTs
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CMOS I/O Mode
VDD Supply Voltage l4.75 5.00 5.25 V
OVDD Supply Voltage l1.71 5.25 V
IVDD Supply Current 666ksps Sample Rate, 2 Channels Enabled
666ksps Sample Rate, 2 Channels Enabled, VREFBUF = 5V (Note 14)
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
13.7
12.3
1.2
65
65
16.0
14.8
2.0
225
500
mA
mA
mA
μA
µA
IOVDD Supply Current 666ksps Sample Rate, 2 Channels Enabled (CL = 25pF)
Acquisition Mode
Power Down Mode
l
l
l
2.2
1
1
3.4
20
20
mA
μA
μA
PDPower Dissipation 666ksps Sample Rate, 2 Channels Enabled
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
74
6.0
0.33
0.33
89
10
1.2
2.6
mW
mW
mW
mW
LVDS I/O Mode
VDD Supply Voltage l4.75 5.00 5.25 V
OVDD Supply Voltage l2.375 5.25 V
IVDD Supply Current 666ksps Sample Rate, 2 Channels Enabled
666ksps Sample Rate, 2 Channels Enabled, VREFBUF = 5V (Note 14)
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
l
15.7
14.4
2.7
65
65
18.0
16.8
3.8
225
500
mA
mA
mA
μA
µA
IOVDD Supply Current 666ksps Sample Rate, 2 Channels Enabled (RL = 100Ω)
Acquisition Mode (RL = 100Ω)
Power Down Mode
l
l
l
7.4
7
1
9.5
8.2
20
mA
mA
μA
PDPower Dissipation 666ksps Sample Rate, 2 Channels Enabled
Acquisition Mode
Power Down Mode (C-Grade and I-Grade)
Power Down Mode (H-Grade)
l
l
l
l
97
31
0.33
0.33
114
40
1.2
2.6
mW
mW
mW
mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency 2 Channels Enabled
1 Channel Enabled
l
l
666
1000
ksps
ksps
tCYC Time Between Conversions 2 Channels Enabled, fSMPL = 666ksps
1 Channel Enabled, fSMPL = 1000ksps
l
l
1500
1000
ns
ns
tCONV Conversion Time N Channels Enabled, 1 ≤ N ≤ 2 l450 • N –40 500 • N –40 550 • N –40 ns
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
aDc TiMing characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
LTC2341-18
7
234118f
For more information www.linear.com/LTC2341-18
aDc TiMing characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tACQ Acquisition Time
(tACQ = tCYC – tCONV – tBUSYLH)
2 Channels Enabled, fSMPL = 666ksps
1 Channel Enabled, fSMPL = 1000ksps
l
l
410
460
520
520
ns
ns
tCNVH CNV High Time l40 ns
tCNVL CNV Low Time l410 ns
tBUSYLH CNV↑ to BUSY Delay CL = 25pF l30 ns
tQUIET Digital I/O Quiet Time from CNV↑l20 ns
tPDH PD High Time l40 ns
tPDL PD Low Time l40 ns
tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 0.1μF 200 ms
CMOS I/O Mode
tSCKI SCKI Period (Notes 16, 17) l10 ns
tSCKIH SCKI High Time l4 ns
tSCKIL SCKI Low Time l4 ns
tSSDISCKI SDI Setup Time from SCKI↑(Note 16) l2 ns
tHSDISCKI SDI Hold Time from SCKI↑(Note 16) l1 ns
tDSDOSCKI SDO Data Valid Delay from SCKI↑CL = 25pF (Note 16) l7.5 ns
tHSDOSCKI SDO Remains Valid Delay from SCKI↑CL = 25pF (Note 16) l1.5 ns
tSKEW SDO to SCKO Skew (Note 16) l–1 0 1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓CL = 25pF (Note 16) l0 ns
tEN Bus Enable Time After CS↓(Note 16) l15 ns
tDIS Bus Relinquish Time After CS↑(Note 16) l15 ns
LVDS I/O Mode
tSCKI SCKI Period (Note 18) l4 ns
tSCKIH SCKI High Time (Note 18) l1.5 ns
tSCKIL SCKI Low Time (Note 18) l1.5 ns
tSSDISCKI SDI Setup Time from SCKI (Notes 10, 18) l1.2 ns
tHSDISCKI SDI Hold Time from SCKI (Notes 10, 18) l–0.2 ns
tDSDOSCKI SDO Data Valid Delay from SCKI (Notes 10, 18) l6 ns
tHSDOSCKI SDO Remains Valid Delay from SCKI (Notes 10, 18) l1 ns
tSKEW SDO to SCKO Skew (Note 10) l–0.4 0 0.4 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓(Note 10) l0 ns
tEN Bus Enable Time After CS↓l50 ns
tDIS Bus Relinquish Time After CS↑l15 ns
LTC2341-18
8
234118f
For more information www.linear.com/LTC2341-18
CMOS Timings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: VDDLBYP is the output of an internal voltage regulator, and should
only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND,
as described in the Pin Functions section. Do not connect this pin to any
external circuitry.
Note 4: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
currents of up to 100mA below ground or above VDD or OVDD without
latch-up.
Note 5: VDD = 5V unless otherwise specified.
Note 6: Recommended operating conditions.
Note 7: Exceeding these limits on one channel may corrupt conversion
results on the other channel. Refer to Absolute Maximum Ratings section
for pin voltage limits related to device reliability.
Note 8: VDD = 5V, OVDD = 2.5V, fSMPL = 666ksps, internal reference and
buffer, fully differential input signal drive in SoftSpan ranges 7 and 6,
bipolar input signal drive in SoftSpan ranges 3 and 2, unipolar input signal
drive in SoftSpan ranges 5, 4 and 1, unless otherwise specified.
Note 9: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 10: Guaranteed by design, not subject to test.
Note 11: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error
is the offset voltage measured from –0.5LSB when the output code
flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111.
Full-scale error for these SoftSpan ranges is the worst-case deviation of
the first and last code transitions from ideal and includes the effect of
offset error. For unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is
the offset voltage measured from 0.5LSB when the output code flickers
between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Full-
scale error for these SoftSpan ranges is the worst-case deviation of the
last code transition from ideal and includes the effect of offset error.
Note 12: All specifications in dB are referred to a full-scale input in the
relevant SoftSpan input range, except for crosstalk, which is referred to
the crosstalk injection signal amplitude.
Note 13: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 14: When REFBUF is overdriven, the internal reference buffer must
be disabled by setting REFIN = 0V.
Note 15: IREFBUF varies proportionally with sample rate and the number of
active channels.
Note 16: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
and OVDD = 5.25V.
Note 17: A tSCKI period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising edge capture.
Note 18: VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
aDc TiMing characTerisTics
Figure 1. Voltage Levels for Timing Specifications
LVDS Timings (Differential)
0.8 • OVDD
0.2 • OVDD
50% 50%
234118 F01
0.2 • OVDD
0.8 • OVDD
0.2 • OVDD
0.8 • OVDD
tDELAY
tWIDTH
tDELAY
+200mV
–200mV
0V 0V
234118 F01b
–200mV
+200mV
–200mV
+200mV
tDELAY
tWIDTH
tDELAY
LTC2341-18
9
234118f
For more information www.linear.com/LTC2341-18
Typical perForMance characTerisTics
Integral Nonlinearity
vs Output Code and Range
Integral Nonlinearity
vs Output Code and Range
Integral Nonlinearity
vs Output Code and Range
Integral Nonlinearity
vs Output Code
DC Histogram (Zero-Scale) DC Histogram (Near Full-Scale)
Integral Nonlinearity
vs Output Code and Channel
Differential Nonlinearity
vs Output Code and Channel
TA = 25°C, VDD=5V, OVDD=2.5V, Internal
Reference and Buffer (VREFBUF =4.096V), fSMPL = 666ksps, unless otherwise noted.
32k Point FFT fSMPL=666kHz,
fIN=2kHz
±4.096V RANGE
σ = 1.5
CODE
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
20000
40000
60000
80000
COUNTS
234118 G07
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
ALL CHANNELS
OUTPUT CODE
–131072
–65536
0
65536
131072
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL ERROR (LSB)
234118 G01
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
SNR = 95.1dB
THD = –111dB
SINAD = 95.0dB
SFDR = 112dB
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 G09
ALL RANGES
ALL CHANNELS
OUTPUT CODE
0
65536
131072
196608
262144
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
1.00
DNL ERROR (LSB)
234118 G02
±2.048V AND ±2V
RANGES
BIPOLAR DRIVE (IN
–
= 2.5V)
ONE CHANNEL
OUTPUT CODE
–131072
–65536
0
65536
131072
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL ERROR (LSB)
234118 G03
±4.096V AND ±4V
RANGES
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
ONE CHANNEL
±2.048V AND ±2V
RANGES
OUTPUT CODE
–131072
–65536
0
65536
131072
–4.0
–3.0
–2.0
–1.0
0
1.0
2.0
3.0
4.0
INL ERROR (LSB)
234118 G04
0V TO 4.096V AND 0V TO 4V RANGES
UNIPOLAR DRIVE (IN
–
= 0V)
ONE CHANNEL
0V TO 2.048V RANGE
OUTPUT CODE
0
65536
131072
196608
262144
–4.0
–3.0
–2.0
–1.0
0
1.0
2.0
3.0
4.0
INL ERROR (LSB)
234118 G05
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
±4.096V RANGE
ARBITRARY DRIVE
IN
+
/IN
–
COMMON MODE
SWEPT 0V TO 5V
OUTPUT CODE
–131072
–65536
0
65536
131072
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL ERROR (LSB)
234118 G06
σ = 2.2
±4.096V RANGE
σ = 1.6
CODE
131052
131056
131060
131064
131068
131072
0
20000
40000
60000
80000
COUNTS
234118 G08
LTC2341-18
10
234118f
For more information www.linear.com/LTC2341-18
Typical perForMance characTerisTics
32k Point FFT fSMPL = 666kHz,
fIN=2kHz
SNR, SINAD vs VREFBUF,
fIN=2kHz
THD, Harmonics vs VREFBUF,
fIN=2kHz
SNR, SINAD
vs Input Frequency
THD, Harmonics
vs Input Frequency
THD, Harmonics vs Input
Common Mode, fIN = 2kHz
32k Point Arbitrary Two-Tone FFT
fSMPL=666kHz, IN+=–7dBFS 2kHz
Sine, IN–=–7dBFS 3.3kHz Sine
SNR, SINAD vs Input Level,
fIN=2kHz
CMRR vs Input Frequency and
Channel
TA = 25°C, VDD=5V, OVDD=2.5V, Internal
Reference and Buffer (VREFBUF =4.096V), fSMPL = 666ksps, unless otherwise noted.
SFDR = 112dB
SNR = 95.2dB
±4.096V RANGE
ARBITRARY DRIVE
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 G10
0V TO 4.096V RANGE
UNIPOLAR DRIVE (IN
–
= 0V)
SNR = 89.3dB
THD = –113dB
SINAD = 89.2dB
SFDR = 113dB
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 G11
SNR
SINAD
±V
REFBUF
RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
REFBUF VOLTAGE (V)
2.5
3
3.5
4
4.5
5
90
92
94
96
98
100
SNR, SINAD (dBFS)
234118 G12
THD
2ND
3RD
±V
REFBUF
RANGE
FULLY DIFFERENIAL DRIVE (IN
–
= –IN
+
)
REFBUF VOLTAGE (V)
2.5
3
3.5
4
4.5
5
–140
–135
–130
–125
–120
–115
–110
–105
–100
THD, HARMONICS (dBFS)
234118 G13
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
SNR
SINAD
FREQUENCY (Hz)
100
1k
10k
100k
1M
78
82
86
90
94
98
102
106
SNR, SINAD (dBFS)
234418 G14
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
THD
2ND
3RD
FREQUENCY (Hz)
100
1k
10k
100k
1M
–130
–120
–110
–100
–90
–80
–70
–60
THD, HARMONICS (dBFS)
234118 G15
2ND
THD
3RD
±4.096V RANGE
1V
P–P
FULLY DIFFERENTIAL DRIVE
INPUT COMMON MODE (V)
0
1
2
3
4
5
–150
–140
–130
–120
–110
–100
THD, HARMONICS (dBFS)
234118 G16
SNR
SINAD
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
INPUT LEVEL (dBFS)
–40
–30
–20
–10
0
95.0
95.2
95.4
95.6
95.8
96.0
SNR, SINAD (dBFS)
234118 G17
±4.096V RANGE
IN
+
= IN
–
= 3.6V
P–P
SINE
ALL CHANNELS
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
60
70
80
90
100
110
120
130
CMRR (dB)
234118 G18
LTC2341-18
11
234118f
For more information www.linear.com/LTC2341-18
Typical perForMance characTerisTics
SNR, SINAD vs Temperature,
fIN=2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
INL, DNL vs Temperature
Positive Full-Scale Error vs
Temperature and Channel
Negative Full-Scale Error vs
Temperature and Channel
Zero-Scale Error vs
Temperature and Channel
Crosstalk vs Input Frequency and
Channel
TA = 25°C, VDD=5V, OVDD=2.5V, Internal
Reference and Buffer (VREFBUF =4.096V), fSMPL = 666ksps, unless otherwise noted.
Supply Current vs Temperature
Power-Down Current
vs Temperature
CH1
±4.096V RANGE
IN0
+
= –IN0
–
= 3.6V
P–P
SINE
ALL CHANNELS CONVERTING
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
–145
–140
–135
–130
–125
–120
–115
–110
–105
–100
–95
–90
CROSSTALK (dB)
234118 G19
SNR
SINAD
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
92.0
92.5
93.0
93.5
94.0
94.5
95.0
95.5
96.0
96.5
97.0
SNR, SINAD (dBFS)
234118 G20
THD
2ND
3RD
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–130
–125
–120
–115
–110
–105
–100
THD, HARMONICS (dBFS)
234118 G21
MAX INL
MIN INL
MAX DNL
MIN DNL
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL, DNL ERROR (LSB)
234118 G22
±4.096V RANGE
REFBUF OVERDRIVEN
V
REFBUF
= 4.096V
ALL CHANNELS
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–0.100
–0.075
–0.050
–0.025
0.000
0.025
0.050
0.075
0.100
FULL-SCALE ERROR (%)
234118 G23
±4.096V RANGE
REFBUF OVERDRIVEN
V
REFBUF
= 4.096V
ALL CHANNELS
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–0.100
–0.075
–0.050
–0.025
0.000
0.025
0.050
0.075
0.100
FULL–SCALE ERROR (%)
234118 G24
±4.096V RANGE
ALL CHANNELS
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–10
–8
–6
–4
–2
0
2
4
6
8
10
ZERO-SCALE ERROR (LSB)
234118 G25
I
OVDD
I
VDD
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
–4
–2
0
2
4
6
8
10
12
14
16
18
20
SUPPLY CURRENT (mA)
234118 G26
I
OVDD
I
VDD
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
0.01
0.1
1
10
100
1000
POWER-DOWN CURRENT (µA)
234118 G27
LTC2341-18
12
234118f
For more information www.linear.com/LTC2341-18
Typical perForMance characTerisTics
Internal Reference Output
vs Temperature PSRR vs Frequency
Supply Current vs Sampling Rate
Power Dissipation vs Sampling
Rate, N Channels Enabled
Step Response
(Large-Signal Settling) Step Response (Fine Settling)
Offset Error vs Input Common
Mode and Channel
TA = 25°C, VDD=5V, OVDD=2.5V, Internal
Reference and Buffer (VREFBUF =4.096V), fSMPL = 666ksps, unless otherwise noted.
OV
DD
V
DD
IN
+
= IN
–
= 0V
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
50
60
70
80
90
100
110
120
130
140
150
PSRR (dB)
234118 G30
±4.096V RANGE
ALL CHANNELS
INPUT COMMON MODE (V)
0
1
2
3
4
5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
OFFSET ERROR (LSB)
234118 G28
15 UNITS
TEMPERATURE (°C)
–55
–35
–15
5
25
45
65
85
105
125
2.044
2.045
2.046
2.047
2.048
2.049
2.050
2.051
2.052
INTERNAL REFERENCE OUTPUT (V)
234118 G29
I
OVDD
I
VDD
SAMPLING FREQUENCY (kHz)
0
111
222
333
444
555
666
0
2
4
6
8
10
12
14
16
18
SUPPLY CURRENT (mA)
234118 G31
N = 1
N = 2
SAMPLING FREQUENCY (kHz)
0
200
400
600
800
1000
0
10
20
30
40
50
60
70
80
90
POWER DISSIPATION (mW)
234118 G32
±2.048V RANGE
IN
+
= 666.6398kHz
SQUARE WAVE
IN
–
= 2.048V
DRIVEN BY 50Ω SOURCE
SETTLING TIME (ns)
–100
–50
0
50
100
150
200
250
300
350
400
–131072
–98304
–65536
–32768
0
32768
65536
98304
131072
OUTPUT CODE (LSB)
234118 G33
±2.048V RANGE
IN
+
= 666.6398kHz
SQUARE WAVE
IN
–
= 2.048V
DRIVEN BY 50Ω SOURCE
SETTLING TIME (ns)
–100
–50
0
50
100
150
200
250
300
350
400
–500
–400
–300
–200
–100
0
100
200
300
400
500
DEVIATION FROM FINAL VALUE (LSB)
234118 G34
LTC2341-18
13
234118f
For more information www.linear.com/LTC2341-18
pin FuncTions
Pins that are the Same for All Digital I/O Modes
IN0+/IN0–, IN1+/IN1– (Pins 8/7, 2/1): Positive and Negative
Analog Inputs, Channels 0 and 1. The converter simultane-
ously samples and digitizes (VIN+ – VIN–) for both channels.
Wide input common mode range (0V ≤ VCM ≤ VDD) and
high common mode rejection allow the inputs to accept
a wide variety of signal swings. Full-scale input range is
determined by the channel’s SoftSpan configuration.
GND (Pins 3, 4, 5, 6, 9, 11, 20, 29, 31, 32, 33): Ground.
Solder all GND pins to a solid ground plane.
REFIN (Pin 10): Bandgap Reference Output/Reference
Buffer Input. An internal bandgap reference nominally
outputs 2.048V on this pin. An internal reference buffer
amplifies VREFIN to create the converter master reference
voltage VREFBUF = 2•VREFIN on the REFBUF pin. When
using the internal reference, bypass REFIN to GND (Pin11)
close to the pin with a 0.1μF ceramic capacitor to filter
the bandgap output noise. If more accuracy is desired,
overdrive REFIN with an external reference in the range
of 1.25V to 2.2V.
REFBUF (Pin 12): Internal Reference Buffer Output. An
internal reference buffer amplifies VREFIN to create the
converter master reference voltage VREFBUF = 2•VREFIN on
this pin, nominally 4.096V when using the internal bandgap
reference. Bypass REFBUF to GND (Pin 11) close to the
pin with a 47μF ceramic capacitor. The internal reference
buffer may be disabled by grounding its input at REFIN.
With the buffer disabled, overdrive REFBUF with an ex-
ternal reference voltage in the range of 2.5V to 5V. When
using the internal reference buffer, limit the loading of any
external circuitry connected to REFBUF to less than 10µA.
Using a high input impedance amplifier to buffer VREFBUF
to any external circuits is recommended.
PD (Pin 13): Power Down Input. When this pin is brought
high, the LTC2341-18 is powered down and subsequent
conversion requests are ignored. If this occurs during a
conversion, the device powers down once the conversion
completes. If this pin is brought high twice without an
intervening conversion, an internal global reset is initi-
ated, equivalent to a power-on-reset event. Logic levels
are determined by OVDD.
LVDS/CMOS (Pin 14): I/O Mode Select. Tie this pin to OVDD
to select LVDS I/O mode, or to ground to select CMOS I/O
mode. Logic levels are determined by OVDD.
CNV (Pin 15): Conversion Start Input. A rising edge on
this pin puts the internal sample-and-holds into the hold
mode and initiates a new conversion. CNV is not gated
by CS, allowing conversions to be initiated independent
of the state of the serial I/O bus.
BUSY (Pin 26): Busy Output. The BUSY signal indicates
that a conversion is in progress. This pin transitions low-
to-high at the start of each conversion and stays high until
the conversion is complete. Logic levels are determined
by OVDD.
VDDLBYP (Pin 28): Internal 2.5V Regulator Bypass Pin. The
voltage on this pin is generated via an internal regulator
operating off of VDD. This pin must be bypassed to GND
close to the pin with a 2.2μF ceramic capacitor. Do not
connect this pin to any external circuitry.
VDD (Pin 30): 5V Power Supply. The range of VDD is 4.75V
to 5.25V. This pin must be bypassed to GND close to the
pin with a 0.1μF ceramic capacitor.
LTC2341-18
14
234118f
For more information www.linear.com/LTC2341-18
pin FuncTions
CMOS I/O Mode
SDI+/SDI–, SDO+ (Pin 16/17, 24): LVDS Serial Data I/O.
In CMOS I/O mode, these pins are Hi-Z.
SDO0, SDO1 (Pins 18, 23): CMOS Serial Data Outputs,
Channels 0 and 1. The most recent conversion result along
with channel configuration information is clocked out onto
the SDO pins on each rising edge of SCKI. Output data
formatting is described in the Digital Interface section.
Leave unused SDO outputs unconnected. Logic levels are
determined by OVDD.
SCKI (Pin 19): CMOS Serial Clock Input. Drive SCKI with
the serial I/O clock. SCKI rising edges latch serial data in
on SDI and clock serial data out on SDO0 and SDO1. For
standard SPI bus operation, capture output data at the
receiver on rising edges of SCKI. SCKI is allowed to idle
either high or low. Logic levels are determined by OVDD.
OVDD (Pin 21): I/O Interface Power Supply. In CMOS I/O
mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD
to GND (Pin 20) close to the pin with a 0.1μF ceramic
capacitor.
SCKO (Pin 22): CMOS Serial Clock Output. SCKI rising
edges trigger transitions on SCKO that are skew-matched
to the serial output data streams on SDO0 and SDO1. The
resulting SCKO frequency is half that of SCKI. Rising and
falling edges of SCKO may be used to capture SDO data
at the receiver (FPGA) in double data rate (DDR) fashion.
For standard SPI bus operation, SCKO is not used and
should be left unconnected. SCKO is forced low at the
falling edge of BUSY. Logic levels are determined by OVDD.
SDI (Pin 25): CMOS Serial Data Input. Drive this pin with the
desired 6-bit SoftSpan configuration word (see Table1a),
latched on the rising edges of SCKI. If both channels will
be configured to operate only in SoftSpan 7, tie SDI to
OVDD. Logic levels are determined by OVDD.
CS (Pin 27): Chip Select Input. The serial data I/O bus is
enabled when CS is low and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI.
Logic levels are determined by OVDD.
LVDS I/O Mode
SDI+/SDI– (Pins 16/17): LVDS Positive and Negative Serial
Data Input. Differentially drive SDI+/SDI– with the desired
6-bit SoftSpan configuration word (see Table 1a), latched
on both the rising and falling edges of SCKI+/SCKI–. The
SDI+/SDI– input pair is internally terminated with a 100Ω
differential resistor when CS = 0.
SCKI+/SCKI– (Pins 18/19): LVDS Positive and Negative
Serial Clock Input. Differentially drive SCKI+/SCKI– with
the serial I/O clock. SCKI+/SCKI– rising and falling edges
latch serial data in on SDI+/SDI– and clock serial data out
on SDO+/SDO–. Idle SCKI+/SCKI– low, including when
transitioning CS. The SCKI+/SCKI– input pair is internally
terminated with a 100Ω differential resistor when CS = 0.
OVDD (Pin 21): I/O Interface Power Supply. In LVDS I/O
mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD
to GND (Pin 20) close to the pin with a 0.1μF ceramic
capacitor.
SCKO+/SCKO– (Pins 22/23): LVDS Positive and Negative
Serial Clock Output. SCKO+/SCKO– outputs a copy of the
input serial I/O clock received on SCKI+/SCKI–, skew-
matched with the serial output data stream on SDO+/SDO–.
Use the rising and falling edges of SCKO+/SCKO– to cap-
ture SDO+/SDO– data at the receiver (FPGA). The SCKO+/
SCKO– output pair must be differentially terminated with
a 100Ω resistor at the receiver (FPGA).
SDO+/SDO– (Pins 24/25): LVDS Positive and Negative
Serial Data Output. The most recent conversion result
along with channel configuration information is clocked
out onto SDO+/SDO– on both rising and falling edges of
SCKI+/SCKI–, beginning with channel 0. The SDO+/SDO–
output pair must be differentially terminated with a 100Ω
resistor at the receiver (FPGA).
CS (Pin 27): Chip Select Input. The serial data I/O bus is
enabled when CS is low, and is disabled and Hi-Z when
CS is high. CS also gates the external shift clock, SCKI+/
SCKI–. The internal 100Ω differential termination resistors
on the SCKI+/SCKI– and SDI+/SDI– input pairs are disabled
when CS is high. Logic levels are determined by OVDD.
LTC2341-18
15
234118f
For more information www.linear.com/LTC2341-18
conFiguraTion Tables
Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each
Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 6-Bit SoftSpan Configuration Word S[5:0]. Use
Serial Interface to Write SoftSpan Configuration Word to LTC2341-18, as shown in Figure 19
BINARY SoftSpan CODE
SS[2:0] ANALOG INPUT RANGE FULL SCALE RANGE BINARY FORMAT OF
CONVERSION RESULT
111 ±VREFBUF 2 • VREFBUF Tw o ’s Complement
110 ±VREFBUF/1.024 2 • VREFBUF/1.024 Tw o ’s Complement
101 0V to VREFBUF VREFBUF Straight Binary
100 0V to VREFBUF/1.024 VREFBUF/1.024 Straight Binary
011 ±0.5 • VREFBUF VREFBUF Tw o ’s Complement
010 ±0.5 • VREFBUF/1.024 VREFBUF/1.024 Tw o ’s Complement
001 0V to 0.5 • VREFBUF 0.5 • VREFBUF Straight Binary
000 Channel Disabled Channel Disabled All Zeros
Table 1b. Reference Configuration Table. The LTC2341-18 Supports Three Reference Configurations. Analog Input Range Scales with
the Converter Master Reference Voltage, VREFBUF
REFERENCE CONFIGURATION VREFIN VREFBUF BINARY SoftSpan CODE
SS[2:0] ANALOG INPUT RANGE
Internal Reference with
Internal Buffer 2.048V 4.096V
111 ±4.096V
110 ±4V
101 0V to 4.096V
100 0V to 4V
011 ±2.048V
010 ±2V
001 0V to 2.048V
External Reference with
Internal Buffer
(REFIN Pin Externally
Overdriven)
1.25V
(Min Value) 2.5V
111 ±2.5V
110 ±2.441V
101 0V to 2.5V
100 0V to 2.441V
011 ±1.25V
010 ±1.221V
001 0V to 1.25V
2.2V
(Max Value) 4.4V
111 ±4.4V
110 ±4.297V
101 0V to 4.4V
100 0V to 4.297V
011 ±2.2V
010 ±2.148V
001 0V to 2.2V
LTC2341-18
16
234118f
For more information www.linear.com/LTC2341-18
REFERENCE CONFIGURATION VREFIN VREFBUF BINARY SoftSpan CODE
SS[2:0] ANALOG INPUT RANGE
External Reference
Unbuffered
(REFBUF Pin
Externally Overdriven,
REFIN Pin Grounded)
0V 2.5V
(Min Value)
111 ±2.5V
110 ±2.441V
101 0V to 2.5V
100 0V to 2.441V
011 ±1.25V
010 ±1.221V
001 0V to 1.25V
0V 5V
(Max Value)
111 ±5V
110 ±4.883V
101 0V to 5V
100 0V to 4.883V
011 ±2.5V
010 ±2.441V
001 0V to 2.5V
conFiguraTion Tables
Table 1b. Reference Configuration Table (Continued). The LTC2341-18 Supports Three Reference Configurations. Analog Input Range
Scales with the Converter Master Reference Voltage, VREFBUF
LTC2341-18
17
234118f
For more information www.linear.com/LTC2341-18
FuncTional block DiagraM
CMOS I/O Mode
SDO0
SDO1
SCKO
SDI
SCKI
CS
BUSY
18-BIT
SAR ADC
CMOS
SERIAL
I/O
INTERFACE
234118 BD01
18 BITS
REFERENCE
BUFFER
REFBUFREFINGND
VDDLBYP
VDD OVDD
LTC2341-18
CONTROL
LOGIC
2.048V
REFERENCE
2.5V
REGULATOR
LVDS/CMOSPDCNV
IN0+
IN0–S/H
IN1+
IN1–S/H
2-CHANNEL MULTIPLEXER
20k 2×
LVDS I/O Mode
SDO+
SDO–
SCKO+
SCKO–
SDI+
SDI–
SCKI+
SCKI–
CS
BUSY
18-BIT
SAR ADC
LVDS
SERIAL
I/O
INTERFACE
234118 BD02
18 BITS
REFERENCE
BUFFER
REFBUFREFINGND
VDDLBYP
VDD OVDD
LTC2341-18
CONTROL
LOGIC
2.048V
REFERENCE
2.5V
REGULATOR
LVDS/CMOSPDCNV
IN0+
IN0–S/H
IN1+
IN1–S/H
2-CHANNEL MULTIPLEXER
20k 2×
LTC2341-18
18
234118f
For more information www.linear.com/LTC2341-18
TiMing DiagraM
LVDS I/O Mode
CMOS I/O Mode
1 2 3 4 5 6 7 8 9 10 11 12
S5 S3S4 S1S2 S0
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C0
0 0 C0
SS1SS2 SS0 D17
CNV
CS = PD = 0
CONVERT
DON’T CARE
ACQUIREBUSY
SDO1
SCKO
SDO0
SCKI
SDI
DON’T CARE
SAMPLE N SAMPLE N + 1
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
CHANNEL 0
CONVERSION N
CHANNEL 1
CONVERSION N
CHANNEL 1
CONVERSION N
CHANNEL 0
CONVERSION N
234118 TD01
CONVERSION RESULT
CHANNEL ID
CHANNEL ID
SoftSpan CONVERSION RESULT
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17DON’T CARE
CONVERSION RESULT SoftSpan CONVERSION RESULT
13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 2624
S5 S3S4 S1S2 S0
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17 D16 D15
CNV
(CMOS)
CS = PD = 0
234118 TD02
CONVERT
DON’T CARE
ACQUIRE
BUSY
(CMOS)
SCKO
(LVDS)
SDO
(LVDS)
SCKI
(LVDS)
SDI
(LVDS)
DON’T CARE
SAMPLE N
SAMPLE
N + 1
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
CHANNEL 0
CONVERSION N
CHANNEL 1
CONVERSION N
CONVERSION RESULT SoftSpan
42 43 44 45 46 47 48
D0 SS1SS2 SS0 D17
CHANNEL 0
CONVERSION N
CONVERSION
RESULT
SoftSpan
0 0 C0 0 0 C0
CHANNEL ID CHANNEL ID
LTC2341-18
19
234118f
For more information www.linear.com/LTC2341-18
applicaTions inForMaTion
OVERVIEW
The LTC2341-18 is an 18-bit, low noise 2-channel si-
multaneous sampling successive approximation register
(SAR) ADC with differential, wide common mode range
inputs. Using the integrated low-drift reference and buf-
fer (VREFBUF = 4.096V nominal), both channels of this
SoftSpan ADC can be independently configured on a
conversion-by-conversion basis to accept ±4.096V, 0V to
4.096V, ±2.048V, or 0V to 2.048V signals. The input signal
range may be expanded up to ±5V using an external 5V
reference. One channel may also be disabled to increase
throughput on the other channel.
The wide input common mode range and high CMRR
(105dB typical, VIN+ = VIN– = 3.6VP-P 200Hz Sine) of the
LTC2341-18 analog inputs allow the ADC to directly digi-
tize a variety of signals, simplifying signal chain design.
This input signal flexibility, combined with ±4LSB INL,
no missing codes at 18-bits, and 95dB SNR, makes the
LTC2341-18 an ideal choice for many applications requir-
ing wide dynamic range.
The LTC2341-18 supports pin-selectable SPI CMOS
(1.8V to 5V) and LVDS serial interfaces, enabling it to
communicate equally well with legacy microcontrollers
and modern FPGAs. In CMOS mode, applications may
employ one or two lanes of serial output data, allowing
the user to optimize bus width and data throughput. The
LTC2341-18 typically dissipates 74mW when converting
two analog input channels simultaneously at 666ksps
per channel throughput. An optional power-down mode
may be employed to further reduce power consumption
during inactive periods.
CONVERTER OPERATION
The LTC2341-18 operates in two phases. During the ac-
quisition phase, the sampling capacitors in both channels’
sample-and-hold (S/H) circuits connect to their respective
analog input pins and track the differential analog input
voltage (VIN+ – VIN–). A rising edge on the CNV pin transi-
tions both channels’ S/H circuits from track mode to hold
mode, simultaneously sampling the input signals on both
channels and initiating a conversion. During the conversion
phase, each channel’s sampling capacitors are connected,
one channel at a time, to an 18-bit charge redistribution
capacitor D/A converter (CDAC). The CDAC is sequenced
through a successive approximation algorithm, effectively
comparing the sampled input voltage with binary-weighted
fractions of the channel’s SoftSpan full-scale range (e.g.,
VFSR/2, VFSR/4 … VFSR/262144) using a differential
comparator. At the end of this process, the CDAC output
approximates the channel’s sampled analog input. Once
both channels have been converted in this manner, the
ADC control logic prepares the 18-bit digital output codes
from each channel for serial transfer.
TRANSFER FUNCTION
The LTC2341-18 digitizes each channel’s full-scale voltage
range into 218 levels. In conjunction with the ADC master
reference voltage, VREFBUF, a channel’s SoftSpan configu-
ration determines its input voltage range, full-scale range,
LSB size, and the binary format of its conversion result, as
shown in Tables 1a and 1b. For example, employing the
internal reference and buffer (VREFBUF = 4.096V nominal),
SoftSpan 7 configures a channel to accept a ±4.096V bi-
polar analog input voltage range, which corresponds to a
8.192V full-scale range with a 31.25μV LSB. Other SoftSpan
configurations and reference voltages may be employed to
convert both larger and smaller bipolar and unipolar input
ranges. Conversion results are output in two’s comple-
ment binary format for all bipolar SoftSpan ranges, and
in straight binary format for all unipolar SoftSpan ranges.
The ideal two’s complement transfer function is shown in
Figure2, while the ideal straight binary transfer function
is shown in Figure3.
LTC2341-18
20
234118f
For more information www.linear.com/LTC2341-18
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
234118 F02
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 – 1LSB–FSR/2
FSR = +FS – –FS
1LSB = FSR/262144
Figure 2. LTC2341-18 Two’s Complement Transfer Function
INPUT VOLTAGE (V)
OUTPUT CODE (STRAIGHT BINARY)
234118 F03
111...111
111...110
100...001
100...000
000...000
000...001
011...110
UNIPOLAR
ZERO
011...111
FSR – 1LSB0V
FSR = +FS
1LSB = FSR/262144
Figure 3. LTC2341-18 Straight Binary Transfer Function
ANALOG INPUTS
Each channel of the LTC2341-18 simultaneously samples
the voltage difference (VIN+ – VIN–) between its analog
input pins over a wide common mode input range while
attenuating unwanted signals common to both input
pins by the common-mode rejection ratio (CMRR) of
the ADC. Wide common mode input range coupled with
applicaTions inForMaTion
high CMRR allows the IN+/IN– analog inputs to swing
with an arbitrary relationship to each other, provided
both pins remain between ground and VDD. This feature
of the LTC2341-18 enables it to accept a wide variety
of signal swings, including traditional classes of analog
input signals such as pseudo-differential unipolar, pseudo-
differential bipolar, and fully differential, simplifying signal
chain design.
In all SoftSpan ranges, each channel’s analog inputs can
be modeled by the equivalent circuit shown in Figure4.
At the start of acquisition, the 80pF sampling capacitors
(CIN) connect to the analog input pins IN+/IN– through the
sampling switches, each of which has approximately 90Ω
(RIN) of on-resistance. The initial voltage on both sampling
capacitors at the start of acquisition is approximately equal
to the sampled common-mode voltage (VIN++VIN–)/2
from the prior conversion. The external circuitry connected
to IN+ and IN– must source or sink the charge that flows
through RIN as the sampling capacitors settle from their
initial voltages to the new input pin voltages over the course
of the acquisition interval. During conversion and power
down modes, the analog inputs draw only a small leakage
current. The diodes at the inputs provide ESD protection.
Figure 4. Equivalent Circuit for Differential Analog Inputs,
Single Channel Shown
IN
+
RIN
90Ω
RIN
90Ω
CIN
80pF
CIN
80pF
V
DD
VDD
BIAS
VOLTAGE
IN
–234118 F04
LTC2341-18
21
234118f
For more information www.linear.com/LTC2341-18
applicaTions inForMaTion
Bipolar SoftSpan Input Ranges
For channels configured in SoftSpan ranges 7, 6, 3, or
2, the LTC2341-18 digitizes the differential analog input
voltage (VIN+ – VIN–) over a bipolar span of ±VREFBUF,
±VREFBUF/1.024, ±0.5 • VREFBUF, or ±0.5 • VREFBUF/1.024,
respectively, as shown in Table 1a. These SoftSpan ranges
are useful for digitizing input signals where IN+ and IN–
swing above and below each other. Traditional examples
include fully differential input signals, where IN+ and
IN– are driven 180 degrees out-of-phase with respect
to each other centered around a common mode voltage
(VIN+ + VIN–)/2, and pseudo-differential bipolar input
signals, where IN+ swings above and below a reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode input range and high CMRR
of the IN+/IN– analog inputs allow them to swing with an
arbitrary relationship to each other, provided each pin
remains between ground and VDD. The output data format
for all bipolar SoftSpan ranges is two’s complement.
Unipolar SoftSpan Input Ranges
For channels configured in SoftSpan ranges 5, 4, or 1, the
LTC2341-18 digitizes the differential analog input voltage
(VIN+ – VIN–) over a unipolar span of 0V to VREFBUF, 0V
to VREFBUF/1.024, or 0V to 0.5 • VREFBUF, respectively, as
shown in Table 1a. These SoftSpan ranges are useful for
digitizing input signals where IN+ remains above IN–. A
traditional example includes pseudo-differential unipolar
input signals, where IN+ swings above a ground reference
level, driven on IN–. Regardless of the chosen SoftSpan
range, the wide common mode range and high CMRR of
the IN+/IN– analog inputs allow them to swing with an
arbitrary relationship to each other, provided each pin
remains between ground and VDD. The output data format
for all unipolar SoftSpan ranges is straight binary.
INPUT DRIVE CIRCUITS
The initial voltage on each channel’s sampling capacitors
at the start of acquisition must settle to the new input
pin voltages during the acquisition interval. The external
circuitry connected to IN+ and IN– must source or sink
the charge that flows through RIN as this settling occurs.
The LTC2341-18 sampling network RC time constant of
7.2ns implies an 18-bit settling time to a full-scale step of
approximately 13•(RIN•CIN)=94ns. The impedance and
self-settling of external circuitry connected to the analog
input pins will increase the overall settling time required.
Low impedance sources can directly drive the inputs of
the LTC2341-18 without gain error, but high impedance
sources should be buffered to ensure sufficient settling
during acquisition and to optimize the linearity and distor-
tion performance of the ADC. Settling time is an important
consideration even for DC input signals, as the voltages on
the sampling capacitors will differ from the analog input
pin voltages at the start of acquisition.
Most applications should use a buffer amplifier to drive the
analog inputs of the LTC2341-18. The amplifier provides
low output impedance, enabling fast settling of the analog
signal during the acquisition phase. It also provides isola-
tion between the signal source and the charge flow at the
analog inputs when entering acquisition.
Input Filtering
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a low-
bandwidth filter to minimize noise. The simple one-pole
RC lowpass filter shown in Figure5 is sufficient for many
applications.
At the output of the buffer, a lowpass RC filter network
formed by the 90Ω sampling switch on-resistance (RIN)
and the 80pF sampling capacitance (CIN) limits the input
bandwidth on each channel to 22MHz, which is fast enough
to allow for sufficient transient settling during acquisition
while simultaneously filtering driver wideband noise. A
buffer amplifier with low noise density should be selected
to minimize SNR degradation over this bandwidth. An
additional filter network may be placed between the buf-
fer output and ADC input to further minimize the noise
contribution of the buffer and reduce disturbances to the
buffer from ADC acquisition transients. A simple one-pole
lowpass RC filter is sufficient for many applications. It is
important that the RC time constant of this filter be small
LTC2341-18
22
234118f
For more information www.linear.com/LTC2341-18
enough to allow the analog inputs to completely settle to
18-bit resolution within the ADC acquisition time (tACQ),
as insufficient settling can limit INL and THD performance.
Also note that the minimum acquisition time varies with
sampling frequency (fSMPL) and the number of enabled
channels.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion.
NPO/COG and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Buffering Arbitrary and Fully Differential Analog Input
Signals
The wide common mode input range and high CMRR of
the LTC2341-18 allow each channel’s IN+ and IN– pins to
swing with an arbitrary relationship to each other, provided
both pins remain between ground and VDD. This unique
feature of the LTC2341-18 enables it to accept a wide
applicaTions inForMaTion
variety of signal swings, simplifying signal chain design.
In many applications, connecting a channel’s IN+ and IN–
pins directly to the existing signal chain circuitry will not
allow the channel’s sampling network to settle to 18-bit
resolution within the ADC acquisition time (tACQ). In these
cases, it is recommended that two unity-gain buffers be
inserted between the signal source and the ADC input
pins, as shown in Figure6a. Table 2 lists several amplifier
and lowpass filter combinations recommended for use
in this circuit. The LT6237 combines fast settling, high
linearity, and low offset with 1.1nV/√Hz input-referred
noise density, enabling it to achieve the full ADC data sheet
SNR and THD specifications, as shown in the FFT plots in
Figures6b to 6e. In applications where slightly degraded
SNR performance is acceptable, it is possible to drive the
LTC2341-18 using the lower-power LT6234. The LT6234
combines fast settling, good linearity, and low offset with
1.9nV/√Hz input-referred noise density, enabling it to drive
the LTC2341-18 with 1.9dB SNR loss compared with the
LT6237 when a 24.9Ω, 1nF filter is employed. As shown in
Table 2, the LT6237 may be used without a lowpass filter
at a loss of ≤1dB SNR due to increased wideband noise.
Figure 5. Unipolar Signal Chain with Input Filtering
Table 2. Recommended Amplifier and Filter Combinations for the Buffer Circuits in Figures 6a and 9. AC Performance Measured
Using Circuit in Figure 6a, ±4.096V Range for Fully Differential Input Drive, ±2.048V Range for Bipolar Input Drive
AMPLIFIER RFILT
(Ω)
CFILT
(nF) INPUT SIGNAL DRIVE SNR
(dB)
THD
(dB)
SINAD
(dB)
SFDR
(dB)
½ LT6237 24.9 1 FULLY DIFFERENTIAL 95.2 −114 95.2 115
½ LT6234 24.9 1 FULLY DIFFERENTIAL 93.3 −114 93.3 115
½ LT6237 24.9 1 BIPOLAR 89.3 –110 89.3 111
½ LT6234 24.9 1 BIPOLAR 87.6 −110 87.6 111
½ LT6237 0 0 BIPOLAR 88.6 −110 88.6 111
½ LT6234 0 0 BIPOLAR 83.3 −109 83.3 111
–
+
LTC2341-18
234118 F05
ONLY CHANNEL 0 SHOWN FOR CLARITY
5V
0V
UNIPOLAR
INPUT SIGNAL
IN0+
IN0–
BUFFER
AMPLIFIER
LOWPASS
SIGNAL FILTER
10nF
160Ω
BW = 100kHz
LTC2341-18
23
234118f
For more information www.linear.com/LTC2341-18
applicaTions inForMaTion
6V
–2V
LTC2341-18
234118 F06a
ONLY CHANNEL 0 SHOWN FOR CLARITY
–
+
–
+
0.1µF
47µF
IN0+
IN0–
AMPLIFIER
AMPLIFIER REFINREFBUF
OPTIONAL
LOWPASS FILTERS
CFILT
CFILT
RFILT
RFILT
IN+
IN–
DIFFERENTIAL INPUTS
IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
5V
0V
FULLY
DIFFERENTIAL
5V
0V
BIPOLAR
5V
0V
ARBITRARY
5V
0V
UNIPOLAR
Figure 6a. Buffering Arbitrary, Fully Differential, Bipolar, and Unipolar Signals.
See Table 2 For Recommended Amplifier and Filter Combinations
Figure 6b. Two-Tone Test. IN+ = –7dBFS 2kHz Sine, IN– = –7dBFS
3.3kHz Sine, 32k Point FFT, fSMPL = 666ksps. Circuit Shown in
Figure 6a with LT6237 Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
Arbitrary Drive Fully Differential Drive
Bipolar Drive Unipolar Drive
Figure 6c. IN+/IN– = –1dBFS 2kHz Fully Differential Sine, Common
Mode = 2.5V, 32k Point FFT, fSMPL = 666ksps. Circuit Shown in
Figure 6a with LT6237 Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
Figure 6d. IN+ = –1dBFS 2kHz Bipolar Sine, IN– = 2.5V, 32k Point
FFT, fSMPL = 666ksps. Circuit Shown in Figure 6a with LT6237
Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
Figure 6e. IN+ = –1dBFS 2kHz Unipolar Sine, IN– = 0V, 32k Point
FFT, fSMPL = 666ksps. Circuit Shown in Figure 6a with LT6237
Amplifiers, RFILT = 24.9Ω, CFILT = 1nF
SFDR = 114dB
SNR = 95.3dB
±4.096V RANGE
ARBITRARY DRIVE
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 F06b
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
SNR = 95.3dB
THD = –113dB
SINAD = 95.3dB
SFDR = 116dB
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 F06c
±2.048V RANGE
BIPOLAR DRIVE (IN
–
= 2.5V)
SNR = 89.5dB
THD = –110dB
SINAD = 89.5dB
SFDR = 112dB
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 F06d
0V TO 4.096V RANGE
UNIPOLAR DRIVE (IN
–
= 0V)
SNR = 89.4dB
THD = –112dB
SINAD = 89.3dB
SFDR = 114dB
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 F06e
LTC2341-18
24
234118f
For more information www.linear.com/LTC2341-18
The two-tone test shown in Figure6b demonstrates the
arbitrary input drive capability of the LTC2341-18. This test
simultaneously drives IN+ with a −7dBFS 2kHz single-ended
sine wave and IN− with a −7dBFS 3.3kHz single-ended sine
wave. Together, these signals sweep the analog inputs
across a wide range of common mode and differential
mode voltage combinations, similar to the more general
arbitrary input signal case. They also have a simple spec-
tral representation. An ideal differential converter with no
common-mode sensitivity will digitize this signal as two
−7dBFS spectral tones, one at each sine wave frequency.
The FFT plot in Figure6b demonstrates the LTC2341-18
response approaches this ideal, with 114dB of SFDR
limited by the converter's second harmonic distortion
response to the 3.3kHz sine wave on IN+.
The ability of the LTC2341-18 to accept arbitrary signal
swings over a wide input common mode range with high
CMRR can simplify application solutions. Figure7 depicts
one way of using the LTC2341-18 to digitize signals of this
type. The two channels of the LTC2341-18 simultaneously
sense the voltage on and bidirectional current through a
sense resistor over a wide common mode range. In many
applications of this type, the impedance of the external
circuitry is low enough that the ADC sampling network
can fully settle without buffering.
The common mode input range of the LTC2341-18 includes
VDD, allowing the circuit shown in Figure8a to amplify and
measure a load current (ILOAD) from a single 5V supply.
Figure 8b shows a measured transient supply current
step of an LTC3207 LED driver load. Note the LTC6252
supplies limit the usable current sense range of this circuit
to 50mA to 450mA.
Figure9a illustrates a more general method of amplifying
an input signal. The amplifier stage provides a differential
gain of approximately 10V/V to the desired sensor signal
while the unwanted common mode signal is attenuated
by the ADC CMRR. Figure9b shows measured CMRR
performance of this solution, which is competitive with
the best commercially available instrumentation amplifiers.
applicaTions inForMaTion
Figure 7. Simultaneously Sense Voltage (CH0) and Current
(CH1) Over a Wide Common Mode Range
Figure 8a. Sense 50mA to 450mA Current from Single 5V
Supply with Amplification
Figure 8b. Transient Supply Current Step Measured Using
Circuit in Figure 8a Loaded with LTC3207 LED Driver
LTC2341-18
234118 F07
0.1µF
47µF
0V ≤ VS1 ≤ 5V
0V ≤ V
S2
≤ 5V
VS1 – VS2
R
SENSE
ISENSE =
IN0+
IN0–
IN1+
IN1–
REFINREFBUF
ISENSE
R
SENSE
VS2
VS1
0V TO 4.096V RANGE
TIME (µs)
0
10
20
30
40
50
80
100
120
140
160
180
200
I
LOAD
(mA)
234118 F08b
5V
LTC2341-18
234118 F08a
ONLY CHANNEL 0 SHOWN FOR CLARITY
0.1µF
47µF
IN0+
IN0–
VDD
REFINREFBUF
LTC6252
I
LOAD
5V
2.49k
274Ω
–
+
1Ω
LOAD
LTC2341-18
25
234118f
For more information www.linear.com/LTC2341-18
Buffering Single-Ended Analog Input Signals
While the circuit shown in Figure6a is capable of buffering
single-ended input signals, the circuit shown in Figure10
is preferable when the single-ended signal reference level
is inherently low impedance and doesn't require buffering.
This circuit eliminates one driver and lowpass filter, reduc-
ing part count, power dissipation, and SNR degradation
due to driver noise. Using the recommended driver and
filter combinations in Table 2, the performance of this
circuit with single-ended input signals is on par with the
performance of the circuit in Figure6a.
ADC REFERENCE
As shown previously in Table 1b, the LTC2341-18 supports
three reference configurations. The first uses both the in-
ternal bandgap reference and reference buffer. The second
externally overdrives the internal reference but retains the
internal buffer, which isolates the external reference from
ADC conversion transients. This configuration is ideal
for sharing a single precision external reference across
multiple ADCs. The third disables the internal buffer and
overdrives the REFBUF pin externally.
Internal Reference with Internal Buffer
The LTC2341-18 has an on-chip, low noise, low drift
(20ppm/°C maximum), temperature compensated band-
gap reference that is factory trimmed to 2.048V. The
reference output connects through a 20kΩ resistor to
applicaTions inForMaTion
Figure 9b. CMRR vs Input Frequency. Circuit Shown in Figure 9a
Figure 9a. Digitize Differential Signals with High CMRR
Figure 10. Buffering Single-Ended Input Signals. See Table 2 For Recommended
Amplifier and Filter Combinations
±4.096V RANGE
IN
+
= IN
–
= 5V
pp
SINE
FREQUENCY (Hz)
10
100
1k
10k
100k
80
90
100
110
120
130
140
150
CMRR (dB)
234118 F09b
6V
–2V
LTC2341-18
234118 F09a
ONLY CHANNEL 0 SHOWN FOR CLARITY
+
–
+
–
0.1µF
47µF
IN0+
IN0–
½ LT6237
½ LT6237
REFINREFBUF
LOWPASS FILTERS
BW ~ 6.4MHz
1nF
1nF
24.9Ω
24.9Ω
549Ω
IN
+
IN
–
2.49k
2.49k
LTC2341-18
234118 F10
ONLY CHANNEL 0 SHOWN FOR CLARITY
–
+
0.1µF
47µF
IN0+
IN0–
AMPLIFIER
REFINREFBUF
OPTIONAL
LOWPASS FILTER
CFILT
RFILT
6V
–2V
IN+
IN–
5V
0V
UNIPOLAR
LTC2341-18
26
234118f
For more information www.linear.com/LTC2341-18
the REFIN pin, which serves as the input to the on-chip
reference buffer, as shown in Figure11a. When employing
the internal bandgap reference, the REFIN pin should be
bypassed to GND (Pin 11) close to the pin with a 0.1μF
ceramic capacitor to filter wideband noise. The reference
buffer amplifies VREFIN to create the converter master
reference voltage VREFBUF = 2•VREFIN on the REFBUF pin,
nominally 4.096V when using the internal bandgap refer-
ence. Bypass REFBUF to GND (Pin 11) close to the pin with
at least a 47μF ceramic capacitor (X7R, 10V, 1210 size or
X5R, 10V, 0805 size) to compensate the reference buffer,
absorb transient conversion currents, and minimize noise.
External Reference with Internal Buffer
If more accuracy and/or lower drift is desired, REFIN can
be easily overdriven by an external reference since 20kΩ
of resistance separates the internal bandgap reference
output from the REFIN pin, as shown in Figure11b. The
valid range of external reference voltage overdrive on the
REFIN pin is 1.25V to 2.2V, resulting in converter mas-
ter reference voltages VREFBUF between 2.5V and 4.4V,
respectively. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power, and high
accuracy, the LTC6655-2.048 is well suited for use with the
LTC2341-18 when overdriving the internal reference. The
LTC6655-2.048 offers 0.025% (maximum) initial accuracy
and 2ppm/°C (maximum) temperature coefficient for high
precision applications. The LTC6655-2.048 is fully speci-
fied over the H-grade temperature range, complementing
the extended temperature range of the LTC2341-18 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7µF to 100µF
ceramic capacitor close to the REFIN pin is recommended.
External Reference with Disabled Internal Buffer
The internal reference buffer supports VREFBUF = 4.4V
maximum. By grounding REFIN, the internal buffer may
be disabled allowing REFBUF to be overdriven with an
external reference voltage between 2.5V and 5V, as shown
in Figure11c. Maximum input signal swing and SNR are
achieved by overdriving REFBUF using an external 5V
reference. The buffer feedback resistors load the REFBUF
pin with 13kΩ even when the reference buffer is disabled.
applicaTions inForMaTion
234118 F11a
47µF
6.5k
20k
LTC2341-18
REFERENCE
BUFFER
REFBUF
REFIN
GND
BANDGAP
REFERENCE
6.5k
0.1µF
234118 F11b
47µF
6.5k
20k
LTC2341-18
REFERENCE
BUFFER
REFBUF
REFIN
GND
BANDGAP
REFERENCE
6.5k
2.7µF
LTC6655-2.048
Figure 11a. Internal Reference with Internal Buffer Configuration
Figure 11b. External Reference with Internal Buffer Configuration
234118 F11c
47µF
6.5k
20k
LTC2341-18
REFERENCE
BUFFER
REFBUF
REFIN
GND
BANDGAP
REFERENCE
6.5k
LTC6655-5
Figure 11c. External Reference with Disabled Internal
Buffer Configuration
LTC2341-18
27
234118f
For more information www.linear.com/LTC2341-18
The LTC6655-5 offers the same small size, accuracy, drift,
and extended temperature range as the LTC6655-2.048,
and achieves a typical SNR of 96.5dB when paired with
the LTC2341-18. Bypass the LTC6655-5 to GND (Pin 11)
close to the REFBUF pin with at least a 47μF ceramic ca-
pacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to
absorb transient conversion currents and minimize noise.
The LTC2341-18 converter draws a charge (QCONV) from
the REFBUF pin during each conversion cycle. On short
time scales most of this charge is supplied by the external
REFBUF bypass capacitor, but on longer time scales all of
the charge is supplied by either the reference buffer, or
when the internal reference buffer is disabled, the external
reference. This charge draw corresponds to a DC current
equivalent of IREFBUF = QCONV•fSMPL, which is proportional
to sample rate. In applications where a burst of samples
is taken after idling for long periods of time, as shown in
Figure12, IREFBUF quickly transitions from approximately
0.4mA to 1.5mA (VREFBUF = 5V, fSMPL=666kHz). This
current step triggers a transient response in the external
reference that must be considered, since any deviation
in VREFBUF affects converter accuracy. If an external
reference is used to overdrive REFBUF, the fast settling
LTC6655 family of references is recommended.
Internal Reference Buffer Transient Response
For optimum performance in applications employing burst
sampling, the external reference with internal reference
buffer configuration should be used. The internal reference
buffer incorporates a proprietary design that minimizes
movements in VREFBUF when responding to a burst of
conversions following an idle period. Figure13 compares
the burst conversion response of the LTC2341-18 with an
applicaTions inForMaTion
CNV
IDLE
PERIOD
IDLE
PERIOD
234118 F12
Figure 12. CNV Waveform Showing Burst Sampling
input near full scale for two reference configurations. The
first configuration employs the internal reference buffer
with REFIN externally overdriven by an LTC6655-2.048,
while the second configuration disables the internal ref-
erence buffer and overdrives REFBUF with an external
LTC6655-4.096. In both cases REFBUF is bypassed to
GND with a 47µF ceramic capacitor.
DYNAMIC PERFORMANCE
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion, and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2341-18 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Figure 13. Burst Conversion Response of the LTC2341-18,
fSMPL=666ksps
INTERNAL REFERENCE BUFFER
EXTERNAL REFERENCE ON REFBUF
±4.096V RANGE
IN
+
= 4V
IN
–
= 0V
TIME (µs)
0
100
200
300
400
500
–5
0
5
10
15
20
DEVIATION FROM FINAL VALUE (LSB)
234118 F13
LTC2341-18
28
234118f
For more information www.linear.com/LTC2341-18
applicaTions inForMaTion
Figure 14. 32k Point FFT fSMPL = 666ksps, fIN = 2kHz
POWER CONSIDERATIONS
The LTC2341-18 provides two power supply pins: the 5V
core power supply (VDD) and the digital input/output (I/O)
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2341-18 to communicate with CMOS logic
operating between 1.8V and 5V, including 2.5V and 3.3V
systems. When using LVDS I/O mode, the range of OVDD
is 2.375V to 5.25V.
Power Supply Sequencing
The LTC2341-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2341-18 has
an internal power-on-reset (POR) circuit which resets the
converter on initial power-up and whenever VDD drops
below 2V. Once the supply voltage re-enters the nominal
supply voltage range, the POR reinitializes the ADC. No
conversions should be initiated until at least 10ms after
a POR event to ensure the initialization period has ended.
When employing the internal reference buffer, allow 200ms
for the buffer to power up and recharge the REFBUF bypass
capacitor. Any conversion initiated before these times will
produce invalid results.
±4.096V RANGE
FULLY DIFFERENTIAL DRIVE (IN
–
= –IN
+
)
SNR = 95.1dB
THD = –111dB
SINAD = 95.0dB
SFDR = 112dB
FREQUENCY (kHz)
0
111
222
333
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
234118 F14
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies below half the sampling frequency, exclud-
ing DC. Figure14 shows that the LTC2341-18 achieves a
typical SINAD of 95.0dB in the ±4.096V range at a 666kHz
sampling rate with a fully differential 2kHz input signal.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure14 shows
that the LTC2341-18 achieves a typical SNR of 95.1dB in
the ±4.096V range at a 666kHz sampling rate with a fully
differential 2kHz input signal.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD =20log V2
2+V3
2+V4
2...VN
2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics, respectively. Figure 14 shows
that the LTC2341-18 achieves a typical THD of –111dB
(N=6) in the ±4.096V range at a 666kHz sampling rate
with a fully differential 2kHz input signal.
LTC2341-18
29
234118f
For more information www.linear.com/LTC2341-18
TIMING AND CONTROL
CNV Timing
The LTC2341-18 sampling and conversion is controlled by
CNV. A rising edge on CNV transitions both channels’ S/H
circuits from track mode to hold mode, simultaneously
sampling the input signals on both channels and initiat-
ing a conversion. Once a conversion has been started, it
cannot be terminated early except by resetting the ADC,
as discussed in the Reset Timing section. For optimum
performance, drive CNV with a clean, low jitter signal and
avoid transitions on data I/O lines leading up to the rising
edge of CNV. Additionally, to minimize channel-to-channel
crosstalk, avoid high slew rates on the analog inputs for
100ns before and after the rising edge of CNV. Converter
status is indicated by the BUSY output, which transitions
low-to-high at the start of each conversion and stays high
until the conversion is complete. Once CNV is brought high
to begin a conversion, it should be returned low between
40ns and 60ns later or after the falling edge of BUSY to
minimize external disturbances during the internal conver-
sion process. If CNV is returned low after the falling edge
of BUSY, it should be held low for at least 410ns before
bringing it high again, since the converter acquisition
time (tACQ) is set by the CNV low time (tCNVL) in this case.
Internal Conversion Clock
The LTC2341-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 550 • N – 40ns
with N channels enabled. With a minimum acquisition time
of 410ns when converting two channels simultaneously,
throughput performance of 666ksps is guaranteed without
any external adjustments.
Power Down Mode
When PD is brought high, the LTC2341-18 is powered
down and subsequent conversion requests are ignored. If
this occurs during a conversion, the device powers down
once the conversion completes. In this mode, the device
draws only a small regulator standby current resulting in a
typical power dissipation of 0.33mW. To exit power down
mode, bring the PD pin low and wait at least 10ms before
initiating a conversion. When employing the internal refer-
ence buffer, allow 200ms for the buffer to power up and
recharge the REFBUF bypass capacitor. Any conversion
initiated before these times will produce invalid results.
Reset Timing
A global reset of the LTC2341-18, equivalent to a power-
on-reset event, may be executed without needing to cycle
the supplies. This feature is useful when recovering from
system-level events that require the state of the entire sys-
tem to be reset to a known synchronized value. To initiate
a global reset, bring PD high twice without an intervening
conversion, as shown in Figure15. The reset event is trig-
gered on the second rising edge of PD, and asynchronously
ends based on an internal timer. Reset clears all serial data
output registers and restores the internal SoftSpan configu-
ration register default state of both channels in SoftSpan7.
If reset is triggered during a conversion, the conversion is
immediately halted. The normal power down behavior as-
sociated with PD going high is not affected by reset. Once
PD is brought low, wait at least 10ms before initiating a
conversion. When employing the internal reference buffer,
allow 200ms for the buffer to power up and recharge the
REFBUF bypass capacitor. Any conversion initiated before
these times will produce invalid results.
applicaTions inForMaTion
CNV
tCONV
tCNVH
tPDH
tPDL
BUSY
RESET RESET TIME
SET INTERNALLY
SECOND RISING EDGE OF
PD TRIGGERS RESET
PD tWAKE
234118 F15
Figure 15. Reset Timing for the LTC2341-18
LTC2341-18
30
234118f
For more information www.linear.com/LTC2341-18
Auto Nap Mode
The LTC2341-18 automatically enters nap mode after a
conversion has finished and completely powers up once a
new conversion is initiated on the rising edge of CNV. Auto
nap mode causes the power dissipation of the LTC2341-
18 to decrease as the sampling frequency is reduced,
as shown in Figure16. This decrease in average power
dissipation occurs because a portion of the LTC2341-18
circuitry is turned off during nap mode, and the fraction
of the conversion cycle (tCYC) spent napping increases as
the sampling frequency (fSMPL) is decreased.
applicaTions inForMaTion
Serial CMOS I/O Mode
As shown in Figure17, in CMOS I/O mode the serial data
bus consists of a serial clock input, SCKI, serial data input,
SDI, serial clock output, SCKO, and two lanes of serial
data output, SDO0 and SDO1. Communication with the
LTC2341-18 across this bus occurs during predefined
data transaction windows. Within a window, the device
accepts 6-bit SoftSpan configuration words for the next
conversion on SDI and outputs 24-bit packets containing
conversion results and channel configuration information
from the previous conversion on SDO0 and SDO1. New
data transaction windows open 10ms after powering up
or resetting the LTC2341-18, and at the end of each con-
version on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
a minimum tQUIET time of 20ns prior to the start of the
next conversion, as shown in Figure17. New SoftSpan
configuration words are only accepted within this recom-
mended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
next conversion, but this will degrade conversion accuracy
and therefore is not recommended.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SCKO is forced low and
SDO0 and SDO1 are updated with the latest conversion
results from analog input channels 0 and 1, respectively.
Rising edges on SCKI serially clock conversion results
and analog input channel configuration information out
on SDO0 and SDO1 and trigger transitions on SCKO that
are skew-matched to the data on SDO0 and SDO1. The
resulting SCKO frequency is half that of SCKI. SCKI rising
edges also latch SoftSpan configuration words provided on
SDI, which are used to program the internal 6-bit SoftSpan
configuration register. See the section Programming the
SoftSpan Configuration Register in CMOS I/O Mode for
further details. SCKI is allowed to idle either high or low
in CMOS I/O mode. As shown in Figure18, the CMOS
bus is enabled when CS is low and is disabled and Hi-Z
when CS is high, allowing the bus to be shared across
multiple devices.
Figure 16. Power Dissipation of the LTC2341-18
Decreases with Decreasing Sampling Frequency
I
OVDD
I
VDD
SAMPLING FREQUENCY (kHz)
0
111
222
333
444
555
666
0
2
4
6
8
10
12
14
16
18
SUPPLY CURRENT (mA)
234118 F16
DIGITAL INTERFACE
The LTC2341-18 features CMOS and LVDS serial interfaces,
selectable using the LVDS/CMOS pin. The flexible OVDD
supply allows the LTC2341-18 to communicate with any
CMOS logic operating between 1.8V and 5V, including
2.5V and 3.3V systems, while the LVDS interface sup-
ports low noise digital designs. In CMOS mode, applica-
tions may employ either one or two lanes of serial data
output, allowing the user to optimize bus width and data
throughput. Together
, these I/O interface options enable
the LTC2341-18 to communicate equally well with legacy
microcontrollers and modern FPGAs.
LTC2341-18
31
234118f
For more information www.linear.com/LTC2341-18
applicaTions inForMaTion
0 0 C0
0 0 C0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S5 S4 S3 S2 S1 S0
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17
CNV
CS = PD = 0
DON’T CARE
tACQ
BUSY
SDO1
SCKO
SDO0
SCKI
SDI
DON’T CARE
SAMPLE N
RECOMMENDED DATA TRANSACTION WINDOW
SAMPLE N + 1
SOFTSPAN CONFIGURATION WORD FOR CONVERSION N + 1
CHANNEL 0
24-BIT PACKET
CONVERSION N
CHANNEL 1
24-BIT PACKET
CONVERSION N
CHANNEL 1
24-BIT PACKET
CONVERSION N
CHANNEL 0
24-BIT PACKET
CONVERSION N
234118 TD01
tHSDISCKI
CONVERSION RESULT SOFTSPAN CONVERSION RESULT
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17DON’T CARE
CONVERSION RESULT SOFTSPAN CONVERSION RESULT
tSSDISCKI tSCKIH
tBUSYLH
tSCKIL
tHSDOSCKI
tDSDOSCKI
tSCKI
tQUIET
tDSDOBUSYL
tCNVH
tSKEW
tCONV
tCNVL
tCYC
CHANNEL ID
CHANNEL ID
Figure 17. Serial CMOS I/O Mode
Figure 18. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS
CS
PD = 0
DON’T CARE
BUSY
SDO1
SCKO
SDO0
SCKI
SDI
DON’T CARE
DON’T CARE
DON’T CARE
234118 F18
Hi-Z
Hi-Z CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET
(PARTIAL)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
CHANNEL 1 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 0 PACKET
(PARTIAL)
NEW SoftSpan CONFIGURATION WORD
(OVERWRITES INTERNAL CONFIG REGISTER)
TWELVE ALL-ZERO WORDS AND ONE PARTIAL WORD
(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)
tEN tDIS
LTC2341-18
32
234118f
For more information www.linear.com/LTC2341-18
The data on SDO0 and SDO1 are grouped into 24-bit
packets consisting of an 18-bit conversion result, fol-
lowed by two zeros, 1-bit analog channel ID, and 3-bit
SoftSpan code, all presented MSB first. As suggested in
Figures17 and 18, each SDO lane outputs these packets
for both analog input channels in a sequential, alternating
manner
. For example, SDO0 first outputs the 24-bit packet
corresponding to analog input channel 0, then outputs the
packet for channel 1, then continues to alternate between
packets for channels 0 and 1. Likewise, SDO1 has the
same alternating pattern as SDO0, but starting with the
output for channel 1.
When interfacing the LTC2341-18 with a standard SPI
bus, capture output data at the receiver on rising edges of
SCKI. SCKO is not used in this case. Multiple SDO lanes
are also usually not useful in this case. In other applica-
tions, such as interfacing the LTC2341-18 with an FPGA
or CPLD, rising and falling edges of SCKO may be used to
capture serial output data on SDO0 and SDO1 in double
data rate (DDR) fashion. Capturing data using SCKO adds
robustness to delay variations over temperature and supply.
Two Lane Serial CMOS Output Data Capture
As shown in Table 3, full 666ksps per channel throughput
can be achieved with a 65MHz SCKI frequency by captur-
ing the first packet (24 SCKI cycles total) from SDO0 and
SDO1. This configuration also allows conversion results
from both channels to be captured using as few as 18 SCKI
cycles if the 1-bit analog channel ID and 3-bit SoftSpan
code are not needed. Two lane data capture is usually best
suited for use with FPGA or CPLD capture hardware, but
may be useful in other application-specific cases.
One Lane Serial CMOS Output Data Capture
Applications that cannot accommodate two lanes of
serial data capture may employ just one lane without
reconfiguring the LTC2341-18. For example, capturing
the first two packets (48 SCKI cycles total) from SDO0 or
SDO1 provides data for both analog input channels. As
shown in Table 3, full 666ksps per channel throughput can
be achieved with a 65MHz SCKI frequency in the two lane
case, but the maximum CMOS SCKI frequency of 100MHz
limits the throughput to less than 666ksps per channel in
the one lane case.
Programming the SoftSpan Configuration Register in
CMOS I/O Mode
The internal 6-bit SoftSpan configuration register controls
the SoftSpan range for both analog input channels of
the LTC2341-18. The default state of this register after
power-up or resetting the device is all ones, configuring
both channels to convert in SoftSpan 7, the ±VREFBUF
range (see Table 1a). The state of this register may be
modified by providing a new 6-bit SoftSpan configuration
word on SDI during the data transaction window shown
in Figure17. New SoftSpan configuration words are only
accepted within this recommended data transaction win-
dow, but SoftSpan changes take effect immediately with
no additional analog input settling time required before
starting the next conversion. Setting a channel’s SoftSpan
code to SS[2:0] = 000 immediately disables the channel,
resulting in a corresponding reduction in tCONV on the next
conversion. Similarly, enabling a previously disabled chan-
nel requires no additional analog input settling time before
applicaTions inForMaTion
Table 3. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Two Channels Enabled.
Shaded Entries Denote Throughputs That Are Not Achievable In a Given Configuration. Calculated Using fSCKI = (Number of SCKI
Cycles)/(tACQ,MIN – tQUIET)
I/O MODE NUMBER OF SDO
LANES
NUMBER OF SCKI
CYCLES
REQUIRED fSCKI (MHz) TO ACHIEVE THROUGHPUT OF
666ksps/CHANNEL
(tACQ = 410ns)
333ksps/CHANNEL
(tACQ = 1910ns)
166ksps/CHANNEL
(tACQ = 4910ns)
CMOS
2 18 50 10 4
2 24 65 13 5
1 48 Not Achievable 26 10
LVDS 1 24 65 (130Mbps) 13 (26Mbps) 5 (10Mbps)
LTC2341-18
33
234118f
For more information www.linear.com/LTC2341-18
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure19.
If fewer than 6 SCKI rising edges are provided during a
data transaction window, the partial word received on SDI
will be ignored and the SoftSpan configuration register will
not be updated. If exactly 6 SCKI rising edges are provided,
the SoftSpan configuration register will be updated to
match the received SoftSpan configuration word, S[5:0].
The one exception to this behavior occurs when S[5:0] is
all zeros. In this case, the SoftSpan configuration register
will not be updated, allowing applications to retain the
current SoftSpan configuration state by idling SDI low. If
more than 6 SCKI rising edges are provided during a data
transaction window, each complete 6-bit word received on
SDI will be interpreted as a new SoftSpan configuration
word and applied to the SoftSpan configuration register
as described above. Any partial words are ignored.
Typically, applications will update the SoftSpan configura-
tion register in the manner shown in Figures 17 and 18.
After the opening of a new data transaction window at the
falling edge of BUSY, the user supplies a 6-bit SoftSpan
configuration word on SDI during the first 6 SCKI cycles.
This new word overwrites the internal configuration reg-
ister contents following the 6th SCKI rising edge. The user
then holds SDI low for the remainder of the data transaction
window causing the register to retain its contents regardless
of the number of additional SCKI cycles applied. SoftSpan
settings may be retained across multiple conversions by
holding SDI low for the entire data transaction window,
regardless of the number of SCKI cycles applied.
Serial LVDS I/O Mode
In LVDS I/O mode, information is transmitted using posi-
tive and negative signal pairs (LVDS+/LVDS−) with bits
differentially encoded as (LVDS+ − LVDS−). These signals
are typically routed using differential transmission lines
applicaTions inForMaTion
1 2 3 4 5 6
S5 S3S4 S1S2 S0DON’T CARE
SCKI
SDI
SoftSpan CONFIGURATION WORD
CMOS I/O MODE
SoftSpan CONFIGURATION WORD
INTERNAL 6-BIT SoftSpan CONFIGURATION REGISTER
(SAME FOR CMOS AND LVDS)
LVDS I/O MODE
12 0345
tSCKI
1 2 3 4 5 6
S5 S3S4 S1S2 S0DON’T CARE
SCKI
(LVDS)
SDI
(LVDS)
CHANNEL 1 SoftSpan
CODE SS[2:0]
CHANNEL 0 SoftSpan
CODE SS[2:0]
234118 F19
tSCKIH tSCKIL tSSDISCKI tHSDISCKI
tSCKIH tSSDISCKI
tHSDISCKI
tSCKIL
tSCKI
Figure 19. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan
Configuration Register, and SoftSpan Code for Each Analog Input Channel
LTC2341-18
34
234118f
For more information www.linear.com/LTC2341-18
with 100Ω characteristic impedance. Logical 1s and 0s
are nominally represented by differential +350mV and
−350mV, respectively. For clarity, all LVDS timing diagrams
and interface discussions adopt the logical rather than
physical convention.
As shown in Figure20, in LVDS I/O mode the serial data
bus consists of a serial clock differential input, SCKI, serial
data differential input, SDI, serial clock differential output,
SCKO, and serial data differential output, SDO. Communi-
cation with the LTC2341-18 across this bus occurs during
predefined data transaction windows. Within a window,
the device accepts 6-bit SoftSpan configuration words for
the next conversion on SDI and outputs 24-bit packets
containing conversion results and channel configuration
information from the previous conversion on SDO. New
data transaction windows open 10ms after powering up
or resetting the LTC2341-18, and at the end of each con-
version on the falling edge of BUSY. In the recommended
use case, the data transaction should be completed with
a minimum tQUIET time of 20ns prior to the start of the
next conversion, as shown in Figure20. New SoftSpan
configuration words are only accepted within this recom-
mended data transaction window, but SoftSpan changes
take effect immediately with no additional analog input
settling time required before starting the next conversion.
It is still possible to read conversion data after starting the
next conversion, but this will degrade conversion accuracy
and therefore is not recommended.
Just prior to the falling edge of BUSY and the opening of
a new data transaction window, SDO is updated with the
latest conversion results from analog input channel0. Both
rising and falling edges on SCKI serially clock conversion
results and analog input channel configuration information
out on SDO. SCKI is also echoed on SCKO, skew-matched
to the data on SDO. Whenever possible, it is recommended
that rising and falling edges of SCKO be used to capture
DDR serial output data on SDO, as this will yield the best
robustness to delay variations over supply and tempera-
ture. SCKI rising and falling edges also latch SoftSpan
configuration words provided on SDI, which are used to
applicaTions inForMaTion
Figure 20. Serial LVDS I/O Mode
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 2624
S5 S4 S3 S2 S1 S0
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SS1SS2 SS0 D17 D16 D15
CNV
(CMOS)
CS = PD = 0
234118 F20
DON’T CARE
tACQ
BUSY
(CMOS)
SCKO
(LVDS)
SDO
(LVDS)
SCKI
(LVDS)
SDI
(LVDS)
DON’T CARE
SAMPLE N
tCNVL
tCYC
RECOMMENDED DATA TRANSACTION WINDOW
SAMPLE N + 1
SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1
CHANNEL 0
24-BIT PACKET
CONVERSION N
CHANNEL 1
24-BIT PACKET
CONVERSION N
CHANNEL ID CHANNEL ID
CONVERSION RESULT SoftSpan
4241 43 44 45 46 47 48
D0 SS1SS2 SS0 D17
CHANNEL 0
24-BIT PACKET
CONVERSION N
CONVERSION
RESULT
SoftSpan
tSKEW
tCNVH
tBUSYLH
tDSDOSCKI
tHSDOSCKI
tDSDOBUSYL
tSSDISCKI
tHSDISCKI
tQUIET
tCONV
0 0 C00 0 C0
tSCKI tSCKIH
tSCKIL
LTC2341-18
35
234118f
For more information www.linear.com/LTC2341-18
applicaTions inForMaTion
program the internal 6-bit SoftSpan configuration register.
See the section Programming the SoftSpan Configuration
Register in LVDS I/O Mode for further details. As shown in
Figure21, the LVDS bus is enabled when CS is low and is
disabled and Hi-Z when CS is high, allowing the bus to be
shared across multiple devices. Due to the high speeds
involved in LVDS signaling, LVDS bus sharing must be
carefully considered. Transmission line limitations imposed
by the shared bus may limit the maximum achievable bus
clock speed. LVDS inputs are internally terminated with a
100Ω differential resistor when CS is low, while outputs
must be differentially terminated with a 100Ω resistor at
the receiver (FPGA). SCKI must idle in the low state in
LVDS I/O mode, including when transitioning CS.
The data on SDO are grouped into 24-bit packets consisting
of an 18-bit conversion result, followed by two zeros, 1-bit
analog channel ID and 3-bit SoftSpan code, all presented
MSB first. As suggested in Figures 20 and 21, SDO outputs
these packets for both analog input channels in a sequential,
alternating manner. For example, SDO first outputs the
24-bit packet corresponding to analog input channel0,
then outputs the packet for channel1, then continues to
alternate between packets for channels 0 and 1.
Serial LVDS Output Data Capture
As shown in Table 3, full 666ksps per channel throughput
can be achieved with a 65MHz SCKI frequency by captur-
ing two packets (24 SCKI cycles total) of DDR data from
SDO. The LTC2341-18 supports LVDS SCKI frequencies
up to 250MHz.
Programming the SoftSpan Configuration Register in
LVDS I/O Mode
The internal 6-bit SoftSpan configuration register controls
the SoftSpan range for both analog input channels of
the LTC2341-18. The default state of this register after
power-up or resetting the device is all ones, configuring
both channels to convert in SoftSpan 7, the ±VREFBUF
range (see Table 1a). The state of this register may be
modified by providing a new 6-bit SoftSpan configuration
word on SDI during the data transaction window shown
in Figure20. New SoftSpan configuration words are only
accepted within this recommended data transaction win-
dow, but SoftSpan changes take effect immediately with
no additional analog input settling time required before
starting the next conversion. Setting a channel’s SoftSpan
code to SS[2:0] = 000 immediately disables the channel,
Figure 21. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS
CS
(CMOS)
PD = 0
DON’T CARE
BUSY
(CMOS)
SCKO
(LVDS)
SDO
(LVDS)
SCKI
(LVDS)
SDI
(LVDS)
DON’T CARE
DON’T CARE
DON’T CARE
234118 F21
Hi-Z
Hi-Z CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET
(PARTIAL)
Hi-Z
Hi-Z
NEW SoftSpan CONFIGURATION WORD
(OVERWRITES INTERNAL CONFIG REGISTER)
TWELVE ALL-ZERO WORDS AND ONE PARTIAL WORD
(INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE)
tEN tDIS
LTC2341-18
36
234118f
For more information www.linear.com/LTC2341-18
resulting in a corresponding reduction in tCONV on the next
conversion. Similarly, enabling a previously disabled chan-
nel requires no additional analog input settling time before
starting the next conversion. The mapping between the
serial SoftSpan configuration word, the internal SoftSpan
configuration register, and each channel’s 3-bit SoftSpan
code is illustrated in Figure19.
If fewer than 6 SCKI edges (rising plus falling) are provided
during a data transaction window, the partial word received
on SDI will be ignored and the SoftSpan configuration
register will not be updated. If exactly 6 SCKI edges are
provided, the SoftSpan configuration register will be up-
dated to match the received SoftSpan configuration word,
S[5:0]. The one exception to this behavior occurs when
S[5:0] is all zeros. In this case, the SoftSpan configura-
tion register will not be updated, allowing applications to
retain the current SoftSpan configuration state by idling
SDI low. If more than 6 SCKI edges are provided during a
data transaction window, each complete 6-bit word received
on SDI will be interpreted as a new SoftSpan configuration
word and applied to the SoftSpan configuration register
as described above. Any partial words are ignored.
Typically, applications will update the SoftSpan configura-
tion register in the manner shown in Figures 20 and 21.
After the opening of a new data transaction window at
the falling edge of BUSY, the user supplies a 6-bit DDR
SoftSpan configuration word on SDI during the first 6
SCKI cycles. This new word overwrites the internal con-
figuration register contents following the 3rd SCKI falling
edge. The user then holds SDI low for the remainder of
the data transaction window causing the register to retain
its contents regardless of the number of additional SCKI
cycles applied. SoftSpan settings may be retained across
multiple conversions by holding SDI low for the entire
data transaction window, regardless of the number of
SCKI cycles applied.
applicaTions inForMaTion
To obtain the best performance from the LTC2341-18, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Also minimize the length of the REFBUF to GND (Pin 11)
bypass capacitor return loop, and avoid routing CNV near
signals which could potentially disturb its rising edge.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common re-
turns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2581, the evaluation kit for the LTC2341-18.
boarD layouT
LTC2341-18
37
234118f
For more information www.linear.com/LTC2341-18
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
Please refer to http://www.linear.com/product/LTC2341-18#packaging for the most recent package drawings.
5.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 ±0.10
3.45 ±0.10
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.50 REF
(4 SIDES)
4.10 ±0.05
5.50 ±0.05
0.25 ±0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
3.45 ±0.05
3.45 ±0.05
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
LTC2341-18
38
234118f
For more information www.linear.com/LTC2341-18
LINEAR TECHNOLOGY CORPORATION 2016
LT 1016 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2341-18
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2344-18/LTC2344-16 18-Bit/16-Bit, 400ksps, 4-Channel Simultaneous
Sampling, ±4/±1.25LSB INL, Serial ADC
5V Supply, SoftSpan Inputs with Wide Common Mode Range, 95/93.4dB
SNR, Serial CMOS and LVDS I/O, 5mm × 5mm QFN-32 Package
LTC2345-18/LTC2345-16 18-Bit/16-Bit, 200ksps, 8-Channel Simultaneous
Sampling, ±5/±1.25LSB INL, Serial ADC
5V Supply, SoftSpan Inputs with Wide Common Mode Range, 92/91dB
SNR, Serial CMOS and LVDS I/O, 7mm × 7mm QFN-48 Package
LTC2348-18/LTC2348-16 18-/16-Bit, 200ksps, 8-Channel Simultaneous
Sampling, ±3/±1LSB INL, Serial ADC ±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2335-18/LTC2335-16 18-Bit/16-Bit, 1Msps, 8-Channel Multiplexed,
±3/±1LSB INL, Serial ADC
±10.24V SoftSpan Inputs with Wide Common Mode Range, 97/94dB SNR,
Serial CMOS and LVDS I/O, 7mm × 7mm LQFP-48 Package
LTC2378-20/LTC2377-20/
LTC2376-20
20-Bit, 1Msps/500ksps/250ksps,
±0.5ppm INL Serial, Low Power ADC
2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and
4mm × 3mm DFN-16 Packages
LTC2338-18/LTC2337-18/
LTC2336-18
18-Bit, 1Msps/500ksps/250ksps, Serial,
Low Power ADC
5V Supply, ±10.24V Fully Differential Input, 100dB SNR, MSOP-16 Package
LTC2328-18/LTC2327-18/
LTC2326-18
18-Bit, 1Msps/500ksps/250ksps, Serial,
Low Power ADC
5V Supply, ±10.24V Pseudo-Differential Input, 95dB SNR,
MSOP-16 Package
LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC 5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR,
DGC, 5mm × 5mm QFN-32 Package
LTC1859/LTC1858/
LTC1857
16-/14-/12-Bit, 8-Channel, 100ksps, Serial ADC ±10V, SoftSpan, Single-Ended or Differential Inputs, Single 5V Supply,
SSOP-28 Package
DACs
LTC2756/LTC2757 18-Bit, Serial/Parallel IOUT SoftSpan DAC ±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm
LQFP-48 Package
LTC2668 16-Channel 16-/12-Bit ±10V VOUT SoftSpan DACs ±4LSB INL, Precision Reference 10ppm/°C Max, 6mm × 6mm QFN-40 Package
References
LT6657 Low Drift Low Noise Buffered Reference 5V/3V/2.5V, 1.5ppm/°C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT6236/LT6237/LT6238 Single/Dual/Quad Operational Amplifier with
Low Wideband Noise
215MHz, 3.5mA/Amplifier, 1.1nV/√Hz
LT6233/LT6234/LT6235 Single/Dual/Quad Low Noise Rail-to-Rail Output
Op Amps
60MHz,1.2mA,1.2nV/√Hz,15V/μs,0.5mV
LTC6252/LTC6253/
LTC6254
720MHz, 3.5mA Power Efficient Rail-to-Rail I/O
Op Amp
720MHz GBW, Unity Gain Stable, Low Noise
Sense Current from Rail with Amplification
5V
LTC2341-18
234118 TA02
ONLY CHANNEL 0 SHOWN FOR CLARITY
0.1µF
47µF
IN0+
IN0–
VDD
REFINREFBUF
LTC6252
I
LOAD
5V
2.49k
274Ω
–
+
1Ω
LOAD
