Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. B
11/08/2011
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS61WV5128EDBLL
IS64WV5128EDBLL
FEATURES
• High-speed access time: 8, 10 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
• Single power supply
— Vdd 2.4V to 3.6V (10 ns)
— Vdd 3.3V ± 10% (8 ns)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and Automotive temperature support
• Lead-free available
• Error Detection and Error Correction
512K x 8 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
DESCRIPTION
The ISSI IS61/64WV5128EDBLL is a high-speed,
4,194,304-bit static RAMs organized as 524,288 words by
8 bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with inno-
vative circuit design techniques, yields high-performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of
the memory.
The IS61/64WV5128EDBLL is packaged in the JEDEC
standard 44-pin TSOP-II, 36-pin SOJ and 36-pin Mini BGA
(6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
NOVEMBER 2011
Memory Array
(512Kx8)
ECC Array
(512Kx4)
Decoder
I/O Data
Circuit ECC Column I/O
8 8 12
8 4
Control
Circuit
/CE
/OE
/WE
IO0-7
A0-A18
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Rev. B
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IS61/64WV5128EDBLL
PIN CONFIGURATION (HIGH SPEED) (61/64WV5128ALL/BLL)
36 mini BGA
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
Vdd Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
DD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
44
43
42
41
44-Pin TSOP (Type II)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
OE
A10
NC
WE
NC
A18
CE
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
V
DD
GND
I/O2
I/O3
A14
36-Pin SOJ
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vterm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V
Vdd Vdd Relates to GND –0.3 to 4.0 V
tstg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
Cin Input Capacitance Vin = 0V 6 pF
Ci/O Input/Output Capacitance VOut = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a = 25°C, f = 1 MHz, Vdd = 3.3V.
ERROR DETECTION AND ERROR CORRECTION
• Independent ECC with hamming code for each byte
• Detect and correct one bit error per byte
• Better reliability than parity code schemes which can only detect an error but not correct an error
• Backward Compatible: Drop in replacement to current in industry standard devices (without ECC)
TRUTH TABLE
Mode CE WE OE I/O Operation VDD Current
Not Selected H X X High-Z isb1, isb2
(Power-down)
Output Disabled L H H High-Z iCC
Read L H L dOut iCC
Write L L X din iCC
OPERATING RANGE (VDD)1
Range Ambient Temperature IS61WV5128EDBLL IS64WV5128EDBLL
VDD (8, 10nS) VDD (10nS)
Industrial –40°C to +85°C 2.4V-3.6V (10ns) —
3.3V ± 10% (8ns)
Automotive (A1) –40°C to +85°C — 2.4V-3.6V
Automotive (A3) –40°C to +125°C — 2.4V-3.6V
Note:
1. Contact SRAM@issi.com for 1.8V option
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Rev. B
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IS61/64WV5128EDBLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
iCC Vdd Dynamic Operating Vdd = Max., Com. — 40 — 30 — 25 mA
Supply Current iOut = 0 mA, f = fmax Ind. — 45 — 35 — 30
Auto. — — — 50 — 45
typ.(2) 21 21
iCC1 Operating Vdd = Max., Com. — 20 — 20 — 20 mA
Supply Current iOut = 0 mA, f = 0 Ind. — 25 — 25 — 25
Auto. — — — 40 — 40
isb1 TTL Standby Current Vdd = Max., Com. — 10 — 10 — 10 mA
(TTL Inputs) Vin = Vih or Vil Ind. — 15 — 15 — 15
CE ≥ Vih, f = 0 Auto. — — — 30 — 30
isb2 CMOS Standby Vdd = Max., Com. — 5 — 5 — 5 mA
Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 6 — 6 — 6
Vin ≥ Vdd – 0.2V, or Auto. — — — 15 — 15
Vin ≤ 0.2V
, f = 0 typ.(2) 1.5 1.5
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
VOh Output HIGH Voltage Vdd = Min., iOh = –1.0 mA 1.8 — V
VOl Output LOW Voltage Vdd = Min., iOl = 1.0 mA — 0.4 V
Vih Input HIGH Voltage 2.0 Vdd + 0.3 V
Vil Input LOW Voltage(1) –0.3 0.8 V
ili Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA
ilO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V aC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 10%
Symbol Parameter Test Conditions Min. Max. Unit
VOh Output HIGH Voltage Vdd = Min., iOh = –4.0 mA 2.4 — V
VOl Output LOW Voltage Vdd = Min., iOl = 8.0 mA — 0.4 V
Vih Input HIGH Voltage 2 Vdd + 0.3 V
Vil Input LOW Voltage(1) –0.3 0.8 V
ili Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA
ilO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V aC (pulse width < 10 ns). Not 100% tested.
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READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
trC Read Cycle Time 8 — 10 — 20 — ns
taa Address Access Time — 8 — 10 — 20 ns
tOha Output Hold Time 2.0 — 2.0 — 2.5 — ns
taCe CE Access Time — 8 — 10 — 20 ns
tdOe OE Access Time — 4.5 — 4.5 — 8 ns
thzOe(2) OE to High-Z Output — 3 — 4 — 8 ns
tlzOe(2) OE to Low-Z Output 0 — 0 — 0 — ns
thzCe(2 CE to High-Z Output 0 3 0 4 0 8 ns
tlzCe(2) CE to Low-Z Output 3 — 3 — 3 — ns
tPu Power Up Time 0 — 0 — 0 — ns
tPd Power Down Time — 8 — 10 — 20 ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
AC TEST LOADS
Figure 1.
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Figure 2.
ZO = 50Ω
1.5V
50Ω
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS
Parameter Unit
(2.4V-3.6V)
Input Pulse Level 0.4V to Vdd-0.3V
Input Rise and Fall Times 1V/ ns
Input and Output Timing Vdd/2
and Reference Level (VRef)
Output Load See Figures 1 and 2
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Rev. B
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IS61/64WV5128EDBLL
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil)
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10 -20
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
twC Write Cycle Time 8 — 10 — 20 — ns
tsCe CE to Write End 6.5 — 8 — 12 — ns
taw Address Setup Time 6.5 — 8 — 12 — ns
to Write End
tha Address Hold from Write End 0 — 0 — 0 — ns
tsa Address Setup Time 0 — 0 — 0 — ns
tPwe1 WE Pulse Width 6.5 — 8 — 12 — ns
tPwe2 WE Pulse Width (OE = LOW) 8.0 — 10 — 17 — ns
tsd Data Setup to Write End 5 — 6 — 9 — ns
thd Data Hold from Write End 0 — 0 — 0 — ns
thzwe(2) WE LOW to High-Z Output — 3.5 — 5 — 9 ns
tlzwe(2) WE HIGH to Low-Z Output 2 — 2 — 2 — ns
Notes:
1. Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising
or falling edge of the signal that terminates the write. Shaded area product in development
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IS61/64WV5128EDBLL
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
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Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > Vih.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATAIN VALID
t
LZWE
t
SD
CE_WR2.eps
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
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DATA RETENTION WAVEFORM (CE Controlled)
HIGH SPEED
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V
idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 0.5 5 mA
Ind. — — 6
Auto. 15
tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns
trdr Recovery Time See Data Retention Waveform trC — — ns
Note 1: Typical values are measured at Vdd = Vdr(min), Ta = 25
O
C and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
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Automotive (A1) Range: -40°C to +85°C
Speed (ns) Order Part No. Package
10 IS64WV5128EDBLL-10BA1 36 mini BGA (6mm x 8mm)
IS64WV5128EDBLL-10BLA1 36 mini BGA (6mm x 8mm), Lead-free
IS64WV5128EDBLL-10CTA1 TSOP (Type II), Copper Leadframe
IS64WV5128EDBLL-10CTLA1 TSOP (Type II), Lead-free, Copper Leadframe
IS64WV5128EDBLL-10KLA1 400-mil Plastic SOJ, Lead-free
Automotive (A3) Range: -40°C to +125°C
Speed (ns) Order Part No. Package
10 IS64WV5128EDBLL-10BA3 36 mini BGA (6mm x 8mm)
IS64WV5128EDBLL-10BLA3 36 mini BGA (6mm x 8mm), Lead-free
IS64WV5128EDBLL-10CTA3 TSOP (Type II), Copper Leadframe
IS64WV5128EDBLL-10CTLA3 TSOP (Type II), Lead-free, Copper Leadframe
IS64WV5128EDBLL-10KLA3 400-mil Plastic SOJ, Lead-free
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No. Package
10 IS61WV5128EDBLL-10BI 36 mini BGA (6mm x 8mm)
IS61WV5128EDBLL-10BLI 36 mini BGA (6mm x 8mm), Lead-free
IS61WV5128EDBLL-10TI TSOP (Type II)
IS61WV5128EDBLL-10TLI TSOP (Type II), Lead-free
IS61WV5128EDBLL-10KLI 400-mil Plastic SOJ, Lead-free
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
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IS61/64WV5128EDBLL
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
Θ
06/04/2008
Package Outline
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NOTE :
5. Reference document : JEDEC SPEC MS-027.
1. Controlling dimension : mm
at the seating plane after final test.
3. Dimension b2 does not include dambar protrusion/intrusion.
4. Formed leads shall be planar with respect to one another within 0.1mm
2. Dimension D and E1 do not include mold protrusion .
12/20/2007
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IS61/64WV5128EDBLL
NOTE :
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
08/12/2008
Package Outline