This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.1 / July. 2009 1
128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O
Specification of
128M (8Mx16bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x16
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.1 / July. 2009 2
128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O
Document Title
128Mbit (4Bank x 2M x 16bits) MOBILE DDR SDRAM
Revision History
Revision No. History Draft Date Remark
0.1 - Initial Draft Sep. 2007 Preliminary
0.2 - Define
IDD specification Feb. 2008 Preliminary
1.0 -. Modify
IDD Values(p.22 & p.23) , AC Characteristics(p24) Jun. 2008
1.1 -. Omit a typo in package information July. 2009
Rev 1.1 / July. 2009 3
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
FEATURES SUMMARY
●
●●
●
Mobile DDR SDRAM
- Double data rate architecture: two data transfer per
clock cycle
●
●●
●
Mobile DDR SDRAM INTERFACE
- x16 bus width: H5MS1262EFP
- Multiplexed Address (Row address and Column ad-
dress)
●
●●
●
SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V
●
●●
●
MEMORY CELL ARRAY
- 128Mbit (x16 device) = 2M x 4Bank x 16 I/O
●
●●
●
DATA STROBE
- x16 device: LDQS and UDQS
- Bidirectional, data strobe (DQS) is transmitted and re-
ceived with data, to be used in capturing data at the
receiver
- Data and data mask referenced to both edges of DQS
●
●●
●
LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature Compensated Self Refresh)
- DS (Drive Strength)
- DPD (Deep Power Down): DPD is an optional feature,
so please contact Hynix office for the DPD feature
●
●●
●
INPUT CLOCK
- Differential clock inputs (CK, CK)
●
●●
●
Data MASK
- LDM and UDM: Input mask signals for write data
- DM masks write data-in at the both rising and
falling edges of the data strobe
●
●●
●
MODE RERISTER SET, EXTENDED MODE REGIS-
TER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation
(Low Power DDR SDRAM)
●
●●
●
CAS LATENCY
- Programmable CAS latency 2 or 3 supported
●
●●
●
BURST LENGTH
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
●
●●
●
AUTO PRECHARGE
- Option for each burst access
●
●●
●
AUTO REFRESH AND SELF REFRESH MODE
●
●●
●
CLOCK STOP MODE
- Clock stop mode is a feature supported by Mobile DDR
SDRAM.
- Keep to the JEDEC Standard regulation
●
●●
●
INITIALIZING THE MOBILE DDR SDRAM
- Occurring at device power up or interruption of device
power
●
●●
●
PACKAGE
- HY5MS5B6BLFP: 60 Ball Lead free FBGA
●
●●
●
Operation Temperature
- Extended Temp. : -25
o
C ~ 85
o
C
- Mobile Temp. : -30
o
C ~ 85
o
C
●
● ●
●
This product is in compliance with the directive
pertaining of RoHS.
Rev 1.1 / July. 2009 4
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
DESCRIPTION
The Hynix H5MS1262EFP Series is 268,435,456-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile
DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones
with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 4,194,304
x16.
The HYNIX H5MS1262EFP series uses a double-data-rate architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2
n
prefetch architecture with an interface designed to transfer two data per clock
cycle at the I/O pins.
The Hynix H5MS1262EFP Series offers fully synchronous operations referenced to both rising and falling edges of the
clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates
from a differential clock
: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK
),
data, data strobe and data mask inputs are sampled on both rising and falling edges of it (
Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK
). The data
paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible
with LVCMOS.
Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits reg-
istered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and the starting column location
for the burst access.
The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 loca-
tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end
of the burst access.
As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM)
allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation
times.
The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which
are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh.
A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on
any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disa-
bled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be
used for Read with Autoprecharge enabled and for Write bursts.
Rev 1.1 / July. 2009 5
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
The Hynix H5MS1262EFP series has the special Low Power function of Auto TCSR (Temperature Compensated Self
Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables
to automatically adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode
can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM
(Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of
a power switch and giving up mother-board power-line layout flexibility.
All inputs are LVCMOS compatible. Devices will have a V
DD
and V
DDQ
supply of 1.8V (nominal).
The Hynix H5MS1262EFP series is available in the following package:
- 60Ball FBGA [size: 8mm x 10mm, t=1.0mm
max
]
128Mb Mobile DDR SDRAM ORDERING INFORMATION
Part Number Clock Frequency Organization Interface Temp. Package
H5MS1262EFP-J3E 166MHz(CL3) / 83MHz(CL2)
4banks x 2Mb x 16 LVCMOS
Extended
Temp. : -25
o
C
~ 85
o
C
60Ball Lead
Free
H5MS1262EFP-K3E 133MHz(CL3) / 83MHz(CL2)
H5MS1262EFP-L3E 100MHz(CL3) / 66MHz(CL2)
H5MS1262EFP-J3M 166MHz(CL3) / 83MHz(CL2)
Mobile Temp.
: -30
o
C ~
85
o
C
60Ball Lead
Free
H5MS1262EFP-K3M 133MHz(CL3) / 83MHz(CL2)
H5MS1262EFP-L3M 100MHz(CL3) / 66MHz(CL2)
Rev 1.1 / July. 2009 6
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
INFORMATION for Hynix KNOWN GOOD DIE
With the advent of Multi-Chip package (MCP), Package on Package (PoP) and System in a Package (SiP) applications,
customer demand for Known Good Die (KGD) has increased.
Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solu-
tions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies
such as systems-in-a-package (SIP) and multi-chip package (MCP) to reduce the board area required, making them
ideal for hand-held PCs, and many other portable digital applications.
Hynix Mobile SDRAM will be able to continue its constant effort of enabling the advanced package products of all appli-
cation customers.
- Please Contact Hynix Office for Hynix KGD product availability and informations.
Rev 1.1 / July. 2009 7
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
60Ball FBGA ASSIGNMENT
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CKE
A9
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CK
A11
A
B
C
D
E
F
G
H
A6 A7
J
VSS A4
K
VSSQ
DQ14
DQ12
DQ10
DQ8
NC
/CK
NC
A8
A5
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
/WE
/CS
A10
A2
DQ0
DQ2
DQ4
DQ6
LDQS
LDM
/CAS
BA0
A0
A3
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VDD
/RAS
BA1
A1
VDD
123456789
Top view
Rev 1.1 / July. 2009 8
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Mobile DDR SDRAM PIN DESCRIPTIONS
SYMBOL TYPE DESCRIPTION
CK, CK INPUT
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossings of CK and CK (both directions of crossing).
CKE INPUT
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in
any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is
achieved asynchronously.
CS INPUT
Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command
code.
RAS, CAS, WE INPUT Command Inputs: RAS, CAS and WE (along with CS) define the command being entered
BA0, BA1 INPUT
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA0 and BA1 also determine which mode register
is to be loaded during a MODE REGISTER SET command (MRS, EMRS or SRR).
A0 ~ A11 INPUT
Address inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. The address inputs also provide the op-code during
a MODE REGISTER SET command. A10 sampled during a PRECHARGE command deter-
mines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).
If only one bank is to be precharged, the bank is selected by BA0, BA1.
For 128Mb (x16), Row Address: A0 ~ A11, Column Address: A0 ~ A8
Auto-precharge flag: A10
DQ0 ~ DQ15 I/O Data Bus: data input / output pin
LDM ~ UDM INPUT
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ
and DQS loading.
For x16 devices, LDM corresponds to the data on DQ0-DQ7, and UDM corresponds to the
data on DQ8-DQ15.
LDQS ~ UDQS I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
center-aligned with write data. Used to capture write data.
For x16 device, LDQS corresponds to the data on DQ0-DQ7, and UDQS corresponds to the
data on DQ8-DQ15.
V
DD
SUPPLY Power supply
V
SS
SUPPLY Ground
V
DDQ
SUPPLY I/O Power supply
V
SSQ
SUPPLY I/O Ground
NC - No Connect: No internal electrical connection is present.
Rev 1.1 / July. 2009 9
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Mobile DDR SDRAM
16
Sense AMP & I/O Gate
Output Buffer & Logic
Address
Register
Mode Register
State Machine Address Buffers
Bank Select
Row Active
CAS
Latency
CLK
CKE
/CS
/RAS
/CAS
/WE
LDM
~UDM
A0
A1
BA1
BA0
A11
PASR
Refresh
DQ0
DQ15
Row decoders
Row decoders
Row decoders
Row decoders
Column decoders
2Mx16 Bank0
2Mx16 Bank1
2Mx16 Bank2
2Mx16 Bank3
Memory
Cell
Array
Data Out Control
Burst
Length
/CLK
Input Buffer & Logic
DS
32
16
32
Data Strobe
Transmitter
Data Strobe
Receiver
DS
LDQS
~
UDQS
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
Write Data Register
2-bit Prefetch Unit
Row
Pre
Decoder
Column
Pre
Decoder
Column Add
Counter
Burst
Counter
Column Active
Rev 1.1 / July. 2009 10
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
REGISTER DEFINITION I
Mode Register Set (MRS) for Mobile DDR SDRAM
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 CAS Latency BT Burst Length
Burst Type
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0 Burst Length
A3 = 0 A3=1
0 0 0 Reserved Reserved
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
CAS Latency
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Rev 1.1 / July. 2009 11
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
REGISTER DEFINITION II
Extended Mode Register Set (EMRS) for Mobile DDR SDRAM
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 DS 0 0 PASR
DS (Drive Strength)
A6 A5 Drive
Strength
0 0 Full
0 1 Half (Default)
1 0 Quarter
1 1 Octant
PASR (Partial Array Self Refresh)
A2 A1 A0 Self Refresh Coverage
0 0 0 All Banks (Default)
0 0 1 Half of Total Bank (BA1=0)
0 1 0 Quarter of Total Bank (BA1=BA0=0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One Eighth of Total Bank
(BA1 = BA0 = Row Address MSB=0)
1 1 0 One Sixteenth of Total Bank
(BA1 = BA0 = Row Address 2 MSBs=0)
1 1 1 Reserved
Rev 1.1 / July. 2009 12
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
REGISTER DEFINITION III
Status Register (SR) for Mobile DDR SDRAM
Note)
1. The revision number starts at ‘0000’ and increments by ‘0001’ each time a change in the manufacturer’s specification, IBIS, or
process occurs.
2. Low temperature out of range.
3. High temperature out of range - no refresh rate can guarantee functionality.
4. The refresh rate multiplier is based on the memory’s temperature sensor.
5. Required average periodic refresh interval = tREFI * multiplier.
6. Status Register is only for Read.
7. To read out Status Register values, BA[1:0] set to 01b and A[12:0] set to all 0 with MRS command followed by Read command
with that BA[1:0] and A[12:0] are Don’t care.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 0 0 0 0 0 0 0 0 0
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Density - DW Refresh Rate Revision Identification Manufacturers Identification
0 0 1 0 0 X X X X
1)
X
1)
X
1)
X
1)
0110
Density
DQ15 DQ14 DQ13 Density
0 0 0 128
0 0 1 256
0 1 0 512
0 1 1 1024
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
DW (Device Width)
DQ11 Device Width
0 16 bits
1 32 bits
Refresh Rate
DQ10 DQ9 DQ8 Refresh Rate
0 0 x 4
2)
0 1 0 4
0 1 1 2
1 0 0 1
1 0 1 0.5
1 1 0 0.25
1 1 1 0.25
3)
Manufacturers Identification
DQ3 DQ2 DQ1 DQ0 Manufacturer
0 1 1 0 Hynix
xxxx Reserved or
other companies
Rev 1.1 / July. 2009 13
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
COMMAND TRUTH TABLE
DM TRUTH TABLE
Note:
1. All states and sequences not shown are illegal or reserved.
2. DESLECT and NOP are functionally interchangeable.
3. Autoprecharge is non-persistent. A10 High enables Autoprecharge, while A10 Low disables Autoprecharge
4. Burst Terminate applies to only Read bursts with auto precharge disabled. This command is undefined and should not be used for
Read with Autoprecharge enabled, and for Write bursts.
5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.
6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and BA0-BA1 are
don
'
t care.
7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.
8. All address inputs and I/O are
''
don
'
t care
''
except for CKE. Internal refresh counters control Bank and Row addressing.
9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.
10. BA0 and BA1 value select among MRS, EMRS and SRR.
11. Used to mask write data, provided coincident with the corresponding data.
12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
Function CS RAS CAS WE BA A10/AP ADDR Note
DESELECT (NOP) H X X X X X X 2
NO OPERATION (NOP) L H H H X X X 2
ACTIVE (Select Bank and activate Row) L L H H V Row Row
READ (Select bank and column and start read burst) L H L H V L Col
READ with AP (Read Burst with Autoprecharge) L H L H V H Col 3
WRITE (Select bank and column and start write
burst) L H L L V L Col
WRITE with AP (Write Burst with Autoprecharge) L H L L V H Col 3
BURST TERMINATE or enter DEEP POWER DOWN L H H L X X X 4, 5
PRECHARGE (Deactivate Row in selected bank) L L H L V L X 6
PRECHARGE ALL (Deactivate rows in all Banks) L L H L X H X 6
AUTO REFRESH or enter SELF REFRESH L L L H X X X 7,8,9
MODE REGISTER SET L L L L V Op code 10
Function DM DQ Note
Write Enable L Valid 11
Write Inhibit H X 11
Rev 1.1 / July. 2009 14
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
CKE TRUTH TABLE
Note:
1. CKEn is the logic state of CKE at clock edge
n
; CKE
n
-1 was the state of CKE at the previous clock edge.
2. Current state is the state of LP DDR immediately prior to clock edge
n
.
3. COMMAND
n
is the command registered at clock edge n, and ACTION
n
is the result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP are functionally interchangeable.
6. Power Down exit time (t
XP
) should elapse before a command other than NOP or DESELECT is issued.
7. SELF REFRESH exit time (t
XSR
) should elapse before a command other than NOP or DESELECT is issued.
8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description.
9. The clock must toggle at least one time during the t
XP
period.
10. The clock must toggle at least once during the t
XSR
time.
CKE
n-1
CKE
n
Current State
COMMAND
n
ACTION
n
Note
L L Power Down X Maintain Power Down
L L Self Refresh X Maintain Self Refresh
L L Deep Power Down X Maintain Deep Power
Down
L H Power Down NOP or DESELECT Exit Power Down 5,6,9
L H Self Refresh NOP or DESELECT Exit Self Refresh 5,7,10
L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5,8
H L All Banks Idle NOP or DESELECT Precharge Power
Down Entry 5
H L Bank(s) Active NOP or DESELECT Active Power Down
Entry 5
H L All Banks Idle AUTO REFRESH Self Refresh entry
H L All Banks Idle BURST TERMINATE Enter Deep Power
Down
H H See the other Truth Tables
Rev 1.1 / July. 2009 15
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
CURRENT STATE BANK
n
TRUTH TABLE
(COMMAND TO BANK
n
)
Note:
1. The table applies when both CKE
n
-1 and CKE
n
are HIGH, and after t
XSR
or t
XP
has been met if the previous state was Self Refresh
or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.
5. A command other than NOP should not be issued to the same bank while a READ or WRITE Burst with auto precharge is enabled.
6. The new Read or Write command could be auto precharge enabled or auto precharge disabled.
Current State
Command
Action Notes
CS RAS CAS WE Description
Any
H X X X DESELECT (NOP) Continue previous Operation
L H H H NOP Continue previous Operation
Idle
L L H H ACTIVE Select and activate row
L L L H AUTO REFRESH Auto refresh 10
L L L L MODE REGISTER SET Mode register set 10
L L H H PRECHARGE No action if bank is idle
Row Active
L H L H READ Select Column & start read burst
L H L L WRITE Select Column & start write burst
L L H L PRECHARGE Deactivate Row in bank (or banks) 4
Read
(without Auto
recharge)
L H L H READ Truncate Read &
start new Read burst 5,6
L H L L WRITE Truncate Read &
start new Write burst 5,6,13
L L H L PRECHARGE Truncate Read, start Precharge
L H H L BURST TERMINATE Burst terminate 11
Write
(without Auto
precharge)
L H L H READ Truncate Write &
start new Read burst 5,6,12
L H L L WRITE Truncate Write &
start new Write burst 5,6
L L H L PRECHARGE Truncate Write, start Precharge 12
Rev 1.1 / July. 2009 16
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
7. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and t
RCD
has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
8. The following states must not be interrupted by a command issued to the same bank.
DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring
during these states. Allowable commands to the other bank are determined by its current state and Truth Table3,
and according to Truth Table 4.
Precharging: Starts with the registration of a PRECHARGE command and ends when t
RP
is met.
Once t
RP
is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when t
RCD
is met.
Once t
RCD
is met, the bank will be in the
''
row active
''
state.
Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends
when t
RP
has been met. Once t
RP
has been met, the bank will be in the idle state.
Write with AP Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends
when t
RP
has been met. Once t
RP
is met, the bank will be in the idle state.
9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
to each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when t
RFC
is met.
Once t
RFC
is met, the LP DDR will be in an
''
all banks idle
''
state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.
Once t
MRD
is met, the LP DDR will be in an
''
all banks idle
''
state.
Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when t
RP
is met.
Once t
RP
is met, the bank will be in the idle state.
10. Not bank-specific; requires that all banks are idle and no bursts are in progress.
11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank.
12. Requires appropriate DM masking.
13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end
the READ prior to asserting a WRITE command.
Rev 1.1 / July. 2009 17
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
CURRENT STATE BANK
n
TRUTH TABLE
(COMMAND TO BANK
m
)
Current State
Command
Action Notes
CS RAS CAS WE Description
Any
H X X X DESELECT (NOP) Continue previous Operation
L H H H NOP Continue previous Operation
Idle X X X X ANY Any command allowed to bank m
Row Activating,
Active, or Pre-
charging
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8
L H L L WRITE Start WRITE burst 8
L L H L PRECHARGE Precharge
Read with Auto
Precharge dis-
abled
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8
L H L L WRITE Start WRITE burst 8,10
L L H L PRECHARGE Precharge
Write with Auto
precharge dis-
abled
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 8,9
L H L L WRITE Start WRITE burst 8
L L H L PRECHARGE Precharge
Read with Auto
Precharge
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 5,8
L H L L WRITE Start WRITE burst 5,8,10
L L H L PRECHARGE Precharge
Write with Auto
precharge
L L H H ACTIVE Activate Row
L H L H READ Start READ burst 5,8
L H L L WRITE Start WRITE burst 5,8
L L H L PRECHARGE Precharge
Rev 1.1 / July. 2009 18
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Note:
1. The table applies when both CKE
n
-1 and CKE
n
are HIGH, and after t
XSR
or t
XP
has been met if the previous state was
Self Refresh or Power Down.
2. DESELECT and NOP are functionally interchangeable.
3. All states and sequences not shown are illegal or reserved.
4. Current State Definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and t
RCD
has been met. No data bursts/accesses and
no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.
5. Read with AP enabled and Write with AP enabled: The read with Autoprecharge enabled or Write with Autoprecharge
enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the
precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the
earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the
precharge period begins when t
WR
ends, with t
WR
measured as if Auto Precharge was disabled. The access period starts
with registration of the command and ends where the precharge period (or t
RP
) begins. During the precharge period,
of the Read with Autoprecharge enabled or Write with Autoprecharge enabled states, ACTIVE, PRECHARGE, READ, and
WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands
to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data
and WRITE data must be avoided).
6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.
7. A BURST TERMINATE command cannot be issued to another bank;
it applies to the bank represented by the current state only.
8. READs or WRITEs listed in the Command column include READs and WRITEs with AUTO PRECHARGE enabled and
READs and WRITEs with AUTO PRECHARGE disabled.
9. Requires appropriate DM masking.
10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command
must be issued to end the READ prior to asserting a WRITE command.
Rev 1.1 / July. 2009 19
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
ABSOLUTE MAXIMUM RATING
Note1, H5MS1262EFP-XXE Series : Extended Temp. : -25
o
C ~ 85
o
C, H5MS1262EFP-XXM Series : Mobile Temp. : -30
o
C ~ 85
o
C
AC and DC OPERATING CONDITIONS
OPERATING CONDITION
CLOCK INPUTS
(CK, CK)
Address And Command Inputs
(A0~An, BA0, BA1, CKE, CS, RAS, CAS, WE)
Data Inputs
(DQ, DM, DQS)
Data Outputs
(DQ, DQS)
Parameter Symbol Rating Unit
Operating Case Temperature
1)
T
C
-25 ~ 85
o
C
-30 ~ 85
o
C
Storage Temperature T
STG
-55 ~ 150
o
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-0.3 ~ V
DDQ
+0.3 V
Voltage on V
DD
relative to V
SS
V
DD
-0.3 ~ 2.7 V
Voltage on V
DDQ
relative to V
SS
V
DDQ
-0.3 ~ 2.7 V
Short Circuit Output Current I
OS
50 mA
Power Dissipation P
D
0.7 W
Parameter Symbol Min Typ Max Unit Note
Supply Voltage V
DD
1.7 1.8 1.95 V 1
I/O Supply Voltage V
DDQ
1.7 1.8 1.95 V 1
Parameter Symbol Min Max Unit Note
DC Input Voltage V
IN
-0.3 V
DDQ+
0.3 V
DC Input Differential Voltage V
ID(DC)
0.4*V
DDQ
V
DDQ+
0.6 V 2
AC Input Differential Voltage V
ID(AC)
0.6*V
DDQ
V
DDQ+
0.6 V 2
AC Differential Crosspoint Voltage V
IX
0.4*V
DDQ
0.6*V
DDQ
V 3
Parameter Symbol Min Max Unit Note
Input High Voltage V
IH
0.8*V
DDQ
V
DDQ+
0.3 V
Input Low Voltage V
IL
-0.3 0.2*V
DDQ
V
Parameter Symbol Min Max Unit Note
DC Input High Voltage V
IHD(DC)
0.7*V
DDQ
V
DDQ+
0.3 V
DC Input Low Voltage V
ILD(DC)
-0.3 0.3*V
DDQ
V
AC Input High Voltage V
IHD(AC)
0.8*V
DDQ
V
DDQ+
0.3 V
AC Input Low Voltage V
ILD(AC)
-0.3 0.2*V
DDQ
V
Parameter Symbol Min Max Unit Note
DC Output High Voltage (IOH = -0.1mA) V
OH
0.9*V
DDQ
- V
DC Output Low Voltage (IOL = 0.1mA) V
OL
- 0.1*V
DDQ
V
Rev 1.1 / July. 2009 20
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Leakage Current
Note:
1. All voltages are referenced to VSS = 0V and VSSQ must be same potential and VDDQ must not exceed the level of VDD.
2. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on CK.
3. The value of VIX is expected to be 0.5*VDDQ and must track variations in the DC level of the same.
4. V
IN
= 0 to 1.8V. All other pins are not tested under V
IN
=0V.
5. D
OUT
is disabled. V
OUT
= 0 to 1.95V.
AC OPERATING TEST CONDITION
Note: 1. The circuit shown on the right represents the timing
load used in defining the relevant timing parameters of
the part. It is not intended to be either a precise repre-
sentation of the typical system environment nor a depic-
tion of the actual load presented by a production tester.
System designers will use IBIS or other simulation tools
to correlate the timing reference load to system environ-
ment. Manufacturers will correlate to their production
(generally a coaxial transmission line terminated at the
tester electronics). For the half strength driver with a
nominal 10pF load parameters tAC and tQH are
expected to be in the same range. However, these
parameters are not subject to production test but are
estimated by design and characterization. Use of IBIS or other simulation tools for system design validation is suggested.
Input / Output Capacitance
Note:
1. These values are guaranteed by design and are tested on a sample base only.
2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.
3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD,
VDDQ are applied and all other pins (except the pin under test) floating. DQ
'
s should be in high impedance state. This may be
achieved by pulling CKE to low level.
4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This
is required to match signal propagation times of DQ, DQS and DM in the system.
Parameter Symbol Min Max Unit Note
Input Leakage Current I
LI
-1 1 uA 4
Output Leakage Current I
LO
-1.5 1.5 uA 5
Parameter Symbol Value Unit Note
AC Input High/Low Level Voltage V
IH
/ V
IL
0.8*V
DDQ
/0.2*V
DDQ
V
Input Timing Measurement Reference Level Voltage V
trip
0.5*V
DDQ
V
Input Rise/Fall Time t
R
/ t
F
1 ns
Output Timing Measurement Reference Level Voltage V
outref
0.5*V
DDQ
V
Output Load Capacitance for Access Time Measurement CL pF 1
Parameter Symbol Speed Unit Note
Min Max
Input capacitance, CK, CK CCK 1.5 3.5 pF
Input capacitance delta, CK, CK CDCK - 0.25 pF
Input capacitance, all other input-only pins CI 1.5 3.0 pF
Input capacitance delta, all other input-only pins CDI - 0.5 pF
Input/output capacitance, DQ, DM, DQS CIO 2.0 4.5 pF 4
Input/output capacitance delta, DQ, DM, DQS CDIO - 0.5 pF 4
Test Load for Full Drive Strength Buffer
(20 pF)
Test Load for Half Drive Strength Buffer
(10 pF)
Output
OutputOutput
Output
Z
O
=50Ω
Rev 1.1 / July. 2009 21
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Mobile DDR OUTPUT SLEW RATE CHARACTERRISTICS
Note:
1. Measured with a test load of 20pF connected to VSSQ
2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC)
3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process
variation.
Mobile DDR AC OVERSHOOT / UNDERSHOOT SPECIFICATION
Note:
1. This specification is intended for devices with no clamp protection and is guaranteed by design.
Parameter Min Max Unit Note
Pull-up and Pull-Down Slew Rate for Full Strength Driver 0.7 2.5 V/ns 1, 2
Pull-up and Pull-Down Slew Rate for Half Strength Driver 0.3 1.0 V/ns 1, 2
Output Slew Rate Matching ratio (Pull-up to Pull-down) 0.7 1.4 - 3
Parameter Specification
Maximum peak amplitude allowed for overshoot 0.5V
Maximum peak amplitude allowed for undershoot 0.5V
The area between overshoot signal and VDD must be less than or equal to 3V-ns
The area between undershoot signal and GND must be less than or equal to 3V-ns
2.5V
2.0V
1.5V
1.0V
0.5V
0.0V
-0.5V
Overshoot
Undershoot
VDD
VSS
Max. Amplitude = 0.5V Max. Area = 3V-ns
Time (ns)
Voltage (V)
Rev 1.1 / July. 2009 22
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
DC CHARACTERISTICS
Parameter Symbol Test Condition
Max
Unit Note
DDR
333
DDR
266
DDR
200
Operating one bank
active-precharge current IDD0
tRC = tRC(min); tCK = tCK(min); CKE is HIGH; CS is
HIGH between valid commands; address inputs are
SWITCHING; data bus inputs are STABLE
45 40 35 mA 1
Precharge power-down
standby current IDD2P
all banks idle; CKE is LOW; CS is HIGH; tCK =
tCK(min); address and control inputs are SWITCH-
ING; data bus inputs are STABLE
0.3 mA
Precharge power-down
standby current
with clock stop
IDD2PS
all banks idle; CKE is LOW; CS is HIGH; CK = LOW;
CK = HIGH; address and control inputs are SWITCH-
ING; data bus inputs are STABLE
0.3 mA
Precharge non power-down
standby current IDD2N
all banks idle; CKE is HIGH; CS is HIGH, tCK =
tCK(min); address and control inputs are SWITCH-
ING; data bus inputs are STABLE
5
mA
Precharge non power-down
standby current
with clock stop
IDD2NS
all banks idle; CKE is HIGH; CS is HIGH; CK = LOW;
CK = HIGH; address and control inputs are SWITCH-
ING; data bus inputs are STABLE
3
Active power-down
standby current IDD3P
one bank active; CKE is LOW; CS is HIGH; tCK =
tCK(min); address and control inputs are SWITCH-
ING; data bus inputs are STABLE
2
mA
Active power-down
standby current
with clock stop
IDD3PS
one bank active; CKE is LOW; CS is HIGH; CK =
LOW; CK = HIGH; address and control inputs are
SWITCHING; data bus inputs are STABLE
1.2
Active non power-down
standby current IDD3N
one bank active; CKE is HIGH; CS is HIGH; tCK =
tCK
(min);
address and control inputs are SWITCH-
ING; data bus inputs are STABLE
10 mA
Active non power-down
standby current
with clock stop
IDD3NS
one bank active; CKE is HIGH; CS is HIGH; CK =
LOW; CK = HIGH; address and control inputs are
SWITCHING; data bus inputs are STABLE
8 mA
Operating burst read current IDD4R
one bank active; BL=4; CL=3; tCK = tCK
(min)
;
continuous read bursts; IOUT=0mA; address inputs
are SWITCHING, 50% data change each burst trans-
fer
100 90 70 mA
1
Operating burst write current IDD4W
one bank active; BL=4; tCK=tCK
(min)
; continuous
write bursts; address inputs are SWITCHING; 50%
data change each burst transfer
80 70 60 mA
Auto Refresh Current IDD5
tRC=tRFC
(min)
; tCK=tCK
(min);
burst refresh; CKE
is HIGH; address and control inputs are SWITCH-
ING; data bus inputs are STABLE
80 mA
Self Refresh Current IDD6
CKE is LOW; CK=LOW; CK=HIGH;
Extended Mode Register set to all 0's; address and
control inputs are STABLE; data bus inputs are STA-
BLE
See Next Page uA 2
Deep Power Down Current IDD8 Address, control and data bus inputs are STABLE 10 uA 4
Rev 1.1 / July. 2009 23
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is 1V/ns
3. Definitions for IDD:
LOW is defined as V
IN
≤
0.1 * V
DDQ
HIGH is defined as V
IN
≥
0.9 * V
DDQ
STABLE is defined as inputs stable at a HIGH or LOW level
SWITCHING is defined as
- address and command: inputs changing between HIGH and LOW once per two clock cycles
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle
DM and DQS are STABLE
4. Please contact Hynix office for more information and ability for DPD operation. Deep Power Down operation is a hynix optional
function.
5. IDD values are for full operating range of voltage and temperature.
DC CHARACTERISTICS
- I
DD6
Note:
1. VDD / VDDQ = 1.8V
2. Related numerical values in this 45
o
C are examples for reference sample value only.
3. With a on-chip temperature sensor, auto temperature compensated self refresh will automatically adjust the interval of self-refresh
operation according to case temperature variations.
Temp.
(
o
C)
Memory Array Unit
4 Banks 2 Banks 1 Bank
45 135 125 120
uA
85 250 185 170
uA
Rev 1.1 / July. 2009 24
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) (Sheet 1 of 2)
Parameter Symbol
DDR333 DDR266 DDR200
Unit Note
Min Max Min Max Min Max
DQ Output Access Time (from CK, CK)
t
AC 2.0 5.0 2.0 6.0 2.0 6.0 ns
DQS Output Access Time (from CK, CK)
t
DQSCK 2.0 5.0 2.0 6.0 2.0 6.0 ns
Clock High-level Width
t
CH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock Low-level Width
t
CL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock Half Period
t
HP
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-
tCL,
tCH
(Min)
-ns 1,2
System Clock Cycle Time
CL = 3
t
CK3 6.0 - 7.5 - 10 - ns
3
CL = 2
t
CK2 12 12 - 15 - ns
DQ and DM Input Setup Time
t
DS 0.6 0.8 0.8 ns 4,5,6
DQ and DM Input Hold Time
t
DH 0.6 0.8 0.8 ns 4,5,6
DQ and DM Input Pulse Width
t
DIPW 1.6 - 2.0 - 2.0 - ns 7
Address and Control Input Setup Time
t
IS 1.1 1.3 1.3 ns 6,8,9
Address and Control Input Hold Time
t
IH 1.1 1.3 1.3 ns 6,8,9
Address and Control Input Pulse Width
t
IPW 2.2 - 2.6 - 3.0 - ns 7
DQ & DQS Low-impedance time from CK, CK
t
LZ 1.0 - 1.0 - 1.0 - ns 10
DQ & DQS High-impedance time from CK, CK
t
HZ 5.0 6.0 6.0 ns 10
DQS - DQ Skew
t
DQSQ 0.5 0.6 0.65 ns 11
DQ / DQS output hold time from DQS
t
QH tHP -
tQHS
tHP -
tQHS
tHP -
tQHS ns 2
Data Hold Skew Factor
t
QHS 0.65 0.75 1.0 ns 2
Write Command to 1st DQS Latching Transition
t
DQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS Input High-Level Width
t
DQSH 0.4 0.4 0.35 tCK
DQS Input Low-Level Width
t
DQSL 0.4 0.4 0.35 tCK
DQS Falling Edge of CK Setup Time
t
DSS 0.2 0.2 0.2 tCK
DQS Falling Edge Hold Time from CK
t
DSH 0.2 0.2 0.2 tCK
Rev 1.1 / July. 2009 25
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) (Sheet 2 of 2)
Parameter Symbol
DDR333 DDR266 DDR200
Unit Note
Min Max Min Max Min Max
MODE REGISTER SET Command Period
t
MRD 2 - 2 - 2 - tCK
MRS(SRR) to Read Command Period
t
SRR 2 - 2 - 2 - tCK
Minimum Time between Status Register Read to
Next Valid Command
t
SRC CL+1 - CL+1 - CL+1 - tCK
Write Preamble Setup Time
t
WPRES 0 - 0 - 0 - ns 12
Write Postamble
t
WPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 13
Write Preamble
t
WPRE 0.25 - 0.25 - 0.25 - tCK
Read Preamble
CL = 3 t
RPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 14
CL = 2 t
RPRE 0.5 1.1 0.5 1.1 0.5 1.1 tCK 14
Read Postamble
t
RPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
ACTIVE to PRECHARGE Command Period
t
RAS 42 70,000 45 70,000 50 70,000 ns
ACTIVE to ACTIVE Command Period
t
RC 60 - 75 - 80 - ns
AUTO REFRESH to ACTIVE/AUTO REFRESH
Command Period
t
RFC 80 - 80 - 80 - ns
ACTIVE to READ or WRITE Delay
t
RCD 18 - 22.5 - 30 - ns 15
PRECHARGE Command Period
t
RP 18 - 22.5 - 30 - ns 15
ACTIVE Bank
A
to ACTIVE Bank
B
Delay
t
RRD 12 - 15 - 15 - ns
WRITE Recovery Time
t
WR 15 - 15 - 15 - ns
Auto Precharge Write Recovery + Precharge Time
t
DAL (tWR/tCK) + (tRP/tCK) tCK 16
Internal Write to Read Command Delay
t
WTR 1 - 1 - 1 - tCK
Self Refresh Exit to next valid Command Delay
t
XSR 120 - 120 - 120 - ns
Exit Power Down to next valid Command Delay
t
XP tIS +
1CLK -tIS +
1CLK -tIS +
1CLK - ns
CKE
min
. Pulse Width (High and Low)
t
CKE 1 - 1 - 1 - tCK
Average Periodic Refresh Interval
t
REFI - 15.6 - 15.6 - 15.6 us 17
Refresh Period
t
REF - 64 - 64 - 64 ms
Rev 1.1 / July. 2009 26
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Note:
1. Min (t
CL
, t
CH
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for t
CL
and t
CH
)
2. t
QH
= t
HP
- t
QHS
, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (t
CL
, t
CH
).
t
QHS
accounts for
1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the
worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and
p-channel to n-channel variation of the output drivers.
3. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes.
4. The transition time for DQ, DM and DQS inputs is measured between V
IL
(DC) to V
IH
(AC) for rising input signals, and V
IH
(DC) to
V
IL
(AC) for falling input signals.
5. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
6. Input slew rate ≥ 1.0 V/ns.
7. These parameters guarantee device timing but they are not necessarily tested on each device.
8. The transition time for address and command inputs is measured between V
IH
and V
IL
.
9. A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
10. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
11. t
DQSQ
consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,
LOW, or transitioning from HIGH to LOW at this time, depending on t
DQSS
.
13. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
14. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the
system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
15. Speed bin (CL-t
RCD
-t
RP
) = 3-3-3
16. t
DAL
= (t
WR
/t
CK
) + (t
RP
/t
CK
): for each of the terms above, if not already an integer, round to the next higher integer.
17. A maximum of eight Refresh commands can be posted to any given Low Power DDR SDRAM (Mobile DDR SDRAM), meaning that
the maximum absolute interval between any Refresh command and the next Refresh command is 8*t
REFI
.
Rev 1.1 / July. 2009 27
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Mobile DDR SDRAM OPERATION
State Diagram
IDLE
ALL BANK
PCG.
AUTO
REFRESH
SELF
REFRESH
PCG.
POWER
DOWN
(E)MRS
SET
WRITE READ
Precharge
ALL
ACTIVE
POWER
DOWN
ROW
ACTIVE
MRS,
EMRS
REFS
CKEL
REFA
CKEH
ACT
CKEL
CKEH
WRITE
WRITE READ
REFSX
COMMAND Input
AUTOMATIC
Sequence
DEEP
POWER
DOWN
POWER
ON
PCG.
ALL
BANKS
Power
applied
DPDS
DPDSX
BURST
STOP
WRITEA
READ
READA
BST
READ A
WRITE A
WRITEA READA
READ
PRE
PRE PRE
SRR
READ
SRR
READ
ACT :
Active
BST :
Burst
CKEL :
Enter Power-D own
CKEH :
Exit Pow er-Dow n
DPDS :
Enter Deep
Power-D ow n
DPDSX :
Exit D eep Pow er-
D ow n EM R S
EM RS :
Ext. M ode Reg.
Set
M RS :
M ode Register Set
PRE :
Precharge
PREALL :
Precharge All
Banks
REFA :
Auto R efresh
REFS :
Enter Self Refresh
REFSX :
Exit Self R efresh
READ :
Read w/o Auto
Precharge
READ A :
Read with Auto
Precharge
W RITE :
W rite w /o Auto
Precharge
W RITEA :
W rite w ith Auto
Precharge
SRR :
Status R egister
Read
Rev 1.1 / July. 2009 28
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
DESELECT
The DESELECT function (CS = High) prevents new commands from being executed by the Mobile DDR SDRAM. The
Mobile DDR SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command is used to perform a NOP to a Mobile DDR SDRAM that is selected (CS = Low).
This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are
not affected. (see to next figure)
ACTIVE
The Active command is used to activate a row in a particular bank for a subsequent Read or Write access. The value of
the BA0,BA1 inputs selects the bank, and the address provided on A0-A11 (or the highest address bit) selects the row.
(see to next figure)
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank
must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be acti-
vated.
The row remains active until a PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) com-
mand is issued to the bank.
A PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command must be issued before
opening a different row in the same bank.
CS
A
0~Amax
WE
CAS
Don't Care
CLK
CLK
CKE
BA0, BA1
Bank Address
Row Address
Don't Care
RA
BA
NOP Command ACTIVE Command
RAS
CS
A0~Amax
WE
CAS
CLK
CLK
CKE
BA0, BA1
RAS
(High) (High)
Rev 1.1 / July. 2009 29
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Once a row is Open (with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the
t
RCD
specification. t
RCD
(
MIN
) should be divided by the clock period and rounded up to the next whole number to
determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row
has been closed (precharge). The minimum time interval between successive ACTIVE commands to the same bank is
defined by t
RC
.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in
a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to differ-
ent banks is defined by t
RRD.
Rev 1.1 / July. 2009 30
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
READ / WRITE COMMAND
The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and
address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open
for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.
The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble
and the last data-out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon com-
pletion of a burst, assuming no new READ commands have been initiated, the I/O's will go high-Z.
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank
and address inputs select the starting column location.
The value of A10 determines whether or not auto precharge is used.If auto precharge is selected, the row being
accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open
for subsequent access. Input data appearing on the data bus, is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be
written to the memory; if the DM signal is registered high, the corresponding data-inputs will be ignored, and a write
will not be executed to that byte/column location. The memory controller drives the DQS during write operations. The
initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write
postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z
and any additional input data will be ignored.
READ / WRITE COMMAND
Don't Care
CA
BA
High to enable
Auto Precharge
Low to disable
Auto Precharge
Read Com m and W rite Com mand
CA
BA
CLK
CLK
CKE
CLK
CLK
CKE
(High) (High)
CS
A0~A8
WE
CAS
A10
RAS
BA0, BA1
CS
A0~A8
WE
CAS
A10
RAS
BA0, BA1
Rev 1.1 / July. 2009 31
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
READ
The basic Read timing parameters for DQ are shown next figure (Basic Read Timing Parameters). They apply to all
Read operations. During Read bursts, DQS is driven by the Mobile DDR SDRAM along with the output data. The initial
Low state of the DQS is known as the read preamble; the Low state coincident with last data-out element is known as
the read postamble.
Basic Read Timing Parameters
D o
n
Do
n+ 1
D o
n+ 2
D o
n+ 3
/CLK
CLK
tCK tCK tCH tCL
tRPRE
tD Q SC K
tD Q S Q
m ax
tAC
tLZ tQ H
tD Q S CK
tQ H
tQ H
tH Z
tQ H
tRPRE
tD Q S CK
tLZ
tD Q SC K
tRPST
tAC
tD QSQ m ax
D o
n
D o
n+ 1
D o
n+ 2
D o
n+3
D Q S
D Q
D Q S
D Q
Do n 't C a re
1) D o
n
: D ata O ut from co lum n n
2) All D Q are vaild tA C after the C K ed ge
All DQ are vaild tDQ SQ after th e D QS ed ge, regardless of tA C
tRPST
tACm a x
tACm in
tQ H
tH Z
Rev 1.1 / July. 2009 32
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out elements are
edge aligned to successive edges of DQS. This is shown in next figure with a CAS latency of 2 and 3.
Upon completion of a read burst, assuming no other READ command has been initiated, the DQ will go to High-Z.
Read Burst Showing CAS Latency
/CLK
CLK
Do
n
Do
n
READ NOP NOP NOP NOP NOP
BA,
Col
n
CL =3
CL =2
Don't Care
1) Do
n
: Data out from column n
2) BA, Col
n
= Bank A, Column n
3) Burst Length = 4; 3 subseqnent elements of Data Out appear in the programmed order following Do
n
4) Shown with nominal tAC, tDQSCK and tDQSQ
Command
Address
DQS
DQ
DQS
DQ
Rev 1.1 / July. 2009 33
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
READ to READ
Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the
new burst follows either the last element of a completed burst or the last desired element of a longer burst that is
being truncated. The new READ command should be issued X cycles after the first READ command, where X equals
the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture).
Consecutive Read Bursts
A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are
shown in the first figure of next page. Random read accesses within a page or pages can be performed as shown in
second figure of next page.
/CLK
CLK
Do
n
Do
n
READ NOP REA D NO P NO P NOP
BA ,
Col
n
CL =3
CL =2
Don't C are
1) Do
n
(or
b
): D ata out from colum n n (or colum n b)
2) BA, Col
n (b )
= Bank A, Colum n n (b)
3) Burst Length = 4 or 8 (if 4 , th e bursts are concatenated; if 8, the second burst inte rrupts the first)
4) Read b u rsts are to an active row in any bank
5) Sh o w n w ith nom ina l tAC, tD QSCK and tD QSQ
Co m m an d
Address
DQS
DQ
DQS
DQ
BA ,
Col
b
Do
b
D o
b
Rev 1.1 / July. 2009 34
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Non-Consecutive Read Bursts
Random Read Bursts
/C L K
C L K
D o
n
D o
n
R E A D N O P N O P R E A D N O P N O P
B A ,
C o l
n
C L = 3
C L = 2
D o n 't C a re
1 ) D o
n
( o r
b
) : D a ta o u t f ro m c o lu m n n (o r c o lu m n b )
2 ) B A , C o l
n ( b )
= B a n k A , C o lu m n n ( b )
3 ) B u rs t L e n g t h = 4 ; 3 s u b s eq u e n t e l e m e n t s o f D a ta O u t a p p e a r in t h e p ro g ra m m e d o r de r fo llo w in g D o
n (b )
4 ) S h o w n w ith n o m in a l tA C , t D Q S C K a n d tD Q S Q
C o m m a n d
A d d r e ss
D Q S
D Q
D Q S
D Q
B A ,
C o l
b
D o
b
/ C L K
C L K
D o
n
D o
x '
D o
n
R E A D R E A D R E A D R E A D N O P N O P
B A ,
C o l
n
C L = 3
C L = 2
D o n 't C a r e
1 ) D o
n ,
e t c : D a ta o u t f r o m c o lu m n n , e t c
n ', x ', e t c : D a t a O u t e le m e n t s , a c c o d in g t o t h e p r o g ra m m d b u r s t o r d e r
2 ) B A , C o l
n
= B a n k A , C o lu m n n
3 ) B u r s t L e n g t h = 2 , 4 o r 8 i n c a s e s s h o w n ( if b u r s t o f 4 o r 8 , t h e b u r s t is in t e r ru p t e d )
4 ) R e a d a r e t o a c ti v e r o w s i n a n y b a n k s
C o m m a n d
A d d r e s s
D Q S
D Q
D Q S
D Q
B A ,
C o l
b
D o
b
B A ,
C o l
x
B A ,
C o l
g
D o
n '
D o
x
D o
x '
D o
b '
D o
g
D o
g '
D o
n '
D o
x
D o
b
D o
b '
Rev 1.1 / July. 2009 35
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
READ BURST TERMINATE
Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is
equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ com-
mand where X equals the desired data-out element pairs.
Terminating a Read Burst
/CLK
CLK
REA D
BU RST
Te rm in ate
NO P NOP N OP NOP
BA,
Col
n
CL =3
CL =2
Don't Care
1) D o
n
: D ata ou t from colum n n
2) BA, Col
n
= Bank A, Colum n n
3) Cases show n are bursts of 4 or 8 term inated after 2 data elem ents
4) Shown w ith nom inal tAC, tD Q SCK and tDQ SQ
Com m and
Address
DQ S
DQ
DQ S
DQ
Rev 1.1 / July. 2009 36
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
READ to WRITE
Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If trun-
cation is necessary, the BURST TERMINATE command must be used, as shown in next fig. for the case of nominal
t
DQSS
.
Read to Write
/CLK
CLK
Do
n
Do
n
REA D BS T N O P W RIT E N OP
BA,
Col
n
CL =3
CL =2
Don't Care
1) D O
n
= Data Out from colum n n; DI b = D ata In to colum n b
2) Burst length = 4 or 8 in the cases show n ; if the burst length is 2, the BST com mand can be om mitted
3) Show n w ith nom inal tAC, tDQSCK and tDQSQ
Com m and
Address
DQ S
DQ
DQ S
DQ
BA,
Col
b
NO P
DM
READ BST N OP N OP NOP
BA,
Col
n
Com m and
Address BA,
Col
b
W RITE
tDQSS
DI
b
DI
b
Rev 1.1 / July. 2009 37
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
READ to PRECHARGE
A Read burst may be followed by or truncated with a PRECHARGE command to the same bank (provided Auto Pre-
charge was not activated). The PRECHARGE command should be issued X cycles after the READ command, where X
equal the number of desired data-out element pairs.
Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Note that part of the row precharge time is hidden during the access of the last data-out elements.In the case of a
Read being executed to completion, a PRECHARGE command issued at the optimum time (as described above) pro-
vides the same operation that would result from Read burst with Auto Precharge enabled.
The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at
the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to
truncate bursts.
READ to PRECHARGE
/CLK
CLK
Do
n
Do
n
READ NOP PRE NOP NOP ACT
BA,
Col
n
CL =3
CL =2
Don't Care
1) DO
n
= Data Out from column n
2) Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8
3) Shown with nominal tAC, tDQSCK and tDQSQ
4) Precharge may be applied at (BL / 2) tCK after the READ command.
5) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks.
6) The ACTIVE command may be applied if tRC has been met.
Command
Address
DQS
DQ
DQS
DQ
Bank
(
A or All)
BA,
Row
tRP
Rev 1.1 / July. 2009 38
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Write
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;
if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to
that byte / column location.
Basic Write timing parameters for DQ are shown in Figure; they apply to all Write operations.
Basic Write Timing Parameters
During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the
WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of
DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS
following the last data-in element is called the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS (t
DQSS
) is specified with a rel-
atively wide range - from 75% to 125% of a clock cycle. Next fig. shows the two extremes of t
DQSS
for a burst of 4.
Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain high-Z and any
additional input data will be ignored.
/C LK
CLK
tC K tCH tCL
DI n
DI n
D Q S
D Q S
DQ, DM
DQ, DM
tD Q SS tD Q S H
tD SH tD SH
tW PST
tW PRES
tD S tD H
tW PRE
tD S tD H
tW PRES
tW PRE
tD Q SS tD Q S H
tW PST
tD SS tD SS
tD Q SL
D o n't Ca re
1) D I n: Data in for colum n n
2) 3 subseq uent elem ents o f D ata in are ap p lie d in the program m ed o rd e r follow ing D I n
3) tD Q SS : ea c h rising e dg e o f D QS m ust fall w ithin th e + /-25 (percentage) w indow of the corresp o n ding positive c lock edge
tD Q SL
Case 1:
tD Q SS = m in
Case 2:
tD Q SS = m ax
Rev 1.1 / July. 2009 39
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Write Burst (min. and max. t
DQSS
)
/CLK
CLK
WRITE NOP NOP NOP NOP
BA,
Col
b
tDQSS
min
Don't Care
1) DI b = Data In to column b
2) 3 subsequent elem ents of D ata In are applied in the programm ed order following DI b
3) A non-interrupted burst of 4 is shown
4) A10 is low with the W RITE comm and (Auto Precharge is disabled)
Com mand
Address
DQS
DQ
DQS
DQ
NOP
DM
DM
tDQSS
max
Rev 1.1 / July. 2009 40
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
WRITE to WRITE
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case,
a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of
the clock following the previous WRITE command.The first data-in element from the new burst is applied after either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The
new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of
desired data-in element pairs.
Concatenated Write Bursts
/CLK
CLK
WRITE NOP WRITE NOP NOP
BA,
Col
b
tDQSS
min
Don't Care
1) DI
b
(
n
) = Data In to column b (column n)
2) 3 subsequent elements of Data In are applied in the programmed order following DI b.
3 subsequent elements of Data In are applied in the programmed order following DI n.
3) Non-interrupted bursts of 4 are shown.
4) Each WRITE command may be to any active bank
Command
Address
DQS
DQ
DQS
DQ
NOP
DM
DM
BA,
Col
n
DI
b
DI
n
DI
b
DI
n
tDQSS
max
Rev 1.1 / July. 2009 41
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Non-Concatenated Write Bursts
Random Write Cycles
/ C LK
C L K
W R IT E N O P N O P W R IT E N O P
BA ,
C ol
b
D on 't C are
1) D I
b
(
n
) = D at a In to co lu m n b (o r co lu m n n).
2) 3 su b sequ e n t elem e n ts o f D a t a In a re ap plie d in the p rogra m m ed o rd e r fo llo w ing D I
b
.
3 su b seq u en t e lem e n ts of D ata In a re a p p lie d in the p rog ram m ed o rder follow ing D I
n
.
3) N on -int e rru p ted bu rsts o f 4 are sh o w n .
4) E ac h W R ITE c o m m an d m ay b e to an y active b a n k an d m a y b e to the sam e o r diffe ren t dev ice s.
C om m an d
A d d re s s
D Q S
D Q
N O P
D I
b
D M
tD Q S S
m ax
D I
n
B A,
C ol n
/C LK
CL K
W RITE W RITE W RITE W RIT E NO P
BA ,
Co l
b
Don't Care
1) D I b e tc. = D ata In to colum n b, etc.
; b', etc. = th e next D ata In follow in g D I b, etc. a cco rding to the p rog ram m ed bu rs t ord er
2) Program m ed burst length = 2 , 4 or 8 in cases sh ow n. If burst of 4 or 8, burst w o uld be trunc a te d.
3) Eac h W R ITE co m m and m ay be to any ac tive b an k and m ay be to th e sa m e or differen t devices.
Com m and
Add ress
W RITE
BA ,
Co l
n
BA ,
Col
x
BA ,
Co l
a
BA ,
Col
g
D Q S
DM
tD Q S S
m ax
DQ Di
b
Di
b'
Di
x
Di
x'
D i
n
D i
n'
Di
a
Di
a'
Rev 1.1 / July. 2009 42
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
WRITE to READ
Data for any Write burst may be followed by a subsequent READ command. To follow a Write without truncating the
write burst, tWTR should be met as shown in Figure.
Data for any Write burst may be truncated by a subsequent READ command as shown in Figure. Note that the only
data-in pairs that are registered prior to the t
WTR
period are written to the internal array, and any subsequent data-in
must be masked with DM.
/CLK
CLK
WRITE NOP NOP NOP NOP
BA,
Col
b
Don't Care
1) DI
b
= Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b.
2) A non-interrupted burst of 4 is shown.
3) tWTR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
Command
Address
DQS
DQ
READ
DM
tDQSS
max
BA,
Col
n
tWTR CL=3
NOP
Di
b
Rev 1.1 / July. 2009 43
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Interrupting Write to Read
/CLK
CLK
WRITE NOP NOP READ NOP
BA,
Col
b
Don't Care
1) DI
b
= Data In to column b. DO
n
= Data Out from column n.
2) An interrupted burst of 4 is shown, 2 data elements are written.
3 subsequent elements of Data In are applied in the programmed order following DI b.
3) tWTR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) The READ and WRITE commands are to the same device but not necessarily to the same bank.
Command
Address
DQS
DQ
NOP
DM
tDQSS
max
tWTR CL=3
NOP
DI
b
BA,
Col
n
Do
n
Rev 1.1 / July. 2009 44
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto
Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in
Fig.
Non-Interrupting Write to Precharge
/CLK
CLK
WRITE NOP NOP NOP PRE
BA,
Col
b
Don't Care
1) DI b (n) = Data In to column b (column n)
3 subsequent elements of Data In are applied in the programmed order following DI b.
2) A non-interrupted bursts of 4 are shown.
3) tWR is referenced from the positive clock edge after the last Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
Command
Address
DQS
DQ
NOP
DM
tDQSS
max
BA
(A or All)
tWR
DI
b
Rev 1.1 / July. 2009 45
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.
Note that only data-in pairs that are registered prior to the t
WR
period are written to the internal array, and any subse-
quent data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met.
Interrupting Write to Precharge
/CLK
CLK
WRITE NOP NOP NOP NOP
BA,
Col
b
Don't Care
1) DI b = Data In to column b .
2) An interrupted burst of 4 or 8 is shown, 2 data elements are written.
3) tWR is referenced from the positive clock edge after the last desired Data In pair.
4) A10 is LOW with the WRITE command (Auto Precharge is disabled)
5) *1 = can be Don't Care for programmed burst length of 4
6) *2 = for programmed burst length of 4, DQS becomes Don't Care at this point
Command
Address
DQS
DQ
PRE
DM
tDQSS
max
tWR
DI
b
*
2
*
1
*
1
*
1
*
1
BA
(A or All)
Rev 1.1 / July. 2009 46
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with auto precharge disabled). The most recently
registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation sec-
tion of this datasheet. Note the BURST TERMINATE command is not bank specific. This command should not be used
to terminate write bursts.
BURST TERMINATE COMMAND
Don't Care
CS
A0~Amax
WE
CAS
CLK
CLK
CKE
BA0, BA1
RAS
(High)
Rev 1.1 / July. 2009 47
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.
Another command to the same bank (or banks) being precharged must not be issued until the precharge time (t
RP
) is
completed.
If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged,
A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE
command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the
process of precharging.
PRECHARGE command
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but with-
out requiring an explicit command.
This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write
command. This precharges the bank/row after the Read or Write burst is complete.
Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is
desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.
The user must not issue another command to the same bank until the precharge time (t
RP
) is completed.
Don't Care
BA
Bank Address
A10 defines the precharge
mode when a precharge
command, a read command
or a write command is
issued.
If A10 = High when a
precharge command is
issued, all banks are
precharged.
If A10 = Low when a
precharge command is
issued, only the bank that is
selected by BA1/BA0 is
precharged.
If A10 = High when read or
write command, auto-
precharge function is
enabled.
While A10 = Low, auto-
precharge function is
disabled.
CS
A0~A9,
A11
WE
CAS
CLK
CLK
CKE
BA0, BA1
RAS
A10
(High)
Rev 1.1 / July. 2009 48
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
AUTO REFRESH AND SELF REFRESH
Mobile DDR devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two
ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:
-
AUTO REFRESH.
This command is used during normal operation of the Mobile DDR. It is non persistent, so must be issued each time a
refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile DDR requires
AUTO REFRESH commands at an average periodic interval of t
REFI
.
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile DDR, and the
maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*t
REFI
.
-SELF REFRESH.
This state retains data in the Mobile DDR, even if the rest of the system is powered down (even without external clock-
ing). Note refresh interval timing while in Self Refresh mode is scheduled internally in the Mobile DDR and may vary
and may not meet tREFI time.
''Don't Care'' except CKE, which must remain low. An internal refresh cycle is scheduled on Self Refresh entry. The pro-
cedure for exiting Self Refresh mode requires a series of commands. First clock must be stable before CKE going high.
NOP commands should be issued for the duration of the refresh exit time (t
XSR
), because time is required for the com-
pletion of any internal refresh in progress.
The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is
raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recom-
mended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self
Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section.
The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM
operates refresh cycle asynchronously.
The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled (Low). The Mobile DDR
can accomplish an special Self Refresh operation by the specific modes (PASR) programmed in extended mode regis-
ters. The Mobile DDR can control the refresh rate automatically by the temperature value of Auto TCSR (Temperature
Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of
PASR (Partial Array Self Refresh). The Mobile DDR can reduce the self refresh current(I
DD6
) by using these two
modes.
Rev 1.1 / July. 2009 49
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Don't Care
Auto Refresh Command Self Refresh Command
CS
A
0~Amax
WE
CAS
CLK
CLK
CKE
BA0, BA1
RAS
CS
A0~Amax
WE
CAS
CLK
CLK
CKE
BA0, BA1
RAS
(High)
Rev 1.1 / July. 2009 50
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
SELF REFRESH ENTRY AND EXIT
/CLK
CLK
Enter
Self Refresh
Mode
PRE NOP ARF NOP NOP NOP ARF NOP ACT
Pre
All
CKE
Command
Address
A10(AP)
DQ
BA A
Row
n
Row
n
High-Z
Exit
Self Refresh
Mode
Any Command
(Auto Refresh
Recommended)
Cont't Care
tRP tRFC tXSR tRFC
Rev 1.1 / July. 2009 51
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
MODE REGISTER SET
The Mode Register and the Extended Mode Register are loaded via the address bits. BA0 and BA1 are used to select
among the Mode Register, the Extended Mode Register and Status Register. See the Mode Register description in the
register definition section. The MODE REGISTER SET command can only be issued when all banks are idle and no
bursts are in progress, and a subsequent executable command cannot be issued until t
MRD
is met.
MODE REGISTER SET COMMAND
Code = Mode Register / Extended Mode Register selection
(BA0, BA1) and op-code (A0 - An)
tMRD DEFINITION
MRS NOP Valid
Code Valid
tMRD
/CLK
CLK
Command
Address
Don't Care
D on 't Ca re
Code
Code
CS
A0 ~ Am ax
W E
CA S
CL K
CL K
CK E
B A0, BA 1
RAS
(H igh )
Rev 1.1 / July. 2009 52
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Mode Register
The mode register contains the specific mode of operation of the Mobile DDR SDRAM. This register includes the selec-
tion of a burst length(2, 4 or 8), a cas latency(2 or 3), a burst type. The mode register set must be done before any
activate command after the power up sequence. Any contents of the mode register be altered by re-programming the
mode register through the execution of mode register set command.
Mode Register Set
BURST LENGTH
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as
shown in Page10. The burst length determines the maximum number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the
interleaved burst types.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved.
CAS LATENCY
The CAS latency is the delay between the registration of a READ command and the availability of the first piece of out-
put data. If a READ command is registered at a clock edge
n
and the latency is 3 clocks, the first data element will be
valid at
n
+ 2t
CK
+ t
AC
. If a READ command is registered at a clock edge
n
and the latency is 2 clocks, the first data
element will be valid at
n
+ t
CK
+ t
AC
.
CLK
CLK
Precharge
All Bank
Mode
Register
Set
CMD
tCK
Comm and
(any)
0 1 2 3 4 5 6
tRP 2 CLK
min
Rev 1.1 / July. 2009 53
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Extended Mode Register
The Extended Mode Register contains the specific features of self refresh operation of the Mobile DDR SDRAM.
The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=1 and BA0=0) and
will retain the stored information until it is reprogrammed, the device is put in Deep Power-Down mode, or the device
loses power. The Extended Mode Register should be loaded when all Banks are idle and no bursts are in progress, and
subsequent operation should only be initiated after t
MRD
. Violating these requirements will result in unspecified opera-
tion.
The Extended Mode Register is written by asserting low on CS, RAS, CAS, WE and high on BA0. The state of address
pins A0 ~ A12 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode regis-
ter. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the con-
troller must wait the specified time before initiating any subsequent operation. Violating either of these requirements
will result in unspecified operation.
This register includes the selection of partial array to be refreshed (full array, half array, quarter array, etc.). The
extended mode register set must be done before any activate command after the power up sequence. Any contents of
the mode register be altered by re-programming the mode register through the execution of extended mode register
set command.
PARTIAL ARRAY SELF REFRESH (PASR)
With PASR, the self refresh may be restricted to a variable portion of the total array. The whole array (default), 1/2
array, 1/4 array, 1/8 array or 1/16 array could be selected.
DRIVE STRENGTH (DS)
The drive strength could be set to full or half via address bits A5 and A6. The half drive strength is intended for lighter
loads or point-to-point environments.
Rev 1.1 / July. 2009 54
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Status Register Read
The Status Register contains the specific die information such as density, device type, data bus width, refresh rate,
revision ID and manufacturers. The Status Register is only for READ. Below figure is Status Register Read Timing Dia-
gram.
To read out the Status Register values, BA[1:0] set to 01b and A[11:0] set to all 0 with MRS command followed by
Read command with that BA[1:0] and A[11:0] are Don’t care.
Note)
1. SRR can only be issued after power-up sequence is complete.
2. SRR can only be issued with all banks precharged.
3. SRR CL is unchanged from value in the mode register.
4. SRR BL is fixed at 2.
5. tSRR = 2 CLK (min)
6. tSRC = CL + 1. (min time between READ to next valid command)
7. No commands other than NOP and DESELECT are allowed between the SRR and the READ.
CMD
tCK tRP tSRR
NOP MRS NOP READ NOP NOP NOP CMD
Register
Value Out
tSRC
CLK
CLK
CMD
BA[1:0]
Add
DQS
DQ[15:0]
01
0
CL = 3
Don
’
’’
’
t care
PRE All or PRE
Rev 1.1 / July. 2009 55
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
POWER DOWN
Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in
progress. If power down occurs when all banks are idle, it is Precharge Power Down.
If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot
stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is
exited by setting CKE high while issuing a Device Deselect or NOP command.
A valid command can be issued after t
XP
. For Clock stop during power down mode, please refer to the Clock Stop sub-
section in Operation section of this datasheet.
NOTE: This case shows CKE low coincident with NO OPERATION.
Alternately POWER DOWN entry can be achieved with CKE low coincident with Device DESELECT.
DEEP POWER DOWN
The Deep Power Down (DPD) mode enables very low standby currents. All internal voltage generators inside the
Mobile DDR SDRAM are stopped and all memory data is lost in this mode.
All the information in the Mode Register and the Extended Mode Register is lost. Next Figure,
DEEP POWER DOWN
COMMAND
shows the DEEP POWER DOWN command All banks must be in idle state with no activity on the data bus
prior to entering the DPD mode. While in this state, CKE must be held in a constant low state.
To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least
200 us. After 200 us a complete re-initialization routing is required following steps 4 through 11 as defined in POWER-
UP and INITIALIZATION SEQUENCES. DPD is an optional feature, so please contact Hynix office for the DPD feature.
Don't Care Don't Care
DEEP POWER DOWN ENTRY COMMAND
POWER-DOWN ENTRY COMMAND
CS
A0~A11
WE
CAS
CLK
CLK
CKE
BA0, BA1
RAS
CS
A0~A11
WE
CAS
CLK
CLK
CKE
BA0, BA1
RAS
Rev 1.1 / July. 2009 56
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Mobile DDR SDRAM Deep Power Down Entry and Exit
Before entering deep power down the DRAM must be in an all banks idle state with no activity on the data bus. Upon
entering deep power down all data will be lost. While in deep power down CKE must be held in a constant low state.
Upon exiting deep power down NOP command must be maintained for 200us. After 200us a complete initialization
routine is required following steps 4 through 11 as defined in POWER-UP and INITIALIZATION SEQUENCES.
Mobile DDR SDRAM Deep Power-Down Entry and Exit
Note:
1. Clock must be stable before exiting deep power down mode. That is, the clock must be cycling within specifications by Ta0.
2. Device must be in the all banks idle state prior to entering Deep Power Down mode.
3. 200us is required before any command can be applied upon exiting DPD.
4. DPD = Deep Power Down command.
5. Upon exiting Deep Power Down a precharge all command must be issued followed by two auto refresh commands and a load
mode register sequence.
DON'T CARE
NOP DPD
4
NOP VALID
5
VALID
T
0
T
1
Ta0
1
Ta
1
Tb
1
tCK
tIH
tIS
tCH tCL
tIS tIH
tIS tIH tIS
tRP
2
Deep Power Down Mode Exit Deep Power Down Mode
T=200us
3
CK
CK
CKE
COM
ADD
DQS
DQ
DM
tIS
Rev 1.1 / July. 2009 57
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
CAS LATENCY DEFINITION
CAS latency definition of Mobile DDR SDRAM must be must be loaded when all banks are idle, and the controller must
wait the specified time before initiating the subsequent operation.
CAS latency definition: with CL = 3 the first data element is valid at (2 * t
CK
+ t
AC
) after the clock at which the READ
command was registered (See Figure 2)
CAS LATENCY DEFINITION
NOTE
1. DQ transitioning after DQS transition define t
DQSQ
window.
2. All DQ must transition by t
DQSQ
after DQS transitions, regardless of tAC.
3. tAC is the DQ output window relative to CK, and is the long term component of DQ skew.
Read NOP NOP NOP NOP
T
0
T
1
T
3
T
4
T
5
T
2
T
2n
T
3n
T
4n
T
5n
T
6
NOP NOP
T
2
T
2n
T
3
T
3n
T
4
T
4n
T
5
T
5n
All DQ values,
collectively
2
CL = 3
tLZ
tRPRE
tLZ
tDQSCK tDQSCK
tRPST
DQS
CMD
CK
CK
tAC
tDQSQ
Rev 1.1 / July. 2009 58
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Clock Stop Mode
Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption
during idle periods of the device.
Conditions: the Mobile DDR SDRAM supports clock stop in case:
●
The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of required clock pulses per access
command depends on the device's AC timing parameters and the
clock frequency;
●
The related timing condition (t
RCD
, t
WR
, t
RP
, t
RFC
, t
MRD
) has been met;
●
CKE is held HIGH.
When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be
entered with CK held LOW and CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command
have to be issued for at least one clock cycle before the next access command may be applied. Additional clock pulses
might be required depending on the system characteristics.
Figure1 illustrates the clock stop mode:
●
Initially the device is in clock stop mode;
●
The clock is restarted with the rising edge of T0 and a NOP on the command inputs;
●
With T
1
a valid access command is latched; this command is followed by NOP commands in order to allow for clock
stop as soon as this access command has completed;
●
T
n
is the last clock pulse required by the access command latched with T
1.
●
The timing condition of this access command is met with the completion of T
n
; therefore Tn is the last clock pulse
required by this command and the clock is then stopped.
Clock Stop Mode
CK
ADD
CMD NOP NOP NOPNOP
Valid
Clock
Stopped
Exit Clock
Stop Mode
Valid
Command
Enter Clock
Stop Mode Don't Care
(High-Z)
CK
CM
D
T
0
T
1
T
2
T
n
CKE
DQ,
DQS
Timing Condition
Rev 1.1 / July. 2009 59
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
Data mask
1,2)
Mobile DDR SDRAM uses a DQ write mask enable signal (DM) which masks write data.
Data masking is only available in the write cycle for Mobile DDR SDRAM. Data masking is available during write, but
data masking during read is not available.
DM command masks burst write data with reference to data strobe signal and it is not related with read data. DM com-
mand can be initiated at both the rising edge and the falling edge of the DQS. DM latency for write operation is zero.
For x16 data I/O, Mobile DDR SDRAM is equipped with LDM and UDM which control DQ0~DQ7 and DQ8~DQ15
respectively.
Note:
1) Mobile SDR SDRAM can mask both read and write data, but the read mask is not supported by Mobile DDR SDRAM.
2) Differences in Functions and Specifications (next table)
Data Masking (Write cycle: BL=4)
Item Mobile DDR SDRAM Mobile SDR SDRAM
Data mask
Write mask only
Write mask/Read mask
WRITE WRITE
DM
CMD
CK
CK
D0 D1 D3 D0 D1 D3
Hi-
Z
DQS
DQ
Data
Masking
Data
Masking
tDQSS
tDQSL
tDS tDH
tDQSH
Hi-
Z
Rev 1.1 / July. 2009 60
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
POWER-UP AND INITIALIZATION SEQUENCES
Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other thank
those specified may result in undefined operation. If there is any interruption to the device power, the initialization
routine should be followed. The steps to be followed for device initialization are listed below.
●
●●
●
Step1: Provide power, the device core power (V
DD
) and the device I/O power (V
DDQ
) must be brought up simulta-
neously to prevent device latch-up. Although not required, it is recommended that V
DD
and V
DDQ
are from
the same power source. Also assert and hold CLOCK ENABLE (CKE) to a LVCMOS logic high level.
●
●●
●
Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply stable
clock.
●
●●
●
Step 3: There must be at least 200us of valid clocks before any command may be given to the DRAM. During this
time NOP or DESELECT commands must be issued on the command bus.
●
●●
●
Step 4: Issue a PRECHARGE ALL command.
●
●●
●
Step 5: Provide NOPs or DESELECT commands for at least t
RP
time.
●
●●
●
Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least t
RFC
time. Issue
the second AUTO REFRESH command followed by NOPs or DESELECT command for at least t
RFC
time.
Note as part of the initialization sequence there must be two auto refresh commands issued. The typical
flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.
●
●●
●
Step 7: Using the MRS command, load the base mode register. Set the desired operating modes.
●
●●
●
Step 8: Provide NOPs or DESELECT commands for at least t
MRD
time.
●
●●
●
Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note the
order of the base and extended mode register programming is not important.
●
●●
●
Step 10: Provide NOP or DESELCT commands for at least t
MRD
time.
●
●●
●
Step 11: The DRAM has been properly initialized and is ready for any valid command.
Rev 1.1 / July. 2009 61
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
The Initialization flow sequence is below.
Initialization Waveform Sequence
VDD
VDDQ
/CLK
CLK
CKE
CMD
DM
ADDR
A10
BA0,
BA1
DQ,
DQS
T=200usec tRP tMRD
tRFC tMRD
VDD/VDDQ
Powered up
CLOCK stable
Auto
Refresh
NOP ARFPRE MRSARF ACTMRS
CODE RACODE
CODE RACODE
BA0=L
BA1=L BA
BA0=L
BA1=H
tRFC
Load
Mode
Register
tCH tCL
tCK
ALL
BANKS
tIS tIH
tIS tIH
tIS tIH
tIS tIH
DON'T CARE
High-Z
Precharge
All
Auto
Refresh
Load
Extended
Mode
Register
Rev 1.1 / July. 2009 62
Mobile DDR SDRAM 128Mbit (8M x 16bit)
H5MS1262EFP Series
PACKAGE INFORMATION
60 Ball 0.8mm pitch 8mm FBGA [8.0 x 10.0 mm
2
, t=1.0mm max]
Unit
[mm]
0.8
Bottom
VIEW
0.340
+/-0.05
0.80 Typ.
0.80
Typ. 1.00 max
3.20
1.60
0.450
+/- 0.05
A1 INDEX MARK
1.375
10.00
Typ.
1.40
8
.
00
Typ
.