LT4295
1
Rev. B
For more information www.analog.com
TYPICAL APPLICATION
FEATURES DESCRIPTION
IEEE 802.3bt PD Interface
with Forward/Flyback Controller
IEEE 802.3bt 71.3W (Class 8) PD Controller and Power Supply in Forward Mode
APPLICATIONS
n High Power Wireless Data Systems
n Outdoor Security Camera Equipment
n Commercial and Public Information Displays
n High Temperature Applications
n IEEE 802.3af/at/bt Powered Device (PD) with
Forward/Flyback Controller
n Supports Up to 71.3W PDs
n 5-Event Classification Sensing
n Superior Surge Protection (100V Absolute Maximum)
n Wide Junction Temperature Range (–40°C to 125°C)
n >94% End-to-End Efficiency with LT4321 Ideal Bridge
n External Hot Swap N-Channel MOSFET for Lowest
Power Dissipation and Highest System Efficiency
n No-Opto Flyback Operation
n Auxiliary Power Support as Low as 9V
n Easy Migration of LTPoE++
®
PDs to IEEE 802.3bt PDs
n Pin Compatible with LT4276A/B/C
n 28-Lead 4mm × 5mm QFN Package
The LT
®
4295 is an IEEE 802.3af/at/bt-compliant powered
device (PD) interface controller with a switching regulator
controller. The T2P output indicates the number of clas-
sification events received during IEEE 802.3bt-compliant
mutual identification and negotiation of available power.
The LT4295 supports both forward and flyback power
supply topologies. The flyback topology supports No-Opto
feedback. Auxiliary input voltages can be accurately sensed
with just a resistor divider connected to the AUX pin.
The LT4295 utilizes an external, low RDS(on) N-channel
hot swap MOSFET and supports the LT4320/LT4321 ideal
diode bridges, to extend the end-to-end power delivery
efficiency and eliminate costly heat sinks.
The LT4295 also includes an on-chip detection signature
resistor, thermal protection, slope compensation, and
many user configurable settings including classification
signature, inrush current, switcher frequency, gate drive
delay, soft-start and load compensation.
••
VPORT
VPORT
RCLASS
AUX
RCLASS++
SW
VCC VCC
VIN
VCC
0.1µF
10µFBAV19WS
(TRR ≤50ns)
22µF
HS
GATE HS
SRC FFS
DLY PG
SG
ITHB
TO MICROPROCESSOR
ISEN+
ISEN–
4295 TA01
GND FB31 ROSC T2PSS
100µH
AUX
37V TO 57V
+
–
–
+
FMMT723
20mΩ
5V
13A
+
–
3.3k
10k
0.1µF 100pF
10nF
100k
LT4295
OPTO
+
Single-Signature
Power Classification
(at PD Input)
CLASS POWER
0 13W
1 3.84W
2 6.49W
3 13W
4 25.5W
5 40W
6 51W
7 62W
8 71.3W
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LT4295
2
Rev. B
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VPORT, HSSRC, VIN Voltages .................. –0.3V to 100V
HSGATE Current.................................................. ±20mA
VCC Voltage .................................................. –0.3V to 8V
RCLASS, RCLASS++
Voltages .............................. –0.3V to 8V (and ≤ VPORT)
SFST, FFSDLY, ITHB, T2P Voltages ... –0.3V to VCC+0.3V
ISEN+, ISEN– Voltages ...........................................±0.3V
FB31 Voltage ..................................................+12V/–30V
RCLASS/RCLASS++ Current .............................. –50mA
AUX Current ........................................................ ±1.4mA
ROSC Current ..................................................... ±100µA
RLDCMP Current ................................................±500µA
T2P Current .........................................................–2.5mA
Operating Junction Temperature Range (Note 3)
LT4295I ................................................–40°C to 85°C
LT4295H ............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
9 10
TOP VIEW
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJC = 3.4°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
11 12 13
28 27 26 25 24
14
23
6
5
4
3
2
1
GND
AUX
RCLASS++
RCLASS
T2P
VCC
VCC
VCC
DNC
VCC
PG
GND
SG
ISEN+
ISEN–
RLDCMP
VPORT
NC
HSGATE
HSSRC
VIN
SWVCC
VCC
ROSC
SFST
FFSDLY
ITHB
FB31
7
17
18
19
20
21
22
16
815
29
GND
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT4295IUFD#PBF LT4295IUFD#TRPBF 4295 28-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C
LT4295HUFD#PBF LT4295HUFD#TRPBF 4295 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
ORDER INFORMATION
LT4295
3
Rev. B
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VPORT, HSSRC, VIN Operating Voltage At VPORT Pin l60 V
VSIG VPORT Detection Signature Range At VPORT Pin l1.5 10 V
VCLASS VPORT Classification Signature Range At VPORT Pin l12.5 21 V
VMARK VPORT Mark Event Range At VPORT Pin, After 1st Classification Event l5.6 10 V
VPORT AUX Range At VPORT Pin, VAUX ≥ 6.45V l8 60 V
Detect/Class Hysteresis Window l1.0 V
Reset Threshold l2.6 5.6 V
VHSON Hot Swap Turn-On Voltage l 35 37 V
VHSOFF Hot Swap Turn-Off Voltage l 30 31 V
Hot Swap On/Off Hysteresis Window l3 V
Supply Current
VPORT, HSSRC and VIN Supply Current VVPORT = VHSSRC = VVIN = 60V l2 mA
VPORT Supply Current During Classification VVPORT = 17.5V, RCLASS, RCLASS++ Open l0.7 1.0 1.3 mA
VPORT Supply Current During Mark Event VVPORT = VMARK after 1st Classification Event l0.4 2.2 mA
Detection and Classification Signature
Detection Signature Resistance VSIG (Note 4) l23.6 24.4 25.5 kΩ
Resistance During Mark Event VMARK (Note 4) l5.2 8.3 11.4 kΩ
RCLASS/RCLASS++ Voltage –10mA ≥ IRCLASS ≥ –36mA, VCLASS l1.36 1.40 1.43 V
Classification Signature Stability Time VVPORT Step GND to 17.5V,
35.7Ω from RCLASS to GND
l2 ms
Digital Interface
VAUXT AUX Threshold VPORT = 17.5V, VIN = VHSSRC = 18.5V l6.05 6.25 6.45 V
IAUXH AUX Pin Current VAUX = 6.05V, VPORT = 17.5V, VIN = 9V, VCC = 0V l3.3 5.3 7.3 µA
T2P Output High VVCC - VT2P, –1mA Load l0.3 V
T2P Leakage VT2P = 0V l–1 1 µA
Hot Swap Control
IGPU HSGATE Pull Up Current VHSGATE - VHSSRC = 5V (Note 5) l–27 –22 –18 µA
HSGATE Voltage –10µA Load, with Respect to HSSRC l10 14 V
HSGATE Pull Down Current VHSGATE - VHSSRC = 5V l400 µA
VCC Supply
VCCREG VCC Regulation Voltage l7.2 7.6 8.0 V
Feedback Amplifier
VFB FB31 Regulation Voltage l3.11 3.17 3.23 V
FB31 Pin Bias Current RLDCMP Open -0.1 µA
gm Feedback Amplifier Average
Trans-Conductance Time Average, –2µA < IITHB < 2µA l–52 –40 –26 µA/V
ISINK ITHB Average Sink Current Time Average, VFB31 = 0V l4.4 8.0 13.4 µA
Soft-Start
ISFST Charging Current VSFST = 0.5V, 3.0V l–49 –42 –36 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVPORT = VHSSRC = VVIN = 40V, VVCC = VCCREG, ROSC, PG, and SG Open,
RFFSDLY = 5.23kΩ to GND. AUX connected to GND unless otherwise specified. (Note 2)
LT4295
4
Rev. B
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Outputs
PG, SG Output High Level I = –1mA lVCC –0.1 V
PG, SG Output Low Level I = 1mA l1 V
PG Rise Time, Fall Time PG = 1000pF 15 ns
SG Rise Time, Fall Time SG = 400pF 15 ns
Current Sense/Overcurrent
VFAULT Overcurrent Fault Threshold VISEN+ – VISEN–l125 140 155 mV
ΔVSENSE/
ΔVITHB
Current Sense Comparator Threshold with
Respect to VITHB
l–130 –111 –92 mV/V
VITHB(OS) VITHB Offset l3.03 3.17 3.33 V
Timing
fOSC Default Switching Frequency ROSC Pin Open l 200 214 223 kHz
Switching Frequency 45.3kΩ from ROSC to GND l280 300 320 kHz
fT2P T2P Signal Frequency fSW/256
T2P Duty Cycle in PoE Operation (Note 7) After 4-Event Classification
After 5-Event Classification
(RCLASS++ Has Resistor to GND)
50
25 %
%
T2P Duty Cycle in Auxiliary Supply
Operation (Note 7) V(AUX) > VAUXT, and RCLASS++ Has Resistor to
GND 25 %
tMIN Minimum PG On Time l175 250 330 ns
DMAX Maximum PG Duty Cycle l63 66 70 %
tPGDELAY PG Turn-On Delay-Flyback
PG Turn-On Delay-Forward
5.23kΩ from FFSDLY to GND
52.3kΩ from FFSDLY to GND
10.5kΩ from FFSDLY to VCC
52.3kΩ from FFSDLY to VCC
45
171
92
391
ns
ns
ns
ns
tFBDLY Feedback Amp Enable Delay Time 350 ns
tFB Feedback Amp Sense Interval 550 ns
tPGSG PG Falling to SG Rising Delay Time-Flyback
PG Falling to SG Falling Delay Time-
Forward
Resistor from FFSDLY to GND
10.5kΩ from FFSDLY to VCC
52.3kΩ from FFSDLY to VCC
20
67
301
ns
ns
ns
tSTART Start Timer (Note 6) Delay After Power Good l80 86 93 ms
tFAULT Fault Timer (Note 6) Delay After Overcurrent Fault l80 86 93 ms
IMPS MPS Current l10 12 14 mA
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VVPORT = VHSSRC = VVIN = 40V, VVCC = VCCREG, ROSC, PG, and SG Open,
RFFSDLY = 5.23kΩ to GND. AUX connected to GND unless otherwise specified. (Note 2)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltages with respect to GND unless otherwise noted. Positive
currents are into pins; negative currents are out of pins unless otherwise
noted.
Note 3. This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature can exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4. Detection signature resistance specifications do not include
resistance added by the external diode bridge which can add as much as
1.1kΩ to the port resistance.
Note 5. IGPU available in PoE powered operation. That is, available after
V(VPORT) > VHSON and V(AUX) < VAUXT, over the range where V(VPORT) is
between VHSOFF and 60V.
Note 6. Guaranteed by design, not subject to test.
Note 7. Specified as the percentage of the period which T2P is low
impedance with respect to VCC.
LT4295
5
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
VFB31 vs Temperature
Feedback Amplifier Output Current
vs VFB31
Switching Frequency
vs Temperature
Current Sense Voltage
vs Duty Cycle, ITHB
PG Delay Time vs Temperature in
Flyback Mode
PG, SG Delay Time vs
Temperature in Forward Mode
Input Current vs Input Voltage
25k Detection Signature Range
Detection Signature Resistance
vs Input Voltage VCC Current vs Temperature
VPORT VOLTAGE (V)
0
0
VPORT CURRENT (mA)
0.4
0.3
0.2
0.1
0.5
6 8
10
2 4
4295 G01
125°C
85°C
25°C
–40°C
VPORT VOLTAGE (V)
1
23.75
SIGNATURE RESISTANCE (kΩ)
25.75
25.25
24.75
24.25
26.25
65 87
9
2 43
4295 G02
125°C
85°C
25°C
–40°C
TEMPERATURE (°C)
–50
0
V
CC
CURRENT (mA)
10
8
6
4
2
12
5025 10075
125
0–25
4295 G03
214kHz
300kHz
TEMPERATURE (°C)
–50
3.162
V
FB31
(V)
3.176
3.174
3.172
3.170
3.168
3.166
3.164
3.178
5025 10075
125
0–25
4295 G04
FB31 VOLTAGE (V)
2.57
–15
ITHB CURRENT (µA)
10
5
–5
0
–10
15
3.17 3.37 3.57
3.77
2.77 2.97
4295 G05
125°C
85°C
25°C
–40°C
TEMPERATURE (°C)
–50
0
DELAY TIME (ns)
350
200
250
300
150
100
50
400
5025 10075
125
0–25
4295 G09
TPGDELAY, 52.3k FROM FFSDLY TO VCC
TPGSG, 52.3k FROM FFSDLY TO VCC
TPGDELAY, 10.5k FROM FFSDLY TO VCC
TPGSG, 10.5k FROM FFSDLY TO VCC
TEMPERATURE (°C)
–50
175
FREQUENCY (kHz)
300
275
250
225
200
325
5025 10075
125
0–25
4295 G06
45.3k FROM ROSC TO GND
ROSC OPEN
VITHB = 1.8V
VITHB = 2.3V
VITHB = 2.6V
VITHB = 2.9V
DUTY CYCLE (%)
0
0
V
(ISEN+ - ISEN–)
(mV)
140
80
100
120
60
40
20
160
4030 6050
70
2010
4295 G07
VITHB = 0.96V (FB31 = 0V)
TEMPERATURE (°C)
–50
0
PG DELAY TIME (ns)
200
150
100
50
250
5025 10075 1250–25
4295 G08
TPGDELAY, 5.23k FROM FFSDLY TO GND
TPGDELAY, 52.3k FROM FFSDLY TO GND
LT4295
6
Rev. B
For more information www.analog.com
PIN FUNCTIONS
GND(Pins 1, 19, Exposed Pad Pin 29): Device Ground.
Exposed Pad must be electrically and thermally connected
to pins 1, 19 and PCB GND.
AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive
divider from the auxiliary power input to set the voltage
at which the auxiliary supply takes over. Asserting AUX
pulls down HSGATE, disconnects the detection signature
resistor and disables classification signature. The AUX pin
sinks I
AUXH
when below its threshold voltage, of V
AUXT
, to
provide hysteresis. Connect to GND if not used.
RCLASS++ (Pin 3): Class Select Input. Connect a resistor
between RCLASS++ to GND per Table1.
RCLASS (Pin 4): Class Select Input. Connect a resistor
between RCLASS and GND per Table1.
T2P (Pin 5): PSE Type Indicator. Open drain with respect
to VCC. See the T2P Output section for pin behavior.
VCC (Pins 6, 7, 8, 9, 21): Switching Regulator Controller
Supply Voltage. Connect a local ceramic capacitor from
VCC pin 21 to GND pin 19 as close as possible to LT4295
as shown in Table3.
ROSC (Pin 10): Programmable Frequency Adjustment.
Resistor to GND programs operating frequency. Leave
open for default frequency of 214kHz.
SFST (Pin 11): Soft-Start. Capacitor to GND sets soft-
start timing.
FFSDLY (Pin 12): Forward/Flyback Select and Primary
Gate Delay Adjustment. Resistor to GND adjusts gate
drive delay for a flyback topology. Resistor to VCC adjusts
gate drive delay for a forward topology.
ITHB (Pin 13): Current Threshold Control. The voltage
on this pin corresponds to the peak current of the exter-
nal primary FET. Note that the voltage gain from ITHB to
the input of the current sense comparator (VSENSE) is
negative.
FB31 (Pin 14): Feedback Input. In flyback mode, connect
external resistive divider from the third winding feedback.
Reference voltage is 3.17V. Connect to GND in forward
mode.
RLDCMP (Pin 15): Load Compensation Adjustment.
Optional resistor to GND controls output voltage set point
as a function of peak switching current. Leave RLDCMP
open if load compensation is not needed.
ISEN– (Pin 16): Current Sense, Negative Input. Route as
a dedicated trace to the return side of the current sense
resistor.
ISEN+ (Pin 17): Current Sense, Positive Input. Route as
a dedicated trace to the sense side of the current sense
resistor.
SG (Pin 18): Secondary (Synchronous) Gate Drive Output.
PG (Pin 20): Primary Gate Drive Output.
DNC (Pin 22): Do Not Connect. Leave pin open.
SWVCC (Pin 23): Switch Driver for VCC’s Buck Regulator.
This pin drives the base of a PNP in a buck regulator to
generate VCC.
VIN (Pin 24): Buck Regulator Supply Voltage. Usually
separated from HSSRC by a pi filter.
HSSRC (Pin 25): External Hot Swap MOSFET Source.
Connect to source of the external MOSFET.
HSGATE (Pin 26): External Hot Swap MOSFET Gate
Control Output. Capacitance to GND determines inrush
time.
NC (Pin 27): No Connection. Not internally connected.
VPORT (Pin 28): PD Interface Supply Voltage and External
Hot Swap MOSFET Drain Connection.
LT4295
7
Rev. B
For more information www.analog.com
BLOCK DIAGRAM
–
+
–
+
–
+
+
–
–
+
–
+
–
+
+
–
+
–
SLOPE
COMP
OSC
TSD
CP
SWITCHING
REGULATOR
CONTROLLER
PD INTERFACE
CONTROLLER
START-UP
REGULATOR
INTERNAL
BUCK
CONTROLLER
1.4V
1.4V
HSGATE
HSSRC
11V
VPORT
VPORT SWVCCV
IN
VCC
ITHB
SFST
FFSDLY
ROSC
ISEN+
ISEN–
4295 BD
T2P
GND
PG
SG
VCC
VPORT
RCLASS
RCLASS
++
AUX
VAUXT
IAUXH
FB31
RLDCMP
FEEDBACK AMP
gm = –40µA/V
LOAD
COMP
CURRENT
FAULT
COMPARATOR
CURRENT
SENSE
COMPARATOR
VFB
VFAULT
AV = 10
AV = 1
VCC
VSENSE
VITHB(OS)
AV =∆VSENSE
∆VITHB
LT4295
8
Rev. B
For more information www.analog.com
OVERVIEW
Power over Ethernet (PoE) continues to gain popularity as
products take advantage of the combination of DC power
and high speed data available from a single RJ45 con-
nector. The LT4295 is IEEE 802.3bt-compliant and allows
up to 71.3 Watt operation while maintaining backwards
compatibility with existing PSE systems. The LT4295
combines a PoE PD interface controller and a switching
regulator controller capable of either flyback or forward
isolated power supply operation.
SIGNIFICANT DIFFERENCES FROM PREVIOUS
PRODUCTS
The LT4295 has several significant differences from pre-
vious Analog Devices products. These differences are
briefly summarized below.
IEEE 802.3bt vs LTPoE++ Available PD Power
The LT4295 supports IEEE 802.3bt PD power levels up
to 71.3 Watts. A PD requiring more than 71.3 Watts is
beyond the allowable power levels of IEEE 802.3bt.
The LT4293, LT4275A and LT4276A are available to sup-
port PD power levels up to 90W under the LTPoE++ stan-
dard. See the Related Parts section for a list of LTPoE++
PSEs and PDs.
ITHB Is Inverted from the Usual ITH pin
The ITHB pin voltage has an inverse relationship to the cur-
rent sense comparator threshold, VSENSE. Furthermore, the
ITHB pin offset voltage, VITHB(OS), is 3.17V. See Figure1.
APPLICATIONS INFORMATION
Figure1. VSENSE vs. VITHB
Duty-Cycle Based Soft-Start
The LT4295 uses a duty cycle ramp soft-start that injects
charge into ITHB. This allows startup without appreciable
overshoot using inexpensive external components.
The Feedback Pin FB31 is 3.17V Rather Than 1.25V
The error amp feedback voltage VFB is 3.17V.
Flyback/Forward Mode Is Pin Selectable
The LT4295 operates in flyback mode if FFSDLY is pulled
down by a resistor to GND. It operates in forward mode
if FFSDLY is pulled up by a resistor to VCC. The value of
this resistor determines the tPGDELAY and tPGSG.
T2P Pin Response
The T2P pin outputs high impedance to VCC, low imped-
ance to VCC, 50% duty cycle, or 25% duty cycle, respon-
sive to the number of class/mark event and responsive to
Table1. Single-Signature Classification, Power Levels and Resistor Selection
PD REQUESTED
CLASS PD REQUESTED POWER PD TYPE NOMINAL CLASS CURRENT
RESISTOR (1%)
RCLS RCLS++
0 13W Type 1 2.5mA 1.00kΩ Open
1 3.84W Type 1 or 3 10.5mA 150Ω Open
2 6.49W Type 1 or 3 18.5mA 80.6Ω Open
3 13W Type 1 or 3 28mA 52.3Ω Open
4 25.5W Type 2 or 3 40mA 35.7Ω Open
5 40W Type 3 40mA/2.5mA 1.00kΩ 37.4Ω
6 51W Type 3 40mA/10.5mA 150Ω 47.5Ω
7 62W Type 4 40mA/18.5mA 80.6Ω 64.9Ω
8 71.3W Type 4 40mA/28mA 52.3Ω 118Ω
V
SENSE
∆VSENSE
∆VITHB
VITHB
VITHB(OS)
4295 F01
LT4295
9
Rev. B
For more information www.analog.com
Figure2. Type 3 or Type 4 PSE, 1-Event Class Sequence
Figure3. Type 2 PSE, 2-Event Class Sequence
APPLICATIONS INFORMATION
PoE or auxiliary power operation. See T2P Output section
in the Applications Information.
VCC Is Powered by Internally Driven Buck Regulator
The LT4295 includes a buck regulator controller that must
be used to generate the VCC supply voltage.
POE MODES OF OPERATION
The LT4295 has several modes of operation, depending
on the input voltage sequence applied to the VPORT pin.
Detection Signature
During detection, the PSE looks for a 25kΩ detection sig-
nature resistor which identifies the device as a PD. The
LT4295 detection signature resistor is smaller than 25k
to compensate for the additional series resistance intro-
duced by the IEEE required diode bridge or the LT4321-
based ideal diode bridge.
IEEE 802.3bt Single-Signature vs Dual-Signature PDs
IEEE 802.3bt defines two PD topologies: single-signature and
dual-signature. The LT4295 primarily targets single-signature
PD topologies, eliminating the need for a second PD control-
ler. All PD descriptions and IEEE 802.3 standard references in
this data sheet are limited in scope to single-signature PDs.
The LT4295 may be deployed in dual-signature PD appli-
cations. For more information, contact Analog Devices
Applications.
Classification Signature and Mark
The class/mark process varies depending on the PSE type.
A PSE, after a successful detection, may apply a classifi-
cation probe voltage of 15.5V to 20.5V and measure the
PD classification signature current. Once the PSE applies a
classification probe voltage, the PSE returns the PD voltage
into the mark voltage range before applying another clas-
sification probe voltage, or powering up the PD.
An example of 1-Event classification is shown in Figure2.
In 2-Event classification, a PSE probes for power clas-
sification twice as shown in Figure3. An IEEE 802.3bt
PSE may apply as many as 5 events before powering up
the PD.
4295 F02
V
PORT
VHSON
VHSOFF
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST MARK
1ST CLASS
POWER ON
4295 F03
V
PORT
VHSON
VHSOFF
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST CLASS
1ST MARK 2ND MARK
2ND CLASS
POWER ON
IEEE 802.3bt Physical Classification and Demotion
IEEE 802.3bt defines physical classification to allow a PD
to request a power allocation from the connected PSE and
to allow the PSE to inform the PD of the PSE’s available
power. Demotion is provided if the PD Requested Power
level is not available at the PSE. If demoted, the PD must
operate in a lower power state.
IEEE 802.3bt provides nine PD classes and four PD types,
as shown in Table1. The LT4295 class is configured by
setting the RCLS and RCLS++ resistor values.
The number of class/mark events issued by the PSE
directly indicates the power allocated to the PD and is
summarized in Table2.
LT4295
10
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Table2. PSE Allocated Power
PD REQUESTED
CLASS
NUMBER OF PSE CLASS/MARK EVENTS
12345
0 13W
1 3.84W
2 6.49W
3 13W
413W 25.5W
513W 25.5W 40W
613W 25.5W 51W
713W 25.5W 51W 62W
813W 25.5W 51W 71.3W
Note: Bold indicates the PD has been demoted.
IEEE 802.3bt PSEs present a single classification event
(see Figure 2) to Class 0 through 3 PDs. A Class 0
through3 PD presents its class signature to the PSE and
is then powered on if sufficient power is available. Power
limited IEEE 802.3bt PSEs may issue a single event to
Class 4 and higher PDs in order to demote those PDs to
Class 3 (13W).
IEEE 802.3bt PSEs present up to three classification
events depending on type to Class 4 PDs (see Figure4).
Class 4 PDs present a class signature 4 on all events. This
third event differentiates a Class 4 PD from a higher class
PD. Power limited IEEE 802.3bt PSEs may issue three
events to Class 5 and higher PDs in order to demote those
PDs to Class 4 (25.5W).
Figure4. Type 3 or Type 4 PSE, 3-Event Class Sequence
Figure5. Type 3 or Type 4 PSE, 4-Event Class Sequence
Figure6. Type 4 PSE, 5-Event Class Sequence
4295 F04
V
PORT
VHSON
VHSOFF
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST CLASS
1ST MARK 2ND MARK 3RD MARK
2ND CLASS 3RD CLASS
POWER ON
4295 F05
V
PORT
VHSON
VHSOFF
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST
CLASS 2ND
CLASS 3RD
CLASS 4TH
CLASS
POWER ON
1ST
MARK 2ND
MARK 3RD
MARK 4TH
MARK
4295 F06
V
PORT
VHSON
VHSOFF
VCLASSMIN
VMARKMAX
VSIGMIN
VRESET
DETECT
1ST
CLASS 2ND
CLASS 3RD
CLASS 4TH
CLASS 5TH
CLASS
POWER ON
1ST
MARK 2ND
MARK 3RD
MARK 4TH
MARK 5TH
MARK
IEEE 802.3bt PSEs present four classification events (see
Figure5) to Class 5 and 6 PDs. Class 5 and 6 PDs present
a class signature 4 on the first two events. Class 5 and 6
PDs present a class signature 0 or 1, respectively, on the
remaining events. Power limited IEEE 802.3bt PSEs may
issue four events to Class 7 and higher PDs in order to
demote those PDs to Class 6 (51W).
IEEE 802.3bt PSEs present five classification events (see
Figure6) to Class 7 and 8 PDs. Class 7 and 8 PDs present
a class signature 4 on the first two events. Class 7 and 8
PDs present a class signature 2 or 3 respectively, on the
remaining events.
The PD must monitor the number of classification/mark
events, which is communicated through the LT4295
T2Ppin.
LT4295
11
Rev. B
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APPLICATIONS INFORMATION
Figure7. Programming IINRUSH
Figure8. VCC Buck Regulator
Classification Resistors (RCLS and RCLS++)
The R
CLS
and R
CLS++
resistors set the classification cur-
rents corresponding to the PD power classification. Select
the value of RCLS and RCLS++ from Table1 and connect the
1% resistor between the RCLASS, RCLASS++ pin and GND.
Detection Signature Corrupt During Mark Event
During the mark event, the LT4295 presents <11kΩ to the
port as required by the IEEE 802.3 specification.
Inrush and Powered On
After the PSE detects and optionally classifies the PD, the
PSE then powers on the PD. When the PD port voltage
rises above the VHSON threshold, it begins to source IGPU
out of the HSGATE pin. This current flows into an external
capacitor CGATE in Figure7 and causes a voltage to ramp
up the gate of the external MOSFET. The external MOSFET
acts as a source follower and ramps the voltage up on
the output bulk capacitor, CPORT, thereby determining the
inrush current, IINRUSH. Design IINRUSH to be ~100mA.
LT4295
HSGATE
GND
4276 F07
VPORT HSSRC
CGATE
IGPU
3.3k
+
C
PORT
VPORT
I
INRUSH
IINRUSH =IGPU •CPORT
CGATE
the switching regulator controller operates after a delay
of tSTART.
EXTERNAL VCC SUPPLY
The external VCC supply must be configured as a buck reg-
ulator shown in Figure8. To optimize the buck regulator,
use the external component values in Table3 correspond-
ing to the VIN operating range. This buck regulator runs
in discontinuous mode with the inductor peak current
considerably higher than average load current on VCC.
Thus, the saturation current rating of the inductor must
exceed the values shown in Table3. Place the capacitor, C,
as close as possible to VCC pin 21 and GND pin 19. For
optimal performance, place these components as close
as possible to the LT4295.
V
IN
Re
VCC
VIN
VCC
GND
SWVCC
LT4295
FMMT723
PBSS9110T
L
D
C
4276 F08
The LT4295 internal charge pump enables an N-channel
MOSFET solution, replacing a larger and more costly
P-channel FET. The low RDS(ON) MOSFET also maximizes
power delivery and efficiency, reduces power and heat
dissipation, and eases thermal design.
DELAY START
After the HSGATE charges up to approximately 7V above
HSSRC, fully enhancing the external hot swap MOSFET,
Table3. Buck Regulator Component Selection
VIN C L ISAT ReD
9V-57V
PoE 22µF
10µF 22µH
100µH ≥1.2A
≥300mA
1Ω
20Ω Schottky
Ultrafast Diode
AUXILIARY SUPPLY OVERRIDE
If the AUX pin is held above V
AUXT
, the LT4295 enters
auxiliary power operation. In this mode the detection sig-
nature resistor is disconnected, classification is disabled,
and HSGATE is pulled down.
The AUX pin allows for setting the auxiliary supply turn
on (V
AUXON
) and turn off (V
AUXOFF
) voltage thresholds.
The auxiliary supply hysteresis voltage, VAUXHYS, is set
by sinking current, IAUXH, only when the AUX pin voltage
is less than VAUXT. Use the following equations to set
LT4295
12
Rev. B
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APPLICATIONS INFORMATION
VAUXON and VAUXOFF via R1 and R2 in Figure9. Note that
an internal 6.5V Zener limits the voltage on the AUX pin.
A capacitor up to 1000pF may be placed between the AUX
pin and GND to improve noise immunity. VAUXON must be
lower than VHSOFF.
is determined by the AUX pin, the RCLASS++ pin, and
the number of classification events. The LT4295 uses a
4-state encoding for the T2P output. T2P state and the
associated PSE allocated power are shown in Table4.
The highest priority input is the AUX pin. AUX is asserted
to enter the auxiliary power state and deasserted to
enter the PoE state. In the auxiliary power state, the T2P
pin indicates the highest available power, based on PD
Requested Class. The auxiliary power supply must be
sized to provide at least the PD Requested Power.
Second, PD Requested Class and PD Requested Power
are configured using the RCLASS and RCLASS++ pins. The
RCLASS++ pin alone can be used to determine if the PD
Class is 0−4 or 5−8, as shown in Table1.
Last, the number of classification events determines
the amount of power allocated by the PSE as described
inTable2.
Figure9. AUX Threshold and Hysteresis Calculation
LT4295
GND
4295 F09
AUX
R1
VAUX
+
–
R2
R1=
V
AUXON
−V
AUXOFF
IAUXH =
V
AUXHYS
IAUXH
R2 =R1
VAUXOFF
VAUXT −1
R1≥VAUX(MAX) −VAUXT
1.4mA
T2P Output
The LT4295 communicates the PSE allocated power to
the PD application via the T2P pin. The T2P pin state
Table4. T2P Response to Determine PSE Allocated Power
STATE
PD REQUESTED
CLASS
NUMBER OF
CLASSIFICATION
EVENTS T2P* PSE ALLOCATED POWER
Auxiliary 0−4 N/A Low-Z Aux. Power
5-8 N/A 25% Aux. Power
PoE
0−4 1 Hi-Z Min (PD Requested
Power, 13W)
≥ 2 Low-Z 25.5W
5−8
1 Hi-Z 13W
2 or 3 Low-Z 25.5W
4 50% Min (PD Requested
Power, 51W)
5 25% Min (PD Requested
Power, 71.3W)
* Specified as the percentage of the period which T2P is low impedance with respect to VCC.
LT4295
13
Rev. B
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Table5. LT4295 Interoperability {T2P Response*, PSE Allocated Power, Number of Classification Events}
PD
REQUESTED
CLASS (PD
REQUESTED
POWER)
PSE TYPE, CLASS (POWER)
AUXILIARY
POWER
SOURCE**
IEEE
802.3
Type 1
IEEE
802.3
Type 2
IEEE 802.3
Type 3
IEEE 802.3
Type 4
Class 3
(13W)
Class 4
(25.5W)
Class 4
(25.5W)
Class 5
(40W)
Class 6
(51W)
Class 7
(62W)
Class 8
(71.3W)
Class 0-3
(up to 13W)
Hi-Z
up to 13W
1-Event
Hi-Z
up to 13W
1-Event
Hi-Z
up to 13W
1-Event
Hi-Z
up to 13W
1-Event
Hi-Z
up to 13W
1-Event
Hi-Z
up to 13W
1-Event
Hi-Z
up to 13W
1-Event
Low-Z
Aux. Power
N/A
Class 4
(25.5W)
Hi-Z
13W
1-Event
Low-Z
25.5W
2-Event
Low-Z
25.5W
3-Event
Low-Z
25.5W
3-Event
Low-Z
25.5W
3-Event
Low-Z
25.5W
3-Event
Low-Z
25.5W
3-Event
Low-Z
Aux. Power
N/A
Class 5
(40W)
Hi-Z
13W
1-Event
Low-Z
25.5W
2-Event
Low-Z
25.5W
3-Event
50%
40W
4-Event
50%
40W
4-Event
50%
40W
4-Event
50%
40W
4-Event
25%
Aux. Power
N/A
Class 6
(51W)
Hi-Z
13W
1-Event
Low-Z
25.5W
2-Event
Low-Z
25.5W
3-Event
Low-Z
25.5W
3-Event
50%
51W
4-Event
50%
51W
4-Event
50%
51W
4-Event
25%
Aux. Power
N/A
Class 7
(62W)
Hi-Z
13W
1-Event
Low-Z
25.5W
2-Event
Low-Z
25.5W
3-Event
Low-Z
25.5W
3-Event
50%
51W
4-Event
25%
62W
5-Event
25%
62W
5-Event
25%
Aux. Power
N/A
Class 8
(71.3W)
Hi-Z
13W
1-Event
Low-Z
25.5W
2-Event
Low-Z
25.5W
3-Event
Low-Z
25.5W
3-Event
50%
51W
4-Event
50%
51W
4-Event
25%
71.3W
5-Event
25%
Aux. Power
N/A
Note 1. Shade of blue indicates the PD has been demoted
* Specified as the percentage of the period which T2P is low impedance with respect to VCC
** Auxiliary Power Supply must be sized to provide PD Requested Power
Interoperability Across Various PSEs and Auxiliary
Power Source
Table5 summarizes the expected T2P response, the PSE
allocated power, and the number of classification events.
The result is a function of PD Requested Class and power
source—Auxiliary or PoE.
SWITCHING REGULATOR CONTROLLER OPERATION
The switching regulator controller portion of the LT4295
is a current mode controller capable of implementing
either a flyback or a forward power supply. When used in
flyback mode, no opto-isolator is required for feedback
because the output voltage is sensed via the transformer’s
third winding.
T2P Response*
PSE Allocated Power
Number of Classification Events
25%
71.3W
5-Event
LT4295
14
Rev. B
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Figure10. PG and SG Timing Relationship in Flyback Mode
Figure11. Example PG and SG Connections in Flyback Mode
PG
SG
4295 F10
tPGDELAY
tPGon
tPGSG
•
•
••
PG
SGGND
LT4295
4295 F11
FFSDLY
RFFSDLY
ISEN+
ISEN–
+
Flyback Mode
The LT4295 is programmed into flyback mode by placing
a resistor R
FFSDLY
from the FFSDLY pin to GND. This resis-
tor must be in the range of 5.23kΩ to 52.3kΩ. If using a
potentiometer to adjust RFFSDLY, ensure the adjustment
of the potentiometer does not exceed 52.3kΩ.The value
of RFFSDLY determines tPGDELAY according to the following
equations:
t
PGDELAY ≈
2.69ns / k
Ω
•R
FFSDLY +
30ns
tPGSG ≈20ns
The SG pin must be connected to the secondary side
MOSFET through a gate drive transformer as shown
in Figure11. Add a Schottky diode from PG to GND as
shown in Figure11 to prevent PG from going negative.
Forward Mode
The LT4295 is programmed into forward mode by placing
a resistor RFFSDLY from the FFSDLY pin to VCC. The RFFSDLY
resistor must be in the range of 10.5kΩ to 52.3kΩ. If
using a potentiometer to adjust R
FFSDLY
ensure the adjust-
ment of the potentiometer does not exceed 52.3kΩ.
The value of RFFSDLY determines tPGDELAY and tPGSG
according to the following equations:
tPGDELAY ≈ 7.16ns/kΩ • RFFSDLY + 17ns
tPGSG ≈ 5.60ns/kΩ • RFFSDLY + 7.9ns
The PG and SG relationships in forward mode are shown
in Figure12.
In forward mode, the SG pin has the correct polarity
to drive the active clamp P-channel MOSFET through a
simple level shifter as shown in Figure13. Add a Schottky
diode from the PG to GND as shown in Figure13 to pre-
vent PG from going negative.
Figure12. PG and SG Timing Relationship in Forward Mode
Figure13. Example PG and SG Connections in Forward Mode
PG
SG
4295 F12
tPGDELAY tPGSG
••
PG
V
CC
VCC
SG
GND
LT4295
4295 F13
FFSDLY
RFFSDLY
ISEN+
ISEN–
APPLICATIONS INFORMATION
LT4295
15
Rev. B
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Feedback Amplifier
In the flyback mode, the feedback amplifier senses the
output voltage through the transformer’s third winding as
shown in Figure14. The amplifier is enabled only during
the fixed interval, tFB, as shown in Figure15. This elimi-
nates the opto-isolator in isolated designs, thus greatly
improving the dynamic response and stability over life-
time. Since t
FB
is a fixed interval, the time-averaged trans-
conductance, gm, varies as a function of the user-selected
switching frequency.
APPLICATIONS INFORMATION
FEEDBACK AMPLIFIER OUTPUT, ITHB
As shown in the Block Diagram, V
SENSE
is the input of
the Current Sense Comparator. VSENSE is derived from
the output of a linear amplifier whose input is the voltage
on the ITHB pin, VITHB.
This linear amplifier inverts its input, VITHB, with a gain,
ΔV
SENSE
/ΔV
ITHB
, and with an offset voltage of V
ITHB(OS)
to yield its output, VSENSE. This relationship is shown
graphically in Figure1. Note the slope ΔVSENSE/ΔVITHB is
a negative number and is provided in the electrical char-
acteristics table.
V
ITHB =V
ITHB(OS) +VSENSE •ΔVSENSE
ΔV
ITHB
⎛
⎝
⎜⎞
⎠
⎟
–1
The block diagram shows V
SENSE
is compared against
the voltage across the current sense resistor, V(ISEN+)-
V(ISEN
–
) modified by the internal slope compensation
voltage discussed subsequently.
LOAD COMPENSATION
As can be seen in Figure15, the voltage on the FB31 pin
droops slightly during the flyback period. This is mostly
caused by resistances of components of the secondary
side such as: the secondary winding, RDS(ON) of the syn-
chronous MOSFET, ESR of the output capacitor, etc. These
resistances cause a feedback error that is proportional to
the current in the secondary loop at the time of feedback
sample window. To compensate for this error, the LT4295
places a voltage proportional to the peak current in the
primary winding on the RLDCMP pin.
Determining Feedback and Load Compensation
Resistors
Because the resistances of components on the secondary
side are generally not well known, an empirical method
must be used to determine the feedback and load com-
pensation resistor values.
INITIALLY SET R
FB2 =
2k
Ω
RFB1 ≈RFB2
VOUT
V
FB
NTHIRD
NSECONDARY
– RFB2
Figure14. Feedback and Load Compensation Connection
PG
FB31
VOLTAGE
GND
SG
4295 F15
t
FB
t
FBDLY
VFB
Figure15. Feedback Amplifier Timing Diagram
+
–
+
–
+
–
•
•
•
FEEDBACK
FB31 LT4295 THIRD
PRIMARY
4295 F14
SECONDARY
ITHB
PG
ISEN+
ISEN–
RLDCMP
RFB2
VIN
V
OUT
RSENSE
VFB
RFB1
RLDCMP
AV = 10
LT4295
16
Rev. B
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APPLICATIONS INFORMATION
Connect the resistor RLDCMP between the RLDCMP
pin and GND. RLDCMP must be at least 10kΩ. Adjust
RLDCMP for minimum change of VOUT over the full input
and output load range. A potentiometer in series with
10kΩ may be initially used for RLDCMP and adjusted.
The potentiometer+10kΩ may then be removed, mea-
sured, and replaced with the equivalent fixed resistor. The
resulting VOUT differs from the desired VOUT due to offset
injected by load compensation. The change to RFB2 to
correct this is predicted by:
ΔRFB2 =ΔVOUT
V
FB
NTHIRD
N
SECONDARY
RFB2
2
R
FB1
Where: ΔVOUT is the desired change to VOUT
ΔRFB2 is the required change to RFB2
NTHIRD/NSECONDARY is the transformer third
winding to secondary winding
OPTO-ISOLATOR FEEDBACK
For forward mode operation, the flyback voltage cannot be
sensed across the transformer. Thus, opto-isolator feed-
back must be used. When using opto-isolator feedback,
connect the FB31 pin to GND and leave the RLDCMP pin
open. In this condition, the feedback amplifier sinks an
average current of ISINK into the ITHB pin. An example for
feedback connections is shown in Figure16. Note that
since I
SINK
is time-averaged over the switching period,
the sink current varies as a function of the user-selected
switching frequency.
SOFT-START
In PoE applications, a proper soft-start design is required
to prevent the PD from drawing more current than the
PSE can provide.
The soft-start time, tSFST, is approximately the time in
which the power supply output voltage, V
OUT
, is charging
its output capacitance, C
OUT
. This results in an inrush cur-
rent at the port of the PD, Iport_inrush (not to be confused
with I
INRUSH
discussed earlier in Applications Information
section). Care must be taken in selecting tSFST to pre-
vent the PD from drawing more current than the PSE can
provide.
In the absence of an output load current, the Iport_inrush,
is approximated by the following equation:
Iport_inrush ≈COUT • VOUT
2
η• t
SFST
• V
IN
where η is the power supply efficiency,
VIN is the input voltage of the PD
Iport_inrush plus the port current due to the load current
must be below the current the PSE can provide. Note that
the PSE current capability depends on the PSE operating
standard.
The LT4295 contains a soft-start function that controls
tSFST by connecting an external capacitor, CSFST, between
the SFST pin and GND. The SFST pin is pulled up with
ISFST when the LT4295 begins switching. The voltage
ramp on the SFST pin is proportional to the duty cycle
ramp for PG.
For flyback mode, the soft-start time is:
tSFST =600µA
nF
CSFST
I
SFST
⎛
⎝
⎜⎞
⎠
⎟tPGon +tPGDELAY – tMIN
( )
where tPGon is the time when PG is high as shown in
Figure8 once the power supply is in steady-state.
In forward mode, each of the back page applications sche-
matics provides a chart with tSFST vs. CSFST. Select the
application and choose a value of CSFST that corresponds
to the desired soft-start time.
Figure16. Opto-isolator Feedback Connections in the
Forward Mode
LT4295
ITHB
4295 F16
VCC
VOUT
CX
RX
FB31GND
LT4295
17
Rev. B
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APPLICATIONS INFORMATION
SHORT CIRCUIT RESPONSE
If the power supply output voltage is shorted, overloaded,
or if the soft-start capacitor is too small, an overcurrent
fault event occurs when the voltage across the sense pins
exceeds VFAULT (after the blanking period of tMIN). This
begins the internal fault timer tFAULT. For the duration of
tFAULT, the LT4295 turns off PG and SG and pulls the
SFST pin to GND. After tFAULT expires, the LT4295 initi-
ates soft-start.
The fault and soft-start sequence repeats as long as the
short circuit or overload conditions persist. This condition
is recognized by the PG waveform shown in Figure17
re peating at an interval of tFAULT.
CURRENT SENSE COMPARATOR
The LT4295 uses a differential current sense comparator
to reduce the effects of stray resistance and inductance on
the measurement of the primary current. ISEN+ and ISEN–
must be Kelvin connected to the sense resistor pads.
Like most switching regulator controllers, the current
sense comparator begins sensing the current tMIN after
PG turns on. Then, the comparator turns PG off after
the voltage across ISEN+ and ISEN– exceeds the current
sense comparator threshold, VSENSE. Note that the voltage
across ISEN+ and ISEN– is modified by LT4295’s internal
slope compensation.
SLOPE COMPENSATION
The LT4295 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the duty cycle is greater than or near 50%.
The slope compensation of the LT4295 does not reduce
the maximum peak current at higher duty cycles.
CONTROL LOOP COMPENSATION
In flyback mode, loop frequency compensation is per-
formed by connecting a resistor/capacitor network from
the output of the feedback amplifier (ITHB pin) to GND as
shown in Figure14. In forward mode, loop compensation
is performed by varying RX and CX in Figure16.
ADJUSTABLE SWITCHING FREQUENCY
The LT4295 has a default switching frequency, fOSC, of
214 kHz when the ROSC pin is left open. If a higher switch-
ing frequency, fSW, is desired (up to 300kHz), a resistor
no smaller than 45.3kΩ may be added between the ROSC
pin to GND. The resistor can be calculated below:
ROSC =
3900k
Ω
• kHz
f
SW – f
OSC
( )
kΩ
( )
tFAULT
4295 F17
Figure17. PG Waveforms with Output Shorted
OVERTEMPERATURE PROTECTION
The IEEE 802.3 specification requires a PD to withstand
any applied voltage from 0V to 57V indefinitely. During
classification, however, the power dissipation in the
LT4295 may be as high as 1.5W. The LT4295 can easily
tolerate this power for the maximum IEEE classification
timing but overheats if this condition persists abnormally.
The LT4295 includes an overtemperature protection
feature which is intended to protect the device during
momentary overload conditions. If the junction tempera-
ture exceeds the overtemperature threshold, the LT4295
pulls down HSGATE pin, disables classification, and dis-
ables the switching regulator operation.
LT4295
18
Rev. B
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APPLICATIONS INFORMATION
A silicon diode bridge consumes up to 4% of the avail-
able power. In addition, silicon diode bridges exhibit poor
pairset-to-pairset unbalance performance. Each branch of
a silicon diode bridge shares source/return current, and
thermal runaway can cause large, non-compliant current
unbalances between pairsets.
While using Schottky diodes can help reduce the power
loss with a lower forward voltage, the Schottky bridge
may not be suitable for high temperature PD applications.
Schottky diode bridges exhibit temperature induced leak-
age currents. The leakage current has a voltage depen-
dency that can invalidate the measured detection signa-
ture. In addition, these leakage currents can back-feed
through the unpowered branch and the unused bridge,
violating IEEE 802.3 specifications.
For high efficiency applications, the LT4295 supports an
LT4321-based PoE ideal diode bridge that reduces the
forward voltage drop from 0.7V to 20mV per diode while
maintaining IEEE 802.3 compliance. The LT4321 simpli-
fies thermal design, eliminates costly heatsinks, and can
operate in space-constrained applications.
MAXIMUM DUTY CYCLE
The maximum duty cycle of the PG pin is modified by the
chosen tPGDELAY and fSW. It is calculated below:
MAX POWER SUPPLY DUTY CYCLE
= DMAX – tPGDELAY • fSW
For an appropriate margin during transient operation, the
forward or flyback power supply should be designed so
that its maximum steady-state duty cycle should be about
10% lower than the LT4295 Maximum Power Supply Duty
Cycle calculated above.
EXTERNAL INTERFACE AND COMPONENT SELECTION
PoE Input Bridge
A PD is required to polarity-correct its input voltage. There
are several different options available for bridge rectifiers;
silicon diodes, Schottky diodes, and ideal diodes. When
silicon or Schottky diode bridges are used, the diode for-
ward voltage drops affect the voltage at the VPORT pin.
The LT4295 is designed to tolerate these voltage drops.
Note, the voltage parameters shown in the Electrical
Characteristics section are specified at the LT4295 pack-
age pins.
LT4295
19
Rev. B
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APPLICATIONS INFORMATION
Auxiliary Input Diode Bridge
Some PDs are required to receive AC or DC power from
an auxiliary power source. A diode bridge is typically
required to handle the voltage rectification and polarity
correction.
In high efficiency applications, or in low auxiliary input
voltage applications, the voltage drop across the rectifier
cannot be tolerated. The LT4295 can be configured with
an LT4320-based ideal diode bridge to recover the diode
voltage drop and ease thermal design.
For applications with auxiliary input voltages below 10V,
the LT4295 must be configured with an LT4320-based
ideal diode bridge to recover the voltage drop and guaran-
tee the minimum VPORT voltage is within the VPORT AUX
range as specified in the Electrical Characteristics table.
Input Capacitor
A 0.1μF capacitor is needed from VPORT to GND to meet
the input impedance requirement in IEEE 802.3 and to
properly bypass the LT4295. When operating with the
LT4321, locally bypass each with a 0.047μF capacitor, thus
keeping the total port capacitance within specification.
Transient Voltage Suppressor
The LT4295 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events
due to Ethernet cable surges. To protect the LT4295 from
an overvoltage event, install a unidirectional transient volt-
age suppressor (TVS) such as an SMAJ58A between the
VPORT and GND pins. For PD applications that require an
auxiliary power input, install a TVS between VIN and GND.
For extremely high cable discharge and surge protection,
contact Analog Devices Applications.
LT4295
20
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
13W PoE Power Supply in Flyback Mode with 5V, 2.3A Output
Efficiency vs Load Current VOUT vs Load Current
++VOUT
5V AT 2.3A
–VOUT
Q1
L1: COILCRAFT, DO1813P-181HC
L2: COILCRAFT, DO1608C-103
L4: COILCRAFT, DO1608C-104
C2: 22µF, 6.3V, MURATA GRM31CR70J226KE19
C5: 47µF, 6.3V, PANASONIC 6SVP47M
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750313109
Q1: PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
VPORT
GND
L2
10µH L1
180nH
L4
100µH
10µF
100V
10nF
100V
3.3k
10µF
10V
HSSRC SWVCC FB31
PG
SG
ITHBROSCSFSTFFSDLYRCLASSGND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7
2.2µF
FDN86246
BAT54WS
BAT46WS
T2
4295 TA02a
PSMN4R2-30MLD
MMBT3906 MMBT3904
T1
1nF
1µF
6.04k
20Ω
2k
270Ω
1/4W
11Ω
1/4W
60mΩ
1/4W
15Ω
100Ω
1µF
330pF
0.1µF
107k5.23k52.3Ω
8.2Ω
PTVS58VP1UTP
4.7nF
2.2nF
2KV
20k
10k
2.2nF
C2
22µF C5
47µF
6.3V
47pF
630V
0.1µF
100V
2.2nF
2kV
BAV19WS
••
•
•
•
FMMT723
LOAD CURRENT (A)
76
EFFICIENCY (%)
90
88
86
84
82
80
78
92
0.5
2.5
1 1.5 20
4295 TA02b
VPORT = 37V
VPORT = 48V
VPORT = 57V
LOAD CURRENT (A)
4.80
V
OUT
(V)
5.15
5.10
5.05
5.00
4.95
4.90
4.85
5.20
0.5
2.5
1 1.5 20
4295 TA02c
VPORT = 37V
VPORT = 48V
VPORT = 57V
LT4295
21
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
40W PoE Power Supply in Flyback Mode with 12V, 3A Output
Efficiency vs Load Current VOUT vs Load Current
+
+VOUT
12V AT 3A
–VOUT
Q1
L2
10µH L1
180nH
L4
100µH
10µF
100V
10nF
100V
3.3k
24V
8.2Ω
10µF
10V
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASSRCLASS++GND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7
2.2µF
BSZ90020NS3
BAT54WS
BAT46WS
MOC207M
VOUT
TO MICROPROCESSOR
4295 TA03a
TPN1600ANH
MMBT3906 MMBT3904
T1
470pF
1µF
6.65k
2.00kΩ
100Ω
1/2W
11Ω
1/2W
25mΩ
1/4W
15Ω
100Ω
1µF
220pF
0.1µF 107k
7.5k37.4Ω
1.00kΩ
PTVS58VP1UTP 3.3nF
2.2nF
2KV
26.1k
10k
2.2nF
C2, C3
10µF C5
33µF
100pF
630V
47nF
100V
2.2nF
2kV
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
47nF
100V
L1: COILCRAFT, DO1813P-181HC
L2: COILCRAFT, DO1608C-103
L4: COILCRAFT, DO1608C-104
C2, C3: 10µF, 16V, MURATA GRM31CR61C106KA88
C5: 33µF, 25V, PANASONIC EEHZA1E330R
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750316115 OR PCA EPC3634G
Q1-Q9: PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
J1: WURTH 7499511001A
BAV19WS
J1
5.1kΩ
10k
20Ω
••
•
•
•
FMMT723
+
+VOUT
12V AT 3A
–VOUT
Q1
L2
10µH L1
180nH
L4
100µH
10µF
100V
10nF
100V
3.3k
24V
8.2Ω
10µF
10V
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASSRCLASS++GND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7
2.2µF
BSZ90020NS3
BAT54WS
BAT46WS
MOC207M
VOUT
TO MICROPROCESSOR
4295 TA03a
TPN1600ANH
MMBT3906 MMBT3904
T1
470pF
1µF
6.65k
2.00kΩ
100Ω
1/2W
11Ω
1/2W
25mΩ
1/4W
15Ω
100Ω
1µF
220pF
0.1µF 107k
7.5k37.4Ω
1.00kΩ
PTVS58VP1UTP 3.3nF
2.2nF
2KV
26.1k
10k
2.2nF
C2, C3
10µF C5
33µF
100pF
630V
47nF
100V
2.2nF
2kV
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
47nF
100V
L1: COILCRAFT, DO1813P-181HC
L2: COILCRAFT, DO1608C-103
L4: COILCRAFT, DO1608C-104
C2, C3: 10µF, 16V, MURATA GRM31CR61C106KA88
C5: 33µF, 25V, PANASONIC EEHZA1E330R
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750316115 OR PCA EPC3634G
Q1-Q9: PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
J1: WURTH 7499511001A
BAV19WS
J1
5.1kΩ
10k
20Ω
••
•
•
•
FMMT723
VPORT = 44V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
80
82
84
86
88
90
92
94
EFFICIENCY (%)
4295 TA03b
VPORT = 44V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
11.98
12.00
12.02
12.04
12.06
12.08
12.10
12.12
12.14
V
(OUT)
(V)
4295 TA03c
LT4295
22
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
Efficiency vs Load Current VOUT vs Load Current
71.3W PoE Power Supply in Forward Mode with 5V, 13A Output
CSFST (µF) tSFST (ms)
0.10 1.2
0.33 3.8
1.0 12
3.3 38
Q1
10nF
100V
3.3k
L4
100µH
10µF
10V
BAV19WS
FMMT723
8.2Ω
PTVS58VP1UTP
0.1µF
100V
L1
2.2µH
C5
100µF
(×2)
C8
100µF
6HVA100M
+
+
L2
4.9µH
22µF
100V
HSSRC SWVCC FFSDLY
PG
SG
ITHBROSCSFSTRCLASS++
RCLASSGND FB31
T2P
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
VCC
+VOUT
+VOUT
+5V AT
13A
–VOUT
VCC
C7
2.2µF
(×2)
BAT54WS
BSC190N12NS3
4295 TA04a
20m
1/2W
100Ω
1206
10nF
250V
5Ω
100nF
250V
750Ω
330Ω 240Ω
4.7n
ZR431
10k 10.0k
10.0k
1k
10Ω
10Ω
CMMSH1-40L BSC054N04NSBSC054N04NS
CMMSH1-40L
T1
CMMSH1-40L
8.2V
CMHZ4694
18V
CMHZ5248B
18V
CMHZ5248B
2.2nF
2kV
33nF
0.1µF
0.1µF
10k
0.1µF FDMC2523P
CMMSH1-40L
M0C207M
MMBT3904
VPORT
GND
13k
20Ω
52.3Ω 118Ω
0.47µF 100pF
100k
107k
••
L1: COILCRAFT, XAL-1010-222ME
L2: WÜRTH, 744314490
L4: COILCRAFT, DO1608C-104
C5, 100µF, 6.3V, SUNCON 6HVA100M
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35L
C8: 100µF, 6.3V, SUNCON 6HVA100M
T1: WÜRTH, 750313095
Q1: PSMN040-100MSE
TO MICROPROCESSOROPTO
10nF
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
2
4
6
8
10
12
14
76
78
80
82
84
86
88
90
92
94
EFFICIENCY (%)
4295 TA04b
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
2
4
6
8
10
12
14
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
V
(OUT)
(V)
4295 TA04c
LT4295
23
Rev. B
For more information www.analog.com
Efficiency vs Load Current VOUT vs Load Current
TYPICAL APPLICATIONS
71.3W PoE Power Supply in Forward Mode with 12V, 5.5A Output
CSFST (µF) tSFST (ms)
0.10 1.5
0.33 4.9
1.0 15
3.3 48
+
L2
6.5µH
22µF
100V
HSSRC
SWVCC FFSDLY
PG
SG
ITHBROSCSFSTRCLASS++
RCLASSGND FB31
T2P
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
VCC
+VOUT
+VOUT
+12V AT
5.5A
–VOUT
VCC
C7
2.2µF
(×2)
BAT54WS
BSC190N12NS3
4295 TA05a
15mΩ
1/2W
100Ω
1206
33nF
250V
0.22µF
250V
750Ω
820Ω 20k
ZR431
10k
10.0k
100pF
38.3k
13k
10Ω
CMMSH1-60
BSC123N08S3
BSC123N08S3
T1
CMMSH1-100
CMMSH1-100
13V
CMHZ4700
7.5V
CMHZ5236B
2.2nF
2kV
6.8nF
0.1µF
0.1µF
10k
0.1µF FDMC2523P
CMMSH1-40L
M0C207M
MMBT3904
29.4k
VCC
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
52.3Ω
118Ω
1µF 100pF
100pF
100k
107k 330pF
20Ω ••
7.5Ω
Q1
10nF
100V
47nF
100V
3.3k
L4
100µH
10µF
10V
8.2Ω
PTVS58VP1UTP
47nF
100V
L1
8.2µH
22µF
16V
(×2) C8
100µF
L1: COILCRAFT, XAL-1010-822ME
L2: WÜRTH, 744314650
L4: COILCRAFT, DO1608C-104
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35L
C8: 100µF, 16V, SUNCON 16HVA100M
T1: PCA EPC3577G-LF
T2: WÜRTH, 749022016
Q1: PSMN040-100MSE
Q2-Q9: PSMN075-100MSE
TO MICROPROCESSOROPTO
FMMT723
820pF
100pF
+VOUT
+VOUT
7.5V
CMHZ5236B
5.1k
FMMT624
FMMT624
5.1k
100pF
BAV19WS
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
1
2
3
4
5
6
78
80
82
84
86
88
90
92
94
EFFICIENCY (%)
4295 TA05b
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
1
2
3
4
5
6
11.60
11.70
11.80
11.90
12.00
12.10
12.20
12.30
12.40
V
(OUT)
(V)
4295 TA05c
LT4295
24
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
40W PoE Power Supply in Flyback Mode with 5V, 7.3A Output
Efficiency vs Load Current VOUT vs Load Current
+
+VOUT
5V AT 7.3A
–VOUT
Q1
L1: COILCRAFT, DO1813P-181HC
L2: COILCRAFT, DO1608C-103
L4: COILCRAFT, DO1608C-104
C2, C3: 47µF, 6.3V, GRM31CR60J476ME19L
C5: 47µF, 6.3V, PANASONIC 6SVP47M
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35L
T1: WÜRTH, 750314783 OR PCA EPC3586G
Q1-Q9: PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
J1: WURTH 7499511001A
L2
10µH L1
180nH
L4
100µH
10µF
100V
10nF
100V
47nF
100V
3.3k
24V
8.2Ω
10µF
10V
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASS++
RCLASS
GND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7
2.2µF
BSZ900N20
NS3G
BAT54WS
BAT46WS
TO MICROPROCESSOR
4295 TA06a
PSMN2R4-30MLD
MMBT3906 MMBT3904
T1
1nF
1µF
5.90k
2.00kΩ
80Ω
1/4W
5.1Ω
1/4W
40mΩ
1/4W
15Ω
100Ω
20Ω
1µF
220pF
0.1µF
107k7.50k
RLDCMP
51k
37.4Ω
1.00kΩ
PTVS58VP1UTP 3.3nF
2.2nF
2KV
20k
10k
2.2nF
C2, C3
47µF||47µF C5
47µF
100pF
100V
47nF
100V
2.2nF
2kV
OPTO
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
BAV19WS
J1
••
•
•
•
FMMT723
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
1
2
3
4
5
6
7
78
80
82
84
86
88
90
92
94
EFFICIENCY (%)
4295 TA06b
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
1
2
3
4
5
6
7
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
V
(OUT)
(V)
4295 TA06c
LT4295
25
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
25.5W PoE and 9V to 57V Auxiliary Input Power Supply in Flyback Mode with 12V, 1.9A Output
Efficiency vs Load Current VOUT vs Load Current
+
+VOUT
12V AT 1.9A
–VOUT
Q1
L1: COILCRAFT, DO1813P-561ML
L2: WÜRTH, 7443330820
L3: MURATA, LQM21PN2R2NGCD
L4: COILCRAFT, DO1813H-223
C2, C3: 10µF, 16V, MURATA GRM31CR61C106KA88
C5: 33µF, 20V, KEMET, T494V336M020AS
C7, C8: 3.3µF, 100V, TDK C3225X7S2A335M
T1: PCA EPC3601G OR WÜRTH 750315422
Q1-Q9:PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
J1: WURTH 7499511611A
L2
8.2µH
L3
2.2µH
1µF
680µF
L1
560nH
L4
22µH
10µF
100V
100nF
100V
0.1µF
3.3k 158k
931k
24V
47nF
100V
8.2Ω
22µF
10V
PMEG10010ELR
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASSGND
VPORT
AUX
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7, C8
3.3µF
FDMC86160
BAT54WS
BAT46WS
TO MICROPROCESSOR
4295 TA07a
BSZ900NF20NS3
CMLT7820G CMLT3820G
T1
220pF
1µF
4.75k
2.00k
62Ω
1/4W
82Ω||82Ω
1/4W
15mΩ
1/2W
15Ω
100Ω
1µF
220pF
0.1µF
107k9.31k
RLDCMP
51k35.7Ω
PTVS58VP1UTP
4.7nF
2.2nF
2KV
43k
10k
2.2nF
C2, C3
10µF||10µF C5
33µF
100pF
100V
47nF
100V
2.2nF
2kV
OPTO
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
TG2
TG1 OUTP
OUTN
IN1
IN2
BG2
BG1
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
LT4320
BSZ110N06NS3 x4
MMSD4148 x3
VAUX
9V TO 57VDC
OR 24VAC
1Ω
••
•
•
•
+
FMMT723
J1
V
AUX
= 9V
V
AUX
= 24V
V
AUX
= 42.5V
V
AUX
= 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
72
76
80
84
88
92
EFFICIENCY (%)
4295 TA07b
V
AUX
= 9V
V
AUX
= 24V
V
AUX
= 42.5V
V
AUX
= 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
11.50
11.75
12.00
12.25
12.50
V
(OUT)
(V)
4295 TA07c
LT4295
26
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
25.5W PoE Power Supply in Flyback Mode with 3.3V, 6.8A Output
Efficiency vs Load Current VOUT vs Load Current
++VOUT
3.3V AT 6.8A
–VOUT
Q1
L1: COILCRAFT, DO1813P-181HC
L2: COILCRAFT, DO1608C-103
L4: COILCRAFT, DO1608C-104
C2, C3: 22µF, 6.3V, MURATA GRM31CR70J226KE19
C5: 68µF, 4V, 4SVPA68MAA
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750310743 OR PCA EPC3408G
Q1-Q9: PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
J1: WURTH 7499511001A
L2
10µH L1
180nH
L4
100µH
10µF
100V
10nF
100V
47nF
100V
3.3k
24V
8.2Ω
10µF
10V
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASSGND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7
2.2µF
BSZ900N20NS3
BAT54WS
BAT46WS
TO MICROPROCESSOR
4295 TA08a
PSMN2R4-30MLD
MMBT3906 MMBT3904
T1
1nF
47Ω
1µF
6.49k
2k
100Ω
1/4W
5.1Ω
1/4W
40mΩ
1/4W
15Ω
100Ω
1µF
470pF
0.1µF
107k6.81k35.7Ω
PTVS58VP1UTP 4.7nF
2.2nF
2KV
8.25k
10k
2.2nF
C2, C3
22µF||22µF C5
68µF
100pF
100V
47nF
100V
2.2nF
2kV
OPTO
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
B0540WS
BAV19WS
J1
20Ω
••
•
•
•
FMMT723
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
2
4
6
8
78
80
82
84
86
88
90
92
EFFICIENCY (%)
4295 TA08b
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
2
4
6
8
3.20
3.30
3.40
3.50
V
(OUT)
(V)
4295 TA08c
LT4295
27
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
25.5W PoE Power Supply in Flyback Mode with 24V, 0.95A Output
Efficiency vs Load Current VOUT vs Load Current
+
+VOUT
24V AT 0.95A
–VOUT
Q1
L2: COILCRAFT, DO1608C-103
L4: COILCRAFT, DO1608C-104
C2: 4.7µF, 50V, MURATA GRM31CR71H475KA12
C5: 22µF, 35V, PANASONIC EEH-ZA1V220R
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750314782 OR PCA EPC3603G
Q1-Q9: PSMN075-100MSE
T2: PCA EPA4271GE OR PULSE PE-68386NL
J1: WURTH 7499511001
L2
10µH
L4
100µH
10µF
100V
10nF
100V
3.3k
24V
8.2Ω
10µF
10V
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASSGND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7
2.2µF
BSZ520N15NS3G
BAT54WS
BAT46WS
TO MICROPROCESSOR
4295 TA09a
BSZ12DN20NS3
MMBT3906 MMBT3904
T1
150pF
0.1µF
6.49k
2.00kΩ
20Ω
100Ω
1/4W
120Ω||120Ω
1/4W
40mΩ
1/4W
15Ω
100Ω
1µF
10pF
0.47µF
107k5.23k
RLDCMP
24k35.7Ω
PTVS58VP1UTP 3.3nF
2.2nF
2KV
160k
10k
2.2nF
C2, C3
4.7µF
50V
C5
22µF
47pF
100V
47nF
100V
2.2nF
2kV
OPTO
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
47nF
100V
BAV19WS
••
•
•
•
FMMT723
J1
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
80
82
84
86
88
90
92
EFFICIENCY (%)
4295 TA09b
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.2
0.4
0.6
0.8
1
23.4
23.6
23.8
24.0
24.2
24.4
24.6
V
(OUT)
(V)
4295 TA09c
LT4295
28
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
62W PoE Power Supply in Flyback Mode with 24V, 2.4A Output
Efficiency vs Load Current VOUT vs Load Current
+
+VOUT
24V AT 2.4A
–VOUT
Q1
L1: COILCRAFT, DO1813H-122ML
L2: WURTH, 744314490
L4: COILCRAFT, DO1608C-104
C2: MURATA GRM32ER61H106K
C5: 47µF, 35V, EEE-FT1V470AR
C7, C8: 2.2µF, 100V, MURATA GRM32ER72A225KA35
Q1: NXP PSMN040-100MSE
Q2-Q9: PSMN075-100MSE
T1: PCA EPC3630G OR WURTH 750316231
T2: PCA EPA4271GE OR PULSE PE-68386NL
J1: WURTH 749022016
L2
4.9µH
L4
100µH
L1
1.2µH
22µF
100V
10nF
100V
3.3k
24V
8.2Ω
10µF
10V
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASS++ RCLASSGND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
C7, C8
2.2µF
BSC190N15NS3
BAT54WS
BAT46WS
TO MICROPROCESSOR
4295 TA10a
BSC320N20NS3
PBSS5140T PBSS4140T
T1
330pF
0.1µF
3.74k
2.00kΩ
20Ω
27Ω
1/2W
18Ω
1W
15mΩ
1/2W
15Ω
100Ω
1µF
330pF
0.47µF
107k5.23k
RLDCMP
36k80.6Ω
64.9Ω
PTVS58VP1UTP 10nF
2.2nF
2KV
22k
10k
2.2nF
C2
10µF
50V
C5
47µF
220pF
100V
47nF
100V
4.7nF
2kV
OPTO
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
47nF
100V
BAV19WS
J1
••
•
•
•
FMMT723
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
80
82
84
86
88
90
92
94
EFFICIENCY (%)
4295 TA10b
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
24.0
24.1
24.2
24.3
24.4
24.5
V
(OUT)
(V)
4295 TA10c
LT4295
29
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
71.3W PoE Power Supply in Forward Mode with 24V, 2.7A Output
+
L2
6.5µH
22µF
100V
HSSRC
SWVCC FFSDLY
PG
SG
ITHBROSCSFSTRCLASS++
RCLASSGND FB31
T2P
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC
VCC
+VOUT
+VOUT
+V
OUT
24V AT
2.7A
–V
OUT
VCC
C7
2.2µF
(×2)
BAT54WS
BSC190N12NS3
4295 TA11a
15mΩ
1/2W
82Ω
1206
10nF
250V
47nF
250V
750Ω
820Ω 1.2k
ZR431
10k
10.0k
1nF
86.6k
10k
TPH5900CNH
TPH5900CNH
T1
SMD1200PL-TP
SMD1200PL-TP
13V
CMHZ4700
7.5V
CMHZ5236B
2.2nF
2kV
6.8nF
0.1µF
10k
0.1µF FDMC2523P
CMMSH1-40L
M0C207M
MMBT3904
33k
VCC
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
52.3Ω
118Ω
1µF
100pF
100k
107k 3.3nF
20Ω ••
47Ω
Q1
10nF
100V
47nF
100V
3.3k
L4
100µH
10µF
10V
8.2Ω
PTVS58VP1UTP
47nF
100V
L1
22µH
C2
10µF
35V C1
47µF
35V
L1: PULSE PA2050.223
L2: WÜRTH, 744314650
L4: COILCRAFT, DO1608C-104
C1: PANASONIC EEHZA1V470P
C2: MURATA GRM32ER6YA106KA12
C7: 2.2µF, 100V, MURATA GRM32ER72A225KA35L
Q1: PSMN040-100MSE
Q2-Q9: PSMN075-100MSE
T1: PCA EPC3636G
T2: WÜRTH, 749022016
TO MICROPROCESSOROPTO
FMMT723
220pF
47pF
+VOUT
+VOUT
7.5V
CMHZ5236B
13k
FMMT624
FMMT624
13k
47pF
BAV19WS
CSFST (µF) tSFST (ms)
0.10 1.4
0.22 2.4
0.47 4.4
1.0 15
3.3 46
VOUT vs Load CurrentEfficiency vs Load Current
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
80
82
84
86
88
90
92
94
EFFICIENCY (%)
4295 TA11b
VPORT = 41V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
0.5
1
1.5
2
2.5
3
23.0
23.4
23.8
24.2
24.6
25.0
V
(OUT)
(V)
4295 TA11c
LT4295
30
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05 R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0816 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)
LT4295
31
Rev. B
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/18 Updated max input power to 71.3W per Draft 3.4
Revised T2P Output, PoE Input Bridge, Input Capacitor, and Transient Voltage Supressor Applications Information
Changed RCLASS and/or RCLASS++ resistor values
Added J1 transformer recommendations
1-30
12, 17
20, 26
19, 22-26, 30
B 5/19 Removed Draft number
Added Table 5–Interoperability
1-30
13
LT4295
32
Rev. B
For more information www.analog.com
ANALOG DEVICES, INC. 2016–2019
05/19
www.analog.com
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TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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LTC4269-1 IEEE 802.3at PD Interface with Integrated
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Housekeeping Buck, Slope Compensation
LTC4278 IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
50kHz to 250kHz, 12V Aux Support
51W PoE Power Supply in Flyback Mode with 12V, 3.9A Output
Efficiency vs Load Current VOUT vs Load Current
+VOUT
12V AT 3.9A
–VOUT
Q1
C5: 47µF, 35V, PANASONIC EEHZA1V470P
C7, C8: 2.2µF, 100V, MURATA GRM32ER72A225KA35
T1: WÜRTH, 750316116 OR PCA EPC3633G
T2: PCA EPA4271GE OR PULSE PE-68386NL
Q1: PSMN040-100MSE
Q2-Q9: PSMN075-100MSE L1
L4
100µH
10nF
100V
3.3k
24V
8.2Ω
10µF
10V
HSSRC
SWVCC FB31
PG
SG
T2P
ITHBROSCSFSTFFSDLYRCLASSRCLASS++GND
VPORT
LT4295
HSGATE
ISEN+
ISEN–
VIN VCC TPH1500CNH
BAT54WS
BAT46WS
MOC207M
VOUT
TO MICROPROCESSOR
4295 TA12a
TPH1500CNH
PBSS514OT PBSS414OT
T1
330pF
1µF
5.62k
2.00kΩ
36Ω
1/2W
20Ω
1/2W
20mΩ
1/2W
15Ω
100Ω
1µF
330pF
0.1µF
107k
5.23k47.5Ω
150Ω
PTVS58VP1UTP 3.3nF
2.2nF
2KV
30k
10k
2.2nF
C2, C3
10µF C5
47µF
220pF
630V
47nF
100V
2.2nF
2kV
BG36
LT4321
BG12TG12 TG36
TG78TG45BG45 BG78
OUTP
OUTN
EN
EN
IN12
T2
Q2 Q3
Q4 Q5
Q6 Q7
Q8 Q9
1
DATA
PAIRS
SPARE
PAIRS
2
3
6
4
5
7
8
IN36
IN45
IN78
47nF
100V
L1: WURTH 744316022
L2: WURTH 744316470
L4: COILCRAFT, DO1608C-104
C2, C3: 10µF, 16V, MURATA GRM32DR61C106KA01
J1: WURTH 7499511001A
BAV19WS
J1
5.1kΩ
10k
20Ω
••
•
•
•
L2
4.7µH
+10µF
100V C7, C8
2.2µF
FMMT723
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
1
2
3
4
11.94
11.95
11.96
11.97
11.98
11.99
12.00
12.01
12.02
V
(OUT)
(V)
4295 TA12c
VPORT = 42.5V
VPORT = 50V
VPORT = 57V
LOAD CURRENT (A)
0
1
2
3
4
70
74
78
82
86
90
94
EFFICIENCY (%)
4295 TA12b
