Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 LM48560 BoomerTM Audio Power Amplifier Series High Voltage Class H Ceramic Speaker Driver With Automatic Level Control 1 Features 3 Description * * * * * The LM48560 device is a high voltage, high efficiency, Class H driver for ceramic speakers and piezo actuators. The LM48560 device's Class H architecture offers significant power savings compared to traditional Class AB amplifiers. The device provides 30 VP-P output drive while consuming just 4 mA of quiescent current from a 3.6 V supply. 1 * * * * * * Class H Topology Integrated Boost Converter Bridge-Tied Load (BTL) Output Selectable Differential Inputs Selectable Control Interfaces - (Hardware or Software mode) I2C Programmable ALC Low Supply Current Minimum External Components Micro-Power Shutdown Available in Space-Saving DSBGA Package Key Specifications: - Output Voltage at VDD = 3.6 V, RL = 1.5 F + 10 , THD+N 1% - 30 VP-P (Typical) - Quiescent Power Supply Current at 3.6 V (ALC Enabled) - 4 mA (Typical) - Power Dissipation at 25 VP-P, 1 W (Typical) - Shutdown Current, 0.1 A (Typical) The LM48560 device features TI's unique automatic level control (ALC) that provides output limiter functionality. The LM48560 device features two fully differential inputs with separate gain settings, and a selectable control interface. In software control mode, the gain control and device modes are configured through the I2C interface. In hardware control mode, the gain and input mux are configured through a pair of logic inputs. The LM48560 device has a low power shutdown mode that reduces quiescent current consumption to 0.1 A. The LM48560 device is available in an ultrasmall 16-bump DSBGA package (1.97 mm x 1.97 mm). Device Information(1) PART NUMBER PACKAGE LM48560 2 Applications * * * * Touch Screen Smart Phones Tablet PCs Portable Electronic Devices MP3 Players DSBGA (16) BODY SIZE (NOM) 1.97 mm x 1.97 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit +2.7V to +5.5V D1 L1 4.7 PH CS VDD SW VBST SCL/GAIN SDA/SEL SW/HW CBST BOOST CONVERTER I2C INTERFACE PGND SHDN CIN 0.47 PF 1 PF IN1+ CIN OUT- 0.47 PF CIN 0.47 PF IN1IN2+ MUX/ GAIN STAGE ALC RL 10: OUT+ CIN 0.47 PF SET CL IN2SGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Electrical Characteristics VDD = 3.6 V ....................... I2C Interface Characteristics ..................................... Typical Characteristics .............................................. 8.4 Device Functional Modes........................................ 13 8.5 Programming .......................................................... 14 8.6 Register Maps ......................................................... 15 9 Application and Implementation ........................ 17 9.1 Application Information............................................ 17 9.2 Typical Application ................................................. 17 10 Power Supply Recommendations ..................... 20 11 Layout................................................................... 20 11.1 Layout Guidelines ................................................. 20 11.2 Layout Example .................................................... 20 12 Device and Documentation Support ................. 21 12.1 12.2 12.3 12.4 Parameter Measurement Information ................ 10 Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 11 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 13 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 Rev Date 1.0 08/16/11 Initial WEB released. Description 1.01 09/21/11 Input edits under CLASS H OPERATION. 1.02 11/01/11 Edited curves 30150753, 54, 55, 56, and Figure 26 (I2C Read Cycle). 1.03 11/10/11 Edited Figure 26. 1.04 07/25/12 Input texts/limits edits in the EC table. 1.05 08/22/12 Edited Table 1 and Table 2. E 05/02/2013 Changed layout of National Data Sheet to TI format. F 10/21/2015 Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 5 Pin Configuration and Functions YZR Package 16-Pin DSBGA Top View 4 IN1+ IN2+ SDA/SEL PGND 3 IN1- IN2- SCL/ GAIN SW 2 SGND SHDN SW/HW VDD 1 OUT+ OUT- VBST SET C D A B Pin Functions PIN NO. NAME I/O DESCRIPTION A1 OUT+ O Amplifier Non-Inverting Output A2 SGND -- Amplifier Ground A3 IN1- I Amplifier Inverting Input 1 A4 IN1+ I Amplifier Non-Inverting Input 1 B1 OUT- O Amplifier Inverting Output B2 SHDN I Active Low Shutdown. Connect SHDN to GND to disable device. Connect SHDN to VDD for normal operation B3 IN2- I Amplifier Inverting Input 2 B4 IN2+ I Amplifier Non-Inverting Input 2 C1 VBST -- C2 SW/HW I Mode Selection Control: SW/HW = 0 Hardware Mode SW/HW = 1 Software Mode C3 SCL/GAIN I I2C Serial Clock Input (Software Mode) Gain Select Input (Hardware Mode) see (Table 5) C4 SDA/SEL I/O I2C Serial Data Input (Software Mode) Amplifier Input Select (Hardware Mode) see (Table 5) D1 SET -- ALC Timing Input D2 VDD -- Power Supply D3 SW -- Boost Converter Switching Node D4 PGND -- Boost Converter Ground Boost Converter Output Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 3 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MAX UNIT VDD Supply voltage (2) MIN 6 V SW Voltage 25 V VBST Voltage 21 V VDD 0.3 V Input voltage Power dissipation -0.3 (3) TJ Junction temperature Tstg Storage temperature (1) (2) (3) Internally limited -65 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are measured with respect to the ground pin, unless otherwise specified. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX -TA) / JA or the given in Absolute Maximum Ratings, whichever is lower. 6.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 500 Machine Model (1) (2) (3) (3) UNIT V 100 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Machine model, applicable std. JESD22-A115-A. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Operating free-air temperature -40 85 C VDD Supply voltage 2.7 5.5 V 4 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 6.4 Electrical Characteristics VDD = 3.6 V The following specifications apply for RL = 1.5 F + 10 , CBST = 1 F, CIN = 0.47 F, CSET = 100 nF, AV = 24 dB unless otherwise specified. Limits apply for TA = 25 C. (1) (2) PARAMETER VDD Supply voltage IDD Quiescent power supply current TEST CONDITIONS MIN (3) TYP (4) 2.7 MAX (3) UNIT 5.5 V VIN = 0 V, RL = PD Power consumption ISD Shutdown current TWU Wake-up time VOS Differential output offset voltage ALC Enabled 4 ALC Disabled 3.6 mA 1 W VOUT = 25 VP-P, f = 1 kHz 2.5 4.4 Hardware Mode 0.1 2 From Shutdown 15 AV = 24 V 10 90 mV 5 20 mV 0 0.5 AV = 0 dB (Boost Disabled) GAIN = 0 IN1 IN2 Boost Disabled Gain (software mode) Boost Enabled 0.5 Input resistance A A ms GAIN = 1 5.5 6 6.5 GAIN = 0 23.5 24 24.5 GAIN = 1 29.5 30 30.5 GAIN1 = 0, GAIN0 = 0 -0.5 0 0.5 GAIN1 = 0, GAIN0 = 1 5.5 6 6.5 GAIN1 = 1, GAIN0 = 0 11.5 12 12.5 GAIN1 = 1, GAIN0 = 1 17.5 18 18.5 GAIN1 = 0, GAIN0 = 0 20.5 21 21.5 GAIN1 = 0, GAIN0 = 1 23.5 24 24.5 GAIN1 = 1, GAIN0 = 0 26.5 27 27.5 GAIN1 = 1, GAIN0 = 1 29.5 30 30.5 Gain step size (software mode) RIN mA Software Mode Gain (Hardware Mode) AV 6 dB dB dB 3 AV dB 0 dB 46 50 58 30 dB 46 50 58 200 Hz 25 30 1 kHz 25 30 k THD+N = 1% VOUT Output voltage f THD+N Total harmonic distortion + noise VOUT = 18 VP-P, f = 1 kHz VP-P 0.08% VDD = 3.6 V + 200 mVP-P sine, Inputs = AC GND PSRR Power supply rejection ratio (Figure 22) fRIPPLE = 217 Hz 55 fRIPPLE = 1 kHz 78 dB 76 VCM = 200 mVP-P sine CMRR SNR Common mode rejection ratio (Figure 23) Signal-to-noise-ratio fRIPPLE = 217 Hz 68 dB fRIPPLE = 1k Hz 78 dB Boost Disabled, A-weighted 107 dB Boost Enabled A-weighted 98 dB A-weighted OS (1) (2) (3) (4) Output noise AV 24 dB 0 dB (Boost Disabled) 134 16 VRMS All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Typical values represent most likely parametric norms at TA = 25 C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 5 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com Electrical Characteristics VDD = 3.6 V (continued) The following specifications apply for RL = 1.5 F + 10 , CBST = 1 F, CIN = 0.47 F, CSET = 100 nF, AV = 24 dB unless otherwise specified. Limits apply for TA = 25 C.(1)(2) PARAMETER TEST CONDITIONS MIN (3) TYP (4) MAX (3) UNIT TA Attack time ATK1:ATK0 = 00, CSET = 100 nF 0.83 ms TR Release time RLT1:RLT0 = 00, CSET = 100 nF 0.5 s fSW Boost converter switching frequency ILIMIT Boost converter current limit VIH Logic high input threshold SHDN VIL Logic low input threshold SHDN IIN Input leakage current SHDN 2 MHz 1.5 A 1.4 V 0.1 0.5 V 0.2 A 6.5 I2C Interface Characteristics The following specifications apply for RPU = 1 k to VDD, SW/HW = 1 (Software Mode) unless otherwise specified. Limits apply for TA = 25 C. (1) (2) PARAMETER TEST CONDITIONS VIH Logic Input High Threshold SDA, SCL VIL Logic Input Low Threshold SDA, SCL MIN (3) TYP (4) MAX (3) 1.1 SCL Frequency UNIT V 0.5 V 400 kHz t1 SCL Period 2.5 s t2 SDA Setup Time 250 ns t3 SDA Stable Time 250 ns t4 Start Condition Time 250 ns t5 Stop Condition Time 250 ns (1) (2) (3) (4) All voltages are measured with respect to the ground pin, unless otherwise specified. The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms at TA = 25 C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Charge device model, applicable std. JESD22-C101-C. Figure 1. I2C Timing Diagram SDA SCL S P START condition STOP condition Figure 2. Start and Stop Diagram 6 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 6.6 Typical Characteristics All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified. 50 50 20 10 5 2 THD + N (%) VOUT = 25 VP-P 5 THD + N (%) VOUT = 30 VP-P 20 VOUT = 30 VP-P 10 VOUT = 18 VP-P 1 0.5 0.2 VOUT = 25 VP-P 2 VOUT = 18 VP-P 1 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 20 50 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 3. THD+N vs Frequency CL = 0.6 F, VDD = 3.6 V, Boosted, AV = 24 dB Figure 4. THD+N vs Frequency CL = 1 F, VDD = 3.6 V, Boosted, AV = 24 dB 50 20 10 5 VOUT = 30 VP-P 2 1 10 VOUT = 25 VP-P 5 0.5 2 THD+N (%) THD + N (%) 100 200 VOUT = 18 VP-P 1 0.5 0.2 0.2 0.1 0.05 0.02 0.01 0.005 0.1 0.05 0.02 0.002 0.001 20 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Figure 6. THD+N vs Frequency VDD = 3.6 V, CL = 0.6 F, VOUT = 5 VP-P Unboosted, AV = 0 dB Figure 5. THD+N vs Frequency CL = 1.5 F, VDD = 3.6 V, Boosted, AV = 24 dB 10 5 10 5 2 1 2 1 0.5 THD+N (%) 0.5 THD+N (%) 50 100 200 500 1k 2k FREQUENCY (Hz) FREQUENCY (Hz) 0.2 0.1 0.05 0.2 0.1 0.05 0.02 0.01 0.005 0.02 0.01 0.005 0.002 0.001 20 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. THD+N vs Frequency VDD = 3.6 V, CL = 1 F, VOUT = 5 VP-P Unboosted , AV = 0 dB Figure 8. THD+N vs Frequency VDD = 3.6 V, CL = 1.5 F, VOUT = 5 VP-P Unboosted, AV = 0 dB Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 7 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) 35 8 30 7 OUTPUT VOLTAGE (Vp-p) OUTPUT VOLTAGE (Vp-p) All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified. 25 20 15 10 5 6 5 4 3 2 1 0 10 100 1000 10000 100000 0 10 100 1000 FREQUENCY (Hz) f = 4 kHz f = 3 kHz 1 0.1 f = 2 kHz 0.01 f = 1 kHz f = 200 Hz 0.001 0.01 0.1 1 10 100 Figure 10. Output Voltage vs Frequency CL = 1.5 F, THD+N 1%, Unboosted TOTAL HARMONIC DISTORTION + NOISE (%) TOTAL HARMONIC DISTORTION + NOISE (%) 100 10 100 f = 4 kHz f = 5 kHz f = 3 kHz 10 1 0.1 f = 2 kHz f = 1 kHz 0.01 f = 200 Hz 0.001 0.01 0.1 1 10 100 OUTPUT VOLTAGE (Vp-p) Figure 11. THD+N vs Output Voltage CL = 0.6 F, VDD = 3.6 V, Boosted, AV = 24 dB Figure 12. THD+N vs Output Voltage CL = 1 F, VDD = 3.6 V, Boosted, AV = 24 dB 100 f = 4 kHz f = 5 kHz f = 3 kHz 10 1 0.1 f = 2 kHz f = 1 kHz 0.01 f = 200 Hz 0.001 0.01 100 50 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 0.0005 0.0002 0.0001 1m f = 1 kHz f = 2 kHz THD+N (%) TOTAL HARMONIC DISTORTION + NOISE (%) OUTPUT VOLTAGE (Vp-p) 0.1 1 10 100 Figure 13. THD+N vs Output Voltage CL = 1.5 F, VDD = 3.6 V, Boosted, AV = 24 dB f = 200 Hz 5m 2m OUTPUT VOLTAGE (Vp-p) 8 100000 FREQUENCY (Hz) Figure 9. Output Voltage vs Frequency CL = 1.5 F, THD+N 1%, Boosted f = 5 kHz 10000 10m 20m 100m 500m 1 50m 200m 2 4 OUTPUT VOLTAGE (Vp-p) Figure 14. THD+N vs Output Voltage CL = 1.5 F, VDD = 3.6 V, Unboosted, AV = 0 dB Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 Typical Characteristics (continued) 12 11.5 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 500m ALC Off VOUT = 22VP-P VOUT = 20VP-P Supply Current (mA) OUTPUT VOLTAGE (V) All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified. VOUT = 14VP-P VOUT = 25VP-P VOUT = 17VP-P VOUT = 28VP-P 0 200m 400m 600m 800m 100m 300m 500m 700m 0.9 1 1.1 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 INPUT VOLTAGE (V) Supply Voltage (V) Figure 15. Input Voltage vs Output Voltage ALC Enabled, AV = 21 dB, VDD = 3.6 V Figure 16. Supply Current vs Supply Voltage RL = 2500 TOTAL POWER CONSUMPTION (mW) TOTAL POWER CONSUMPTION (mW) 1000 900 4 kHz 800 700 600 2 kHz 500 400 1 kHz 300 200 200 Hz 100 0 1500 2 kHz 1000 1 kHz 500 200 Hz 0 0 5 10 15 25 20 30 35 4 kHz 2000 0 5 15 20 25 30 35 Figure 18. Total Power Consumption vs Output Voltage VDD = 3.6 V, CL = 1 F Figure 17. Total Power Consumption vs Output Voltage VDD = 3.6 V, CL = 0.6 F 4500 0 4000 -10 4 kHz 3500 -20 3000 -30 2 kHz CMRR (dB) TOTAL POWER CONSUMPTION (mW) 10 VOUT (VPP) VOUT (VPP) 2500 2000 1 kHz 1500 -40 -50 -60 1000 -70 200 Hz 500 -80 0 0 5 10 15 20 25 30 35 -90 10 VOUT (VPP) 100 1000 10000 100000 FREQUENCY (Hz) Figure 19. Total Power Consumption vs Output Voltage VDD = 3.6 V, CL = 1.5 F Figure 20. Common Mode Rejection Ratio vs Frequency VCM= 200 mVP-P, CIN = 10 F, VDD = 3.6 V, CL = 1.5 F Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 9 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) All typical performance curves are taken with conditions seen in Typical Characteristics, unless otherwise specified. +0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) Figure 21. Power Supply Rejection Ratio vs Frequency VRIPPLE = 200 mVP-P, VDD = 3.6 V, CL = 1.5 F 7 Parameter Measurement Information 200 mVp-p ANALYZER VDD + VDD - IN+ ZL DUT IN- Figure 22. PSRR Test Circuit VDD ANALYZER + VDD IN+ IN- DUT ZL 200 mVp-p Figure 23. CMRR Test Circuit 10 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 8 Detailed Description 8.1 Overview The LM48560 device is a fully differential Class H driver for ceramic speakers and piezo actuators. The integrated, high efficiency boost converter dynamically adjusts the amplifier's supply voltage based on the output signal to maintain sufficient headroom while improving efficiency. The LM48560 device's Class H architecture offers significant power savings compared to conventional Class AB drivers. The LM48560 features two fully differential inputs with separate gain settings, and a selectable control interface. In software control mode, the gain control and device modes are configured through the I2C interface. In hardware control mode, the gain and input mux are configured through a pair of logic inputs. 8.2 Functional Block Diagram +2.7V to +5.5V D1 L1 4.7 PH CS VDD SW VBST SCL/GAIN SDA/SEL SW/HW CBST BOOST CONVERTER I2C INTERFACE PGND SHDN CIN 0.47 PF 1 PF IN1+ CIN OUT- 0.47 PF CIN 0.47 PF IN1IN2+ MUX/ GAIN STAGE ALC RL 10: OUT+ CIN 0.47 PF SET CL IN2SGND 8.3 Feature Description 8.3.1 General Amplifier Function The LM48560 device is a fully differential, Class H piezo driver for ceramic speakers and haptic actuators. The integrated, high efficiency boost converter dynamically adjusts the amplifier's supply voltage based on the output signal, increasing headroom and improving efficiency compared to a conventional Class AB driver. The fully differential amplifier takes advantage of the increased headroom and bridge-tied load (BTL) architecture, delivering significantly more voltage than a single-ended amplifier. 8.3.2 Class H Operation Class H is a modification of another amplifier class (typically Class B or Class AB) to increase efficiency and reduce power dissipation. To decrease power dissipation, Class H uses a tracking power supply that monitors the output signal and adjusts the supply accordingly. When the amplifier output is below 3VP-P, the nominal boost voltage is 6 V. As the amplifier output increases above 3 VP-P, the boost voltage tracks the amplifier output as shown in Figure 24. When the amplifier output falls below 3 VP-P, the boost converter returns to its nominal output voltage. Power dissipation is greatly reduced compared to conventional Class AB drivers. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 11 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com Feature Description (continued) VBOOST (2V/DIV) VOUT (2V/DIV) 2 ms/DIV Figure 24. Class H Operation 8.3.3 Differential Amplifier Explanation The LM48560 device features a fully differential amplifier. A differential amplifier amplifies the difference between the two input signals. A major benefit of the fully differential amplifier is the improved common mode rejection ratio (CMRR) over single ended input amplifiers. The increased CMRR of the differential amplifier reduces sensitivity to ground offset related noise injection, especially important in noisy systems. 8.3.4 Automatic Level Control (ALC) The ALC is available in software mode only, and only in boosted mode. In hardware mode ALC is always disabled. The ALC limits the peak output voltage to the programmed value. Consequently, it limits the peak boost voltage, as this is derived from the output voltage. The ALC is continuous, in that it provides a continuous adjustment of the voltage gain to limit the output voltage to the programmed value. The available gain adjustment range is typically 8 dB. When the input amplitude is further increased beyond the ALC attenuation range, the output will again increase. This is illustrated in the Typical Performance Graphs, as seen on the 14 VPP plot in the Input voltage vs Output Voltage curve. The attack and decay of the ALC is programmed by software and works in conjunction with the external capacitor CSET. Typically CSET is 0.1 F, although it can be changed from 0.1 F to 4.7 F to select other ranges of attack and decay time. 8.3.5 Attack Time Attack time (tATK) is the time it takes for the gain to be reduced by 6 dB once the audio signal exceeds the ALC threshold. Fast attack times allow the ALC to react quickly and prevent transients such as symbol crashes from being distorted. However, fast attack times can lead to volume pumping, where the gain reduction and release becomes noticeable, as the ALC cycles quickly. Slower attack times cause the ALC to ignore the fast transients, and instead act upon longer, louder passages. Selecting an attack time that is too slow can lead to increased distortion in the case of the No Clip function, and possible output overload conditions in the case of the Voltage limiter. The attack time is set by a combination of the value of CSET and the attack time coefficient as given by Equation 1: tATK = 20 kCSET / ATK (1) Where ATK is the attack time coefficient (Table 1) set by bits B4:B3 in the Voltage Limit Control Register. The attack time coefficient allows the user to set a nominal attack time. The internal 20 k resistor is subject to temperature change, and it has tolerance between -11% to +20%. Table 1. Attack Time Coefficient 12 B4 B3 ATK 0 0 2.4 0 1 1.7 1 0 1.3 1 1 0.9 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 8.3.6 Release Time Release time (tRL) is the time it takes for the gain to return from 6 dB to its normal level once the audio signal returns below the ALC threshold. A fast release time allows the ALC to react quickly to transients, preserving the original dynamics of the audio source. However, similar to a fast attack time, a fast release time contributes to volume pumping. A slow release time reduces the effect of volume pumping. The release time is set by a combination of the value of CSET and release time coefficient as given by Equation 2: tRL = 20 MCSET / RL (s) (2) where RL is the release time coefficient (Table 2) set by bits B6:B5 in the No Clip Control Register. The release time coefficient allows the user to set a nominal release time. The internal 20 M is subject to temperature change, and it has tolerance between -11% to +20%. Table 2. Release Time Coefficient RL B6 B5 0 0 4 0 1 5.3 1 0 9.5 1 1 11.8 8.3.7 Boost Converter The LM48560 device features an integrated boost converter with a dynamic output control. The device monitors the output signal of the amplifier, and adjusts the output voltage of the boost converter to maintain sufficient headroom while improving efficiency. 8.3.8 Gain Setting The LM48560 device features four internally configured gain settings 0 db, 6 dB, and 30 dB. The device gain is selected through a single pin (GAIN). The gain settings are shown in Table 3. Table 3. Gain Setting GAIN GAIN SETTING IN1 GAIN SETTING IN2 0 0 dB 24 dB 1 6 dB 30 dB 8.3.9 Shutdown Function The LM48560 device features a low current shutdown mode. Set SD = GND to disable the amplifier and boost converter and reduce supply current to 0.01 A. 8.4 Device Functional Modes 8.4.1 Software or Hardware Mode Device operation in hardware or software mode is determined by the state of the SW/HW pin. Connect SW/HW to ground for hardware mode, and connect to VDD for software mode. SW/HW 0 SDA/SEL 0 (Boost Disabled) 1 (Boost Enabled) 1 SDA SCL/GAIN MODE 0 IN1, Av = 0 1 IN1, Av = 6 0 IN2, Av = 24 1 IN2, Av = 30 SCL I2C Mode Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 13 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com 8.4.2 Single-Ended Input Configuration The LM48560 device is compatible with single-ended sources. When configured for single-ended inputs, input capacitors must be used to block and DC component at the input of the device. Figure 25 shows the typical single-ended applications circuit. LM48560 SINGLE-ENDED INPUT IN- IN+ Figure 25. Single-Ended Input Configuration 8.5 Programming 8.5.1 Read/Write I2C Compatible Interface The LM48560 device is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48560 device and the master can communicate at clock rates up to 400 kHz. Figure 1 shows the I2C interface timing diagram. Data on the SDA line must be stable during the HIGH period of SCL. The LM48560 device is a transmit/receive slave-only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a START condition and a STOP condition Figure 2. Each data word, device address and data, transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse Figure 26. The LM48560 device address is 1101111. 8.5.2 Write Sequence The example write sequence is shown in Figure 26. The START signal, the transition of SDA from HIGH to LOW while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus. The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0 indicating the master is writing to the LM48560 device). The data is latched in on the rising edge of the clock. Each address bit must be stable while SDA is HIGH. After the R/W bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48560 device receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register address word is sent, MSB first. Each data bit should be stable while SCL is HIGH. After the 8-bit register address is sent, the LM48560 device sends another ACK bit. Upon receipt of the acknowledge, the 8-bit register data is sent, MSB first. The register data word is followed by an ACK, upon receipt of which, the master issues a STOP bit, allowing SDA to go high while SDA is high. SCL SDA START MSB DEVICE ADDRESS LSB R/W ACK REGISTER ADDRESS ACK REGISTER DATA ACK STOP Figure 26. Example I2C Write Cycle 8.5.3 Read Sequence The example read sequence is shown in Figure 27. The START signal, the transition of SDA from HIGH to LOW while SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus. 14 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 Programming (continued) The 7-bit device address is written to the bus, followed by the R/W = 1 (R/W = 1 indicating the master wants to read data from the LM48560 device). After the R/W bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the slave device. If the LM48560 device receives the correct address, the device pulls the SDA line low, generating and acknowledge bit (ACK). Once the master device registers the ACK bit, the 8-bit register address word is sent, MSB first, followed by an ACK and selected register data from the LM48560 device. The register data is sent MSB first. Following the acknowledgment of the register data word [7:0], the master issues a STOP bit, allowing SDA to go high while SDA is high. ack from slave repeated start ack from slave start MSB Device Address LSB w ack MSB Register 0x00h LSB ack rs ack from slave data from slave ack from master MSB Device Address LSB r ack MSB Data LSB ack stop SCL SDA start Device address = 1101111 w ack register address = 0x00h ack rs Device address = 1101111 r ack register 0x00h data ack stop Figure 27. Example I2C Read Cycle Table 4. Device Address Device Address B7 B6 B5 B4 B3 B2 B1 B0 (R/W) 1 1 0 1 1 1 1 0 Table 5. Mode Selection SW/HW SDA/SEL SCL/GAIN MODE 0 (Boost Disabled) 0 IN1, AV = 0 1 IN1, AV = 6 1 (Boost Enabled) 0 IN2, AV = 24 1 IN2, AV = 30 X X I2C Mode 0 1 8.6 Register Maps Table 6. I2C Control Registers REGISTER ADDRESS Register Name B7 B6 B5 B4 B3 B2 B1 B0 0x00h SHUTDOWN CONTROL X X X X TURN _ON IN_SEL BOOST _EN SHDN 0x01h NO CLIP CONTROL X RLT1 RLT0 ATK1 ATK0 PLEV2 PLEV1 PLEV0 0x02h GAIN CONTROL X X X X X X GAIN1 GAIN0 0x03h TEST MODE X X X X X X X X Table 7. Shutdown Control Register BIT NAME VALUE B7:B4 UNUSED X Unused, set to 0 0 Normal turn on time, tWU = 15 ms 1 Fast turn on time, tWU = 5 ms B3 TURN_ON DESCRIPTION Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 15 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com Table 7. Shutdown Control Register (continued) BIT NAME B2 IN_SEL B1 BOOST_EN B0 SHDN VALUE DESCRIPTION 0 Input 1 selected 1 Input 2 selected 0 Boost disabled 1 Boost enabled 0 Device shutdown 1 Device enabled Table 8. No Clip Control Register BIT NAME VALUE B7 UNUSED X RLT1 (B6) RLT0 (B5) B6:B5 ATK1 (B4) ATK0 (B3) B4:B3 PLEV2 (B2) PLEV1 (B1) PLEV0 (B0) B2:B0 DESCRIPTION Unused, set to 0 B6 B5 Sets Release Time based on CSET. See Release Time section. 0 0 TR = 0.5 s 0 1 TR = 0.38 s 1 0 TR = 0.21 s 1 1 TR = 0.17 s B4 B3 Sets Attack Time based on CSET. See Attack Time section. 0 0 TA = 0.83 ms 0 1 TA = 1.2 ms 1 0 TA = 1.5 ms 1 1 TA = 2.2 ms B2 B1 B0 Sets output voltage limit level. 0 0 0 Voltage Limit disabled 0 0 1 VTH(VLIM) = 14 VP-P 0 1 0 VTH(VLIM) = 17 VP-P 0 1 1 VTH(VLIM) = 20 VP-P 1 0 0 VTH(VLIM) = 22 VP-P 1 0 1 VTH(VLIM) = 25 VP-P 1 1 0 VTH(VLIM) = 28 VP-P 1 1 1 Voltage Limit disabled Table 9. Gain Control Register BIT NAME VALUE DESCRIPTION B7:B2 UNUSED X Unused, set to 0 B1:B0 B1:B0 16 GAIN1(B1) GAIN0 (B0) GAIN1(B1) GAIN0 (B0) B1 B0 Sets amplifier gain. Boost disabled (BOOST_EN = 0) 0 0 0 dB 0 1 6 dB 1 0 12 dB 1 1 18 dB B1 B0 Sets amplifier gain. Boost enabled (BOOST_EN = 1) 0 0 21 dB 0 1 24 dB 1 0 27 dB 1 1 30 dB Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LM48560 device is a high voltage, high efficiency Class H driver for ceramic speakers and piezo actuators. The integrated, high efficiency boost converter dynamically adjusts the amplifier's supply voltage based on the output signal to increase headroom and improve efficiency. The LM48560 device's Class H architecture offers significant power savings compared to traditional Class AB amplifiers. The device provides 30Vp-p output drive while consuming just 4 mA of quiescent current from a 3.6 V supply. The LM48560 device features two fully differential inputs with separate gain settings, and a selectable control interface. In software control mode, the gain control and device modes are configured through the I2C interface. In hardware control mode, the gain and input mux are configured through a pair of logic inputs. The LM48560 device has a low current shutdown mode that disables the amplifier and boost converter and reduces quiescent current consumption to 0.1 A. 9.2 Typical Application Figure 28. Demo Board Schematic Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 17 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com Typical Application (continued) 9.2.1 Design Requirements Table 10 shows the design parameters for this design example. Table 10. Design Parameters PARAMETERS VALUES Supply voltage 2.7 V to 5.5 V Temperature -40 C to 85 C Input voltage -0.3 V to Vdd 0.3 V 9.2.2 Detailed Design Procedure 9.2.2.1 Proper Selection of External Components 9.2.2.1.1 ALC Timing (CSET) Capacitor Selection The recommended range value of CSET is between 0.01 F to 1 F. Lowering the value below 0.01 F can increase the attack time but LM48560 device ALC ability to regulate its output can be disrupted and approaches the hard limiter circuit. This in turn increases the THD+N and audio quality will be severely affected. 9.2.2.1.2 Power Selection of External Components Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1-F ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. 9.2.2.1.3 Boost Converter Capacitor Selection The LM48560 device boost converter requires three external capacitors for proper operation: a 1-F supply bypass capacitor, and 1-F + 100-pF output reservoir capacitors. Place the supply bypass capacitor as close to VDD as possible. Place the reservoir capacitors as close to VBST and VAMP as possible. Low ESR surfacemount multi-layer ceramic capacitors with X7R or X5R temperature characteristics are recommended. Select output capacitors with voltage rating of 25 V or higher. Tantalum, OS-CON and aluminum electrolytic capacitors are not recommended. 9.2.2.1.4 Inductor Selection The LM48560 device boost converter is designed for use with a 4.7-H inductor. Choose an inductor with a saturation current rating greater than the maximum operating peak current of the LM48560 device (> 1A). This ensures that the inductor does not saturate, preventing excess efficiency loss, over heating and possible damage to the inductor. Additionally, choose an inductor with the lowest possible DCR (series resistance) to further minimize efficiency losses. 9.2.2.1.5 Diode Selection Use a Schottkey diode as shown in Figure 28. A 20-V diode such as the NSR0520V2T1G from On Semiconductor is recommended. The NSR0520V2T1G is designed to handle a maximum average current of 500 mA. 18 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 9.2.3 Application Curve Figure 29. Out+, Out- and Vbst Waveforms for a 100 Hz Input Sine Wave Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 19 LM48560 SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 www.ti.com 10 Power Supply Recommendations The LM48560 device is designed be operate with a power supply between 2.7 V and 5.5 V. Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass capacitors as close to the device as possible. Place a 1-F ceramic capacitor from VDD to GND. Additional bulk capacitance may be added as required. 11 Layout 11.1 Layout Guidelines Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due to trace resistance between the LM48560 device and the load results in decreased output power and efficiency. Trace resistance between the power supply and ground has the same effect as a poorly regulated supply, increased ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio performance, minimizes crosstalk between channels and prevents switching noise from interfering with the audio signal. Use of power and ground planes is recommended. Place all digital components and route digital signal traces as far as possible from analog components and traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines must cross either over or under each other, ensure that they cross in a perpendicular fashion. 11.2 Layout Example Use wide traces for power supply inputs and amplifier outputs Route digital signal traces far from analog traces Figure 30. PCB Layout Example 20 Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 LM48560 www.ti.com SNAS513F - AUGUST 2011 - REVISED NOVEMBER 2015 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2011-2015, Texas Instruments Incorporated Product Folder Links: LM48560 21 PACKAGE OPTION ADDENDUM www.ti.com 16-Jan-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM48560TL/NOPB ACTIVE DSBGA YZR 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GO5 LM48560TLX/NOPB ACTIVE DSBGA YZR 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GO5 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Jan-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM48560TL/NOPB DSBGA YZR 16 250 178.0 8.4 LM48560TLX/NOPB DSBGA YZR 16 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.08 2.08 0.76 4.0 8.0 Q1 2.08 2.08 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM48560TL/NOPB DSBGA YZR LM48560TLX/NOPB DSBGA YZR 16 250 210.0 185.0 35.0 16 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YZR0016xxx D 0.6000.075 E TLA16XXX (Rev C) D: Max = 1.99 mm, Min = 1.93 mm E: Max = 1.99 mm, Min = 1.93 mm 4215051/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LM48560TL/NOPB LM48560TLX/NOPB