843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
1
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
GENERAL DESCRIPTION
The ICS843-106 is a Fibre Channel Dual
Output Oscillator and a member of the
HiPerClocksTM family of high performance
devices from ICS. The ICS843-106 uses a
25MHz crystal to synthesize 106.25MHz.
The ICS843-106 has excellent jitter performance. The
ICS843-106 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
FEATURES
•One LVCMOS/LVTTL output, 15Ω output impedance
One LVPECL output pair
•Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
•Output frequency: 106.25MHz
•Random jitter: 3ps (typical)
•Deterministic jitter: 0.24ps (typical)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Available in both standard and lead-free RoHS-compliant
packages
HiPerClockS™
ICS
ICS843-106
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
VCC
XTAL_IN
XTAL_OUT
VEE
1
2
3
4
Q1
nQ1
VCCO
Q0
8
7
6
5
BLOCK DIAGRAM PIN ASSIGNMENT
Clock
Synthesizer
XTAL_IN
XTAL_OUT
Q0
25MHz
LVCMOS
106.25MHz
Q1
nQ1
LVPECL
106.25MHz
ICS843-106
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
DATA SHEET
ICS843-106
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
1
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
2
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
TUO
ecnadepmItuptuO0Q51Ω
rebmuNemaNepyTnoitpircseD
1V
CC
rewoP.nipylppusevitisoP
3,2 ,NI_LATX
TUO_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotallicsolatsyrC
.tuptuoeht
siTUO_LATX
4V
EE
rewoP.nipylppusevitageN
50QtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcdedne-elgniS
51 Ω.ecnadepmituptuo
6V
OCC
rewoP.nipylppustuptuO
8,71Q,1QntuptuO.riaptuptuoLCEPVLlaitnereffiD
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
2
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
3
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5 V
Outputs, V
O (LVCMOS) -0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA
8 Lead TSSOP 101.7°C/W (0 mps)
8 Lead SOIC 112.7°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuO 6.2V
V
LO
1ETON;egatloVwoLtuptuO 5.0V
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
,noitceSnoitamrofnItnemerusaeMretemaraPeeS.2/
."tiucriCtseTdaoLtuptuOV3.3"
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
OCC
4.1-V
OCC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
OCC
0.2-V
OCC
7.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP6.00.1V
05htiwdetanimretstuptuO:1ETON ΩVot
OCC
.V2-
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSevitisoP 0.33.36.3V
V
OCC
egatloVylppuStuptuO 0.33.36.3V
I
EE
tnerruCylppuSrewoP 611Am
I
CC
tnerruCylppuSrewoP 69Am
I
OCC
tnerruCylppuStuptuO 42Am
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
3
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
4
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TABLE 4. CRYSTAL CHARACTERISTICS (NOTE 1)
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 52zHM
ecnareloTycneuqe
rF 03±mpp
gnitarepOrevOytilibatSycneuqerF
egnaRerutarepmeT 03±mpp
C(ecnaticapaCdaoL
L
2ETON;) 81Fp
sraeY01rofgnigA 51±mpp
leveLevirD 1Wm
.ycaruccampp001±tegratevobanwohssretemarapeht,egakcapDMSSU/
94CHnagnisU:1ETON
eeS:2ETON ecafretnItupnIlatsyrC .noitceSnoitamrofnInoitacilppAehtni
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
TUO
ycneuqerFtuptuO 52.601zHM
t
JD
1ETON;rettiJcitsinimreteD 42.0sp
t
JR
1ETON;rettiJmodnaR 3sp
t
SMR
(noitubirtsiDlatoTfoSMR σ;)
2ETON 21.3sp
t
p-p
1ETON;rettiJkaeP-ot-kaeP 42sp
t
CSO
emiTpUtratSnoitallicsO 01sm
t
R
t/
F
tuptuO
emiTllaF/esiR
0Q %08ot%02 001005sp
1Qn/1Q052008sp
cdoelcyCytuDtuptuO 8425%
.0003-AIStsercevaWgnisuderusaeM:1ET
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.41ybdedividtluserREB21-e01@jT,0003-AIStsercevaWgnisuderusaeM:2ETON
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
4
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
5
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
PARAMETER MEASUREMENT INFORMATION
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVPECL OUTPUT RISE/FALL TIME
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
LVCMOS
1.65V ± 0.15V
-1.65V ± 0.15V
Clock
Outputs
20%
80% 80%
20%
tRtF
tPERIOD
tPW
tPERIOD
odc =
V
CC
2
tPW
x 100%
Q0
GND
VCC,
VCCO
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT RISE/FALL TIME
Q1
nQ1
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
SWING
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V ± 0.3V
VEE
VCC,
VCCO
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
5
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
6
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
APPLICATION INFORMATION
Figure 1. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The ICS843-106 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
LVCMOS OUTPUT:
An unused LVCMOS output should be terminated with 100Ω
to ground as close as possible to the device.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
X1
18pF Parallel Cry stal
C1
12p
XTA L_OU T
XTA L_ I N
C2
12p
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
6
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
7
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 2B. LVPECL OUTPUT T ERMINATION
FIGURE 2A. LVPECL OUTPUT T ERMINATION
drive 50Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. Figures 2A and 2B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
V
CC
- 2V
50Ω50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
FOUT FIN
RTT = Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125Ω125Ω
84Ω84Ω
Zo = 50Ω
Zo = 50Ω
FOUT FIN
FREQUENCY STABILITY
The table shown provides a basic guideline in selecting
the proper quartz crystal that meets a timing budget of
±100ppm. For more information on selecting the proper
retemaraPlacipyTstinU
ecnareloTycneuqerF
03±
mpp
ytilibatSycneuqerF
03±
mpp
sraeY01rofgnigA51±mpp
rotallicsOSCIfoycaruccA01±mpp
ycaruccAecnaticapaCdaoL3±mpp
rorrEgnimiTllarevOlatoT 88±m
pp
crystal, see the application note, Crystal Timing Budget
and Accuracy for FemtoClock™ .
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
7
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
8
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843-106.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843-106 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 116mA = 417.6mW
•Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 417.6mW + 30mW = 447.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A
below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.448W * 90.5°C/W = 110.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θθ
θθ
θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
TABLE 6B. THERMAL RESISTANCE θθ
θθ
θJA FOR 8 LEAD SOIC FORCED CONVECTION
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
8
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
9
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 3.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V
CC
- 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCCO_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX
– 1.7V
(VCCO_MAX - VOL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOH_MAX) = [(2V - (V
CC_MAX - VOH_MAX
))/R
L
] * (VCC_MAX
- VOH_MAX) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCC_MAX
- 2V))/R
L
] * (VCC_MAX
- VOL_MAX) = [(2V - (V
CC_MAX - VOL_MAX
))/R
L
] * (VCC_MAX
- VOL_MAX) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 3. LVPECL DRIVER CIRCUIT AND T ERMINATION
Q1
VOUT
VCC
RL
50
VCC - 2V
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
9
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
10
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS843-106 is: 2376
TABLE 7A. θJAVS. AIR FLOW T ABLE FOR 8 LEAD TSSOP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
TABLE 7B. θJAVS. AIR FLOW T ABLE 8 LEAD SOIC
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
10
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
11
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-153
LOBMYS sretemilliM
muminiMmumixaM
N8
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D09.201.3
ECISAB04.6
1E03.405.4
eCISAB56.0
L54
.057.0
α°0°8
aaa--01.0
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8B. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
LOBMYS sretemilliM
MUMINIMMUMIXAM
N8
A53.157.1
1A01.052.0
B33.015.0
C91.052.0
D08.400.5
E08.300.4
eCISAB72.1
H08.502.6
h52.005.0
L04.07
2.1
α°0°8
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
11
843AG-106 www.icst.com/products/hiperclocks.html REV. A JANUARY 10, 2006
12
Integrated
Circuit
Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TABLE 9. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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FL601-GA348SCIDBTPOSST"eerF-daeL"dael8ebutC°07otC°0
TFL601-GA348SCIDBTPOS
ST"eerF-daeL"dael8leer&epat0052C°07otC°0
601-MA348SCIDBTCIOSdael8ebutC°07otC°0
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FL601-MA348SCIDBTCIOS"eerF-daeL"dael8ebutC°07otC°0
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tahtstraP:ETON
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
IDT™ / ICS™ 106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR ICS843-106
12
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
XX-XXXX-XXXXX
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
clockhelp@idt.com
408-284-8200
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
ICS8521
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TSD
ICS8535-01
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER TSD
ICS9148-75
Frequency Generator & Integrated Buffers for Mother Boards TSD
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR TSD
