Vishay Siliconix
DG428, DG429
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers
DESCRIPTION
The DG428, DG429 analog multiplexers have on-chip
address and control latches to simplify design in
microprocessor based applications. Break-before-make
switching action protects against momentary crosstalk of
adjacent input signals.
The DG428 selects one of eight single-ended inputs to a
common output, while the DG429 selects one of four
differential inputs to a common differential output.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up to
the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
The silicon-gate CMOS process enables operation over a
wide range of supply voltages. The absolute maximum
voltage rating is extended to 44 V. Additionally, single supply
operation is also allowed and an epitaxial layer prevents
latchup.
On-board TTL-compatible address latches simplify the digital
interface design and reduce board space in bus-controlled
systems such as data acquisition systems, process controls,
avionics, and ATE.
FEATURES
• Halogen-free according to IEC 61249-2-21
Definition
•Low R
DS(on): 55
• Low Charge Injection: 1 pC
• On-Board TTL Compatible Address Latches
• High Speed - tTRANS: 160 ns
• Break-Before-Make
• Low Power Consumption: 0.3 mW
• Compliant to RoHS Directive 2002/95/EC
BENEFITS
• Improved System Accuracy
• Microprocessor Bus Compatible
• Easily Interfaced
• Reduced Crosstalk
• High Throughput
• Improved Reliability
APPLICATIONS
• Data Acquisition Systems
• Automatic Test Equipment
• Avionics and Military Systems
• Communication Systems
• Microprocessor-Controlled Analog Systems
• Medical Instrumentation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG428 DG428
WR
D
RS
S8
A0A1
EN A2
V- GND
S1V+
S2S5
S3S6
S4S7
Dual-In-Line
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top View
910
Latches
PLCC
14
15
16
17
18
8
7
6
5
4
1231920
111091312
Top View
EN A2
V- GND
S1V+
S2S5
S3S6
4
D
NC
8
7
A
WR
NC
RS
A
Latches
Decoders/Drivers
0
1
S
S
S
www.vishay.com
2
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Logic "0" = VAL 0.8 V
Logic "1" = VAH 2.4 V
X = Don’t Care
DG429 DG429
WR
Da
RS
Db
A0A1
EN GND
V- V+
S1a S1b
S2a S2b
S3a S3b
S4a S4b
Dual-In-Line and SOIC
Decoders/Drivers
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
Top View
910
Latches EN GND
V- VDD
S1a S1b
S2a S2b
S3a S3b
PLCC
14
15
16
17
18
8
7
6
5
4
1231920
111091312
Top View
4a
a
NC
b
4b
A
WR
NC
RS
A
Latches
Decoders/Drivers
0
1
S
D
D
S
TRUTH TABLE - DG428
8-Channel Single-Ended Multiplexer
A2 A
1 A
0 EN WR RS On Switch
Latching
X X X X 1 Maintains previous
switch condition
Reset
X X X X X 0 None (latches
cleared)
Transparent Operation
X X X 0 0 1 None
0 0 0 1 0 1 1
0 0 1 1 0 1 2
0 1 0 1 0 1 3
0 1 1 1 0 1 4
1 0 0 1 0 1 5
1 0 1 1 0 1 6
1 1 0 1 0 1 7
1 1 1 1 0 1 8
TRUTH TABLE - DG429
Differential 4-Channel Multiplexer
A1 A
0 EN WR RS On Switch
Latching
X X X 1 Maintains previous
switch condition
Reset
X X X X 0 None (latches
cleared)
Transparent Operation
X X 0 0 1 None
0 0 1 0 1 1
0 1 1 0 1 2
1 0 1 0 1 3
1 1 1 0 1 4
ORDERING INFORMATION - DG428
Temp Range Package Part Number
- 40 °C to 85 °C
18-pin Plastic DIP DG428DJ
DG428DJ-E3
20-pin PLCC DG428DN
DG428DN-E3
ORDERING INFORMATION - DG429
Temp Range Package Part Number
- 40 °C to 85 °C
18-pin Plastic DIP DG429DJ
DG429DJ-E3
20-pin PLCC DG429DN
DG429DN-E3
18-pin Widebody SOIC DG429DW
DG429DW-E3
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
3
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6.3 mW/°C above 75 °C.
d. Derate 12 mW/°C above 75 °C.
e. Derate 10 mW/°C above 75 °C.
f. Derate 6 mW/°C above 75 °C.
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter Symbol Limit Unit
Voltages Referenced to V- V+ 44
V
GND 25
Digital Inputsa, VS, VD
(V-) - 2 V to (V+) + 2 V
or 30 mA, whichever occurs first
Current (Any Terminal) 30 mA
Peak Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle Max) 100
Storage Temperature (AK Suffix) - 65 to 150 °C
(DJ, DN Suffix) - 65 to 125
Power Dissipation (Package)b
18-pin Plastic DIPc470
mW
18-pin CerDIPd900
20-pin PLCCf800
28-Pin Widebody SOICf450
www.vishay.com
4
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V, WR = 0,
RS = 2.4 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full - 15 15 - 15 15 V
Drain-Source
On-Resistance RDS(on)
VD = ± 10 V, VAL = 0.8 V
IS = - 1 mA, VAH = 2.4 V
Room
Full
55 100
125
100
125
Greatest Change in RDS(on)
Between ChannelsgRDS(on)
- 10 V < VS < 10 V
IS = - 1 mA Room 5 %
Source Off Leakage Current IS(off)
VS = ± 10 V,
VEN = 0 V, VD = ± 10 V
Room
Full
± 0.03 - 0.5
- 50
0.5
50
- 0.5
- 50
0.5
50
nA
Drain Off Leakage Current ID(off)
VEN = 0 V
VD = ± 10 V
VS = ± 10 V
DG428 Room
Full
± 0.07 - 1
- 100
1
100
- 1
- 100
1
100
DG429 Room
Full
± 0.05 - 1
- 50
1
50
- 1
- 50
1
50
Drain On Leakage Current ID(on)
VS = VD = ± 10 V
VEN = 2.4 V
VAL= 0.8 V
VAH = 2.4 V
DG428 Room
Full
± 0.07 - 1
- 100
1
100
- 1
- 100
1
100
DG429 Room
Full
± 0.05 - 1
- 50
1
50
- 1
- 50
1
50
Digital Control
Logic Input Current
Input Voltage High IAH
VA = 2.4 V Full 0.01 1 1
µA
VA = 15 V Full 0.01 1 1
Logic Input Current
Input Voltage Low IAL
VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V Full - 0.01 - 1 - 1
Logic Input Capacitance Cin f = 1 MHz Room 8 pF
Dynamic Characteristics
Transition Time tTRANS See Figure 5 Room
Full
150 250
300
250
300
ns
Break-Before-Make Interval tOPEN See Figure 4 Full 30 10 10
Enable and Write Turn-On Time tON(EN,WR) See Figure 6 and 7 Room
Full
90 150
225
150
225
Enable and Reset Turn-Off Time tOFF(EN,RS) See Figure 6 and 8 Room
Full
55 150
300
150
300
Charge Injection Q VGEN = 0 V, RGEN = 0
CL = 1 nF, See Figure 9 Room 1 pC
Off Isolation OIRR
VEN = 0 V, RL = 300
CL = 15 pF, VS = 7 VRMS
f = 100 kHz
Room - 75 dB
Source Off Capacitance CS(off) VS = 0 V, VEN = 0 V, f = 1 MHz Room 11
pF
Drain Off Capacitance CD(off) VD = 0 V
VEN = 0 V
f = 1 MHz
DG428 Room 40
DG429 Room 20
Drain On Capacitance CD(on)
DG428 Room 54
DG429 Room 34
Minimum Input Timing Requirements
Write Pulse Width tW
See Figure 2
Full 100 100
ns
AX, EN Data Set Up time tSFull 100 100
AX, EN Data Hold Time tHFull 10 10
Reset Pulse Width tRS VS = 5 V, See Figure 3 Full 100 100
Power Supplies
Positive Supply Current I+ VEN = VA = 0, RS = 5 V Room 20 100 100 µA
Negative Supply Current I- Room - 0.001 - 5 - 5
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
5
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. RDS(on) = R
DS(on) MAX – RDS(on) MIN
(
RDS(on) AVE
)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONSa (for single supply)
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V, WR = 0,
RS = 2.4 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55°C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full 0 12 0 12 V
Drain-Source
On-Resistance RDS(on)
VD = ± 10 V, VAL = 0.8 V
IS = - 500 µA, VAH = 2.4 V Room 80 150 150
RDS(on) MatchgRDS(on)
0 V < VS < 10 V
IS = - 1 mA Room 5 %
Source Off Leakage Current IS(off)
VS = 0 V, 10 V,
VEN = 0 V, VD = 10 V, 0 V
Room
Full
± 0.03 - 0.5
- 50
0.5
50
- 0.5
- 50
0.5
50
nA
Drain Off Leakage Current ID(off)
VD = 0 V, 10 V
VS = 10 V, 0 V
VEN = 0 V
DG428 Room
Full
± 0.07 - 1
- 100
1
100
- 1
- 100
1
100
DG429 Room
Full
± 0.05 - 1
- 50
1
50
- 1
- 50
1
50
Drain On Leakage Current ID(on)
VS = VD = 0 V, 10 V
VEN = 2.4 V
VAL= 0.8 V
VAH = 2.4 V
DG428 Room
Full
± 0.07 - 1
- 100
1
100
- 1
- 100
1
100
DG429 Room
Full
± 0.05 - 1
- 50
1
50
- 1
- 50
1
50
Digital Control
Logic Input Current
Input Voltage High IAH
VA = 2.4 V Full 1 1
µA
VA = 12 V Full 1 1
Logic Input Current
Input Voltage Low IAL VEN = 0 V, 2.4 V, VA = 0 V
RS = 0 V, WR = 0 V Full - 1 - 1
Dynamic Characteristics
Transition Time tTRANS S1 = 10 V/ 2 V, S8 = 2 V/ 10 V
See Figure 5
Room
Full
160 280
350
280
350
ns
Break-Before-Make Interval tOPEN See Figure 4 Room
Full
40 25
10
25
10
Enable and WriteTurn-On Time tON(EN,WR) S1 = 5 V
See Figure 6 and 7
Room
Full
110 300
400
300
400
Enable and Reset Turn-Off Time tOFF(EN,RS) S1 = 5 V
See Figure 6 and 8
Room
Full
70 300
400
300
400
Charge Injection Q VGEN = 6 V, RGEN = 0
CL = 1 nF, See Figure 9 Room 4 pC
Off Isolation OIRR
VEN = 0 V, RL = 300
CL = 15 pF, VS = 7 VRMS
f = 100 kHz
Room - 75 dB
Minimum Input Timing Requirements
Write Pulse Width tW
See Figure 2
Full 100 100
ns
AX, EN Data Set Up time tSFull 100 100
AX, EN Data Hold Time tHFull 10 10
Reset Pulse Width tRS VS = 5 V, See Figure 3 Full 100 100
Power Supplies
Positive Supply Current I+ VEN = 0 V, VA = 0, RS = 5 V Room 20 100 100 µA
x 100 %
www.vishay.com
6
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
RDS(on) vs. VD and Supply Voltage
Single Supply RDS(on) vs. VD and Supply
ID , IS Leakages vs. Temperature
0
20
40
60
80
100
120
140
- 20 - 16 - 12 - 8 - 4 0 4 8 1 2 1 6 2 0
V
D
– Drain Voltage (V)
± 5 V
± 8 V
± 20 V
± 15 V
± 12 V
± 10 V
RDS(on) – Drain-Source On-Resistance (Ω)
0 4 8 12 16 20
0
40
80
120
160
200
VD – Drain Voltage (V)
V- = 0 V
V+ = 7.5 V
10 V
12 V
15 V
20 V
RDS(on) – Drain-Source On-Resistance (Ω)
- 55 5 2 5 4 5 6 5 8 5 105 125
1 pA
10 pA
100 pA
1 nA
10 nA
I
S
(of f )
I
D(on),
I
D(of f)
V+ = 15 V
V- = - 15 V
V
S,
V
D
= ± 14 V
Temperature (°C)
IS, ID – Leakage Current
- 35 - 15
RDS(on) vs. VD and Temperature
ID , IS Leakage Currents vs. Analog Voltage
Switching Times vs. Power Supply Voltage
- 15 - 10 - 5 0 5 10 15
0
10
20
30
40
50
60
70
80
90
100
125 °C
85 °C
25 °C
- 40 °C
- 55 °C
V+ = 15 V
V- = - 15 V
RDS(on) – Drain-Source On-Resistance (Ω)
VD – Drain Voltage (V)
- 15 - 10 - 5 0 5 10 15
- 30
- 20
- 10
0
10
20
30
40
I
S( of f)
V+ = 15 V
V- = - 15 V
V
S
= -V
D
for I
D(of f)
V
D
= V
S
for I
D(on)
V
S,
V
D
– Source, Drain Voltage (V)
I
D(on),
I
D(of f)
I
S
, I
D
– Current (pA)
0
50
100
150
200
250
"5 "10 "15 "20
t
TRA N S
t
ON(E N)
t
OFF(E N )
Supply Voltage (V)
Time (ns)
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
7
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
Switching Times vs. Single Supply
Off-Isolation vs. Frequency
Switching Times vs. Temperature
0
50
100
150
200
250
300
350
5 10 15 20
tTRANS
V- = 0 V
Time (ms)
tON
tOFF
V+ – Positive Supply (V)
1 k 10 k 100 k 1 M 10 M
- 20
- 40
- 60
- 80
- 100
- 120
- 140
OIRR (dB)
f – Frequency (Hz)
0
50
100
150
200
- 55 - 35 45 85 125
t
TRA N S
V+ = 15 V
V- = - 15 V
Temperature (°C)
Time (nS)
t
OFF
t
ON
- 15 5 65 105
25
Charge Injection vs. Analog Voltage
Supply Currents vs. Switching Frequency
Input Switching Threshold vs. Positive Supply Voltage
- 15 - 10 - 5 0 5 10 15
- 60
- 40
- 20
0
20
40
60
V
S
– Source Voltage (V)
Q – Charge (pC)
V+ = 12 V
V- = 0 V
V+ = 15 V
V- = - 15 V
1 k 10 k 100 k 1 M 10 M
- 8
- 6
- 4
- 2
0
2
4
6
8
I-
I+
I
GND
E
N
= 5 V
A
X
= 0 or 5 V
Supply Current (mA)
f – Frequency (Hz)
0
0.5
1
1.5
2
2.5
3
0 5 10 15 20
V
V+ Positive – Supply Voltage (V)
TH (V)
www.vishay.com
8
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SCHEMATIC DIAGRAM (Typical Channel)
TIMING DIAGRAMS
TEST CIRCUITS
Figure 1.
S1
EN
D
V+
Sn
V-
Decode/
Drive
Level
Shift
V+
Latches
VREF
V+
V-
DO
Dn
CLK
RESET
QO
Qn
AX
WR
RS
GND
V-
Figure 2.
3 V
0 V
3 V
0 V
50 %
20 %
80 %
EN
tW
tH
WR
A0, A1, (A2)
tS
Figure 3.
3 V
0 V
0 V
50 %
RS
VO
Switch
Output
tRS
tOFF(RS)
80 %
Figure 4. Break-Before-Make
DG428
DG429
EN
V+
GND V-
+ 5 V
35 pF
- 15 V
+ 15 V
+ 2.4 V RS
A0, A1, (A2)D
b, D
All S and Da
WR
300 Ω
VO
50 Ω
Logic
Input
Switch
Output
VO
VS
tOPEN
tr < 20 ns
tf < 20 ns
3 V
0 V
50 %
80 %
0 V
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
9
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TEST CIRCUITS
Figure 5. Transition Time
DG428
DG429
S1b
S1a - S4a, Da
S2b and S3b
Db
RS
A0
A1
50 Ω
WR
300 Ω
VO
± 10 V
± 10 V
S4b
EN
V+
GND V-
35 pF
- 15 V
+ 15 V
+ 2.4 V
RS S1
S2 - S 7
A0
A1
A2
50 Ω
WR
300 Ω
VO
S8
± 10 V
± 10 V
EN
V+
GND V- D
35 pF
- 15 V
+ 15 V
+ 2.4 V
3 V
0 V
Logic
Input
Switch
Output
VS8
VO
tTRANS
tr < 20 ns
tf < 20 ns
S8 ONS1 ON
tTRANS
0 V
VS1
50 %
10 %
90 %
Figure 6. Enable tON/tOFF Time
DG428
DG429
RS
EN
+ 2.4 V S1
S2 - S8
A0
A1
A2
50 Ω
WR
300 Ω
VO
V+
GND V- D
- 5 V
35 pF
- 15 V
+ 15 V
S1b
S1a - S4a, Da
S2b - S4b
RS
Db
A0
A1
50 Ω
WR
300 Ω
VO
EN
+ 2.4 V V+
GND V-
- 5 V
35 pF
- 15 V
+ 15 V
Logic
Input
Switch
Output
VO
tr < 20 ns
tf < 20 ns
3 V
0 V
0 V
tOFF(EN)
tON(EN)
50 %
90 %
VO
www.vishay.com
10
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TEST CIRCUITS
Figure 7. Write Turn-On Time tON(WR)
3 V
0 V
0 V
50 %
DG428
DG429
WR
Switch
Output
VO
20 %
tON(WR)
A0, A1, (A2)
Db, D
EN
WR
300 Ω
Remaining
Switches
S1 or S1b
VO
RS
V+
GND V-
+ 5 V
35 pF
- 15 V
+ 15 V
+ 2.4 V
Figure 8. Reset Turn-Off Time tOFF(RS)
3 V
0 V
0 V
50 %
DG42
DG429
RS
Switch
Output
VO
80 %
tOFF(RS)
RS VO
EN
Remaining
Switches
WR
S1 or S1b
Db, D
A0, A1, (A2)
300 Ω
V+
GND V-
+ 5 V
35 pF
- 15 V
+ 15 V
+ 2.4 V
Figure 9. Charge Injection
EN
V
O
ΔV
O
ΔV
O
is the measured voltage error due to
charge injection. The charge in coulombs is Q =
C
L
x ΔV
O
OFF OFFON
C
L
1 nF
IN
DV
O
2.4 V
RS
A
0
, A
1
, (A
2
)
WR V-
V+
S
3 V
V
g
R
g
- 15 V
GND
+ 15 V
Document Number: 70063
S11-1350–Rev. K, 04-Jul-11
www.vishay.com
11
Vishay Siliconix
DG428, DG429
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DETAILED DESCRIPTION
The internal structure of the DG428, DG429 includes a 5 V
logic interface with input protection circuitry followed by a
latch, level shifter, decoder and finally the switch constructed
with parallel n- and p-channel MOSFETs (see Figure 1).
The input protection on the logic lines A0, A1, A2, EN and
control lines WR, RS shown in Figure 1 minimizes
susceptibility to ESD that may be encountered during
handling and operational transients.
The logic interface is a CMOS logic input with its supply
voltage from an internal + 5 V reference voltage. The output
of the input inverter feeds the data input of a D type latch.
The level sensitive D latch continuously places the DX input
signal on the QX output when the WR input is low, resulting
in transparent latch operation. As soon as WR returns high
the latch holds the data last present on the Dn input, subject
to the "Minimum Input Timing Requirements" table.
Following the latches the Qn signals are level shifted and
decoded to provide proper drive levels for the CMOS
switches. This level shifting ensures full on/off switch
operation for any analog signal level between the V+ and
V- supply rails.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard wired to the logic supply or to V+ if
one of the channels will always be used (except during a
reset) or it can be tied to address decoding circuitry for
memory mapped operation. The RS pin is used as a master
reset. All latches are cleared regardless of the state of any
other latch or control line. The WR pin is used to transfer the
state of the address control lines to their latches, except
during a reset or when EN is low (see Truth Tables).
APPLICATIONS HINTS
Bus Interfacing
The DG428, DG429 minimize the amount of interface
hardware between a microprocessor system bus and the
analog system being controlled or measured. The internal
TTL compatible latches give these multiplexers write-only
memory, that is, they can be programmed to stay in a
particular switch state (e.g., switch 1 on) until the
microprocessor determines it is necessary to turn different
switches on or turn all switches off (see Figure 10).
The input latches become transparent when WR is held low;
therefore, these multiplexers operate by direct command of
the coded switch state on A2, A1, A0. In this mode the DG428
is identical to the popular DG408. The same is true of the
DG429 versus the popular DG409.
During system power-up, RS would be low, maintaining all
eight switches in the off state. After RS returned high the
DG428 maintains all switches in the off state.
When the system program performs a write operation to the
address assigned to the DG428, the address decoder
provides a CS active low signal which is gated with the
WRITE (WR) control signal. At this time the data on the
DATA BUS (that will determine which switch to close) is
stabilizing. When the WR signal returns to the high state,
(positive edge) the input latches of the DG428 save the data
from the DATA BUS. The coded information in the A0, A1, A2
and EN latches is decoded and the appropriate switch is
turned on.
The EN latch allows all switches to be turned off under
program control. This becomes useful when two or more
DG428s are cascaded to build 16-line and larger
multiplexers.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see www.vishay.com/ppg?70063.
Figure 10. Bus Interface
Data Bus
RESET
Address
Decoder
Address
Bus
+ 5 V
V+
V- D
+ 15 V
- 15 V
DG428
Processor
System
Bus
15 V
Analog
Inputs
Analog
Output
WR
RS
S1
S8
A0, A1, A2, EN
WRITE
0.101 mm
0.004″
D–SQUARE
D1–SQUARE
A2
B1
e1
A1
D2
B
A
Package Information
Vishay Siliconix
Document Number: 71263
02-Jul-01 www.vishay.com
1
PLCC: 2OĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A4.20 4.57 0.165 0.180
A12.29 3.04 0.090 0.120
A20.51 – 0.020 –
B0.331 0.553 0.013 0.021
B10.661 0.812 0.026 0.032
D9.78 10.03 0.385 0.395
D18.890 9.042 0.350 0.356
D27.37 8.38 0.290 0.330
e11.27 BS C 0.050 BSC
ECN: S-03946—Rev. C, 09-Jul-01
DWG: 5306
L
A1
B
ALL LEADS
0.101 mm
0.004″
E
D
e
A
H
C
123456789
18 17 16 15 14 13 12 11 10
Package Information
Vishay Siliconix
Document Number: 71266
02-Jul-01 www.vishay.com
1
SOIC (WIDEĆBODY): 18ĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A2.15 2.90 0.085 0.114
A10.10 0.30 0.004 0.012
B0.35 0.45 0.014 0.018
C0.23 0.28 0.009 0.011
D11.25 12.45 0.443 0.490
E7.25 8.00 0.285 0.315
e1.27 BS C 0.050 BSC
H9.80 10.60 0.386 0.417
L0.60 1.00 0.024 0.039
0_8_0_8_
ECN: S-03946—Rev. C, 09-Jul-01
DWG: 5302
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to
obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
