KM68V1002B/BL, KM68V1002BI/BLI Preliminary PRELIMINARY CMOS SRAM Document Title 128Kx8 Bit High Speed Static RAM(3.3V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial release with Design Target. Apr. 1st, 1997 Design Target Rev.1.0 Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Jun. 1st, 1997 Preliminary Rev.2.0 Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete 32-SOJ-300 package. 2.3. Add Capacitive load of the test environment in A.C test load. 2.4. Change D.C characteristics. Previous spec. Changed spec. Items (8/10/12ns part) (8/10/12ns part) ICC 160/150/140mA 160/155/150mA ISB 30mA 50mA Feb. 25th, 1998 Final Rev. 2.1 Change Standby and Data Retention Current for L-ver. Items Previous spec. Changed spec. ISB1 0.5mA 0.7mA IDR at 3.0V 0.4mA 0.5mA IDR at 2.0V 0.3mA 0.4mA Aug. 4th, 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI 128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating) FEATURES GENERAL DESCRIPTION * Fast Access Time 8,10,12ns(Max.) * Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS) : 5mA(Max.) 0.7mA(Max.) - L-Ver. only Operating KM68V1002B/BL - 8 : 160mA(Max.) KM68V1002B/BL - 10 : 155mA(Max.) KM68V1002B/BL - 12 : 150mA(Max.) * Single 3.30.3V Power Supply * TTL Compatible Inputs and Outputs * Fully Static Operation - No Clock or Refresh required * Three State Outputs * 2V Minimum Data Retention ; L-Ver. only * Center Power/Ground Pin Configuration * Standard Pin Configuration KM68V1002BJ : 32-SOJ-400 KM68V1002BT : 32-TSOP2-400F The KM68V1002B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM68V1002B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM68V1002B is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward. ORDERING INFORMATION KM68V1002B/BL -8/10/12 Commercial Temp. KM68V1002BI/BLI -8/10/12 Industrial Temp. PIN CONFIGURATION(Top View) FUNCTIONAL BLOCK DIAGRAM Clk Gen. Pre-Charge Circuit A0 A2 A3 A4 A5 Row Select A1 Memory Array 256 Rows 512x8 Columns Data Cont. 1 32 A16 A1 2 31 A15 A2 3 30 A14 A3 4 29 A13 CS 5 28 OE I/O1 6 27 I/O8 I/O2 7 26 I/O7 Vcc 8 Vss 9 I/O3 10 A6 A7 I/O1 ~I/O8 A0 I/O Circuit Column Select CLK Gen. 25 Vss SOJ/ 24 Vcc TSOP2 23 I/O6 I/O4 11 22 I/O5 WE 12 21 A12 A4 13 20 A11 A5 14 19 A10 A6 15 18 A9 A7 16 17 A8 PIN FUNCTION A8 A9 A10 A11 A12 A13 A14 A15 A16 Pin Name A0 - A 16 CS WE OE Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O 1 ~ I/O8 -2- Pin Function Data Inputs/Outputs VCC Power(+3.3V) VSS Ground N.C No Connection Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Voltage on Any Pin Relative to VSS -0.5 to 4.6 V VCC -0.5 to 4.6 V Power Dissipation Operating Temperature Unit VIN, VOUT Voltage on VCC Supply Relative to VSS Storage Temperature Rating PD 1.0 W TSTG -65 to 150 C Commercial TA 0 to 70 C Industrial TA -40 to 85 C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70C) Symbol Min Typ Max Unit Supply Voltage Parameter VCC 3.0 3.3 3.6 V Ground VSS 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3*** V Input Low Voltage VIL -0.3** - 0.8 V * The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 6ns) for I 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width 6ns) for I 20mA. DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=3.30.3V, unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC -2 2 A Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC -2 2 A Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN = V IH or VIL, IOUT=0mA - 160 mA Standby Current ISB Min. Cycle, CS=VIH ISB1 f=0MHz, CS VCC-0.2V, VINVCC-0.2V or VIN0.2V Output Low Voltage Level VOL IOL=8mA Output High Voltage Level VOH IOH=-4mA 8ns 10ns - 155 12ns - 150 - 50 mA Normal - 5 mA L-Ver. - 0.7 - 0.4 V 2.4 - V * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25C, f=1.0MHz) Symbol Test Conditions MIN Max Unit Input/Output Capacitance Item CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 6 pF * Capacitance is sampled and not 100% tested. -3- Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI AC CHARACTERISTICS (TA=0 to 70C, VCC=3.30.3V, unless otherwise noted.) TEST CONDITIONS* Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below * The above test conditions are also applied at industrial temperature range. Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V RL = 50 DOUT VL = 1.5V ZO = 50 319 DOUT 30pF* 353 * Capacitive Load consists of all components of the test environment. 5pF* * Including Scope and Jig Capacitance READ CYCLE* Parameter Read Cycle Time Symbol tRC KM68V1002B/BL-8 KM68V1002B/BL-10 KM68V1002B/BL-12 Min Max Min Max Min Max 8 - 10 - 12 - Unit ns Address Access Time tAA - 8 - 10 - 12 ns Chip Select to Output tCO - 8 - 10 - 12 ns Output Enable to Valid Output tOE - 4 - 5 - 6 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 4 0 5 0 6 ns Output Disable to High-Z Output tOHZ 0 4 0 5 0 6 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns Chip Selection to Power DownTime tPD - 8 - 10 - 12 ns * The above parameters are also guaranteed at industrial temperature range. -4- Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI WRITE CYCLE* Parameter Symbol KM68V1002B/BL-8 KM68V1002B/BL-10 KM68V1002B/BL-12 Min Max Min Max Min Max Unit Write Cycle Time tWC 8 - 10 - 12 - ns Chip Select to End of Write tCW 6 - 7 - 8 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 6 - 7 - 8 - ns Write Pulse Width(OE High) tWP 6 - 7 - 8 - ns Write Pulse Width(OE Low) tWP1 8 - 10 - 12 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 4 0 5 0 6 ns Data to Write Time Overlap tDW 4 - 5 - 6 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - 3 - ns * The above parameters are also guaranteed at industrial temperature range. TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tOH Data Out tAA Valid Data Previous Valid Data -5- Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOE tOHZ OE tOLZ tOH tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out -6- Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW (10) (9) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP(2) WE tDW Data in High-Z Data Valid tLZ Data out tDH High-Z tWHZ(6) High-Z(8) High-Z NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. -7- Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * X means Dont Care. DATA RETENTION CHARACTERISTICS*(TA=0 to 70C) Parameter Symbol Test Condition Min. Typ. Max. Unit 2.0 - 3.6 V VCC=3.0V, CSVCC-0.2V VINVCC-0.2V or VIN0.2V - - 0.5 mA VCC=2.0V, CSVCC-0.2V VINVCC-0.2V or VIN0.2V - - 0.4 See Data Retention Wave form(below) 0 - - ns 5 - - ms VCC for Data Retention VDR CSVCC-0.2V Data Retention Current IDR Data Retention Set-Up Time tSDR Recovery Time tRDR * The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0V VIH VDR CSVCC - 0.2V CS GND -8- Rev 2.1 August 1998 Preliminary PRELIMINARY CMOS SRAM KM68V1002B/BL, KM68V1002BI/BLI Units:millimeters/Inches PACKAGE DIMENSIONS 32-SOJ-400 #17 10.16 0.400 #32 11.18 0.12 0.440 0.005 9.40 0.25 0.370 0.010 0.20 #1 #16 0.008 0.69 MIN 0.027 21.36 MAX 0.841 20.95 0.12 0.825 0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 ( 0.95 ) 0.0375 0.43 +0.10 -0.05 3.76 MAX 0.148 0.10 MAX 0.004 +0.10 -0.05 0.71 1.27 0.050 0.017 +0.004 -0.002 +0.10 -0.05 +0.004 -0.002 0.028 +0.004 -0.002 32-TSOP2-400F 0~8 0.25 ( 0.010 ) #17 0.45 ~0.75 0.018 ~ 0.030 11.76 0.20 0.463 0.008 #1 10.16 0.400 #32 ( 0.50 ) 0.020 #16 0.15 +0.10 -0.05 0.006 +0.004 -0.002 21.35 MAX 0.841 20.95 0.10 0.825 0.004 1.00 0.10 0.039 0.004 ( 0.95 ) 0.037 0.40 0.10 0.016 0.004 1.27 0.050 1.20 0.047 MAX 0.10 MAX 0.004 MAX 0.05 0.002MIN -9- Rev 2.1 August 1998