SST29VF512-70-4I-WHE - Microchip Technology, Inc.

S71160-11-000 3/05

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to cha nge without notice.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• Single Voltage Read and Write Operations

– 4.5-5.5V for SST29SF512/0x0

– 2.7-3.6V for SST29VF512/0x0

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 10 mA (typical)

– Standby Current:

30 µA (typical) for SST29SF512/0x0

1 µA (typical) for SST29VF512/0x0

• Sector-Erase Capability

– Uniform 128 Byte sectors

• Fast Read Access Time:

– 55 ns for SST29SF512/0x0

– 70 ns for SST29VF512/0x0

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Chip-Erase Ti me: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time:

1 second (typical) for SST29SF/VF512

2 seconds (typical) for SST29SF/VF010

4 seconds (typical) for SST29SF/VF020

8 seconds (typical) for SST29SF/VF040

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• TTL I/O Compatibility for SST29SF512/0x0

• CMOS I/O Compatibility for SST29VF512/0x0

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

• All non-Pb (lead-free) devic es are RoHS compliant

PRODUCT DESCRIPTION

The SST29SF512/0x0 and SST29 VF512/0x0 ar e 64K x8 /

128K x8 / 256K x8 / 512K x8 CMOS Small-Sector Flash

(SSF) manufactured with SST’s proprietary, high-perfor-

mance CMOS SuperFlash technology. The split-gate cell

design and thick-oxide tunneling injector attain better reli-

ability and manufacturability compared with alternate

approaches. The SST29SF512/0x0 devices write (Pro-

gram or Erase) with a 4.5-5.5V power supply. The

SST29VF512/0x0 devices write (Program or Erase) with a

2.7-3.6V power supply. These devices confor m to JEDEC

standard pin assignments f or x8 memories.

Featuring high performance Byte-Program, the

SST29SF512/0x0 and SST29VF512/0x0 devices provide

a maximum Byte-Program time of 20 µsec. To protect

against inadvertent wr ite, they have on-chip hardware and

Software Data Protection schemes. Designed, manufac-

tured, and tested f or a wide spectrum of applica tions, these

de vices are offered with a guaranteed endurance of at least

10,000 cycles. Data retention is rated at greater than 100

years.

The SST29SF512/0x0 and SST29VF512/0x0 devices are

suited f or applications that require con ve nient and econom-

ical updating of program, configuration, or data memory.

For all system applications, they significantly improve per-

f ormance and reliability, while lowering power consumption.

They inherently use less energ y during Erase and Progr am

than alternative flash technologies. The total energy con-

sumed is a function of the applied voltage, current, and

time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and

has a shorter erase time , the total energ y consumed during

any Erase or Program operation is less than alternative

flash technologies . They also improv e fle xibility while lo wer-

ing the cost for program, data, and configuration storage

applications.

The SuperFlash technology provides fixed Erase and Pro-

gram ti mes, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardw are does no t ha v e t o be modified or de-r ated as is

necessary with alternative flash technologies , whose Erase

and Program times increase with accumulated Erase/ Pro-

gram cycles.

To meet high density, surface mount requirements, the

SST29SF512/0x0 and SST29VF512/0x0 devices are

offered in 32-lead PLCC and 32-lead TSOP packages.

See Figures 1 and 2 f or pin assignments.

SST29SF/VF512 / 010 / 020 / 040512Kb / 1Mb / 2Mb / 4Mb (x8)

Byte-Program, Small-Sector flash memories

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address b us is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whiche v er o ccurs first.

Read

The Read operation of the SST29SF512/0x0 and

SST29VF512/0x0 de vices are controlled b y CE# and OE#,

both have to be low for the system to obtain data from the

outputs. CE# is used for device selection. When CE# is

high, the chip is deselected and only standb y pow er is con-

sumed. OE# is the output control and is used to gate data

from the output pins. The data bus is in high impedance

state when either CE# or OE# is high. Refer to the Read

cycle timing diagr am f or further details (Figure 3).

Byte-Program Operation

The SST29SF512/0x0 and SST29VF512/0x0 devices are

programmed on a byte-by-byte basis. Before program-

ming, the sector wher e the byte e xists must be fully erased.

The Program operation is accomplished in three steps. The

first step is the three-b yte load sequence for Software Data

Protection. The second step is to load byte address and

byte data. During the Byte-Program operation, the

addresses are latched on the falling edge of either CE# or

WE#, whiche v er occurs last . The data is latched on the ris-

ing edge of either CE# or WE#, whiche v er occurs first . The

third step is the internal Program operation which is initi-

ated after the rising edge of the f ourth WE# or CE#, which-

e ver occurs fir st. The Program oper ation, once initiated, will

be completed, within 20 µs. See Figures 4 and 5 for WE#

and CE# controlled Program operation timing diagrams

and Figure 15 for flowcharts. During the Program opera-

tion, the only valid reads are Data# Polling and Toggle Bit.

During the internal Program operation, the host is free to

perf orm additional tasks. An y commands written during the

internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase oper ation allows the system to er ase the

device on a sector-by-sector basis. The SST29SF512/0x0

and SST29VF512/0x0 offer Sector-Erase mode. The sec-

tor architecture is based on uniform sector size of 128

Bytes. The Sector-Erase operation is initiated by executing

a six-byte command sequence with Sector-Erase com-

mand (20H) and sector address (SA) in the last bus cycle.

The sector address is latched on the falling edge of the

sixth WE# pulse, while the command (20H) is latched on

the rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figure 8 for timing

waveforms. Any commands issued during the Sector-

Erase operat ion are ignored.

Chip-Erase Operation

The SST29SF512/0x0 and SST29VF512/0x0 devices pro-

vide a Chip-Erase operation, which allows the user to

erase the entire memory arra y to the “1s” state. Th is is use-

ful when the entire d e vice must be quic kly er ased.

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 555H in the last

byte sequence. The internal Erase operation begins with

the rising edge of the sixth WE# or CE#, whichev er occurs

first. During the internal Erase oper ation, the only valid read

is Toggle Bit or Dat a# P olling. See Table 4 for the comman d

sequence, Figure 9 for timing diagram, and Figure 18 for

the flowchart. Any commands written during the Chip-

Erase operation will be ignored.

Write Operation Status Detection

The SST29SF512/0x0 and SST29VF512/0x0 devices

provide two softw are means to detect the completion of a

Write (Program or Erase) cycle, in order to optimize the

system Write cycle time. The softw are detection includes

two status bits: Data# P olling (DQ7) and Toggle Bit (DQ6).

The End-of-Write detection mode is enabled after the ris-

ing edge of WE# which initiates the inter nal Program or

Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system; therefore, either a Data# Poll-

ing or Toggle Bit read may be simultaneous with the

completion of the Write cycle. If this occurs, the system

ma y possib ly get an erroneous result, i.e., valid data may

appear to conflict with either DQ7 or DQ6. In order to pre-

vent spurious rejection, if an erroneous result occurs, the

software routine should include a loop to read the

accessed location an additional two (2) times. If both

reads are valid, then the device has comp lete d the Write

cycle, otherwise the rejection is valid.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Data# Polling (DQ7)

When the SST29SF512/0x0 and SST29VF512/0x0

devices are in the internal Program operation, any

attempt to read DQ7 will produce the complement of the

true data. Once the Program operation is completed,

DQ7 will produce true data. Note that even though DQ7

may ha ve v alid data immediately following the completion

of an internal Write operation, the remaining data outputs

may still be invalid: valid data on the entire data bus will

appear in subsequent successive Read cycles after an

interval of 1 µs. During internal Erase operation, any

attempt to read DQ7 will produce a ‘0’. Once the internal

Erase operation is completed, DQ7 will produce a ‘1’. The

Data# Polling is valid after the rising edge of fourth WE#

(or CE#) pulse for Program operation. For Sector- or

Chip-Erase, the Data# Polling is valid after the rising

edge of sixth WE# (or CE#) pulse. See Figure 6 for

Data# Polling timing diagram and Figure 16 for a flow-

chart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ 6 will produce alternating ‘0’s

and ‘1’s, i.e., toggling between 0 and 1. When the inter nal

Program or Erase operation is completed, the toggling will

stop. The device is then ready for the next operation. The

Toggle Bit is valid after the rising edge of fourth WE# (or

CE#) pulse for Program operation. For Sector or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth

WE# (or CE#) pulse . See Figure 7 f or Toggle Bit timing dia-

gram and Figure 16 f or a flowchart.

Data Protection

The SST29SF512/0x0 and SST29VF512/0x0 de vice s pro-

vide both hardware and software features to protect non-

v olatile data from inadv ertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 2.5V for SST29SF512/0x0.

The Write operation is inhibited when VDD is less than 1.5V.

f or SST29VF512/0x0.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Wr ite operation. This prevents inadvert-

ent writes during power-up or po wer-do wn.

Software Data Protection (SDP)

The SST29SF512/0x0 and SST29VF512/0x0 provide the

JEDEC approved Software Data Protection scheme for all

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three- byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or po wer-down. Any Erase operation

requires the inclusion of a six-byte load sequence. These

de vices are shipped with th e Software Da ta Protection per-

manently enabled. See Table 4 for the specific software

command codes . During SDP command sequence , in valid

commands will abort the device to read mode , within TRC.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Product Identification

The Product Identification mode identifies the devices as

SST29SF512, SST29SF010, SST29SF020, SST29SF040

and SST29VF512, SST29VF010, SST29VF020,

SST29VF040 and manufacturer as SST. This mode may

be accessed by software operations. Users may use the

Softwar e Product Identificat ion operation to ident ify the part

(i.e., using the device ID) when using multiple manufactur-

ers in the same soc k et. F or details , see Table 4 for software

operation, Figure 10 for the Software ID Entry and Read

timing diagram and Figure 17 for the Software ID Entry

command sequence f lowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode , the Softw are

Product Identificat ion mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the de vice to the Read oper ation.

Please note that the Software ID Exit command is ignored

during an internal Program or Er ase operation. See Tab le 4

for software command codes, Figure 11 for timing wave-

f orm, and Figure 17 f or a fl owchart.

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’ s ID 0000H BFH

Device ID

SST29SF512 0001H 20H

SST29VF512 0001H 21H

SST29SF010 0001H 22H

SST29VF010 0001H 23H

SST29SF020 0001H 24H

SST29VF020 0001H 25H

SST29SF040 0001H 13H

SST29VF040 0001H 14H

T1.3 1160

Y-Decoder

I/O Buffers and Data Latches

1160 B1.0

Address Buffers & Latches

X-Decoder

DQ7 - DQ0

emory

ddress

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

VDD

WE#

A12

A15

A16

VDD

WE#

A12

A15

A16

VDD

WE#

A17

A12

A15

A16

A18

VDD

WE#

A17

32-lead PLCC

Top View

1160 32-plcc NH P1.1

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

SST29SF/VF512SST29SF/VF010SST29SF/VF020

ST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF04

SST29SF/VF512

SST29SF/VF512SST29SF/VF010SST29SF/VF020

ST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF04

SST29SF/VF512

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

Address Inputs To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the

sector.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is inter nally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply v oltage: 4.5-5.5V for SST29SF512/0x0

2.7-3.6V for SST29 VF512/0 x0

VSS Ground

NC No Connection Pin not connected internally

T2.5 1160

TABLE 3: OPERATION MODES S ELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector address,

XXH for Chip -Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.4 1160

A11

A13

A14

WE#

VDD

A15

A12

A11

A13

A14

WE#

VDD

A16

A15

A12

A11

A13

A14

A17

WE#

VDD

A16

A15

A12

A11

A13

A14

A17

WE#

VDD

A18

A16

A15

A12

SST29SF/VF512SST29SF/VF010SST29SF/VF020SST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040SST29SF/VF512

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

1160 32-tsop WH P2.1

Standard Pinout

Top View

Die Up

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command

Sequence 1st Bus

Write Cycle 2nd Bus

Write Cycle 3rd Bus

Write Cyc le 4th Bus

Write Cyc le 5th Bus

Write Cycle 6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 555H AAH 2AAH 55H 555H A0H BA2Data

Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX320H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Software ID Entry4,5 555H AAH 2AAH 55H 555H 90H

Software ID Exit6XXH F0H

Software ID Exit6555H AAH 2AAH 55H 555H F0H

T4.7 1160

1. Address format A14-A0 (Hex),

Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF512.

Addresses A15-AMS can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF0x0.

AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040.

2. BA = Program Byte address

3. SAX for Sector-Erase; uses AMS-A7 address lines for SST29SF/VF512/0x0

4. The device does not remain in Software Product ID mode if powered down.

5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,

SST29SF512 Device ID = 20H, is read with A0 = 1

SST29VF512 Device ID = 21H, is read with A0 = 1

SST29SF010 Device ID = 22H, is read with A0 = 1

SST29VF010 Device ID = 23H, is read with A0 = 1

SST29SF020 Device ID = 24H, is read with A0 = 1

SST29VF020 Device ID = 25H, is read with A0 = 1

SST29SF040 Device ID = 13H, is read with A0 = 1

SST29VF040 Device ID = 14H, is read with A0 = 1

6. Both Software ID Exit operations are equivalent

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions ma y affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Solder Reflo w Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST29SF512/0 X0

Range Ambient Temp VDD

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

OPERATING RANGE FOR SST29VF512/0 X0

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 55 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns

See Figures 12, 13, and 14

TABLE 5: DC OPERATING CHARACTERISTICS VDD = 4.5-5.5V FOR SST29SF512/0 X0

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

VDD=VDD Max

Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Write 20 mA CE#=WE#=VIL, OE#=VIH

ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max

ISB2 Standby VDD Curren t (C MOS input) 100 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Lo w Voltage 0.4 V IOL=2.1 µA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Mi n

T5.7 1160

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

TABLE 6: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V FOR SST29VF512/0 X0

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

VDD=VDD Max

Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Write 20 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Lo w Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Mi n

T6.9 1160

TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T7.1 1160

TABLE 8: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)

Parameter Desc ription Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T8.1 1160

TABLE 9: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T9.2 1160

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

AC CHARACTERISTICS

TABLE 10: READ CYCLE TIMING PARAMETERS

VDD = 4.5-5.5V FOR SST29SF512/0X0 AND 2.7-3.6V FOR SST 29VF512/0X0

Symbol Parameter

SST29SF512/0x0-55 SST29VF512/0x0-70

UnitsMin Max Min Max

TRC Read Cycle Time 55 70 ns

TCE Chip Enable Access Time 55 70 ns

TAA Address Access Time 55 70 ns

TOE Output Enable Access Time 30 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

CE# Low to Active Output 0 0 ns

TOLZ1OE# Low to Active Output 0 0 ns

TCHZ1CE# High to High-Z Output 20 25 ns

TOHZ1OE# High to High-Z Output 20 25 ns

TOH1Output Hold from Address Change 00ns

T10.10 1160

TABLE 11: PROGRAM/ERASE CYCLE TIMING PARAMETERS

VDD = 4.5-5.5V FOR SST29SF512/0X0 AND 2.7-3.6V FOR SST 29VF512/0X0

Symbol Parameter Min Max Units

TBP Byte-Program Time 20 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change t hat could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 40 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TSCE Chip-Erase 100 ms

T11.9 1160

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 3: READ CYCLE TIMING DIAGRAM

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

1160 F03.1

DDRESS AMS-0

DQ7-0

WE#

OE#

CE# TCE

TRC TAA

TOE

TOLZVIH

HIGH-Z TCLZ TOH TCHZ HIGH-Z

D ATA V ALIDD ATA V ALID

TOHZ

Note: AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

1160 F04.1

DDRESS AMS-0

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

555 2AA 555 ADDR

AA 55 A0 DATA

BYTE

(ADDR/DATA)

OE#

WE#

TBP

INTERNAL PROGRAM OPERATION STARTS

Note: AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

FIGURE 6: DATA# POLLING TIMING DIAGRAM

1160 F05.1

DDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

555 2AA 555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

1160 F06.1

DDRESS AMS-0

DQ7DD# D# D

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 7: TOGGLE BIT TIMING D IAGRAM

FIGURE 8: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

1160 F07.1

DDRESS AMS-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOE

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

1160 F08.1

DDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

555 2AA 2AA555 555

55 2055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TWP

Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are interchangeable as

long as minimum timings are met. (See Table 11)

AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

SAX = Sector Address.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 9: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

FIGURE 10: SOFTWARE ID ENTRY AND READ

1160 F09.1

DDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

555 2AA 2AA555 555

55 1055AA 80 AA

555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

SCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchangeable as

long as minimum timings are met. (See Table 11)

AMS = Most significant address

AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

1160 F10.1

DDRESS A14-0

DQ7-0

WE#

SW1SW0 SW2

Device ID

555 2AA 555 0000 0001

OE#

CE#

Three-Byte Sequence for

Software ID Entry

TWP

TWPH TAA

BF55AA 90

TIDA

Note: Device ID = 20H for SST29SF512, 22H for SST29SF010, 24H for SST29SF020, 13H for SST29SF040

21H for SST29VF512, 23H for SST29VF010, 25H for SST29VF020, 14H for SST29VF040

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 11: SOFTWARE ID EXIT AND RESET

1160 F11.1

DDRESS A14-0

DQ7-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

555 2AA 555

Three-Byte Sequence for

Sofware ID Exit and Reset

OE#

CE#

AA 55 F0

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29SF512/0X0

FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS FOR SST29VF512/0X0

FIGURE 14: TEST LOAD EXAMPLES

1160 F12.0

REFERENCE POINTS OUTPUTINPUT VIT

IHT

VILT

VOT

A C test inputs are driven at VIHT (3.0V) for a logic “1” and VILT (0V) f or a logic “0”. Measurement reference points f or inputs

and outputs are VIT (1.5 VDD) and VOT (1.5 VDD). Input rise and f all times (10% ↔ 90%) are <10 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1160 F12.0

REFERENCE POINTS OUTPUTINPUT VIT

IHT

VILT

VOT

A C test inputs are driv en at VIHT (0. 9 VDD) f or a logic “1” and VILT (0.1 VDD) f or a log ic “0”. Measurement reference points

f or inputs and outputs are VIT (0.5 VDD) and V OT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1160 F14a.0

SST29SF040

T O TESTER

O DUT

CLRL LOW

RL HIG

VDD

1160 F14b.0

T O TESTER

O DUT

SST29VF040

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 15: BYTE-PROGRAM ALGORITHM

1160 F15.0

Start

Load data: AAH

Address: 555H

Load data: 55H

Address: 2AAH

Load data: A0H

Address: 555H

Load Byte

Address/Byte

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 16: WAIT OPTIONS

1160 F16.0

W ait TBP,

TSCE, or TSE

Byte-

Program/Erase

Initiated

Internal Timer Toggle Bit

Yes

Program/Erase

Completed

Does DQ6

match?

Read same

byte

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read byte

Is DQ7 =

true data?

Read DQ7

Byte-

Program/Erase

Initiated

Byte-

Program/Erase

Initiated

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 17: SOFTWARE ID COMMAND FLOWCHARTS

1160 F17.0

Load data: AAH

Address: 555H

Software ID Entry

ommand Sequence

Load data: 55H

Address: 2AAH

Load data: 90H

Address: 555H

W ait TIDA

Read Software ID

Load data: AAH

Address: 555H

Software ID Exit &

Reset Command Sequence

Load data: 55H

Address: 2AAH

Load data: F0H

Address: 555H

Load data: F0H

Address: XXH

Return to normal

operation

W ait TIDA

Return to normal

operation

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

FIGURE 18: ERASE COMMAND SEQUENCE

1160 F18.0

Load data: AAH

Address: 555H

Chip-Erase

ommand Sequence

Load data: 55H

Address: 2AAH

Load data: 80H

Address: 555H

Load data: 55H

Address: 2AAH

Load data: 10H

Address: 555H

Load data: AAH

Address: 555H

W ait TSCE

Chip erased

to FFH

Load data: AAH

Address: 555H

Sector-Erase

Command Sequence

Load data: 55H

Address: 2AAH

Load data: 80H

Address: 555H

Load data: 55H

Address: 2AAH

Load data: 20H

Address: SAX

Load data: AAH

Address: 555H

W ait TSE

Sector erased

to FFH

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

PRODUCT ORDERING INFORMATION

Device Speed Suffix1 Suffix2

SST29xFxxx - XXX -XX-XXX Environmental Attribute

E1 = non-Pb

Package Modifier

H = 32 leads

Pa ckage Type

N = PLCC

W = TSOP (type 1, die up, 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Enduranc e

4 = 10,000 cycles

Read Access Speed

55 = 55 ns

70 = 70 ns

Device Density

040 = 4 Mbit

020 = 2 Mbit

010 = 1 Mbit

512 = 512 Kbit

Function

F = Chip- or Sector-Erase

Byte-Program

Voltage

S = 4.5-5.5V

V = 2.7-3.6V

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Valid combinations for SST29SF512

SST29SF512-55-4C-NH SST29SF512-55-4C-WH

SST29SF512-55-4C-NHE SST29SF512-55-4C-WHE

SST29SF512-55-4I-NH SST29SF512-55-4I-WH

SST29SF512-55-4I-NHE SST29SF512-55-4I-WHE

Valid combinations for SST29VF512

SST29VF512-70-4C-NH SST29VF512-70-4C-WH

SST29VF512-70-4C-NHE SST29VF512-70-4C-WHE

SST29VF512-70-4I-NH SST29VF512-70-4I-WH

SST29VF512-70-4I-NHE SST29VF512-70-4I-WHE

Valid combinations for SST29SF010

SST29SF010-55-4C-NH SST29SF010-55-4C-WH

SST29SF010-55-4C-NHE SST29SF010-55-4C-WHE

SST29SF010-55-4I-NH SST29SF010-55-4I-WH

SST29SF010-55-4I-NHE SST29SF010-55-4I-WHE

Valid combinations for SST29VF010

SST29VF010-70-4C-NH SST29VF010-70-4C-WH

SST29VF010-70-4C-NHE SST29VF010-70-4C-WHE

SST29VF010-70-4I-NH SST29VF010-70-4I-WH

SST29VF010-70-4I-NHE SST29VF010-70-4I-WHE

Valid combinations for SST29SF020

SST29SF020-55-4C-NH SST29SF020-55-4C-WH

SST29SF020-55-4C-NHE SST29SF020-55-4C-WHE

SST29SF020-55-4I-NH SST29SF020-55-4I-WH

SST29SF020-55-4I-NHE SST29SF020-55-4I-WHE

Valid combinations for SST29VF020

SST29VF020-70-4C-NH SST29VF020-70-4C-WH

SST29VF020-70-4C-NHE SST29VF020-70-4C-WHE

SST29VF020-70-4I-NH SST29VF020-70-4I-WH

SST29VF020-70-4I-NHE SST29VF020-70-4I-WHE

Valid combinations for SST29SF040

SST29SF040-55-4C-NH SST29SF040-55-4C-WH

SST29SF040-55-4C-NHE SST29SF040-55-4C-WHE

SST29SF040-55-4I-NH SST29SF040-55-4I-WH

SST29SF040-55-4I-NHE SST29SF040-55-4I-WHE

Valid combinations for SST29VF040

SST29VF040-70-4C-NH SST29VF040-70-4C-WH

SST29VF040-70-4C-NHE SST29VF040-70-4C-WHE

SST29VF040-70-4I-NH SST29VF040-70-4I-WH

SST29VF040-70-4I-NHE SST29VF040-70-4I-WHE

Note: Valid combination s are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determ ine availabi lity of new combinations.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

PACKAGING DIAGRAMS

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE C ODE: NH

.040

.030

.021

.013 .530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

T OP VIEW SIDE VIEW BO TT OM VIEW

1232

.400

BSC

32-plcc-NH-

ote: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

dentifier .020 R.

MAX. R.

x 30˚

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM

SST PACKAGE C ODE: WH

32-tsop-WH

-7

ote: 1.Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2.All linear dimensions are in millimeters (max/min).

3.Coplanarity: 0.1 mm

4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0˚- 5˚

DETAIL

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040

SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

TABLE 12: REVISION HISTORY

Number Description Date

05 •2002 Data Book May 2002

06 •Removed 512 Kbit, 1 Mbit, and 2 Mbit parts

•Commercial temperature and 70 ns parts removed

•PH package is no longer offered

•Part number changes - see page 22 for additional information

•Changes to Tables 5 and 6 on page 8 and page 9:

– Clarified Test Conditions for Power Supply Curr ent and Read parameters

– Clarified IDD Write to be Program and Erase

– Corrected IDD Program and Erase from 20 mA to 30 mA

– Corrected IDD Read from 20 mA to 25 mA

•Clarified measurement reference points VIT and VOT to be 1.5V instead of 1.5VDD

•Corrected th e VOL test co ndition IOL to be 2.1 mA instead of 2.1 µA in Table 5 on page 8

Mar 2003

07 •Corrected th e Test Co nd itio ns for the Read Paramete r in Table 5 on page 8 Apr 2003

08 •Added Commercial temperatures for all packages (See page 22 for details) Aug 2003

09 •2004 Data Book

•Changed status to “Data Sheet” Dec 2003

10 •Added 70 ns technical data and MPNs for SST29VF040 only F eb 2004

11 •Added RoHS compliance information on page 1 and in the

“Product Or de ring In form at ion ” on pa ge 21

•Reinstated 512 Kbit , 1 Mbit, and 2 Mbit de vices and MPNs (e xcluding the PDI P pac kage)

•Removed 55 ns technical data and MPNs for SST29VF040

•Added non-Pb MPNs for all de vices

•Clarified the solder temperature profile under “Absolute Maximum Stress Ratings” on

page 8

Mar 2005

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036